diff --git a/.gitignore b/.gitignore index c670072..f6ae3b8 100644 --- a/.gitignore +++ b/.gitignore @@ -1,10 +1,10 @@ *.flock -*/incremental_db/ -*/output_files/ -*/nios_system/ +incremental_db/ +output_files/ +nios_system/ +db/ *.bsf *.cmp *.sopcinfo *.rpt *.qsys_edit -*/db/ \ No newline at end of file diff --git a/db/a_dpfifo_q131.tdf b/db/a_dpfifo_q131.tdf deleted file mode 100644 index e177be3..0000000 --- a/db/a_dpfifo_q131.tdf +++ /dev/null @@ -1,79 +0,0 @@ ---a_dpfifo ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=64 LPM_SHOWAHEAD="OFF" lpm_width=8 lpm_widthu=6 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" aclr clock data empty full q rreq sclr usedw wreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=AUTO" RAM_BLOCK_TYPE="AUTO" ---VERSION_BEGIN 13.0 cbx_altdpram 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_fifo_common 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_scfifo 2013:06:12:18:03:43:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION a_fefifo_7cf (aclr, clock, rreq, sclr, wreq) -RETURNS ( empty, full, usedw_out[5..0]); -FUNCTION dpram_nl21 (data[7..0], inclock, outclock, outclocken, rdaddress[5..0], wraddress[5..0], wren) -RETURNS ( q[7..0]); -FUNCTION cntr_1ob (aclr, clock, cnt_en, sclr) -RETURNS ( q[5..0]); - ---synthesis_resources = lut 18 M9K 1 reg 20 -SUBDESIGN a_dpfifo_q131 -( - aclr : input; - clock : input; - data[7..0] : input; - empty : output; - full : output; - q[7..0] : output; - rreq : input; - sclr : input; - usedw[5..0] : output; - wreq : input; -) -VARIABLE - fifo_state : a_fefifo_7cf; - FIFOram : dpram_nl21; - rd_ptr_count : cntr_1ob; - wr_ptr : cntr_1ob; - rd_ptr[5..0] : WIRE; - valid_rreq : WIRE; - valid_wreq : WIRE; - -BEGIN - fifo_state.aclr = aclr; - fifo_state.clock = clock; - fifo_state.rreq = rreq; - fifo_state.sclr = sclr; - fifo_state.wreq = wreq; - FIFOram.data[] = data[]; - FIFOram.inclock = clock; - FIFOram.outclock = clock; - FIFOram.outclocken = (valid_rreq # sclr); - FIFOram.rdaddress[] = ((! sclr) & rd_ptr[]); - FIFOram.wraddress[] = wr_ptr.q[]; - FIFOram.wren = valid_wreq; - rd_ptr_count.aclr = aclr; - rd_ptr_count.clock = clock; - rd_ptr_count.cnt_en = valid_rreq; - rd_ptr_count.sclr = sclr; - wr_ptr.aclr = aclr; - wr_ptr.clock = clock; - wr_ptr.cnt_en = valid_wreq; - wr_ptr.sclr = sclr; - empty = fifo_state.empty; - full = fifo_state.full; - q[] = FIFOram.q[]; - rd_ptr[] = rd_ptr_count.q[]; - usedw[] = fifo_state.usedw_out[]; - valid_rreq = rreq; - valid_wreq = wreq; -END; ---VALID FILE diff --git a/db/a_fefifo_7cf.tdf b/db/a_fefifo_7cf.tdf deleted file mode 100644 index 3398db0..0000000 --- a/db/a_fefifo_7cf.tdf +++ /dev/null @@ -1,90 +0,0 @@ ---a_fefifo ALLOW_RWCYCLE_WHEN_FULL="OFF" LPM_NUMWORDS=64 lpm_widthad=6 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" aclr clock empty full rreq sclr usedw_out wreq ---VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_fifo_common 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION cntr_do7 (aclr, clock, cnt_en, sclr, updown) -RETURNS ( q[5..0]); - ---synthesis_resources = lut 6 reg 8 -SUBDESIGN a_fefifo_7cf -( - aclr : input; - clock : input; - empty : output; - full : output; - rreq : input; - sclr : input; - usedw_out[5..0] : output; - wreq : input; -) -VARIABLE - b_full : dffe; - b_non_empty : dffe; - count_usedw : cntr_do7; - equal_af1w[5..0] : WIRE; - equal_one[5..0] : WIRE; - is_almost_empty0 : WIRE; - is_almost_empty1 : WIRE; - is_almost_empty2 : WIRE; - is_almost_empty3 : WIRE; - is_almost_empty4 : WIRE; - is_almost_empty5 : WIRE; - is_almost_full0 : WIRE; - is_almost_full1 : WIRE; - is_almost_full2 : WIRE; - is_almost_full3 : WIRE; - is_almost_full4 : WIRE; - is_almost_full5 : WIRE; - usedw[5..0] : WIRE; - valid_rreq : WIRE; - valid_wreq : WIRE; - -BEGIN - b_full.clk = clock; - b_full.clrn = (! aclr); - b_full.d = ((b_full.q & (b_full.q $ (sclr # rreq))) # (((! b_full.q) & b_non_empty.q) & ((! sclr) & ((is_almost_full5 & wreq) & (! rreq))))); - b_non_empty.clk = clock; - b_non_empty.clrn = (! aclr); - b_non_empty.d = (((b_full.q & (b_full.q $ sclr)) # (((! b_non_empty.q) & wreq) & (! sclr))) # (((! b_full.q) & b_non_empty.q) & (((! b_full.q) & b_non_empty.q) $ (sclr # ((is_almost_empty5 & rreq) & (! wreq)))))); - count_usedw.aclr = aclr; - count_usedw.clock = clock; - count_usedw.cnt_en = (valid_wreq $ valid_rreq); - count_usedw.sclr = sclr; - count_usedw.updown = valid_wreq; - empty = (! b_non_empty.q); - equal_af1w[] = ( B"0", B"0", B"0", B"0", B"0", B"0"); - equal_one[] = ( B"1", B"1", B"1", B"1", B"1", B"0"); - full = b_full.q; - is_almost_empty0 = (usedw[0..0] $ equal_one[0..0]); - is_almost_empty1 = ((usedw[1..1] $ equal_one[1..1]) & is_almost_empty0); - is_almost_empty2 = ((usedw[2..2] $ equal_one[2..2]) & is_almost_empty1); - is_almost_empty3 = ((usedw[3..3] $ equal_one[3..3]) & is_almost_empty2); - is_almost_empty4 = ((usedw[4..4] $ equal_one[4..4]) & is_almost_empty3); - is_almost_empty5 = ((usedw[5..5] $ equal_one[5..5]) & is_almost_empty4); - is_almost_full0 = (usedw[0..0] $ equal_af1w[0..0]); - is_almost_full1 = ((usedw[1..1] $ equal_af1w[1..1]) & is_almost_full0); - is_almost_full2 = ((usedw[2..2] $ equal_af1w[2..2]) & is_almost_full1); - is_almost_full3 = ((usedw[3..3] $ equal_af1w[3..3]) & is_almost_full2); - is_almost_full4 = ((usedw[4..4] $ equal_af1w[4..4]) & is_almost_full3); - is_almost_full5 = ((usedw[5..5] $ equal_af1w[5..5]) & is_almost_full4); - usedw[] = count_usedw.q[]; - usedw_out[] = usedw[]; - valid_rreq = rreq; - valid_wreq = wreq; -END; ---VALID FILE diff --git a/db/altsyncram_0rh1.tdf b/db/altsyncram_0rh1.tdf deleted file mode 100644 index 660af43..0000000 --- a/db/altsyncram_0rh1.tdf +++ /dev/null @@ -1,1042 +0,0 @@ ---altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nios_system_nios2_processor_rf_ram_a.mif" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=32 NUMWORDS_B=32 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_B=32 WIDTHAD_A=5 WIDTHAD_B=5 address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 1 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_0rh1 -( - address_a[4..0] : input; - address_b[4..0] : input; - clock0 : input; - data_a[31..0] : input; - q_b[31..0] : output; - wren_a : input; -) -VARIABLE - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 0, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 1, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 2, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 3, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 4, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 5, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 6, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 7, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 8, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 9, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 10, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 11, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a12 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 12, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a13 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 13, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a14 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 14, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a15 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 15, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a16 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 16, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a17 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 17, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a18 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 18, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a19 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 19, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a20 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 20, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a21 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 21, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a22 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 22, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a23 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 23, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a24 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 24, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a25 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 25, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a26 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 26, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a27 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 27, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a28 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 28, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a29 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 29, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a30 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 30, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a31 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 31, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_wire[4..0] : WIRE; - address_b_wire[4..0] : WIRE; - -BEGIN - ram_block1a[31..0].clk0 = clock0; - ram_block1a[31..0].portaaddr[] = ( address_a_wire[4..0]); - ram_block1a[0].portadatain[] = ( data_a[0..0]); - ram_block1a[1].portadatain[] = ( data_a[1..1]); - ram_block1a[2].portadatain[] = ( data_a[2..2]); - ram_block1a[3].portadatain[] = ( data_a[3..3]); - ram_block1a[4].portadatain[] = ( data_a[4..4]); - ram_block1a[5].portadatain[] = ( data_a[5..5]); - ram_block1a[6].portadatain[] = ( data_a[6..6]); - ram_block1a[7].portadatain[] = ( data_a[7..7]); - ram_block1a[8].portadatain[] = ( data_a[8..8]); - ram_block1a[9].portadatain[] = ( data_a[9..9]); - ram_block1a[10].portadatain[] = ( data_a[10..10]); - ram_block1a[11].portadatain[] = ( data_a[11..11]); - ram_block1a[12].portadatain[] = ( data_a[12..12]); - ram_block1a[13].portadatain[] = ( data_a[13..13]); - ram_block1a[14].portadatain[] = ( data_a[14..14]); - ram_block1a[15].portadatain[] = ( data_a[15..15]); - ram_block1a[16].portadatain[] = ( data_a[16..16]); - ram_block1a[17].portadatain[] = ( data_a[17..17]); - ram_block1a[18].portadatain[] = ( data_a[18..18]); - ram_block1a[19].portadatain[] = ( data_a[19..19]); - ram_block1a[20].portadatain[] = ( data_a[20..20]); - ram_block1a[21].portadatain[] = ( data_a[21..21]); - ram_block1a[22].portadatain[] = ( data_a[22..22]); - ram_block1a[23].portadatain[] = ( data_a[23..23]); - ram_block1a[24].portadatain[] = ( data_a[24..24]); - ram_block1a[25].portadatain[] = ( data_a[25..25]); - ram_block1a[26].portadatain[] = ( data_a[26..26]); - ram_block1a[27].portadatain[] = ( data_a[27..27]); - ram_block1a[28].portadatain[] = ( data_a[28..28]); - ram_block1a[29].portadatain[] = ( data_a[29..29]); - ram_block1a[30].portadatain[] = ( data_a[30..30]); - ram_block1a[31].portadatain[] = ( data_a[31..31]); - ram_block1a[31..0].portawe = wren_a; - ram_block1a[31..0].portbaddr[] = ( address_b_wire[4..0]); - ram_block1a[31..0].portbre = B"11111111111111111111111111111111"; - address_a_wire[] = address_a[]; - address_b_wire[] = address_b[]; - q_b[] = ( ram_block1a[31..0].portbdataout[0..0]); -END; ---VALID FILE diff --git a/db/altsyncram_1rh1.tdf b/db/altsyncram_1rh1.tdf deleted file mode 100644 index 987a124..0000000 --- a/db/altsyncram_1rh1.tdf +++ /dev/null @@ -1,1042 +0,0 @@ ---altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nios_system_nios2_processor_rf_ram_b.mif" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=32 NUMWORDS_B=32 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_B=32 WIDTHAD_A=5 WIDTHAD_B=5 address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 1 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_1rh1 -( - address_a[4..0] : input; - address_b[4..0] : input; - clock0 : input; - data_a[31..0] : input; - q_b[31..0] : output; - wren_a : input; -) -VARIABLE - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 0, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 1, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 2, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 3, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 4, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 5, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 6, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 7, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 8, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 9, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 10, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 11, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a12 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 12, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a13 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 13, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a14 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 14, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a15 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 15, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a16 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 16, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a17 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 17, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a18 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 18, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a19 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 19, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a20 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 20, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a21 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 21, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a22 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 22, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a23 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 23, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a24 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 24, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a25 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 25, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a26 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 26, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a27 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 27, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a28 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 28, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a29 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 29, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a30 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 30, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a31 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 31, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_wire[4..0] : WIRE; - address_b_wire[4..0] : WIRE; - -BEGIN - ram_block1a[31..0].clk0 = clock0; - ram_block1a[31..0].portaaddr[] = ( address_a_wire[4..0]); - ram_block1a[0].portadatain[] = ( data_a[0..0]); - ram_block1a[1].portadatain[] = ( data_a[1..1]); - ram_block1a[2].portadatain[] = ( data_a[2..2]); - ram_block1a[3].portadatain[] = ( data_a[3..3]); - ram_block1a[4].portadatain[] = ( data_a[4..4]); - ram_block1a[5].portadatain[] = ( data_a[5..5]); - ram_block1a[6].portadatain[] = ( data_a[6..6]); - ram_block1a[7].portadatain[] = ( data_a[7..7]); - ram_block1a[8].portadatain[] = ( data_a[8..8]); - ram_block1a[9].portadatain[] = ( data_a[9..9]); - ram_block1a[10].portadatain[] = ( data_a[10..10]); - ram_block1a[11].portadatain[] = ( data_a[11..11]); - ram_block1a[12].portadatain[] = ( data_a[12..12]); - ram_block1a[13].portadatain[] = ( data_a[13..13]); - ram_block1a[14].portadatain[] = ( data_a[14..14]); - ram_block1a[15].portadatain[] = ( data_a[15..15]); - ram_block1a[16].portadatain[] = ( data_a[16..16]); - ram_block1a[17].portadatain[] = ( data_a[17..17]); - ram_block1a[18].portadatain[] = ( data_a[18..18]); - ram_block1a[19].portadatain[] = ( data_a[19..19]); - ram_block1a[20].portadatain[] = ( data_a[20..20]); - ram_block1a[21].portadatain[] = ( data_a[21..21]); - ram_block1a[22].portadatain[] = ( data_a[22..22]); - ram_block1a[23].portadatain[] = ( data_a[23..23]); - ram_block1a[24].portadatain[] = ( data_a[24..24]); - ram_block1a[25].portadatain[] = ( data_a[25..25]); - ram_block1a[26].portadatain[] = ( data_a[26..26]); - ram_block1a[27].portadatain[] = ( data_a[27..27]); - ram_block1a[28].portadatain[] = ( data_a[28..28]); - ram_block1a[29].portadatain[] = ( data_a[29..29]); - ram_block1a[30].portadatain[] = ( data_a[30..30]); - ram_block1a[31].portadatain[] = ( data_a[31..31]); - ram_block1a[31..0].portawe = wren_a; - ram_block1a[31..0].portbaddr[] = ( address_b_wire[4..0]); - ram_block1a[31..0].portbre = B"11111111111111111111111111111111"; - address_a_wire[] = address_a[]; - address_b_wire[] = address_b[]; - q_b[] = ( ram_block1a[31..0].portbdataout[0..0]); -END; ---VALID FILE diff --git a/db/altsyncram_4891.tdf b/db/altsyncram_4891.tdf deleted file mode 100644 index f9cb0e6..0000000 --- a/db/altsyncram_4891.tdf +++ /dev/null @@ -1,819 +0,0 @@ ---altsyncram CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nios_system_nios2_processor_ociram_default_contents.mif" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=256 OPERATION_MODE="SINGLE_PORT" OUTDATA_REG_A="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" WIDTH_A=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=8 address_a byteena_a clock0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 1 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_4891 -( - address_a[7..0] : input; - byteena_a[3..0] : input; - clock0 : input; - data_a[31..0] : input; - q_a[31..0] : output; - wren_a : input; -) -VARIABLE - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a12 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a13 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a14 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a15 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a16 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a17 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a18 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a19 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a20 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a21 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a22 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a23 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a24 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a25 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a26 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a27 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a28 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a29 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a30 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a31 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_wire[7..0] : WIRE; - -BEGIN - ram_block1a[31..0].clk0 = clock0; - ram_block1a[31..0].portaaddr[] = ( address_a_wire[7..0]); - ram_block1a[7..0].portabyteenamasks[] = ( byteena_a[0..0]); - ram_block1a[15..8].portabyteenamasks[] = ( byteena_a[1..1]); - ram_block1a[23..16].portabyteenamasks[] = ( byteena_a[2..2]); - ram_block1a[31..24].portabyteenamasks[] = ( byteena_a[3..3]); - ram_block1a[0].portadatain[] = ( data_a[0..0]); - ram_block1a[1].portadatain[] = ( data_a[1..1]); - ram_block1a[2].portadatain[] = ( data_a[2..2]); - ram_block1a[3].portadatain[] = ( data_a[3..3]); - ram_block1a[4].portadatain[] = ( data_a[4..4]); - ram_block1a[5].portadatain[] = ( data_a[5..5]); - ram_block1a[6].portadatain[] = ( data_a[6..6]); - ram_block1a[7].portadatain[] = ( data_a[7..7]); - ram_block1a[8].portadatain[] = ( data_a[8..8]); - ram_block1a[9].portadatain[] = ( data_a[9..9]); - ram_block1a[10].portadatain[] = ( data_a[10..10]); - ram_block1a[11].portadatain[] = ( data_a[11..11]); - ram_block1a[12].portadatain[] = ( data_a[12..12]); - ram_block1a[13].portadatain[] = ( data_a[13..13]); - ram_block1a[14].portadatain[] = ( data_a[14..14]); - ram_block1a[15].portadatain[] = ( data_a[15..15]); - ram_block1a[16].portadatain[] = ( data_a[16..16]); - ram_block1a[17].portadatain[] = ( data_a[17..17]); - ram_block1a[18].portadatain[] = ( data_a[18..18]); - ram_block1a[19].portadatain[] = ( data_a[19..19]); - ram_block1a[20].portadatain[] = ( data_a[20..20]); - ram_block1a[21].portadatain[] = ( data_a[21..21]); - ram_block1a[22].portadatain[] = ( data_a[22..22]); - ram_block1a[23].portadatain[] = ( data_a[23..23]); - ram_block1a[24].portadatain[] = ( data_a[24..24]); - ram_block1a[25].portadatain[] = ( data_a[25..25]); - ram_block1a[26].portadatain[] = ( data_a[26..26]); - ram_block1a[27].portadatain[] = ( data_a[27..27]); - ram_block1a[28].portadatain[] = ( data_a[28..28]); - ram_block1a[29].portadatain[] = ( data_a[29..29]); - ram_block1a[30].portadatain[] = ( data_a[30..30]); - ram_block1a[31].portadatain[] = ( data_a[31..31]); - ram_block1a[31..0].portare = B"11111111111111111111111111111111"; - ram_block1a[31..0].portawe = wren_a; - address_a_wire[] = address_a[]; - q_a[] = ( ram_block1a[31..0].portadataout[0..0]); -END; ---VALID FILE diff --git a/db/altsyncram_4ed1.tdf b/db/altsyncram_4ed1.tdf deleted file mode 100644 index edb6130..0000000 --- a/db/altsyncram_4ed1.tdf +++ /dev/null @@ -1,5470 +0,0 @@ ---altsyncram BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nios_system_onchip_memory.hex" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=51200 NUMWORDS_A=51200 OPERATION_MODE="SINGLE_PORT" OUTDATA_REG_A="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=16 address_a byteena_a clock0 clocken0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION decode_qsa (data[2..0], enable) -RETURNS ( eq[6..0]); -FUNCTION mux_nob (data[223..0], sel[2..0]) -RETURNS ( result[31..0]); -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = lut 168 M9K 200 reg 3 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_4ed1 -( - address_a[15..0] : input; - byteena_a[3..0] : input; - clock0 : input; - clocken0 : input; - data_a[31..0] : input; - q_a[31..0] : output; - wren_a : input; -) -VARIABLE - address_reg_a[2..0] : dffe; - decode3 : decode_qsa; - mux2 : mux_nob; - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a12 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a13 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a14 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a15 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a16 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a17 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a18 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a19 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a20 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a21 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a22 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a23 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a24 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a25 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a26 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a27 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a28 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a29 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a30 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a31 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a32 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a33 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a34 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a35 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a36 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a37 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a38 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a39 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a40 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a41 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a42 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a43 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a44 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a45 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a46 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a47 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a48 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a49 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a50 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a51 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a52 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a53 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a54 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a55 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a56 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a57 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a58 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a59 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a60 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a61 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a62 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a63 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a64 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a65 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a66 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a67 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a68 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a69 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a70 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a71 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a72 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a73 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a74 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a75 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a76 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a77 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a78 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a79 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a80 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a81 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a82 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a83 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a84 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a85 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a86 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a87 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a88 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a89 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a90 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a91 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a92 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a93 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a94 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a95 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a96 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a97 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a98 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a99 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a100 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a101 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a102 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a103 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a104 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a105 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a106 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a107 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a108 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a109 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a110 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a111 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a112 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a113 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a114 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a115 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a116 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a117 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a118 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a119 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a120 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a121 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a122 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a123 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a124 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a125 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a126 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a127 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a128 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a129 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a130 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a131 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a132 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a133 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a134 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a135 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a136 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a137 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a138 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a139 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a140 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a141 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a142 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a143 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a144 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a145 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a146 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a147 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a148 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a149 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a150 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a151 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a152 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a153 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a154 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a155 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a156 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a157 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a158 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a159 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a160 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a161 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a162 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a163 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a164 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a165 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a166 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a167 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a168 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a169 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a170 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a171 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a172 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a173 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a174 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a175 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a176 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a177 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a178 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a179 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a180 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a181 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a182 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a183 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a184 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a185 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a186 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a187 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a188 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a189 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a190 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a191 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a192 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a193 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a194 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a195 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a196 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a197 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a198 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a199 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a200 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a201 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a202 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a203 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a204 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a205 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a206 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a207 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a208 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a209 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a210 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a211 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a212 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a213 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a214 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a215 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a216 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a217 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a218 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a219 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a220 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a221 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a222 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a223 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_sel[2..0] : WIRE; - address_a_wire[15..0] : WIRE; - -BEGIN - address_reg_a[].clk = clock0; - address_reg_a[].d = address_a_sel[]; - address_reg_a[].ena = clocken0; - decode3.data[2..0] = address_a_wire[15..13]; - decode3.enable = wren_a; - mux2.data[] = ( ram_block1a[223..0].portadataout[0..0]); - mux2.sel[] = address_reg_a[].q; - ram_block1a[223..0].clk0 = clock0; - ram_block1a[223..0].ena0 = clocken0; - ram_block1a[191..0].portaaddr[] = ( address_a_wire[12..0]); - ram_block1a[223..192].portaaddr[] = ( address_a_wire[10..0]); - ram_block1a[7..0].portabyteenamasks[] = ( byteena_a[0..0]); - ram_block1a[15..8].portabyteenamasks[] = ( byteena_a[1..1]); - ram_block1a[23..16].portabyteenamasks[] = ( byteena_a[2..2]); - ram_block1a[31..24].portabyteenamasks[] = ( byteena_a[3..3]); - ram_block1a[39..32].portabyteenamasks[] = ( byteena_a[0..0]); - ram_block1a[47..40].portabyteenamasks[] = ( byteena_a[1..1]); - ram_block1a[55..48].portabyteenamasks[] = ( byteena_a[2..2]); - ram_block1a[63..56].portabyteenamasks[] = ( byteena_a[3..3]); - ram_block1a[71..64].portabyteenamasks[] = ( byteena_a[0..0]); - ram_block1a[79..72].portabyteenamasks[] = ( byteena_a[1..1]); - ram_block1a[87..80].portabyteenamasks[] = ( byteena_a[2..2]); - ram_block1a[95..88].portabyteenamasks[] = ( byteena_a[3..3]); - ram_block1a[103..96].portabyteenamasks[] = ( byteena_a[0..0]); - ram_block1a[111..104].portabyteenamasks[] = ( byteena_a[1..1]); - ram_block1a[119..112].portabyteenamasks[] = ( byteena_a[2..2]); - ram_block1a[127..120].portabyteenamasks[] = ( byteena_a[3..3]); - ram_block1a[135..128].portabyteenamasks[] = ( byteena_a[0..0]); - ram_block1a[143..136].portabyteenamasks[] = ( byteena_a[1..1]); - ram_block1a[151..144].portabyteenamasks[] = ( byteena_a[2..2]); - ram_block1a[159..152].portabyteenamasks[] = ( byteena_a[3..3]); - ram_block1a[167..160].portabyteenamasks[] = ( byteena_a[0..0]); - ram_block1a[175..168].portabyteenamasks[] = ( byteena_a[1..1]); - ram_block1a[183..176].portabyteenamasks[] = ( byteena_a[2..2]); - ram_block1a[191..184].portabyteenamasks[] = ( byteena_a[3..3]); - ram_block1a[199..192].portabyteenamasks[] = ( byteena_a[0..0]); - ram_block1a[207..200].portabyteenamasks[] = ( byteena_a[1..1]); - ram_block1a[215..208].portabyteenamasks[] = ( byteena_a[2..2]); - ram_block1a[223..216].portabyteenamasks[] = ( byteena_a[3..3]); - ram_block1a[0].portadatain[] = ( data_a[0..0]); - ram_block1a[1].portadatain[] = ( data_a[1..1]); - ram_block1a[2].portadatain[] = ( data_a[2..2]); - ram_block1a[3].portadatain[] = ( data_a[3..3]); - ram_block1a[4].portadatain[] = ( data_a[4..4]); - ram_block1a[5].portadatain[] = ( data_a[5..5]); - ram_block1a[6].portadatain[] = ( data_a[6..6]); - ram_block1a[7].portadatain[] = ( data_a[7..7]); - ram_block1a[8].portadatain[] = ( data_a[8..8]); - ram_block1a[9].portadatain[] = ( data_a[9..9]); - ram_block1a[10].portadatain[] = ( data_a[10..10]); - ram_block1a[11].portadatain[] = ( data_a[11..11]); - ram_block1a[12].portadatain[] = ( data_a[12..12]); - ram_block1a[13].portadatain[] = ( data_a[13..13]); - ram_block1a[14].portadatain[] = ( data_a[14..14]); - ram_block1a[15].portadatain[] = ( data_a[15..15]); - ram_block1a[16].portadatain[] = ( data_a[16..16]); - ram_block1a[17].portadatain[] = ( data_a[17..17]); - ram_block1a[18].portadatain[] = ( data_a[18..18]); - ram_block1a[19].portadatain[] = ( data_a[19..19]); - ram_block1a[20].portadatain[] = ( data_a[20..20]); - ram_block1a[21].portadatain[] = ( data_a[21..21]); - ram_block1a[22].portadatain[] = ( data_a[22..22]); - ram_block1a[23].portadatain[] = ( data_a[23..23]); - ram_block1a[24].portadatain[] = ( data_a[24..24]); - ram_block1a[25].portadatain[] = ( data_a[25..25]); - ram_block1a[26].portadatain[] = ( data_a[26..26]); - ram_block1a[27].portadatain[] = ( data_a[27..27]); - ram_block1a[28].portadatain[] = ( data_a[28..28]); - ram_block1a[29].portadatain[] = ( data_a[29..29]); - ram_block1a[30].portadatain[] = ( data_a[30..30]); - ram_block1a[31].portadatain[] = ( data_a[31..31]); - ram_block1a[32].portadatain[] = ( data_a[0..0]); - ram_block1a[33].portadatain[] = ( data_a[1..1]); - ram_block1a[34].portadatain[] = ( data_a[2..2]); - ram_block1a[35].portadatain[] = ( data_a[3..3]); - ram_block1a[36].portadatain[] = ( data_a[4..4]); - ram_block1a[37].portadatain[] = ( data_a[5..5]); - ram_block1a[38].portadatain[] = ( data_a[6..6]); - ram_block1a[39].portadatain[] = ( data_a[7..7]); - ram_block1a[40].portadatain[] = ( data_a[8..8]); - ram_block1a[41].portadatain[] = ( data_a[9..9]); - ram_block1a[42].portadatain[] = ( data_a[10..10]); - ram_block1a[43].portadatain[] = ( data_a[11..11]); - ram_block1a[44].portadatain[] = ( data_a[12..12]); - ram_block1a[45].portadatain[] = ( data_a[13..13]); - ram_block1a[46].portadatain[] = ( data_a[14..14]); - ram_block1a[47].portadatain[] = ( data_a[15..15]); - ram_block1a[48].portadatain[] = ( data_a[16..16]); - ram_block1a[49].portadatain[] = ( data_a[17..17]); - ram_block1a[50].portadatain[] = ( data_a[18..18]); - ram_block1a[51].portadatain[] = ( data_a[19..19]); - ram_block1a[52].portadatain[] = ( data_a[20..20]); - ram_block1a[53].portadatain[] = ( data_a[21..21]); - ram_block1a[54].portadatain[] = ( data_a[22..22]); - ram_block1a[55].portadatain[] = ( data_a[23..23]); - ram_block1a[56].portadatain[] = ( data_a[24..24]); - ram_block1a[57].portadatain[] = ( data_a[25..25]); - ram_block1a[58].portadatain[] = ( data_a[26..26]); - ram_block1a[59].portadatain[] = ( data_a[27..27]); - ram_block1a[60].portadatain[] = ( data_a[28..28]); - ram_block1a[61].portadatain[] = ( data_a[29..29]); - ram_block1a[62].portadatain[] = ( data_a[30..30]); - ram_block1a[63].portadatain[] = ( data_a[31..31]); - ram_block1a[64].portadatain[] = ( data_a[0..0]); - ram_block1a[65].portadatain[] = ( data_a[1..1]); - ram_block1a[66].portadatain[] = ( data_a[2..2]); - ram_block1a[67].portadatain[] = ( data_a[3..3]); - ram_block1a[68].portadatain[] = ( data_a[4..4]); - ram_block1a[69].portadatain[] = ( data_a[5..5]); - ram_block1a[70].portadatain[] = ( data_a[6..6]); - ram_block1a[71].portadatain[] = ( data_a[7..7]); - ram_block1a[72].portadatain[] = ( data_a[8..8]); - ram_block1a[73].portadatain[] = ( data_a[9..9]); - ram_block1a[74].portadatain[] = ( data_a[10..10]); - ram_block1a[75].portadatain[] = ( data_a[11..11]); - ram_block1a[76].portadatain[] = ( data_a[12..12]); - ram_block1a[77].portadatain[] = ( data_a[13..13]); - ram_block1a[78].portadatain[] = ( data_a[14..14]); - ram_block1a[79].portadatain[] = ( data_a[15..15]); - ram_block1a[80].portadatain[] = ( data_a[16..16]); - ram_block1a[81].portadatain[] = ( data_a[17..17]); - ram_block1a[82].portadatain[] = ( data_a[18..18]); - ram_block1a[83].portadatain[] = ( data_a[19..19]); - ram_block1a[84].portadatain[] = ( data_a[20..20]); - ram_block1a[85].portadatain[] = ( data_a[21..21]); - ram_block1a[86].portadatain[] = ( data_a[22..22]); - ram_block1a[87].portadatain[] = ( data_a[23..23]); - ram_block1a[88].portadatain[] = ( data_a[24..24]); - ram_block1a[89].portadatain[] = ( data_a[25..25]); - ram_block1a[90].portadatain[] = ( data_a[26..26]); - ram_block1a[91].portadatain[] = ( data_a[27..27]); - ram_block1a[92].portadatain[] = ( data_a[28..28]); - ram_block1a[93].portadatain[] = ( data_a[29..29]); - ram_block1a[94].portadatain[] = ( data_a[30..30]); - ram_block1a[95].portadatain[] = ( data_a[31..31]); - ram_block1a[96].portadatain[] = ( data_a[0..0]); - ram_block1a[97].portadatain[] = ( data_a[1..1]); - ram_block1a[98].portadatain[] = ( data_a[2..2]); - ram_block1a[99].portadatain[] = ( data_a[3..3]); - ram_block1a[100].portadatain[] = ( data_a[4..4]); - ram_block1a[101].portadatain[] = ( data_a[5..5]); - ram_block1a[102].portadatain[] = ( data_a[6..6]); - ram_block1a[103].portadatain[] = ( data_a[7..7]); - ram_block1a[104].portadatain[] = ( data_a[8..8]); - ram_block1a[105].portadatain[] = ( data_a[9..9]); - ram_block1a[106].portadatain[] = ( data_a[10..10]); - ram_block1a[107].portadatain[] = ( data_a[11..11]); - ram_block1a[108].portadatain[] = ( data_a[12..12]); - ram_block1a[109].portadatain[] = ( data_a[13..13]); - ram_block1a[110].portadatain[] = ( data_a[14..14]); - ram_block1a[111].portadatain[] = ( data_a[15..15]); - ram_block1a[112].portadatain[] = ( data_a[16..16]); - ram_block1a[113].portadatain[] = ( data_a[17..17]); - ram_block1a[114].portadatain[] = ( data_a[18..18]); - ram_block1a[115].portadatain[] = ( data_a[19..19]); - ram_block1a[116].portadatain[] = ( data_a[20..20]); - ram_block1a[117].portadatain[] = ( data_a[21..21]); - ram_block1a[118].portadatain[] = ( data_a[22..22]); - ram_block1a[119].portadatain[] = ( data_a[23..23]); - ram_block1a[120].portadatain[] = ( data_a[24..24]); - ram_block1a[121].portadatain[] = ( data_a[25..25]); - ram_block1a[122].portadatain[] = ( data_a[26..26]); - ram_block1a[123].portadatain[] = ( data_a[27..27]); - ram_block1a[124].portadatain[] = ( data_a[28..28]); - ram_block1a[125].portadatain[] = ( data_a[29..29]); - ram_block1a[126].portadatain[] = ( data_a[30..30]); - ram_block1a[127].portadatain[] = ( data_a[31..31]); - ram_block1a[128].portadatain[] = ( data_a[0..0]); - ram_block1a[129].portadatain[] = ( data_a[1..1]); - ram_block1a[130].portadatain[] = ( data_a[2..2]); - ram_block1a[131].portadatain[] = ( data_a[3..3]); - ram_block1a[132].portadatain[] = ( data_a[4..4]); - ram_block1a[133].portadatain[] = ( data_a[5..5]); - ram_block1a[134].portadatain[] = ( data_a[6..6]); - ram_block1a[135].portadatain[] = ( data_a[7..7]); - ram_block1a[136].portadatain[] = ( data_a[8..8]); - ram_block1a[137].portadatain[] = ( data_a[9..9]); - ram_block1a[138].portadatain[] = ( data_a[10..10]); - ram_block1a[139].portadatain[] = ( data_a[11..11]); - ram_block1a[140].portadatain[] = ( data_a[12..12]); - ram_block1a[141].portadatain[] = ( data_a[13..13]); - ram_block1a[142].portadatain[] = ( data_a[14..14]); - ram_block1a[143].portadatain[] = ( data_a[15..15]); - ram_block1a[144].portadatain[] = ( data_a[16..16]); - ram_block1a[145].portadatain[] = ( data_a[17..17]); - ram_block1a[146].portadatain[] = ( data_a[18..18]); - ram_block1a[147].portadatain[] = ( data_a[19..19]); - ram_block1a[148].portadatain[] = ( data_a[20..20]); - ram_block1a[149].portadatain[] = ( data_a[21..21]); - ram_block1a[150].portadatain[] = ( data_a[22..22]); - ram_block1a[151].portadatain[] = ( data_a[23..23]); - ram_block1a[152].portadatain[] = ( data_a[24..24]); - ram_block1a[153].portadatain[] = ( data_a[25..25]); - ram_block1a[154].portadatain[] = ( data_a[26..26]); - ram_block1a[155].portadatain[] = ( data_a[27..27]); - ram_block1a[156].portadatain[] = ( data_a[28..28]); - ram_block1a[157].portadatain[] = ( data_a[29..29]); - ram_block1a[158].portadatain[] = ( data_a[30..30]); - ram_block1a[159].portadatain[] = ( data_a[31..31]); - ram_block1a[160].portadatain[] = ( data_a[0..0]); - ram_block1a[161].portadatain[] = ( data_a[1..1]); - ram_block1a[162].portadatain[] = ( data_a[2..2]); - ram_block1a[163].portadatain[] = ( data_a[3..3]); - ram_block1a[164].portadatain[] = ( data_a[4..4]); - ram_block1a[165].portadatain[] = ( data_a[5..5]); - ram_block1a[166].portadatain[] = ( data_a[6..6]); - ram_block1a[167].portadatain[] = ( data_a[7..7]); - ram_block1a[168].portadatain[] = ( data_a[8..8]); - ram_block1a[169].portadatain[] = ( data_a[9..9]); - ram_block1a[170].portadatain[] = ( data_a[10..10]); - ram_block1a[171].portadatain[] = ( data_a[11..11]); - ram_block1a[172].portadatain[] = ( data_a[12..12]); - ram_block1a[173].portadatain[] = ( data_a[13..13]); - ram_block1a[174].portadatain[] = ( data_a[14..14]); - ram_block1a[175].portadatain[] = ( data_a[15..15]); - ram_block1a[176].portadatain[] = ( data_a[16..16]); - ram_block1a[177].portadatain[] = ( data_a[17..17]); - ram_block1a[178].portadatain[] = ( data_a[18..18]); - ram_block1a[179].portadatain[] = ( data_a[19..19]); - ram_block1a[180].portadatain[] = ( data_a[20..20]); - ram_block1a[181].portadatain[] = ( data_a[21..21]); - ram_block1a[182].portadatain[] = ( data_a[22..22]); - ram_block1a[183].portadatain[] = ( data_a[23..23]); - ram_block1a[184].portadatain[] = ( data_a[24..24]); - ram_block1a[185].portadatain[] = ( data_a[25..25]); - ram_block1a[186].portadatain[] = ( data_a[26..26]); - ram_block1a[187].portadatain[] = ( data_a[27..27]); - ram_block1a[188].portadatain[] = ( data_a[28..28]); - ram_block1a[189].portadatain[] = ( data_a[29..29]); - ram_block1a[190].portadatain[] = ( data_a[30..30]); - ram_block1a[191].portadatain[] = ( data_a[31..31]); - ram_block1a[192].portadatain[] = ( data_a[0..0]); - ram_block1a[193].portadatain[] = ( data_a[1..1]); - ram_block1a[194].portadatain[] = ( data_a[2..2]); - ram_block1a[195].portadatain[] = ( data_a[3..3]); - ram_block1a[196].portadatain[] = ( data_a[4..4]); - ram_block1a[197].portadatain[] = ( data_a[5..5]); - ram_block1a[198].portadatain[] = ( data_a[6..6]); - ram_block1a[199].portadatain[] = ( data_a[7..7]); - ram_block1a[200].portadatain[] = ( data_a[8..8]); - ram_block1a[201].portadatain[] = ( data_a[9..9]); - ram_block1a[202].portadatain[] = ( data_a[10..10]); - ram_block1a[203].portadatain[] = ( data_a[11..11]); - ram_block1a[204].portadatain[] = ( data_a[12..12]); - ram_block1a[205].portadatain[] = ( data_a[13..13]); - ram_block1a[206].portadatain[] = ( data_a[14..14]); - ram_block1a[207].portadatain[] = ( data_a[15..15]); - ram_block1a[208].portadatain[] = ( data_a[16..16]); - ram_block1a[209].portadatain[] = ( data_a[17..17]); - ram_block1a[210].portadatain[] = ( data_a[18..18]); - ram_block1a[211].portadatain[] = ( data_a[19..19]); - ram_block1a[212].portadatain[] = ( data_a[20..20]); - ram_block1a[213].portadatain[] = ( data_a[21..21]); - ram_block1a[214].portadatain[] = ( data_a[22..22]); - ram_block1a[215].portadatain[] = ( data_a[23..23]); - ram_block1a[216].portadatain[] = ( data_a[24..24]); - ram_block1a[217].portadatain[] = ( data_a[25..25]); - ram_block1a[218].portadatain[] = ( data_a[26..26]); - ram_block1a[219].portadatain[] = ( data_a[27..27]); - ram_block1a[220].portadatain[] = ( data_a[28..28]); - ram_block1a[221].portadatain[] = ( data_a[29..29]); - ram_block1a[222].portadatain[] = ( data_a[30..30]); - ram_block1a[223].portadatain[] = ( data_a[31..31]); - ram_block1a[223..0].portare = B"11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111"; - ram_block1a[223..0].portawe = ( decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0]); - address_a_sel[2..0] = address_a[15..13]; - address_a_wire[] = address_a[]; - q_a[] = mux2.result[]; -END; ---VALID FILE diff --git a/db/altsyncram_mbd1.tdf b/db/altsyncram_mbd1.tdf deleted file mode 100644 index 638b810..0000000 --- a/db/altsyncram_mbd1.tdf +++ /dev/null @@ -1,821 +0,0 @@ ---altsyncram BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nios_system_onchip_memory.hex" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=4096 NUMWORDS_A=4096 OPERATION_MODE="SINGLE_PORT" OUTDATA_REG_A="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=12 address_a byteena_a clock0 clocken0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 16 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_mbd1 -( - address_a[11..0] : input; - byteena_a[3..0] : input; - clock0 : input; - clocken0 : input; - data_a[31..0] : input; - q_a[31..0] : output; - wren_a : input; -) -VARIABLE - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a12 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a13 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a14 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a15 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a16 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a17 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a18 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a19 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a20 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a21 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a22 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a23 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a24 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a25 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a26 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a27 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a28 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a29 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a30 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a31 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_wire[11..0] : WIRE; - -BEGIN - ram_block1a[31..0].clk0 = clock0; - ram_block1a[31..0].ena0 = clocken0; - ram_block1a[31..0].portaaddr[] = ( address_a_wire[11..0]); - ram_block1a[7..0].portabyteenamasks[] = ( byteena_a[0..0]); - ram_block1a[15..8].portabyteenamasks[] = ( byteena_a[1..1]); - ram_block1a[23..16].portabyteenamasks[] = ( byteena_a[2..2]); - ram_block1a[31..24].portabyteenamasks[] = ( byteena_a[3..3]); - ram_block1a[0].portadatain[] = ( data_a[0..0]); - ram_block1a[1].portadatain[] = ( data_a[1..1]); - ram_block1a[2].portadatain[] = ( data_a[2..2]); - ram_block1a[3].portadatain[] = ( data_a[3..3]); - ram_block1a[4].portadatain[] = ( data_a[4..4]); - ram_block1a[5].portadatain[] = ( data_a[5..5]); - ram_block1a[6].portadatain[] = ( data_a[6..6]); - ram_block1a[7].portadatain[] = ( data_a[7..7]); - ram_block1a[8].portadatain[] = ( data_a[8..8]); - ram_block1a[9].portadatain[] = ( data_a[9..9]); - ram_block1a[10].portadatain[] = ( data_a[10..10]); - ram_block1a[11].portadatain[] = ( data_a[11..11]); - ram_block1a[12].portadatain[] = ( data_a[12..12]); - ram_block1a[13].portadatain[] = ( data_a[13..13]); - ram_block1a[14].portadatain[] = ( data_a[14..14]); - ram_block1a[15].portadatain[] = ( data_a[15..15]); - ram_block1a[16].portadatain[] = ( data_a[16..16]); - ram_block1a[17].portadatain[] = ( data_a[17..17]); - ram_block1a[18].portadatain[] = ( data_a[18..18]); - ram_block1a[19].portadatain[] = ( data_a[19..19]); - ram_block1a[20].portadatain[] = ( data_a[20..20]); - ram_block1a[21].portadatain[] = ( data_a[21..21]); - ram_block1a[22].portadatain[] = ( data_a[22..22]); - ram_block1a[23].portadatain[] = ( data_a[23..23]); - ram_block1a[24].portadatain[] = ( data_a[24..24]); - ram_block1a[25].portadatain[] = ( data_a[25..25]); - ram_block1a[26].portadatain[] = ( data_a[26..26]); - ram_block1a[27].portadatain[] = ( data_a[27..27]); - ram_block1a[28].portadatain[] = ( data_a[28..28]); - ram_block1a[29].portadatain[] = ( data_a[29..29]); - ram_block1a[30].portadatain[] = ( data_a[30..30]); - ram_block1a[31].portadatain[] = ( data_a[31..31]); - ram_block1a[31..0].portare = B"11111111111111111111111111111111"; - ram_block1a[31..0].portawe = wren_a; - address_a_wire[] = address_a[]; - q_a[] = ( ram_block1a[31..0].portadataout[0..0]); -END; ---VALID FILE diff --git a/db/altsyncram_r1m1.tdf b/db/altsyncram_r1m1.tdf deleted file mode 100644 index 15e2d8b..0000000 --- a/db/altsyncram_r1m1.tdf +++ /dev/null @@ -1,303 +0,0 @@ ---altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=6 WIDTHAD_B=6 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 1 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_r1m1 -( - address_a[5..0] : input; - address_b[5..0] : input; - clock0 : input; - clock1 : input; - clocken1 : input; - data_a[7..0] : input; - q_b[7..0] : output; - wren_a : input; -) -VARIABLE - ram_block2a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "ena1", - CLK1_INPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 8, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 0, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 8, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block2a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "ena1", - CLK1_INPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 8, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 1, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 8, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block2a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "ena1", - CLK1_INPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 8, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 2, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 8, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block2a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "ena1", - CLK1_INPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 8, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 3, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 8, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block2a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "ena1", - CLK1_INPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 8, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 4, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 8, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block2a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "ena1", - CLK1_INPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 8, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 5, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 8, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block2a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "ena1", - CLK1_INPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 8, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 6, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 8, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block2a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "ena1", - CLK1_INPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 8, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 7, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 8, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_wire[5..0] : WIRE; - address_b_wire[5..0] : WIRE; - -BEGIN - ram_block2a[7..0].clk0 = clock0; - ram_block2a[7..0].clk1 = clock1; - ram_block2a[7..0].ena0 = wren_a; - ram_block2a[7..0].ena1 = clocken1; - ram_block2a[7..0].portaaddr[] = ( address_a_wire[5..0]); - ram_block2a[0].portadatain[] = ( data_a[0..0]); - ram_block2a[1].portadatain[] = ( data_a[1..1]); - ram_block2a[2].portadatain[] = ( data_a[2..2]); - ram_block2a[3].portadatain[] = ( data_a[3..3]); - ram_block2a[4].portadatain[] = ( data_a[4..4]); - ram_block2a[5].portadatain[] = ( data_a[5..5]); - ram_block2a[6].portadatain[] = ( data_a[6..6]); - ram_block2a[7].portadatain[] = ( data_a[7..7]); - ram_block2a[7..0].portawe = wren_a; - ram_block2a[7..0].portbaddr[] = ( address_b_wire[5..0]); - ram_block2a[7..0].portbre = B"11111111"; - address_a_wire[] = address_a[]; - address_b_wire[] = address_b[]; - q_b[] = ( ram_block2a[7..0].portbdataout[0..0]); -END; ---VALID FILE diff --git a/db/altsyncram_sad1.tdf b/db/altsyncram_sad1.tdf deleted file mode 100644 index 674477b..0000000 --- a/db/altsyncram_sad1.tdf +++ /dev/null @@ -1,821 +0,0 @@ ---altsyncram BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nios_system_onchip_memory.hex" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=1024 NUMWORDS_A=1024 OPERATION_MODE="SINGLE_PORT" OUTDATA_REG_A="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=10 address_a byteena_a clock0 clocken0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 4 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_sad1 -( - address_a[9..0] : input; - byteena_a[3..0] : input; - clock0 : input; - clocken0 : input; - data_a[31..0] : input; - q_a[31..0] : output; - wren_a : input; -) -VARIABLE - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a12 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a13 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a14 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a15 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a16 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a17 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a18 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a19 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a20 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a21 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a22 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a23 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a24 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a25 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a26 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a27 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a28 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a29 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a30 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a31 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_wire[9..0] : WIRE; - -BEGIN - ram_block1a[31..0].clk0 = clock0; - ram_block1a[31..0].ena0 = clocken0; - ram_block1a[31..0].portaaddr[] = ( address_a_wire[9..0]); - ram_block1a[7..0].portabyteenamasks[] = ( byteena_a[0..0]); - ram_block1a[15..8].portabyteenamasks[] = ( byteena_a[1..1]); - ram_block1a[23..16].portabyteenamasks[] = ( byteena_a[2..2]); - ram_block1a[31..24].portabyteenamasks[] = ( byteena_a[3..3]); - ram_block1a[0].portadatain[] = ( data_a[0..0]); - ram_block1a[1].portadatain[] = ( data_a[1..1]); - ram_block1a[2].portadatain[] = ( data_a[2..2]); - ram_block1a[3].portadatain[] = ( data_a[3..3]); - ram_block1a[4].portadatain[] = ( data_a[4..4]); - ram_block1a[5].portadatain[] = ( data_a[5..5]); - ram_block1a[6].portadatain[] = ( data_a[6..6]); - ram_block1a[7].portadatain[] = ( data_a[7..7]); - ram_block1a[8].portadatain[] = ( data_a[8..8]); - ram_block1a[9].portadatain[] = ( data_a[9..9]); - ram_block1a[10].portadatain[] = ( data_a[10..10]); - ram_block1a[11].portadatain[] = ( data_a[11..11]); - ram_block1a[12].portadatain[] = ( data_a[12..12]); - ram_block1a[13].portadatain[] = ( data_a[13..13]); - ram_block1a[14].portadatain[] = ( data_a[14..14]); - ram_block1a[15].portadatain[] = ( data_a[15..15]); - ram_block1a[16].portadatain[] = ( data_a[16..16]); - ram_block1a[17].portadatain[] = ( data_a[17..17]); - ram_block1a[18].portadatain[] = ( data_a[18..18]); - ram_block1a[19].portadatain[] = ( data_a[19..19]); - ram_block1a[20].portadatain[] = ( data_a[20..20]); - ram_block1a[21].portadatain[] = ( data_a[21..21]); - ram_block1a[22].portadatain[] = ( data_a[22..22]); - ram_block1a[23].portadatain[] = ( data_a[23..23]); - ram_block1a[24].portadatain[] = ( data_a[24..24]); - ram_block1a[25].portadatain[] = ( data_a[25..25]); - ram_block1a[26].portadatain[] = ( data_a[26..26]); - ram_block1a[27].portadatain[] = ( data_a[27..27]); - ram_block1a[28].portadatain[] = ( data_a[28..28]); - ram_block1a[29].portadatain[] = ( data_a[29..29]); - ram_block1a[30].portadatain[] = ( data_a[30..30]); - ram_block1a[31].portadatain[] = ( data_a[31..31]); - ram_block1a[31..0].portare = B"11111111111111111111111111111111"; - ram_block1a[31..0].portawe = wren_a; - address_a_wire[] = address_a[]; - q_a[] = ( ram_block1a[31..0].portadataout[0..0]); -END; ---VALID FILE diff --git a/db/cntr_1ob.tdf b/db/cntr_1ob.tdf deleted file mode 100644 index f20e091..0000000 --- a/db/cntr_1ob.tdf +++ /dev/null @@ -1,97 +0,0 @@ ---lpm_counter DEVICE_FAMILY="Cyclone IV E" lpm_direction="UP" lpm_port_updown="PORT_UNUSED" lpm_width=6 aclr clock cnt_en q sclr ---VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) -WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) -RETURNS ( combout, cout); - ---synthesis_resources = lut 6 reg 6 -SUBDESIGN cntr_1ob -( - aclr : input; - clock : input; - cnt_en : input; - q[5..0] : output; - sclr : input; -) -VARIABLE - counter_comb_bita0 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita1 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita2 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita3 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita4 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita5 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_reg_bit[5..0] : dffeas; - aclr_actual : WIRE; - clk_en : NODE; - data[5..0] : NODE; - external_cin : WIRE; - s_val[5..0] : WIRE; - safe_q[5..0] : WIRE; - sload : NODE; - sset : NODE; - updown_dir : WIRE; - -BEGIN - counter_comb_bita[5..0].cin = ( counter_comb_bita[4..0].cout, external_cin); - counter_comb_bita[5..0].dataa = ( counter_reg_bit[5..0].q); - counter_comb_bita[5..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir); - counter_comb_bita[5..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1"); - counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); - counter_reg_bit[].clk = clock; - counter_reg_bit[].clrn = (! aclr_actual); - counter_reg_bit[].d = ( counter_comb_bita[5..0].combout); - counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); - counter_reg_bit[].sload = ((sclr # sset) # sload); - aclr_actual = aclr; - clk_en = VCC; - data[] = GND; - external_cin = B"1"; - q[] = safe_q[]; - s_val[] = B"111111"; - safe_q[] = counter_reg_bit[].q; - sload = GND; - sset = GND; - updown_dir = B"1"; -END; ---VALID FILE diff --git a/db/cntr_do7.tdf b/db/cntr_do7.tdf deleted file mode 100644 index cf34edf..0000000 --- a/db/cntr_do7.tdf +++ /dev/null @@ -1,98 +0,0 @@ ---lpm_counter DEVICE_FAMILY="Cyclone IV E" lpm_width=6 aclr clock cnt_en q sclr updown ---VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) -WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) -RETURNS ( combout, cout); - ---synthesis_resources = lut 6 reg 6 -SUBDESIGN cntr_do7 -( - aclr : input; - clock : input; - cnt_en : input; - q[5..0] : output; - sclr : input; - updown : input; -) -VARIABLE - counter_comb_bita0 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita1 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita2 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita3 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita4 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita5 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_reg_bit[5..0] : dffeas; - aclr_actual : WIRE; - clk_en : NODE; - data[5..0] : NODE; - external_cin : WIRE; - s_val[5..0] : WIRE; - safe_q[5..0] : WIRE; - sload : NODE; - sset : NODE; - updown_dir : WIRE; - -BEGIN - counter_comb_bita[5..0].cin = ( counter_comb_bita[4..0].cout, external_cin); - counter_comb_bita[5..0].dataa = ( counter_reg_bit[5..0].q); - counter_comb_bita[5..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir); - counter_comb_bita[5..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1"); - counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); - counter_reg_bit[].clk = clock; - counter_reg_bit[].clrn = (! aclr_actual); - counter_reg_bit[].d = ( counter_comb_bita[5..0].combout); - counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); - counter_reg_bit[].sload = ((sclr # sset) # sload); - aclr_actual = aclr; - clk_en = VCC; - data[] = GND; - external_cin = B"1"; - q[] = safe_q[]; - s_val[] = B"111111"; - safe_q[] = counter_reg_bit[].q; - sload = GND; - sset = GND; - updown_dir = updown; -END; ---VALID FILE diff --git a/db/decode_qsa.tdf b/db/decode_qsa.tdf deleted file mode 100644 index 78baf29..0000000 --- a/db/decode_qsa.tdf +++ /dev/null @@ -1,57 +0,0 @@ ---lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_DECODES=7 LPM_WIDTH=3 data enable eq ---VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - - ---synthesis_resources = lut 8 -SUBDESIGN decode_qsa -( - data[2..0] : input; - enable : input; - eq[6..0] : output; -) -VARIABLE - data_wire[2..0] : WIRE; - enable_wire : WIRE; - eq_node[6..0] : WIRE; - eq_wire[7..0] : WIRE; - w_anode1849w[3..0] : WIRE; - w_anode1866w[3..0] : WIRE; - w_anode1876w[3..0] : WIRE; - w_anode1886w[3..0] : WIRE; - w_anode1896w[3..0] : WIRE; - w_anode1906w[3..0] : WIRE; - w_anode1916w[3..0] : WIRE; - w_anode1926w[3..0] : WIRE; - -BEGIN - data_wire[] = data[]; - enable_wire = enable; - eq[] = eq_node[]; - eq_node[6..0] = eq_wire[6..0]; - eq_wire[] = ( w_anode1926w[3..3], w_anode1916w[3..3], w_anode1906w[3..3], w_anode1896w[3..3], w_anode1886w[3..3], w_anode1876w[3..3], w_anode1866w[3..3], w_anode1849w[3..3]); - w_anode1849w[] = ( (w_anode1849w[2..2] & (! data_wire[2..2])), (w_anode1849w[1..1] & (! data_wire[1..1])), (w_anode1849w[0..0] & (! data_wire[0..0])), enable_wire); - w_anode1866w[] = ( (w_anode1866w[2..2] & (! data_wire[2..2])), (w_anode1866w[1..1] & (! data_wire[1..1])), (w_anode1866w[0..0] & data_wire[0..0]), enable_wire); - w_anode1876w[] = ( (w_anode1876w[2..2] & (! data_wire[2..2])), (w_anode1876w[1..1] & data_wire[1..1]), (w_anode1876w[0..0] & (! data_wire[0..0])), enable_wire); - w_anode1886w[] = ( (w_anode1886w[2..2] & (! data_wire[2..2])), (w_anode1886w[1..1] & data_wire[1..1]), (w_anode1886w[0..0] & data_wire[0..0]), enable_wire); - w_anode1896w[] = ( (w_anode1896w[2..2] & data_wire[2..2]), (w_anode1896w[1..1] & (! data_wire[1..1])), (w_anode1896w[0..0] & (! data_wire[0..0])), enable_wire); - w_anode1906w[] = ( (w_anode1906w[2..2] & data_wire[2..2]), (w_anode1906w[1..1] & (! data_wire[1..1])), (w_anode1906w[0..0] & data_wire[0..0]), enable_wire); - w_anode1916w[] = ( (w_anode1916w[2..2] & data_wire[2..2]), (w_anode1916w[1..1] & data_wire[1..1]), (w_anode1916w[0..0] & (! data_wire[0..0])), enable_wire); - w_anode1926w[] = ( (w_anode1926w[2..2] & data_wire[2..2]), (w_anode1926w[1..1] & data_wire[1..1]), (w_anode1926w[0..0] & data_wire[0..0]), enable_wire); -END; ---VALID FILE diff --git a/db/dpram_nl21.tdf b/db/dpram_nl21.tdf deleted file mode 100644 index ed4cc69..0000000 --- a/db/dpram_nl21.tdf +++ /dev/null @@ -1,48 +0,0 @@ ---altdpram DEVICE_FAMILY="Cyclone IV E" lpm_hint="RAM_BLOCK_TYPE=AUTO" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR="OFF" RDCONTROL_REG="UNREGISTERED" SUPPRESS_MEMORY_CONVERSION_WARNINGS="ON" USE_EAB="ON" WIDTH=8 WIDTHAD=6 data inclock outclock outclocken q rdaddress wraddress wren CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" ---VERSION_BEGIN 13.0 cbx_altdpram 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION altsyncram_r1m1 (address_a[5..0], address_b[5..0], clock0, clock1, clocken1, data_a[7..0], wren_a) -RETURNS ( q_b[7..0]); - ---synthesis_resources = M9K 1 -SUBDESIGN dpram_nl21 -( - data[7..0] : input; - inclock : input; - outclock : input; - outclocken : input; - q[7..0] : output; - rdaddress[5..0] : input; - wraddress[5..0] : input; - wren : input; -) -VARIABLE - altsyncram1 : altsyncram_r1m1; - -BEGIN - altsyncram1.address_a[] = wraddress[]; - altsyncram1.address_b[] = rdaddress[]; - altsyncram1.clock0 = inclock; - altsyncram1.clock1 = outclock; - altsyncram1.clocken1 = outclocken; - altsyncram1.data_a[] = data[]; - altsyncram1.wren_a = wren; - q[] = altsyncram1.q_b[]; -END; ---VALID FILE diff --git a/db/ip/nios_system/nios_system.v b/db/ip/nios_system/nios_system.v deleted file mode 100644 index 7cbf870..0000000 --- a/db/ip/nios_system/nios_system.v +++ /dev/null @@ -1,5964 +0,0 @@ -// nios_system.v - -// Generated using ACDS version 13.0sp1 232 at 2016.12.22.10:07:22 - -`timescale 1 ps / 1 ps -module nios_system ( - input wire clk_clk, // clk.clk - output wire [7:0] leds_export, // leds.export - input wire reset_reset_n, // reset.reset_n - output wire [17:0] ledrs_export, // ledrs.export - input wire [17:0] switches_export, // switches.export - input wire [2:0] push_switches_export, // push_switches.export - output wire [6:0] hex0_export, // hex0.export - output wire [6:0] hex1_export, // hex1.export - output wire [6:0] hex2_export, // hex2.export - output wire [6:0] hex3_export, // hex3.export - output wire [6:0] hex4_export, // hex4.export - output wire [6:0] hex5_export, // hex5.export - output wire [6:0] hex6_export, // hex6.export - output wire [6:0] hex7_export, // hex7.export - output wire lcd_16207_0_RS, // lcd_16207_0.RS - output wire lcd_16207_0_RW, // .RW - inout wire [7:0] lcd_16207_0_data, // .data - output wire lcd_16207_0_E, // .E - output wire lcd_on_export, // lcd_on.export - output wire lcd_blon_export // lcd_blon.export - ); - - wire nios2_processor_instruction_master_waitrequest; // nios2_processor_instruction_master_translator:av_waitrequest -> nios2_processor:i_waitrequest - wire [18:0] nios2_processor_instruction_master_address; // nios2_processor:i_address -> nios2_processor_instruction_master_translator:av_address - wire nios2_processor_instruction_master_read; // nios2_processor:i_read -> nios2_processor_instruction_master_translator:av_read - wire [31:0] nios2_processor_instruction_master_readdata; // nios2_processor_instruction_master_translator:av_readdata -> nios2_processor:i_readdata - wire nios2_processor_data_master_waitrequest; // nios2_processor_data_master_translator:av_waitrequest -> nios2_processor:d_waitrequest - wire [31:0] nios2_processor_data_master_writedata; // nios2_processor:d_writedata -> nios2_processor_data_master_translator:av_writedata - wire [18:0] nios2_processor_data_master_address; // nios2_processor:d_address -> nios2_processor_data_master_translator:av_address - wire nios2_processor_data_master_write; // nios2_processor:d_write -> nios2_processor_data_master_translator:av_write - wire nios2_processor_data_master_read; // nios2_processor:d_read -> nios2_processor_data_master_translator:av_read - wire [31:0] nios2_processor_data_master_readdata; // nios2_processor_data_master_translator:av_readdata -> nios2_processor:d_readdata - wire nios2_processor_data_master_debugaccess; // nios2_processor:jtag_debug_module_debugaccess_to_roms -> nios2_processor_data_master_translator:av_debugaccess - wire [3:0] nios2_processor_data_master_byteenable; // nios2_processor:d_byteenable -> nios2_processor_data_master_translator:av_byteenable - wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest; // nios2_processor:jtag_debug_module_waitrequest -> nios2_processor_jtag_debug_module_translator:av_waitrequest - wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_writedata; // nios2_processor_jtag_debug_module_translator:av_writedata -> nios2_processor:jtag_debug_module_writedata - wire [8:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_address; // nios2_processor_jtag_debug_module_translator:av_address -> nios2_processor:jtag_debug_module_address - wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_write; // nios2_processor_jtag_debug_module_translator:av_write -> nios2_processor:jtag_debug_module_write - wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_read; // nios2_processor_jtag_debug_module_translator:av_read -> nios2_processor:jtag_debug_module_read - wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_readdata; // nios2_processor:jtag_debug_module_readdata -> nios2_processor_jtag_debug_module_translator:av_readdata - wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess; // nios2_processor_jtag_debug_module_translator:av_debugaccess -> nios2_processor:jtag_debug_module_debugaccess - wire [3:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_byteenable; // nios2_processor_jtag_debug_module_translator:av_byteenable -> nios2_processor:jtag_debug_module_byteenable - wire [31:0] onchip_memory_s1_translator_avalon_anti_slave_0_writedata; // onchip_memory_s1_translator:av_writedata -> onchip_memory:writedata - wire [15:0] onchip_memory_s1_translator_avalon_anti_slave_0_address; // onchip_memory_s1_translator:av_address -> onchip_memory:address - wire onchip_memory_s1_translator_avalon_anti_slave_0_chipselect; // onchip_memory_s1_translator:av_chipselect -> onchip_memory:chipselect - wire onchip_memory_s1_translator_avalon_anti_slave_0_clken; // onchip_memory_s1_translator:av_clken -> onchip_memory:clken - wire onchip_memory_s1_translator_avalon_anti_slave_0_write; // onchip_memory_s1_translator:av_write -> onchip_memory:write - wire [31:0] onchip_memory_s1_translator_avalon_anti_slave_0_readdata; // onchip_memory:readdata -> onchip_memory_s1_translator:av_readdata - wire [3:0] onchip_memory_s1_translator_avalon_anti_slave_0_byteenable; // onchip_memory_s1_translator:av_byteenable -> onchip_memory:byteenable - wire [31:0] leds_s1_translator_avalon_anti_slave_0_writedata; // LEDs_s1_translator:av_writedata -> LEDs:writedata - wire [1:0] leds_s1_translator_avalon_anti_slave_0_address; // LEDs_s1_translator:av_address -> LEDs:address - wire leds_s1_translator_avalon_anti_slave_0_chipselect; // LEDs_s1_translator:av_chipselect -> LEDs:chipselect - wire leds_s1_translator_avalon_anti_slave_0_write; // LEDs_s1_translator:av_write -> LEDs:write_n - wire [31:0] leds_s1_translator_avalon_anti_slave_0_readdata; // LEDs:readdata -> LEDs_s1_translator:av_readdata - wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest; // jtag_uart:av_waitrequest -> jtag_uart_avalon_jtag_slave_translator:av_waitrequest - wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata; // jtag_uart_avalon_jtag_slave_translator:av_writedata -> jtag_uart:av_writedata - wire [0:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_address; // jtag_uart_avalon_jtag_slave_translator:av_address -> jtag_uart:av_address - wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect; // jtag_uart_avalon_jtag_slave_translator:av_chipselect -> jtag_uart:av_chipselect - wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_write; // jtag_uart_avalon_jtag_slave_translator:av_write -> jtag_uart:av_write_n - wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_read; // jtag_uart_avalon_jtag_slave_translator:av_read -> jtag_uart:av_read_n - wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata; // jtag_uart:av_readdata -> jtag_uart_avalon_jtag_slave_translator:av_readdata - wire [31:0] ledrs_s1_translator_avalon_anti_slave_0_writedata; // LEDRs_s1_translator:av_writedata -> LEDRs:writedata - wire [1:0] ledrs_s1_translator_avalon_anti_slave_0_address; // LEDRs_s1_translator:av_address -> LEDRs:address - wire ledrs_s1_translator_avalon_anti_slave_0_chipselect; // LEDRs_s1_translator:av_chipselect -> LEDRs:chipselect - wire ledrs_s1_translator_avalon_anti_slave_0_write; // LEDRs_s1_translator:av_write -> LEDRs:write_n - wire [31:0] ledrs_s1_translator_avalon_anti_slave_0_readdata; // LEDRs:readdata -> LEDRs_s1_translator:av_readdata - wire [1:0] switches_s1_translator_avalon_anti_slave_0_address; // switches_s1_translator:av_address -> switches:address - wire [31:0] switches_s1_translator_avalon_anti_slave_0_readdata; // switches:readdata -> switches_s1_translator:av_readdata - wire [1:0] push_switches_s1_translator_avalon_anti_slave_0_address; // push_switches_s1_translator:av_address -> push_switches:address - wire [31:0] push_switches_s1_translator_avalon_anti_slave_0_readdata; // push_switches:readdata -> push_switches_s1_translator:av_readdata - wire [31:0] hex0_s1_translator_avalon_anti_slave_0_writedata; // hex0_s1_translator:av_writedata -> hex0:writedata - wire [1:0] hex0_s1_translator_avalon_anti_slave_0_address; // hex0_s1_translator:av_address -> hex0:address - wire hex0_s1_translator_avalon_anti_slave_0_chipselect; // hex0_s1_translator:av_chipselect -> hex0:chipselect - wire hex0_s1_translator_avalon_anti_slave_0_write; // hex0_s1_translator:av_write -> hex0:write_n - wire [31:0] hex0_s1_translator_avalon_anti_slave_0_readdata; // hex0:readdata -> hex0_s1_translator:av_readdata - wire [31:0] hex1_s1_translator_avalon_anti_slave_0_writedata; // hex1_s1_translator:av_writedata -> hex1:writedata - wire [1:0] hex1_s1_translator_avalon_anti_slave_0_address; // hex1_s1_translator:av_address -> hex1:address - wire hex1_s1_translator_avalon_anti_slave_0_chipselect; // hex1_s1_translator:av_chipselect -> hex1:chipselect - wire hex1_s1_translator_avalon_anti_slave_0_write; // hex1_s1_translator:av_write -> hex1:write_n - wire [31:0] hex1_s1_translator_avalon_anti_slave_0_readdata; // hex1:readdata -> hex1_s1_translator:av_readdata - wire [31:0] hex2_s1_translator_avalon_anti_slave_0_writedata; // hex2_s1_translator:av_writedata -> hex2:writedata - wire [1:0] hex2_s1_translator_avalon_anti_slave_0_address; // hex2_s1_translator:av_address -> hex2:address - wire hex2_s1_translator_avalon_anti_slave_0_chipselect; // hex2_s1_translator:av_chipselect -> hex2:chipselect - wire hex2_s1_translator_avalon_anti_slave_0_write; // hex2_s1_translator:av_write -> hex2:write_n - wire [31:0] hex2_s1_translator_avalon_anti_slave_0_readdata; // hex2:readdata -> hex2_s1_translator:av_readdata - wire [31:0] hex3_s1_translator_avalon_anti_slave_0_writedata; // hex3_s1_translator:av_writedata -> hex3:writedata - wire [1:0] hex3_s1_translator_avalon_anti_slave_0_address; // hex3_s1_translator:av_address -> hex3:address - wire hex3_s1_translator_avalon_anti_slave_0_chipselect; // hex3_s1_translator:av_chipselect -> hex3:chipselect - wire hex3_s1_translator_avalon_anti_slave_0_write; // hex3_s1_translator:av_write -> hex3:write_n - wire [31:0] hex3_s1_translator_avalon_anti_slave_0_readdata; // hex3:readdata -> hex3_s1_translator:av_readdata - wire [31:0] hex4_s1_translator_avalon_anti_slave_0_writedata; // hex4_s1_translator:av_writedata -> hex4:writedata - wire [1:0] hex4_s1_translator_avalon_anti_slave_0_address; // hex4_s1_translator:av_address -> hex4:address - wire hex4_s1_translator_avalon_anti_slave_0_chipselect; // hex4_s1_translator:av_chipselect -> hex4:chipselect - wire hex4_s1_translator_avalon_anti_slave_0_write; // hex4_s1_translator:av_write -> hex4:write_n - wire [31:0] hex4_s1_translator_avalon_anti_slave_0_readdata; // hex4:readdata -> hex4_s1_translator:av_readdata - wire [31:0] hex5_s1_translator_avalon_anti_slave_0_writedata; // hex5_s1_translator:av_writedata -> hex5:writedata - wire [1:0] hex5_s1_translator_avalon_anti_slave_0_address; // hex5_s1_translator:av_address -> hex5:address - wire hex5_s1_translator_avalon_anti_slave_0_chipselect; // hex5_s1_translator:av_chipselect -> hex5:chipselect - wire hex5_s1_translator_avalon_anti_slave_0_write; // hex5_s1_translator:av_write -> hex5:write_n - wire [31:0] hex5_s1_translator_avalon_anti_slave_0_readdata; // hex5:readdata -> hex5_s1_translator:av_readdata - wire [31:0] hex6_s1_translator_avalon_anti_slave_0_writedata; // hex6_s1_translator:av_writedata -> hex6:writedata - wire [1:0] hex6_s1_translator_avalon_anti_slave_0_address; // hex6_s1_translator:av_address -> hex6:address - wire hex6_s1_translator_avalon_anti_slave_0_chipselect; // hex6_s1_translator:av_chipselect -> hex6:chipselect - wire hex6_s1_translator_avalon_anti_slave_0_write; // hex6_s1_translator:av_write -> hex6:write_n - wire [31:0] hex6_s1_translator_avalon_anti_slave_0_readdata; // hex6:readdata -> hex6_s1_translator:av_readdata - wire [31:0] hex7_s1_translator_avalon_anti_slave_0_writedata; // hex7_s1_translator:av_writedata -> hex7:writedata - wire [1:0] hex7_s1_translator_avalon_anti_slave_0_address; // hex7_s1_translator:av_address -> hex7:address - wire hex7_s1_translator_avalon_anti_slave_0_chipselect; // hex7_s1_translator:av_chipselect -> hex7:chipselect - wire hex7_s1_translator_avalon_anti_slave_0_write; // hex7_s1_translator:av_write -> hex7:write_n - wire [31:0] hex7_s1_translator_avalon_anti_slave_0_readdata; // hex7:readdata -> hex7_s1_translator:av_readdata - wire [7:0] lcd_16207_0_control_slave_translator_avalon_anti_slave_0_writedata; // lcd_16207_0_control_slave_translator:av_writedata -> lcd_16207_0:writedata - wire [1:0] lcd_16207_0_control_slave_translator_avalon_anti_slave_0_address; // lcd_16207_0_control_slave_translator:av_address -> lcd_16207_0:address - wire lcd_16207_0_control_slave_translator_avalon_anti_slave_0_write; // lcd_16207_0_control_slave_translator:av_write -> lcd_16207_0:write - wire lcd_16207_0_control_slave_translator_avalon_anti_slave_0_read; // lcd_16207_0_control_slave_translator:av_read -> lcd_16207_0:read - wire [7:0] lcd_16207_0_control_slave_translator_avalon_anti_slave_0_readdata; // lcd_16207_0:readdata -> lcd_16207_0_control_slave_translator:av_readdata - wire lcd_16207_0_control_slave_translator_avalon_anti_slave_0_begintransfer; // lcd_16207_0_control_slave_translator:av_begintransfer -> lcd_16207_0:begintransfer - wire [31:0] lcd_on_s1_translator_avalon_anti_slave_0_writedata; // lcd_on_s1_translator:av_writedata -> lcd_on:writedata - wire [1:0] lcd_on_s1_translator_avalon_anti_slave_0_address; // lcd_on_s1_translator:av_address -> lcd_on:address - wire lcd_on_s1_translator_avalon_anti_slave_0_chipselect; // lcd_on_s1_translator:av_chipselect -> lcd_on:chipselect - wire lcd_on_s1_translator_avalon_anti_slave_0_write; // lcd_on_s1_translator:av_write -> lcd_on:write_n - wire [31:0] lcd_on_s1_translator_avalon_anti_slave_0_readdata; // lcd_on:readdata -> lcd_on_s1_translator:av_readdata - wire [31:0] lcd_blon_s1_translator_avalon_anti_slave_0_writedata; // lcd_blon_s1_translator:av_writedata -> lcd_blon:writedata - wire [1:0] lcd_blon_s1_translator_avalon_anti_slave_0_address; // lcd_blon_s1_translator:av_address -> lcd_blon:address - wire lcd_blon_s1_translator_avalon_anti_slave_0_chipselect; // lcd_blon_s1_translator:av_chipselect -> lcd_blon:chipselect - wire lcd_blon_s1_translator_avalon_anti_slave_0_write; // lcd_blon_s1_translator:av_write -> lcd_blon:write_n - wire [31:0] lcd_blon_s1_translator_avalon_anti_slave_0_readdata; // lcd_blon:readdata -> lcd_blon_s1_translator:av_readdata - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_processor_instruction_master_translator:uav_waitrequest - wire [2:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_processor_instruction_master_translator:uav_burstcount -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount - wire [31:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_processor_instruction_master_translator:uav_writedata -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_writedata - wire [18:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_address; // nios2_processor_instruction_master_translator:uav_address -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_address - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_lock; // nios2_processor_instruction_master_translator:uav_lock -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_lock - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_write; // nios2_processor_instruction_master_translator:uav_write -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_write - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_read; // nios2_processor_instruction_master_translator:uav_read -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_read - wire [31:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_processor_instruction_master_translator:uav_readdata - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_processor_instruction_master_translator:uav_debugaccess -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess - wire [3:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_processor_instruction_master_translator:uav_byteenable -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_processor_instruction_master_translator:uav_readdatavalid - wire nios2_processor_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_processor_data_master_translator:uav_waitrequest - wire [2:0] nios2_processor_data_master_translator_avalon_universal_master_0_burstcount; // nios2_processor_data_master_translator:uav_burstcount -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_burstcount - wire [31:0] nios2_processor_data_master_translator_avalon_universal_master_0_writedata; // nios2_processor_data_master_translator:uav_writedata -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_writedata - wire [18:0] nios2_processor_data_master_translator_avalon_universal_master_0_address; // nios2_processor_data_master_translator:uav_address -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_address - wire nios2_processor_data_master_translator_avalon_universal_master_0_lock; // nios2_processor_data_master_translator:uav_lock -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_lock - wire nios2_processor_data_master_translator_avalon_universal_master_0_write; // nios2_processor_data_master_translator:uav_write -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_write - wire nios2_processor_data_master_translator_avalon_universal_master_0_read; // nios2_processor_data_master_translator:uav_read -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_read - wire [31:0] nios2_processor_data_master_translator_avalon_universal_master_0_readdata; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_processor_data_master_translator:uav_readdata - wire nios2_processor_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_processor_data_master_translator:uav_debugaccess -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_debugaccess - wire [3:0] nios2_processor_data_master_translator_avalon_universal_master_0_byteenable; // nios2_processor_data_master_translator:uav_byteenable -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_byteenable - wire nios2_processor_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_processor_data_master_translator:uav_readdatavalid - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest; // nios2_processor_jtag_debug_module_translator:uav_waitrequest -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> nios2_processor_jtag_debug_module_translator:uav_burstcount - wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> nios2_processor_jtag_debug_module_translator:uav_writedata - wire [18:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> nios2_processor_jtag_debug_module_translator:uav_address - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> nios2_processor_jtag_debug_module_translator:uav_write - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> nios2_processor_jtag_debug_module_translator:uav_lock - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> nios2_processor_jtag_debug_module_translator:uav_read - wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata; // nios2_processor_jtag_debug_module_translator:uav_readdata -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // nios2_processor_jtag_debug_module_translator:uav_readdatavalid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> nios2_processor_jtag_debug_module_translator:uav_debugaccess - wire [3:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> nios2_processor_jtag_debug_module_translator:uav_byteenable - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // onchip_memory_s1_translator:uav_waitrequest -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory_s1_translator:uav_burstcount - wire [31:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory_s1_translator:uav_writedata - wire [18:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory_s1_translator:uav_address - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory_s1_translator:uav_write - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory_s1_translator:uav_lock - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory_s1_translator:uav_read - wire [31:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // onchip_memory_s1_translator:uav_readdata -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // onchip_memory_s1_translator:uav_readdatavalid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory_s1_translator:uav_debugaccess - wire [3:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory_s1_translator:uav_byteenable - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // LEDs_s1_translator:uav_waitrequest -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> LEDs_s1_translator:uav_burstcount - wire [31:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> LEDs_s1_translator:uav_writedata - wire [18:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_address; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_address -> LEDs_s1_translator:uav_address - wire leds_s1_translator_avalon_universal_slave_0_agent_m0_write; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_write -> LEDs_s1_translator:uav_write - wire leds_s1_translator_avalon_universal_slave_0_agent_m0_lock; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_lock -> LEDs_s1_translator:uav_lock - wire leds_s1_translator_avalon_universal_slave_0_agent_m0_read; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_read -> LEDs_s1_translator:uav_read - wire [31:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // LEDs_s1_translator:uav_readdata -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // LEDs_s1_translator:uav_readdatavalid -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> LEDs_s1_translator:uav_debugaccess - wire [3:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> LEDs_s1_translator:uav_byteenable - wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount - wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata - wire [18:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read - wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess - wire [3:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // LEDRs_s1_translator:uav_waitrequest -> LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> LEDRs_s1_translator:uav_burstcount - wire [31:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> LEDRs_s1_translator:uav_writedata - wire [18:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_address; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_address -> LEDRs_s1_translator:uav_address - wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_write; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_write -> LEDRs_s1_translator:uav_write - wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_lock; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_lock -> LEDRs_s1_translator:uav_lock - wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_read; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_read -> LEDRs_s1_translator:uav_read - wire [31:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // LEDRs_s1_translator:uav_readdata -> LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // LEDRs_s1_translator:uav_readdatavalid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> LEDRs_s1_translator:uav_debugaccess - wire [3:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> LEDRs_s1_translator:uav_byteenable - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // switches_s1_translator:uav_waitrequest -> switches_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // switches_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> switches_s1_translator:uav_burstcount - wire [31:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // switches_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> switches_s1_translator:uav_writedata - wire [18:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_address; // switches_s1_translator_avalon_universal_slave_0_agent:m0_address -> switches_s1_translator:uav_address - wire switches_s1_translator_avalon_universal_slave_0_agent_m0_write; // switches_s1_translator_avalon_universal_slave_0_agent:m0_write -> switches_s1_translator:uav_write - wire switches_s1_translator_avalon_universal_slave_0_agent_m0_lock; // switches_s1_translator_avalon_universal_slave_0_agent:m0_lock -> switches_s1_translator:uav_lock - wire switches_s1_translator_avalon_universal_slave_0_agent_m0_read; // switches_s1_translator_avalon_universal_slave_0_agent:m0_read -> switches_s1_translator:uav_read - wire [31:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // switches_s1_translator:uav_readdata -> switches_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // switches_s1_translator:uav_readdatavalid -> switches_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // switches_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> switches_s1_translator:uav_debugaccess - wire [3:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // switches_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> switches_s1_translator:uav_byteenable - wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // push_switches_s1_translator:uav_waitrequest -> push_switches_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> push_switches_s1_translator:uav_burstcount - wire [31:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> push_switches_s1_translator:uav_writedata - wire [18:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_address; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_address -> push_switches_s1_translator:uav_address - wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_write; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_write -> push_switches_s1_translator:uav_write - wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_lock; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_lock -> push_switches_s1_translator:uav_lock - wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_read; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_read -> push_switches_s1_translator:uav_read - wire [31:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // push_switches_s1_translator:uav_readdata -> push_switches_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // push_switches_s1_translator:uav_readdatavalid -> push_switches_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> push_switches_s1_translator:uav_debugaccess - wire [3:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> push_switches_s1_translator:uav_byteenable - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex0_s1_translator:uav_waitrequest -> hex0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex0_s1_translator:uav_burstcount - wire [31:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex0_s1_translator:uav_writedata - wire [18:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex0_s1_translator:uav_address - wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex0_s1_translator:uav_write - wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex0_s1_translator:uav_lock - wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex0_s1_translator:uav_read - wire [31:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex0_s1_translator:uav_readdata -> hex0_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex0_s1_translator:uav_readdatavalid -> hex0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex0_s1_translator:uav_debugaccess - wire [3:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex0_s1_translator:uav_byteenable - wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex1_s1_translator:uav_waitrequest -> hex1_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex1_s1_translator:uav_burstcount - wire [31:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex1_s1_translator:uav_writedata - wire [18:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex1_s1_translator:uav_address - wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex1_s1_translator:uav_write - wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex1_s1_translator:uav_lock - wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex1_s1_translator:uav_read - wire [31:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex1_s1_translator:uav_readdata -> hex1_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex1_s1_translator:uav_readdatavalid -> hex1_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex1_s1_translator:uav_debugaccess - wire [3:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex1_s1_translator:uav_byteenable - wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex2_s1_translator:uav_waitrequest -> hex2_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex2_s1_translator:uav_burstcount - wire [31:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex2_s1_translator:uav_writedata - wire [18:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex2_s1_translator:uav_address - wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex2_s1_translator:uav_write - wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex2_s1_translator:uav_lock - wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex2_s1_translator:uav_read - wire [31:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex2_s1_translator:uav_readdata -> hex2_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex2_s1_translator:uav_readdatavalid -> hex2_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex2_s1_translator:uav_debugaccess - wire [3:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex2_s1_translator:uav_byteenable - wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex3_s1_translator:uav_waitrequest -> hex3_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex3_s1_translator:uav_burstcount - wire [31:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex3_s1_translator:uav_writedata - wire [18:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex3_s1_translator:uav_address - wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex3_s1_translator:uav_write - wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex3_s1_translator:uav_lock - wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex3_s1_translator:uav_read - wire [31:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex3_s1_translator:uav_readdata -> hex3_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex3_s1_translator:uav_readdatavalid -> hex3_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex3_s1_translator:uav_debugaccess - wire [3:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex3_s1_translator:uav_byteenable - wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex4_s1_translator:uav_waitrequest -> hex4_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex4_s1_translator:uav_burstcount - wire [31:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex4_s1_translator:uav_writedata - wire [18:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex4_s1_translator:uav_address - wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex4_s1_translator:uav_write - wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex4_s1_translator:uav_lock - wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex4_s1_translator:uav_read - wire [31:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex4_s1_translator:uav_readdata -> hex4_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex4_s1_translator:uav_readdatavalid -> hex4_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex4_s1_translator:uav_debugaccess - wire [3:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex4_s1_translator:uav_byteenable - wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex5_s1_translator:uav_waitrequest -> hex5_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex5_s1_translator:uav_burstcount - wire [31:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex5_s1_translator:uav_writedata - wire [18:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex5_s1_translator:uav_address - wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex5_s1_translator:uav_write - wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex5_s1_translator:uav_lock - wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex5_s1_translator:uav_read - wire [31:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex5_s1_translator:uav_readdata -> hex5_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex5_s1_translator:uav_readdatavalid -> hex5_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex5_s1_translator:uav_debugaccess - wire [3:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex5_s1_translator:uav_byteenable - wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex6_s1_translator:uav_waitrequest -> hex6_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex6_s1_translator:uav_burstcount - wire [31:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex6_s1_translator:uav_writedata - wire [18:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex6_s1_translator:uav_address - wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex6_s1_translator:uav_write - wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex6_s1_translator:uav_lock - wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex6_s1_translator:uav_read - wire [31:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex6_s1_translator:uav_readdata -> hex6_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex6_s1_translator:uav_readdatavalid -> hex6_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex6_s1_translator:uav_debugaccess - wire [3:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex6_s1_translator:uav_byteenable - wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex7_s1_translator:uav_waitrequest -> hex7_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex7_s1_translator:uav_burstcount - wire [31:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex7_s1_translator:uav_writedata - wire [18:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex7_s1_translator:uav_address - wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex7_s1_translator:uav_write - wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex7_s1_translator:uav_lock - wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex7_s1_translator:uav_read - wire [31:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex7_s1_translator:uav_readdata -> hex7_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex7_s1_translator:uav_readdatavalid -> hex7_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex7_s1_translator:uav_debugaccess - wire [3:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex7_s1_translator:uav_byteenable - wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lcd_16207_0_control_slave_translator:uav_waitrequest -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> lcd_16207_0_control_slave_translator:uav_burstcount - wire [31:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> lcd_16207_0_control_slave_translator:uav_writedata - wire [18:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> lcd_16207_0_control_slave_translator:uav_address - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> lcd_16207_0_control_slave_translator:uav_write - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> lcd_16207_0_control_slave_translator:uav_lock - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> lcd_16207_0_control_slave_translator:uav_read - wire [31:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // lcd_16207_0_control_slave_translator:uav_readdata -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lcd_16207_0_control_slave_translator:uav_readdatavalid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lcd_16207_0_control_slave_translator:uav_debugaccess - wire [3:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> lcd_16207_0_control_slave_translator:uav_byteenable - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lcd_on_s1_translator:uav_waitrequest -> lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> lcd_on_s1_translator:uav_burstcount - wire [31:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> lcd_on_s1_translator:uav_writedata - wire [18:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_address; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_address -> lcd_on_s1_translator:uav_address - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_write; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_write -> lcd_on_s1_translator:uav_write - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_lock; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_lock -> lcd_on_s1_translator:uav_lock - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_read; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_read -> lcd_on_s1_translator:uav_read - wire [31:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // lcd_on_s1_translator:uav_readdata -> lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lcd_on_s1_translator:uav_readdatavalid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lcd_on_s1_translator:uav_debugaccess - wire [3:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> lcd_on_s1_translator:uav_byteenable - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lcd_blon_s1_translator:uav_waitrequest -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> lcd_blon_s1_translator:uav_burstcount - wire [31:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> lcd_blon_s1_translator:uav_writedata - wire [18:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_address; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_address -> lcd_blon_s1_translator:uav_address - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_write; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_write -> lcd_blon_s1_translator:uav_write - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_lock; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_lock -> lcd_blon_s1_translator:uav_lock - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_read; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_read -> lcd_blon_s1_translator:uav_read - wire [31:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // lcd_blon_s1_translator:uav_readdata -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lcd_blon_s1_translator:uav_readdatavalid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lcd_blon_s1_translator:uav_debugaccess - wire [3:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> lcd_blon_s1_translator:uav_byteenable - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket - wire [95:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_ready - wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket - wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid - wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket - wire [95:0] nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data - wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_ready - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket - wire [95:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket - wire [95:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket - wire leds_s1_translator_avalon_universal_slave_0_agent_rp_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid - wire leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket - wire [95:0] leds_s1_translator_avalon_universal_slave_0_agent_rp_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data - wire leds_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket - wire [95:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket - wire [95:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rp_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket - wire switches_s1_translator_avalon_universal_slave_0_agent_rp_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid - wire switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket - wire [95:0] switches_s1_translator_avalon_universal_slave_0_agent_rp_data; // switches_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data - wire switches_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket - wire [95:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rp_data; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_006:sink_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket - wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid - wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket - wire [95:0] hex0_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data - wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_007:sink_ready -> hex0_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket - wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid - wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket - wire [95:0] hex1_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data - wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_008:sink_ready -> hex1_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_009:sink_endofpacket - wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_009:sink_valid - wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_009:sink_startofpacket - wire [95:0] hex2_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_009:sink_data - wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_009:sink_ready -> hex2_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_010:sink_endofpacket - wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_010:sink_valid - wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_010:sink_startofpacket - wire [95:0] hex3_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_010:sink_data - wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_010:sink_ready -> hex3_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_011:sink_endofpacket - wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_011:sink_valid - wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_011:sink_startofpacket - wire [95:0] hex4_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_011:sink_data - wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_011:sink_ready -> hex4_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_012:sink_endofpacket - wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_012:sink_valid - wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_012:sink_startofpacket - wire [95:0] hex5_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_012:sink_data - wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_012:sink_ready -> hex5_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_013:sink_endofpacket - wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_013:sink_valid - wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_013:sink_startofpacket - wire [95:0] hex6_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_013:sink_data - wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_013:sink_ready -> hex6_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_014:sink_endofpacket - wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_014:sink_valid - wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_014:sink_startofpacket - wire [95:0] hex7_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_014:sink_data - wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_014:sink_ready -> hex7_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_015:sink_endofpacket - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_015:sink_valid - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_015:sink_startofpacket - wire [95:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_015:sink_data - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_015:sink_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_ready - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_016:sink_endofpacket - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_016:sink_valid - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_016:sink_startofpacket - wire [95:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_016:sink_data - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_016:sink_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_017:sink_endofpacket - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_017:sink_valid - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_017:sink_startofpacket - wire [95:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_017:sink_data - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_017:sink_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [LEDRs:reset_n, LEDRs_s1_translator:reset, LEDRs_s1_translator_avalon_universal_slave_0_agent:reset, LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, LEDs:reset_n, LEDs_s1_translator:reset, LEDs_s1_translator_avalon_universal_slave_0_agent:reset, LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, addr_router:reset, addr_router_001:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, hex0:reset_n, hex0_s1_translator:reset, hex0_s1_translator_avalon_universal_slave_0_agent:reset, hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex1:reset_n, hex1_s1_translator:reset, hex1_s1_translator_avalon_universal_slave_0_agent:reset, hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex2:reset_n, hex2_s1_translator:reset, hex2_s1_translator_avalon_universal_slave_0_agent:reset, hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex3:reset_n, hex3_s1_translator:reset, hex3_s1_translator_avalon_universal_slave_0_agent:reset, hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex4:reset_n, hex4_s1_translator:reset, hex4_s1_translator_avalon_universal_slave_0_agent:reset, hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex5:reset_n, hex5_s1_translator:reset, hex5_s1_translator_avalon_universal_slave_0_agent:reset, hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex6:reset_n, hex6_s1_translator:reset, hex6_s1_translator_avalon_universal_slave_0_agent:reset, hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex7:reset_n, hex7_s1_translator:reset, hex7_s1_translator_avalon_universal_slave_0_agent:reset, hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, id_router_008:reset, id_router_009:reset, id_router_010:reset, id_router_011:reset, id_router_012:reset, id_router_013:reset, id_router_014:reset, id_router_015:reset, id_router_016:reset, id_router_017:reset, irq_mapper:reset, jtag_uart:rst_n, jtag_uart_avalon_jtag_slave_translator:reset, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lcd_16207_0:reset_n, lcd_16207_0_control_slave_translator:reset, lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:reset, lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lcd_blon:reset_n, lcd_blon_s1_translator:reset, lcd_blon_s1_translator_avalon_universal_slave_0_agent:reset, lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lcd_on:reset_n, lcd_on_s1_translator:reset, lcd_on_s1_translator_avalon_universal_slave_0_agent:reset, lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, nios2_processor:reset_n, nios2_processor_data_master_translator:reset, nios2_processor_data_master_translator_avalon_universal_master_0_agent:reset, nios2_processor_instruction_master_translator:reset, nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:reset, nios2_processor_jtag_debug_module_translator:reset, nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, onchip_memory:reset, onchip_memory_s1_translator:reset, onchip_memory_s1_translator_avalon_universal_slave_0_agent:reset, onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, push_switches:reset_n, push_switches_s1_translator:reset, push_switches_s1_translator_avalon_universal_slave_0_agent:reset, push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_008:reset, rsp_xbar_demux_009:reset, rsp_xbar_demux_010:reset, rsp_xbar_demux_011:reset, rsp_xbar_demux_012:reset, rsp_xbar_demux_013:reset, rsp_xbar_demux_014:reset, rsp_xbar_demux_015:reset, rsp_xbar_demux_016:reset, rsp_xbar_demux_017:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, switches:reset_n, switches_s1_translator:reset, switches_s1_translator_avalon_universal_slave_0_agent:reset, switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset] - wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> onchip_memory:reset_req - wire nios2_processor_jtag_debug_module_reset_reset; // nios2_processor:jtag_debug_module_resetrequest -> rst_controller:reset_in1 - wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket - wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid - wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket - wire [95:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data - wire [17:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel - wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready - wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket - wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid - wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket - wire [95:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data - wire [17:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel - wire cmd_xbar_demux_src1_ready; // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready - wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket - wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid - wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket - wire [95:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data - wire [17:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel - wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready - wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket - wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid - wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket - wire [95:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data - wire [17:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel - wire cmd_xbar_demux_001_src1_ready; // cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready - wire cmd_xbar_demux_001_src2_endofpacket; // cmd_xbar_demux_001:src2_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src2_valid; // cmd_xbar_demux_001:src2_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src2_startofpacket; // cmd_xbar_demux_001:src2_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src2_data; // cmd_xbar_demux_001:src2_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src2_channel; // cmd_xbar_demux_001:src2_channel -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src3_endofpacket; // cmd_xbar_demux_001:src3_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src3_valid; // cmd_xbar_demux_001:src3_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src3_startofpacket; // cmd_xbar_demux_001:src3_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src3_data; // cmd_xbar_demux_001:src3_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src3_channel; // cmd_xbar_demux_001:src3_channel -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src4_endofpacket; // cmd_xbar_demux_001:src4_endofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src4_valid; // cmd_xbar_demux_001:src4_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src4_startofpacket; // cmd_xbar_demux_001:src4_startofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src4_data; // cmd_xbar_demux_001:src4_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src4_channel; // cmd_xbar_demux_001:src4_channel -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src5_endofpacket; // cmd_xbar_demux_001:src5_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src5_valid; // cmd_xbar_demux_001:src5_valid -> switches_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src5_startofpacket; // cmd_xbar_demux_001:src5_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src5_data; // cmd_xbar_demux_001:src5_data -> switches_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src5_channel; // cmd_xbar_demux_001:src5_channel -> switches_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src6_endofpacket; // cmd_xbar_demux_001:src6_endofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src6_valid; // cmd_xbar_demux_001:src6_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src6_startofpacket; // cmd_xbar_demux_001:src6_startofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src6_data; // cmd_xbar_demux_001:src6_data -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src6_channel; // cmd_xbar_demux_001:src6_channel -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src7_endofpacket; // cmd_xbar_demux_001:src7_endofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src7_valid; // cmd_xbar_demux_001:src7_valid -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src7_startofpacket; // cmd_xbar_demux_001:src7_startofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src7_data; // cmd_xbar_demux_001:src7_data -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src7_channel; // cmd_xbar_demux_001:src7_channel -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src8_endofpacket; // cmd_xbar_demux_001:src8_endofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src8_valid; // cmd_xbar_demux_001:src8_valid -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src8_startofpacket; // cmd_xbar_demux_001:src8_startofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src8_data; // cmd_xbar_demux_001:src8_data -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src8_channel; // cmd_xbar_demux_001:src8_channel -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src9_endofpacket; // cmd_xbar_demux_001:src9_endofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src9_valid; // cmd_xbar_demux_001:src9_valid -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src9_startofpacket; // cmd_xbar_demux_001:src9_startofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src9_data; // cmd_xbar_demux_001:src9_data -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src9_channel; // cmd_xbar_demux_001:src9_channel -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src10_endofpacket; // cmd_xbar_demux_001:src10_endofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src10_valid; // cmd_xbar_demux_001:src10_valid -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src10_startofpacket; // cmd_xbar_demux_001:src10_startofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src10_data; // cmd_xbar_demux_001:src10_data -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src10_channel; // cmd_xbar_demux_001:src10_channel -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src11_endofpacket; // cmd_xbar_demux_001:src11_endofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src11_valid; // cmd_xbar_demux_001:src11_valid -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src11_startofpacket; // cmd_xbar_demux_001:src11_startofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src11_data; // cmd_xbar_demux_001:src11_data -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src11_channel; // cmd_xbar_demux_001:src11_channel -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src12_endofpacket; // cmd_xbar_demux_001:src12_endofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src12_valid; // cmd_xbar_demux_001:src12_valid -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src12_startofpacket; // cmd_xbar_demux_001:src12_startofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src12_data; // cmd_xbar_demux_001:src12_data -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src12_channel; // cmd_xbar_demux_001:src12_channel -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src13_endofpacket; // cmd_xbar_demux_001:src13_endofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src13_valid; // cmd_xbar_demux_001:src13_valid -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src13_startofpacket; // cmd_xbar_demux_001:src13_startofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src13_data; // cmd_xbar_demux_001:src13_data -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src13_channel; // cmd_xbar_demux_001:src13_channel -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src14_endofpacket; // cmd_xbar_demux_001:src14_endofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src14_valid; // cmd_xbar_demux_001:src14_valid -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src14_startofpacket; // cmd_xbar_demux_001:src14_startofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src14_data; // cmd_xbar_demux_001:src14_data -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src14_channel; // cmd_xbar_demux_001:src14_channel -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src15_endofpacket; // cmd_xbar_demux_001:src15_endofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src15_valid; // cmd_xbar_demux_001:src15_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src15_startofpacket; // cmd_xbar_demux_001:src15_startofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src15_data; // cmd_xbar_demux_001:src15_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src15_channel; // cmd_xbar_demux_001:src15_channel -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src16_endofpacket; // cmd_xbar_demux_001:src16_endofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src16_valid; // cmd_xbar_demux_001:src16_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src16_startofpacket; // cmd_xbar_demux_001:src16_startofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src16_data; // cmd_xbar_demux_001:src16_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src16_channel; // cmd_xbar_demux_001:src16_channel -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src17_endofpacket; // cmd_xbar_demux_001:src17_endofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src17_valid; // cmd_xbar_demux_001:src17_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src17_startofpacket; // cmd_xbar_demux_001:src17_startofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src17_data; // cmd_xbar_demux_001:src17_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src17_channel; // cmd_xbar_demux_001:src17_channel -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket - wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid - wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket - wire [95:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data - wire [17:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel - wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready - wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket - wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid - wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket - wire [95:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data - wire [17:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel - wire rsp_xbar_demux_src1_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready - wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket - wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid - wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket - wire [95:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data - wire [17:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel - wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready - wire rsp_xbar_demux_001_src1_endofpacket; // rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket - wire rsp_xbar_demux_001_src1_valid; // rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid - wire rsp_xbar_demux_001_src1_startofpacket; // rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket - wire [95:0] rsp_xbar_demux_001_src1_data; // rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data - wire [17:0] rsp_xbar_demux_001_src1_channel; // rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel - wire rsp_xbar_demux_001_src1_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready - wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket - wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux_001:sink2_valid - wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket - wire [95:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux_001:sink2_data - wire [17:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux_001:sink2_channel - wire rsp_xbar_demux_002_src0_ready; // rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_002:src0_ready - wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket - wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux_001:sink3_valid - wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket - wire [95:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux_001:sink3_data - wire [17:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux_001:sink3_channel - wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src0_ready - wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket - wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux_001:sink4_valid - wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket - wire [95:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux_001:sink4_data - wire [17:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux_001:sink4_channel - wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src0_ready - wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket - wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid - wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket - wire [95:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data - wire [17:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel - wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready - wire rsp_xbar_demux_006_src0_endofpacket; // rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket - wire rsp_xbar_demux_006_src0_valid; // rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink6_valid - wire rsp_xbar_demux_006_src0_startofpacket; // rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket - wire [95:0] rsp_xbar_demux_006_src0_data; // rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink6_data - wire [17:0] rsp_xbar_demux_006_src0_channel; // rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink6_channel - wire rsp_xbar_demux_006_src0_ready; // rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_006:src0_ready - wire rsp_xbar_demux_007_src0_endofpacket; // rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket - wire rsp_xbar_demux_007_src0_valid; // rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink7_valid - wire rsp_xbar_demux_007_src0_startofpacket; // rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket - wire [95:0] rsp_xbar_demux_007_src0_data; // rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink7_data - wire [17:0] rsp_xbar_demux_007_src0_channel; // rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink7_channel - wire rsp_xbar_demux_007_src0_ready; // rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_007:src0_ready - wire rsp_xbar_demux_008_src0_endofpacket; // rsp_xbar_demux_008:src0_endofpacket -> rsp_xbar_mux_001:sink8_endofpacket - wire rsp_xbar_demux_008_src0_valid; // rsp_xbar_demux_008:src0_valid -> rsp_xbar_mux_001:sink8_valid - wire rsp_xbar_demux_008_src0_startofpacket; // rsp_xbar_demux_008:src0_startofpacket -> rsp_xbar_mux_001:sink8_startofpacket - wire [95:0] rsp_xbar_demux_008_src0_data; // rsp_xbar_demux_008:src0_data -> rsp_xbar_mux_001:sink8_data - wire [17:0] rsp_xbar_demux_008_src0_channel; // rsp_xbar_demux_008:src0_channel -> rsp_xbar_mux_001:sink8_channel - wire rsp_xbar_demux_008_src0_ready; // rsp_xbar_mux_001:sink8_ready -> rsp_xbar_demux_008:src0_ready - wire rsp_xbar_demux_009_src0_endofpacket; // rsp_xbar_demux_009:src0_endofpacket -> rsp_xbar_mux_001:sink9_endofpacket - wire rsp_xbar_demux_009_src0_valid; // rsp_xbar_demux_009:src0_valid -> rsp_xbar_mux_001:sink9_valid - wire rsp_xbar_demux_009_src0_startofpacket; // rsp_xbar_demux_009:src0_startofpacket -> rsp_xbar_mux_001:sink9_startofpacket - wire [95:0] rsp_xbar_demux_009_src0_data; // rsp_xbar_demux_009:src0_data -> rsp_xbar_mux_001:sink9_data - wire [17:0] rsp_xbar_demux_009_src0_channel; // rsp_xbar_demux_009:src0_channel -> rsp_xbar_mux_001:sink9_channel - wire rsp_xbar_demux_009_src0_ready; // rsp_xbar_mux_001:sink9_ready -> rsp_xbar_demux_009:src0_ready - wire rsp_xbar_demux_010_src0_endofpacket; // rsp_xbar_demux_010:src0_endofpacket -> rsp_xbar_mux_001:sink10_endofpacket - wire rsp_xbar_demux_010_src0_valid; // rsp_xbar_demux_010:src0_valid -> rsp_xbar_mux_001:sink10_valid - wire rsp_xbar_demux_010_src0_startofpacket; // rsp_xbar_demux_010:src0_startofpacket -> rsp_xbar_mux_001:sink10_startofpacket - wire [95:0] rsp_xbar_demux_010_src0_data; // rsp_xbar_demux_010:src0_data -> rsp_xbar_mux_001:sink10_data - wire [17:0] rsp_xbar_demux_010_src0_channel; // rsp_xbar_demux_010:src0_channel -> rsp_xbar_mux_001:sink10_channel - wire rsp_xbar_demux_010_src0_ready; // rsp_xbar_mux_001:sink10_ready -> rsp_xbar_demux_010:src0_ready - wire rsp_xbar_demux_011_src0_endofpacket; // rsp_xbar_demux_011:src0_endofpacket -> rsp_xbar_mux_001:sink11_endofpacket - wire rsp_xbar_demux_011_src0_valid; // rsp_xbar_demux_011:src0_valid -> rsp_xbar_mux_001:sink11_valid - wire rsp_xbar_demux_011_src0_startofpacket; // rsp_xbar_demux_011:src0_startofpacket -> rsp_xbar_mux_001:sink11_startofpacket - wire [95:0] rsp_xbar_demux_011_src0_data; // rsp_xbar_demux_011:src0_data -> rsp_xbar_mux_001:sink11_data - wire [17:0] rsp_xbar_demux_011_src0_channel; // rsp_xbar_demux_011:src0_channel -> rsp_xbar_mux_001:sink11_channel - wire rsp_xbar_demux_011_src0_ready; // rsp_xbar_mux_001:sink11_ready -> rsp_xbar_demux_011:src0_ready - wire rsp_xbar_demux_012_src0_endofpacket; // rsp_xbar_demux_012:src0_endofpacket -> rsp_xbar_mux_001:sink12_endofpacket - wire rsp_xbar_demux_012_src0_valid; // rsp_xbar_demux_012:src0_valid -> rsp_xbar_mux_001:sink12_valid - wire rsp_xbar_demux_012_src0_startofpacket; // rsp_xbar_demux_012:src0_startofpacket -> rsp_xbar_mux_001:sink12_startofpacket - wire [95:0] rsp_xbar_demux_012_src0_data; // rsp_xbar_demux_012:src0_data -> rsp_xbar_mux_001:sink12_data - wire [17:0] rsp_xbar_demux_012_src0_channel; // rsp_xbar_demux_012:src0_channel -> rsp_xbar_mux_001:sink12_channel - wire rsp_xbar_demux_012_src0_ready; // rsp_xbar_mux_001:sink12_ready -> rsp_xbar_demux_012:src0_ready - wire rsp_xbar_demux_013_src0_endofpacket; // rsp_xbar_demux_013:src0_endofpacket -> rsp_xbar_mux_001:sink13_endofpacket - wire rsp_xbar_demux_013_src0_valid; // rsp_xbar_demux_013:src0_valid -> rsp_xbar_mux_001:sink13_valid - wire rsp_xbar_demux_013_src0_startofpacket; // rsp_xbar_demux_013:src0_startofpacket -> rsp_xbar_mux_001:sink13_startofpacket - wire [95:0] rsp_xbar_demux_013_src0_data; // rsp_xbar_demux_013:src0_data -> rsp_xbar_mux_001:sink13_data - wire [17:0] rsp_xbar_demux_013_src0_channel; // rsp_xbar_demux_013:src0_channel -> rsp_xbar_mux_001:sink13_channel - wire rsp_xbar_demux_013_src0_ready; // rsp_xbar_mux_001:sink13_ready -> rsp_xbar_demux_013:src0_ready - wire rsp_xbar_demux_014_src0_endofpacket; // rsp_xbar_demux_014:src0_endofpacket -> rsp_xbar_mux_001:sink14_endofpacket - wire rsp_xbar_demux_014_src0_valid; // rsp_xbar_demux_014:src0_valid -> rsp_xbar_mux_001:sink14_valid - wire rsp_xbar_demux_014_src0_startofpacket; // rsp_xbar_demux_014:src0_startofpacket -> rsp_xbar_mux_001:sink14_startofpacket - wire [95:0] rsp_xbar_demux_014_src0_data; // rsp_xbar_demux_014:src0_data -> rsp_xbar_mux_001:sink14_data - wire [17:0] rsp_xbar_demux_014_src0_channel; // rsp_xbar_demux_014:src0_channel -> rsp_xbar_mux_001:sink14_channel - wire rsp_xbar_demux_014_src0_ready; // rsp_xbar_mux_001:sink14_ready -> rsp_xbar_demux_014:src0_ready - wire rsp_xbar_demux_015_src0_endofpacket; // rsp_xbar_demux_015:src0_endofpacket -> rsp_xbar_mux_001:sink15_endofpacket - wire rsp_xbar_demux_015_src0_valid; // rsp_xbar_demux_015:src0_valid -> rsp_xbar_mux_001:sink15_valid - wire rsp_xbar_demux_015_src0_startofpacket; // rsp_xbar_demux_015:src0_startofpacket -> rsp_xbar_mux_001:sink15_startofpacket - wire [95:0] rsp_xbar_demux_015_src0_data; // rsp_xbar_demux_015:src0_data -> rsp_xbar_mux_001:sink15_data - wire [17:0] rsp_xbar_demux_015_src0_channel; // rsp_xbar_demux_015:src0_channel -> rsp_xbar_mux_001:sink15_channel - wire rsp_xbar_demux_015_src0_ready; // rsp_xbar_mux_001:sink15_ready -> rsp_xbar_demux_015:src0_ready - wire rsp_xbar_demux_016_src0_endofpacket; // rsp_xbar_demux_016:src0_endofpacket -> rsp_xbar_mux_001:sink16_endofpacket - wire rsp_xbar_demux_016_src0_valid; // rsp_xbar_demux_016:src0_valid -> rsp_xbar_mux_001:sink16_valid - wire rsp_xbar_demux_016_src0_startofpacket; // rsp_xbar_demux_016:src0_startofpacket -> rsp_xbar_mux_001:sink16_startofpacket - wire [95:0] rsp_xbar_demux_016_src0_data; // rsp_xbar_demux_016:src0_data -> rsp_xbar_mux_001:sink16_data - wire [17:0] rsp_xbar_demux_016_src0_channel; // rsp_xbar_demux_016:src0_channel -> rsp_xbar_mux_001:sink16_channel - wire rsp_xbar_demux_016_src0_ready; // rsp_xbar_mux_001:sink16_ready -> rsp_xbar_demux_016:src0_ready - wire rsp_xbar_demux_017_src0_endofpacket; // rsp_xbar_demux_017:src0_endofpacket -> rsp_xbar_mux_001:sink17_endofpacket - wire rsp_xbar_demux_017_src0_valid; // rsp_xbar_demux_017:src0_valid -> rsp_xbar_mux_001:sink17_valid - wire rsp_xbar_demux_017_src0_startofpacket; // rsp_xbar_demux_017:src0_startofpacket -> rsp_xbar_mux_001:sink17_startofpacket - wire [95:0] rsp_xbar_demux_017_src0_data; // rsp_xbar_demux_017:src0_data -> rsp_xbar_mux_001:sink17_data - wire [17:0] rsp_xbar_demux_017_src0_channel; // rsp_xbar_demux_017:src0_channel -> rsp_xbar_mux_001:sink17_channel - wire rsp_xbar_demux_017_src0_ready; // rsp_xbar_mux_001:sink17_ready -> rsp_xbar_demux_017:src0_ready - wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket - wire addr_router_src_valid; // addr_router:src_valid -> cmd_xbar_demux:sink_valid - wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket - wire [95:0] addr_router_src_data; // addr_router:src_data -> cmd_xbar_demux:sink_data - wire [17:0] addr_router_src_channel; // addr_router:src_channel -> cmd_xbar_demux:sink_channel - wire addr_router_src_ready; // cmd_xbar_demux:sink_ready -> addr_router:src_ready - wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket - wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_valid - wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket - wire [95:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_data - wire [17:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_channel - wire rsp_xbar_mux_src_ready; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready - wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket - wire addr_router_001_src_valid; // addr_router_001:src_valid -> cmd_xbar_demux_001:sink_valid - wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket - wire [95:0] addr_router_001_src_data; // addr_router_001:src_data -> cmd_xbar_demux_001:sink_data - wire [17:0] addr_router_001_src_channel; // addr_router_001:src_channel -> cmd_xbar_demux_001:sink_channel - wire addr_router_001_src_ready; // cmd_xbar_demux_001:sink_ready -> addr_router_001:src_ready - wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket - wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_valid - wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket - wire [95:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_data - wire [17:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_channel - wire rsp_xbar_mux_001_src_ready; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux_001:src_ready - wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_mux_src_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready - wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket - wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid - wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket - wire [95:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data - wire [17:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel - wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready - wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_mux_001_src_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_001:src_ready - wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket - wire id_router_001_src_valid; // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid - wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket - wire [95:0] id_router_001_src_data; // id_router_001:src_data -> rsp_xbar_demux_001:sink_data - wire [17:0] id_router_001_src_channel; // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel - wire id_router_001_src_ready; // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready - wire cmd_xbar_demux_001_src2_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src2_ready - wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket - wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid - wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket - wire [95:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data - wire [17:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel - wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready - wire cmd_xbar_demux_001_src3_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src3_ready - wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket - wire id_router_003_src_valid; // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid - wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket - wire [95:0] id_router_003_src_data; // id_router_003:src_data -> rsp_xbar_demux_003:sink_data - wire [17:0] id_router_003_src_channel; // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel - wire id_router_003_src_ready; // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready - wire cmd_xbar_demux_001_src4_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src4_ready - wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket - wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid - wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket - wire [95:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data - wire [17:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel - wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready - wire cmd_xbar_demux_001_src5_ready; // switches_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready - wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket - wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid - wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket - wire [95:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data - wire [17:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel - wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready - wire cmd_xbar_demux_001_src6_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready - wire id_router_006_src_endofpacket; // id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket - wire id_router_006_src_valid; // id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid - wire id_router_006_src_startofpacket; // id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket - wire [95:0] id_router_006_src_data; // id_router_006:src_data -> rsp_xbar_demux_006:sink_data - wire [17:0] id_router_006_src_channel; // id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel - wire id_router_006_src_ready; // rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready - wire cmd_xbar_demux_001_src7_ready; // hex0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready - wire id_router_007_src_endofpacket; // id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket - wire id_router_007_src_valid; // id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid - wire id_router_007_src_startofpacket; // id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket - wire [95:0] id_router_007_src_data; // id_router_007:src_data -> rsp_xbar_demux_007:sink_data - wire [17:0] id_router_007_src_channel; // id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel - wire id_router_007_src_ready; // rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready - wire cmd_xbar_demux_001_src8_ready; // hex1_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src8_ready - wire id_router_008_src_endofpacket; // id_router_008:src_endofpacket -> rsp_xbar_demux_008:sink_endofpacket - wire id_router_008_src_valid; // id_router_008:src_valid -> rsp_xbar_demux_008:sink_valid - wire id_router_008_src_startofpacket; // id_router_008:src_startofpacket -> rsp_xbar_demux_008:sink_startofpacket - wire [95:0] id_router_008_src_data; // id_router_008:src_data -> rsp_xbar_demux_008:sink_data - wire [17:0] id_router_008_src_channel; // id_router_008:src_channel -> rsp_xbar_demux_008:sink_channel - wire id_router_008_src_ready; // rsp_xbar_demux_008:sink_ready -> id_router_008:src_ready - wire cmd_xbar_demux_001_src9_ready; // hex2_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src9_ready - wire id_router_009_src_endofpacket; // id_router_009:src_endofpacket -> rsp_xbar_demux_009:sink_endofpacket - wire id_router_009_src_valid; // id_router_009:src_valid -> rsp_xbar_demux_009:sink_valid - wire id_router_009_src_startofpacket; // id_router_009:src_startofpacket -> rsp_xbar_demux_009:sink_startofpacket - wire [95:0] id_router_009_src_data; // id_router_009:src_data -> rsp_xbar_demux_009:sink_data - wire [17:0] id_router_009_src_channel; // id_router_009:src_channel -> rsp_xbar_demux_009:sink_channel - wire id_router_009_src_ready; // rsp_xbar_demux_009:sink_ready -> id_router_009:src_ready - wire cmd_xbar_demux_001_src10_ready; // hex3_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src10_ready - wire id_router_010_src_endofpacket; // id_router_010:src_endofpacket -> rsp_xbar_demux_010:sink_endofpacket - wire id_router_010_src_valid; // id_router_010:src_valid -> rsp_xbar_demux_010:sink_valid - wire id_router_010_src_startofpacket; // id_router_010:src_startofpacket -> rsp_xbar_demux_010:sink_startofpacket - wire [95:0] id_router_010_src_data; // id_router_010:src_data -> rsp_xbar_demux_010:sink_data - wire [17:0] id_router_010_src_channel; // id_router_010:src_channel -> rsp_xbar_demux_010:sink_channel - wire id_router_010_src_ready; // rsp_xbar_demux_010:sink_ready -> id_router_010:src_ready - wire cmd_xbar_demux_001_src11_ready; // hex4_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src11_ready - wire id_router_011_src_endofpacket; // id_router_011:src_endofpacket -> rsp_xbar_demux_011:sink_endofpacket - wire id_router_011_src_valid; // id_router_011:src_valid -> rsp_xbar_demux_011:sink_valid - wire id_router_011_src_startofpacket; // id_router_011:src_startofpacket -> rsp_xbar_demux_011:sink_startofpacket - wire [95:0] id_router_011_src_data; // id_router_011:src_data -> rsp_xbar_demux_011:sink_data - wire [17:0] id_router_011_src_channel; // id_router_011:src_channel -> rsp_xbar_demux_011:sink_channel - wire id_router_011_src_ready; // rsp_xbar_demux_011:sink_ready -> id_router_011:src_ready - wire cmd_xbar_demux_001_src12_ready; // hex5_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src12_ready - wire id_router_012_src_endofpacket; // id_router_012:src_endofpacket -> rsp_xbar_demux_012:sink_endofpacket - wire id_router_012_src_valid; // id_router_012:src_valid -> rsp_xbar_demux_012:sink_valid - wire id_router_012_src_startofpacket; // id_router_012:src_startofpacket -> rsp_xbar_demux_012:sink_startofpacket - wire [95:0] id_router_012_src_data; // id_router_012:src_data -> rsp_xbar_demux_012:sink_data - wire [17:0] id_router_012_src_channel; // id_router_012:src_channel -> rsp_xbar_demux_012:sink_channel - wire id_router_012_src_ready; // rsp_xbar_demux_012:sink_ready -> id_router_012:src_ready - wire cmd_xbar_demux_001_src13_ready; // hex6_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src13_ready - wire id_router_013_src_endofpacket; // id_router_013:src_endofpacket -> rsp_xbar_demux_013:sink_endofpacket - wire id_router_013_src_valid; // id_router_013:src_valid -> rsp_xbar_demux_013:sink_valid - wire id_router_013_src_startofpacket; // id_router_013:src_startofpacket -> rsp_xbar_demux_013:sink_startofpacket - wire [95:0] id_router_013_src_data; // id_router_013:src_data -> rsp_xbar_demux_013:sink_data - wire [17:0] id_router_013_src_channel; // id_router_013:src_channel -> rsp_xbar_demux_013:sink_channel - wire id_router_013_src_ready; // rsp_xbar_demux_013:sink_ready -> id_router_013:src_ready - wire cmd_xbar_demux_001_src14_ready; // hex7_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src14_ready - wire id_router_014_src_endofpacket; // id_router_014:src_endofpacket -> rsp_xbar_demux_014:sink_endofpacket - wire id_router_014_src_valid; // id_router_014:src_valid -> rsp_xbar_demux_014:sink_valid - wire id_router_014_src_startofpacket; // id_router_014:src_startofpacket -> rsp_xbar_demux_014:sink_startofpacket - wire [95:0] id_router_014_src_data; // id_router_014:src_data -> rsp_xbar_demux_014:sink_data - wire [17:0] id_router_014_src_channel; // id_router_014:src_channel -> rsp_xbar_demux_014:sink_channel - wire id_router_014_src_ready; // rsp_xbar_demux_014:sink_ready -> id_router_014:src_ready - wire cmd_xbar_demux_001_src15_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src15_ready - wire id_router_015_src_endofpacket; // id_router_015:src_endofpacket -> rsp_xbar_demux_015:sink_endofpacket - wire id_router_015_src_valid; // id_router_015:src_valid -> rsp_xbar_demux_015:sink_valid - wire id_router_015_src_startofpacket; // id_router_015:src_startofpacket -> rsp_xbar_demux_015:sink_startofpacket - wire [95:0] id_router_015_src_data; // id_router_015:src_data -> rsp_xbar_demux_015:sink_data - wire [17:0] id_router_015_src_channel; // id_router_015:src_channel -> rsp_xbar_demux_015:sink_channel - wire id_router_015_src_ready; // rsp_xbar_demux_015:sink_ready -> id_router_015:src_ready - wire cmd_xbar_demux_001_src16_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src16_ready - wire id_router_016_src_endofpacket; // id_router_016:src_endofpacket -> rsp_xbar_demux_016:sink_endofpacket - wire id_router_016_src_valid; // id_router_016:src_valid -> rsp_xbar_demux_016:sink_valid - wire id_router_016_src_startofpacket; // id_router_016:src_startofpacket -> rsp_xbar_demux_016:sink_startofpacket - wire [95:0] id_router_016_src_data; // id_router_016:src_data -> rsp_xbar_demux_016:sink_data - wire [17:0] id_router_016_src_channel; // id_router_016:src_channel -> rsp_xbar_demux_016:sink_channel - wire id_router_016_src_ready; // rsp_xbar_demux_016:sink_ready -> id_router_016:src_ready - wire cmd_xbar_demux_001_src17_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src17_ready - wire id_router_017_src_endofpacket; // id_router_017:src_endofpacket -> rsp_xbar_demux_017:sink_endofpacket - wire id_router_017_src_valid; // id_router_017:src_valid -> rsp_xbar_demux_017:sink_valid - wire id_router_017_src_startofpacket; // id_router_017:src_startofpacket -> rsp_xbar_demux_017:sink_startofpacket - wire [95:0] id_router_017_src_data; // id_router_017:src_data -> rsp_xbar_demux_017:sink_data - wire [17:0] id_router_017_src_channel; // id_router_017:src_channel -> rsp_xbar_demux_017:sink_channel - wire id_router_017_src_ready; // rsp_xbar_demux_017:sink_ready -> id_router_017:src_ready - wire irq_mapper_receiver0_irq; // jtag_uart:av_irq -> irq_mapper:receiver0_irq - wire [31:0] nios2_processor_d_irq_irq; // irq_mapper:sender_irq -> nios2_processor:d_irq - - nios_system_nios2_processor nios2_processor ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n - .d_address (nios2_processor_data_master_address), // data_master.address - .d_byteenable (nios2_processor_data_master_byteenable), // .byteenable - .d_read (nios2_processor_data_master_read), // .read - .d_readdata (nios2_processor_data_master_readdata), // .readdata - .d_waitrequest (nios2_processor_data_master_waitrequest), // .waitrequest - .d_write (nios2_processor_data_master_write), // .write - .d_writedata (nios2_processor_data_master_writedata), // .writedata - .jtag_debug_module_debugaccess_to_roms (nios2_processor_data_master_debugaccess), // .debugaccess - .i_address (nios2_processor_instruction_master_address), // instruction_master.address - .i_read (nios2_processor_instruction_master_read), // .read - .i_readdata (nios2_processor_instruction_master_readdata), // .readdata - .i_waitrequest (nios2_processor_instruction_master_waitrequest), // .waitrequest - .d_irq (nios2_processor_d_irq_irq), // d_irq.irq - .jtag_debug_module_resetrequest (nios2_processor_jtag_debug_module_reset_reset), // jtag_debug_module_reset.reset - .jtag_debug_module_address (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_address), // jtag_debug_module.address - .jtag_debug_module_byteenable (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable - .jtag_debug_module_debugaccess (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess - .jtag_debug_module_read (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_read), // .read - .jtag_debug_module_readdata (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata - .jtag_debug_module_waitrequest (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest), // .waitrequest - .jtag_debug_module_write (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write - .jtag_debug_module_writedata (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata - .no_ci_readra () // custom_instruction_master.readra - ); - - nios_system_onchip_memory onchip_memory ( - .clk (clk_clk), // clk1.clk - .address (onchip_memory_s1_translator_avalon_anti_slave_0_address), // s1.address - .clken (onchip_memory_s1_translator_avalon_anti_slave_0_clken), // .clken - .chipselect (onchip_memory_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .write (onchip_memory_s1_translator_avalon_anti_slave_0_write), // .write - .readdata (onchip_memory_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .writedata (onchip_memory_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .byteenable (onchip_memory_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable - .reset (rst_controller_reset_out_reset), // reset1.reset - .reset_req (rst_controller_reset_out_reset_req) // .reset_req - ); - - nios_system_jtag_uart jtag_uart ( - .clk (clk_clk), // clk.clk - .rst_n (~rst_controller_reset_out_reset), // reset.reset_n - .av_chipselect (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // avalon_jtag_slave.chipselect - .av_address (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // .address - .av_read_n (~jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read_n - .av_readdata (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata - .av_write_n (~jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write_n - .av_writedata (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata - .av_waitrequest (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest - .av_irq (irq_mapper_receiver0_irq) // irq.irq - ); - - nios_system_LEDs leds ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (leds_s1_translator_avalon_anti_slave_0_address), // s1.address - .write_n (~leds_s1_translator_avalon_anti_slave_0_write), // .write_n - .writedata (leds_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .chipselect (leds_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .readdata (leds_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .out_port (leds_export) // external_connection.export - ); - - nios_system_LEDRs ledrs ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (ledrs_s1_translator_avalon_anti_slave_0_address), // s1.address - .write_n (~ledrs_s1_translator_avalon_anti_slave_0_write), // .write_n - .writedata (ledrs_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .chipselect (ledrs_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .readdata (ledrs_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .out_port (ledrs_export) // external_connection.export - ); - - nios_system_switches switches ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (switches_s1_translator_avalon_anti_slave_0_address), // s1.address - .readdata (switches_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .in_port (switches_export) // external_connection.export - ); - - nios_system_push_switches push_switches ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (push_switches_s1_translator_avalon_anti_slave_0_address), // s1.address - .readdata (push_switches_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .in_port (push_switches_export) // external_connection.export - ); - - nios_system_hex0 hex0 ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (hex0_s1_translator_avalon_anti_slave_0_address), // s1.address - .write_n (~hex0_s1_translator_avalon_anti_slave_0_write), // .write_n - .writedata (hex0_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .chipselect (hex0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .readdata (hex0_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .out_port (hex0_export) // external_connection.export - ); - - nios_system_hex0 hex1 ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (hex1_s1_translator_avalon_anti_slave_0_address), // s1.address - .write_n (~hex1_s1_translator_avalon_anti_slave_0_write), // .write_n - .writedata (hex1_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .chipselect (hex1_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .readdata (hex1_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .out_port (hex1_export) // external_connection.export - ); - - nios_system_hex0 hex2 ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (hex2_s1_translator_avalon_anti_slave_0_address), // s1.address - .write_n (~hex2_s1_translator_avalon_anti_slave_0_write), // .write_n - .writedata (hex2_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .chipselect (hex2_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .readdata (hex2_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .out_port (hex2_export) // external_connection.export - ); - - nios_system_hex0 hex3 ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (hex3_s1_translator_avalon_anti_slave_0_address), // s1.address - .write_n (~hex3_s1_translator_avalon_anti_slave_0_write), // .write_n - .writedata (hex3_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .chipselect (hex3_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .readdata (hex3_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .out_port (hex3_export) // external_connection.export - ); - - nios_system_hex0 hex4 ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (hex4_s1_translator_avalon_anti_slave_0_address), // s1.address - .write_n (~hex4_s1_translator_avalon_anti_slave_0_write), // .write_n - .writedata (hex4_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .chipselect (hex4_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .readdata (hex4_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .out_port (hex4_export) // external_connection.export - ); - - nios_system_hex0 hex5 ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (hex5_s1_translator_avalon_anti_slave_0_address), // s1.address - .write_n (~hex5_s1_translator_avalon_anti_slave_0_write), // .write_n - .writedata (hex5_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .chipselect (hex5_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .readdata (hex5_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .out_port (hex5_export) // external_connection.export - ); - - nios_system_hex0 hex6 ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (hex6_s1_translator_avalon_anti_slave_0_address), // s1.address - .write_n (~hex6_s1_translator_avalon_anti_slave_0_write), // .write_n - .writedata (hex6_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .chipselect (hex6_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .readdata (hex6_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .out_port (hex6_export) // external_connection.export - ); - - nios_system_hex0 hex7 ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (hex7_s1_translator_avalon_anti_slave_0_address), // s1.address - .write_n (~hex7_s1_translator_avalon_anti_slave_0_write), // .write_n - .writedata (hex7_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .chipselect (hex7_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .readdata (hex7_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .out_port (hex7_export) // external_connection.export - ); - - nios_system_lcd_16207_0 lcd_16207_0 ( - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .clk (clk_clk), // clk.clk - .begintransfer (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_begintransfer), // control_slave.begintransfer - .read (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_read), // .read - .write (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_write), // .write - .readdata (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata - .writedata (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_writedata), // .writedata - .address (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_address), // .address - .LCD_RS (lcd_16207_0_RS), // external.export - .LCD_RW (lcd_16207_0_RW), // .export - .LCD_data (lcd_16207_0_data), // .export - .LCD_E (lcd_16207_0_E) // .export - ); - - nios_system_lcd_on lcd_on ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (lcd_on_s1_translator_avalon_anti_slave_0_address), // s1.address - .write_n (~lcd_on_s1_translator_avalon_anti_slave_0_write), // .write_n - .writedata (lcd_on_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .chipselect (lcd_on_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .readdata (lcd_on_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .out_port (lcd_on_export) // external_connection.export - ); - - nios_system_lcd_on lcd_blon ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (lcd_blon_s1_translator_avalon_anti_slave_0_address), // s1.address - .write_n (~lcd_blon_s1_translator_avalon_anti_slave_0_write), // .write_n - .writedata (lcd_blon_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .chipselect (lcd_blon_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .readdata (lcd_blon_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .out_port (lcd_blon_export) // external_connection.export - ); - - altera_merlin_master_translator #( - .AV_ADDRESS_W (19), - .AV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .USE_READ (1), - .USE_WRITE (0), - .USE_BEGINBURSTTRANSFER (0), - .USE_BEGINTRANSFER (0), - .USE_CHIPSELECT (0), - .USE_BURSTCOUNT (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (1), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_LINEWRAPBURSTS (1), - .AV_REGISTERINCOMINGSIGNALS (0) - ) nios2_processor_instruction_master_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (nios2_processor_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address - .uav_burstcount (nios2_processor_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount - .uav_read (nios2_processor_instruction_master_translator_avalon_universal_master_0_read), // .read - .uav_write (nios2_processor_instruction_master_translator_avalon_universal_master_0_write), // .write - .uav_waitrequest (nios2_processor_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest - .uav_readdatavalid (nios2_processor_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid - .uav_byteenable (nios2_processor_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable - .uav_readdata (nios2_processor_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata - .uav_writedata (nios2_processor_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata - .uav_lock (nios2_processor_instruction_master_translator_avalon_universal_master_0_lock), // .lock - .uav_debugaccess (nios2_processor_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess - .av_address (nios2_processor_instruction_master_address), // avalon_anti_master_0.address - .av_waitrequest (nios2_processor_instruction_master_waitrequest), // .waitrequest - .av_read (nios2_processor_instruction_master_read), // .read - .av_readdata (nios2_processor_instruction_master_readdata), // .readdata - .av_burstcount (1'b1), // (terminated) - .av_byteenable (4'b1111), // (terminated) - .av_beginbursttransfer (1'b0), // (terminated) - .av_begintransfer (1'b0), // (terminated) - .av_chipselect (1'b0), // (terminated) - .av_readdatavalid (), // (terminated) - .av_write (1'b0), // (terminated) - .av_writedata (32'b00000000000000000000000000000000), // (terminated) - .av_lock (1'b0), // (terminated) - .av_debugaccess (1'b0), // (terminated) - .uav_clken (), // (terminated) - .av_clken (1'b1), // (terminated) - .uav_response (2'b00), // (terminated) - .av_response (), // (terminated) - .uav_writeresponserequest (), // (terminated) - .uav_writeresponsevalid (1'b0), // (terminated) - .av_writeresponserequest (1'b0), // (terminated) - .av_writeresponsevalid () // (terminated) - ); - - altera_merlin_master_translator #( - .AV_ADDRESS_W (19), - .AV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .USE_READ (1), - .USE_WRITE (1), - .USE_BEGINBURSTTRANSFER (0), - .USE_BEGINTRANSFER (0), - .USE_CHIPSELECT (0), - .USE_BURSTCOUNT (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (1), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_LINEWRAPBURSTS (0), - .AV_REGISTERINCOMINGSIGNALS (1) - ) nios2_processor_data_master_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (nios2_processor_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address - .uav_burstcount (nios2_processor_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount - .uav_read (nios2_processor_data_master_translator_avalon_universal_master_0_read), // .read - .uav_write (nios2_processor_data_master_translator_avalon_universal_master_0_write), // .write - .uav_waitrequest (nios2_processor_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest - .uav_readdatavalid (nios2_processor_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid - .uav_byteenable (nios2_processor_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable - .uav_readdata (nios2_processor_data_master_translator_avalon_universal_master_0_readdata), // .readdata - .uav_writedata (nios2_processor_data_master_translator_avalon_universal_master_0_writedata), // .writedata - .uav_lock (nios2_processor_data_master_translator_avalon_universal_master_0_lock), // .lock - .uav_debugaccess (nios2_processor_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess - .av_address (nios2_processor_data_master_address), // avalon_anti_master_0.address - .av_waitrequest (nios2_processor_data_master_waitrequest), // .waitrequest - .av_byteenable (nios2_processor_data_master_byteenable), // .byteenable - .av_read (nios2_processor_data_master_read), // .read - .av_readdata (nios2_processor_data_master_readdata), // .readdata - .av_write (nios2_processor_data_master_write), // .write - .av_writedata (nios2_processor_data_master_writedata), // .writedata - .av_debugaccess (nios2_processor_data_master_debugaccess), // .debugaccess - .av_burstcount (1'b1), // (terminated) - .av_beginbursttransfer (1'b0), // (terminated) - .av_begintransfer (1'b0), // (terminated) - .av_chipselect (1'b0), // (terminated) - .av_readdatavalid (), // (terminated) - .av_lock (1'b0), // (terminated) - .uav_clken (), // (terminated) - .av_clken (1'b1), // (terminated) - .uav_response (2'b00), // (terminated) - .av_response (), // (terminated) - .uav_writeresponserequest (), // (terminated) - .uav_writeresponsevalid (1'b0), // (terminated) - .av_writeresponserequest (1'b0), // (terminated) - .av_writeresponsevalid () // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (9), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (4), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (1), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) nios2_processor_jtag_debug_module_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write - .av_read (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_read), // .read - .av_readdata (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata - .av_byteenable (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable - .av_waitrequest (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest), // .waitrequest - .av_debugaccess (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_chipselect (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (16), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (4), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (1), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (0), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) onchip_memory_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (onchip_memory_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (onchip_memory_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (onchip_memory_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (onchip_memory_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_byteenable (onchip_memory_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable - .av_chipselect (onchip_memory_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_clken (onchip_memory_s1_translator_avalon_anti_slave_0_clken), // .clken - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) leds_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (leds_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (leds_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (leds_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (leds_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (leds_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (leds_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (leds_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (leds_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_chipselect (leds_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (1), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (1), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) jtag_uart_avalon_jtag_slave_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write - .av_read (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read - .av_readdata (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata - .av_waitrequest (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest - .av_chipselect (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) ledrs_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (ledrs_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (ledrs_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (ledrs_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (ledrs_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_chipselect (ledrs_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) switches_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (switches_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (switches_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (switches_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (switches_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (switches_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_readdata (switches_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_write (), // (terminated) - .av_read (), // (terminated) - .av_writedata (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_chipselect (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) push_switches_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (push_switches_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_readdata (push_switches_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_write (), // (terminated) - .av_read (), // (terminated) - .av_writedata (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_chipselect (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) hex0_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (hex0_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (hex0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (hex0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (hex0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (hex0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (hex0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (hex0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (hex0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (hex0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (hex0_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (hex0_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (hex0_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (hex0_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_chipselect (hex0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) hex1_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (hex1_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (hex1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (hex1_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (hex1_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (hex1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (hex1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (hex1_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (hex1_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (hex1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (hex1_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (hex1_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (hex1_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (hex1_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_chipselect (hex1_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) hex2_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (hex2_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (hex2_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (hex2_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (hex2_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (hex2_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (hex2_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (hex2_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (hex2_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (hex2_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (hex2_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (hex2_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (hex2_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (hex2_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_chipselect (hex2_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) hex3_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (hex3_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (hex3_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (hex3_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (hex3_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (hex3_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (hex3_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (hex3_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (hex3_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (hex3_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (hex3_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (hex3_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (hex3_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (hex3_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_chipselect (hex3_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) hex4_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (hex4_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (hex4_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (hex4_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (hex4_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (hex4_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (hex4_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (hex4_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (hex4_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (hex4_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (hex4_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (hex4_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (hex4_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (hex4_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_chipselect (hex4_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) hex5_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (hex5_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (hex5_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (hex5_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (hex5_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (hex5_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (hex5_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (hex5_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (hex5_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (hex5_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (hex5_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (hex5_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (hex5_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (hex5_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_chipselect (hex5_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) hex6_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (hex6_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (hex6_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (hex6_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (hex6_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (hex6_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (hex6_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (hex6_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (hex6_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (hex6_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (hex6_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (hex6_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (hex6_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (hex6_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_chipselect (hex6_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) hex7_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (hex7_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (hex7_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (hex7_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (hex7_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (hex7_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (hex7_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (hex7_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (hex7_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (hex7_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (hex7_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (hex7_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (hex7_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (hex7_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_chipselect (hex7_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (8), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (13), - .AV_WRITE_WAIT_CYCLES (13), - .AV_SETUP_WAIT_CYCLES (13), - .AV_DATA_HOLD_CYCLES (13) - ) lcd_16207_0_control_slave_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_write), // .write - .av_read (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_read), // .read - .av_readdata (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_writedata), // .writedata - .av_begintransfer (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_begintransfer), // .begintransfer - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_chipselect (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) lcd_on_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (lcd_on_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (lcd_on_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (lcd_on_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (lcd_on_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_chipselect (lcd_on_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) lcd_blon_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (lcd_blon_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (lcd_blon_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (lcd_blon_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (lcd_blon_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_chipselect (lcd_blon_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_master_agent #( - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_BEGIN_BURST (74), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .PKT_BURST_TYPE_H (71), - .PKT_BURST_TYPE_L (70), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_TRANS_EXCLUSIVE (60), - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_THREAD_ID_H (86), - .PKT_THREAD_ID_L (86), - .PKT_CACHE_H (93), - .PKT_CACHE_L (90), - .PKT_DATA_SIDEBAND_H (73), - .PKT_DATA_SIDEBAND_L (73), - .PKT_QOS_H (75), - .PKT_QOS_L (75), - .PKT_ADDR_SIDEBAND_H (72), - .PKT_ADDR_SIDEBAND_L (72), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .ST_DATA_W (96), - .ST_CHANNEL_W (18), - .AV_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_RSP (0), - .ID (1), - .BURSTWRAP_VALUE (3), - .CACHE_VALUE (0), - .SECURE_ACCESS_BIT (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) nios2_processor_instruction_master_translator_avalon_universal_master_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .av_address (nios2_processor_instruction_master_translator_avalon_universal_master_0_address), // av.address - .av_write (nios2_processor_instruction_master_translator_avalon_universal_master_0_write), // .write - .av_read (nios2_processor_instruction_master_translator_avalon_universal_master_0_read), // .read - .av_writedata (nios2_processor_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata - .av_readdata (nios2_processor_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata - .av_waitrequest (nios2_processor_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest - .av_readdatavalid (nios2_processor_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid - .av_byteenable (nios2_processor_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable - .av_burstcount (nios2_processor_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount - .av_debugaccess (nios2_processor_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess - .av_lock (nios2_processor_instruction_master_translator_avalon_universal_master_0_lock), // .lock - .cp_valid (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid - .cp_data (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data - .cp_startofpacket (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket - .cp_endofpacket (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket - .cp_ready (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready - .rp_valid (rsp_xbar_mux_src_valid), // rp.valid - .rp_data (rsp_xbar_mux_src_data), // .data - .rp_channel (rsp_xbar_mux_src_channel), // .channel - .rp_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket - .rp_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket - .rp_ready (rsp_xbar_mux_src_ready), // .ready - .av_response (), // (terminated) - .av_writeresponserequest (1'b0), // (terminated) - .av_writeresponsevalid () // (terminated) - ); - - altera_merlin_master_agent #( - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_BEGIN_BURST (74), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .PKT_BURST_TYPE_H (71), - .PKT_BURST_TYPE_L (70), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_TRANS_EXCLUSIVE (60), - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_THREAD_ID_H (86), - .PKT_THREAD_ID_L (86), - .PKT_CACHE_H (93), - .PKT_CACHE_L (90), - .PKT_DATA_SIDEBAND_H (73), - .PKT_DATA_SIDEBAND_L (73), - .PKT_QOS_H (75), - .PKT_QOS_L (75), - .PKT_ADDR_SIDEBAND_H (72), - .PKT_ADDR_SIDEBAND_L (72), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .ST_DATA_W (96), - .ST_CHANNEL_W (18), - .AV_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_RSP (0), - .ID (0), - .BURSTWRAP_VALUE (7), - .CACHE_VALUE (0), - .SECURE_ACCESS_BIT (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) nios2_processor_data_master_translator_avalon_universal_master_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .av_address (nios2_processor_data_master_translator_avalon_universal_master_0_address), // av.address - .av_write (nios2_processor_data_master_translator_avalon_universal_master_0_write), // .write - .av_read (nios2_processor_data_master_translator_avalon_universal_master_0_read), // .read - .av_writedata (nios2_processor_data_master_translator_avalon_universal_master_0_writedata), // .writedata - .av_readdata (nios2_processor_data_master_translator_avalon_universal_master_0_readdata), // .readdata - .av_waitrequest (nios2_processor_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest - .av_readdatavalid (nios2_processor_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid - .av_byteenable (nios2_processor_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable - .av_burstcount (nios2_processor_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount - .av_debugaccess (nios2_processor_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess - .av_lock (nios2_processor_data_master_translator_avalon_universal_master_0_lock), // .lock - .cp_valid (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid - .cp_data (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data - .cp_startofpacket (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket - .cp_endofpacket (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket - .cp_ready (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready - .rp_valid (rsp_xbar_mux_001_src_valid), // rp.valid - .rp_data (rsp_xbar_mux_001_src_data), // .data - .rp_channel (rsp_xbar_mux_001_src_channel), // .channel - .rp_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket - .rp_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket - .rp_ready (rsp_xbar_mux_001_src_ready), // .ready - .av_response (), // (terminated) - .av_writeresponserequest (1'b0), // (terminated) - .av_writeresponsevalid () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_mux_src_ready), // cp.ready - .cp_valid (cmd_xbar_mux_src_valid), // .valid - .cp_data (cmd_xbar_mux_src_data), // .data - .cp_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_mux_src_channel), // .channel - .rf_sink_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) onchip_memory_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_mux_001_src_ready), // cp.ready - .cp_valid (cmd_xbar_mux_001_src_valid), // .valid - .cp_data (cmd_xbar_mux_001_src_data), // .data - .cp_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_mux_001_src_channel), // .channel - .rf_sink_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) leds_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (leds_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (leds_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (leds_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (leds_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (leds_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (leds_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (leds_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src2_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src2_valid), // .valid - .cp_data (cmd_xbar_demux_001_src2_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src2_channel), // .channel - .rf_sink_ready (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src3_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src3_valid), // .valid - .cp_data (cmd_xbar_demux_001_src3_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src3_channel), // .channel - .rf_sink_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) ledrs_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src4_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src4_valid), // .valid - .cp_data (cmd_xbar_demux_001_src4_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src4_channel), // .channel - .rf_sink_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) switches_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (switches_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (switches_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (switches_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (switches_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (switches_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (switches_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (switches_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src5_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src5_valid), // .valid - .cp_data (cmd_xbar_demux_001_src5_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src5_channel), // .channel - .rf_sink_ready (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) push_switches_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src6_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src6_valid), // .valid - .cp_data (cmd_xbar_demux_001_src6_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src6_channel), // .channel - .rf_sink_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) hex0_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (hex0_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (hex0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (hex0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (hex0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (hex0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (hex0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (hex0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (hex0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (hex0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (hex0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src7_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src7_valid), // .valid - .cp_data (cmd_xbar_demux_001_src7_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src7_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src7_channel), // .channel - .rf_sink_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) hex1_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (hex1_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (hex1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (hex1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (hex1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (hex1_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (hex1_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (hex1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (hex1_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (hex1_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (hex1_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src8_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src8_valid), // .valid - .cp_data (cmd_xbar_demux_001_src8_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src8_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src8_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src8_channel), // .channel - .rf_sink_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) hex2_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (hex2_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (hex2_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (hex2_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (hex2_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (hex2_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (hex2_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (hex2_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (hex2_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (hex2_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (hex2_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src9_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src9_valid), // .valid - .cp_data (cmd_xbar_demux_001_src9_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src9_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src9_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src9_channel), // .channel - .rf_sink_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) hex3_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (hex3_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (hex3_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (hex3_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (hex3_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (hex3_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (hex3_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (hex3_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (hex3_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (hex3_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (hex3_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src10_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src10_valid), // .valid - .cp_data (cmd_xbar_demux_001_src10_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src10_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src10_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src10_channel), // .channel - .rf_sink_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) hex4_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (hex4_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (hex4_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (hex4_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (hex4_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (hex4_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (hex4_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (hex4_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (hex4_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (hex4_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (hex4_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src11_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src11_valid), // .valid - .cp_data (cmd_xbar_demux_001_src11_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src11_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src11_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src11_channel), // .channel - .rf_sink_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) hex5_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (hex5_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (hex5_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (hex5_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (hex5_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (hex5_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (hex5_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (hex5_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (hex5_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (hex5_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (hex5_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src12_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src12_valid), // .valid - .cp_data (cmd_xbar_demux_001_src12_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src12_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src12_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src12_channel), // .channel - .rf_sink_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) hex6_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (hex6_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (hex6_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (hex6_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (hex6_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (hex6_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (hex6_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (hex6_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (hex6_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (hex6_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (hex6_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src13_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src13_valid), // .valid - .cp_data (cmd_xbar_demux_001_src13_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src13_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src13_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src13_channel), // .channel - .rf_sink_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) hex7_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (hex7_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (hex7_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (hex7_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (hex7_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (hex7_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (hex7_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (hex7_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (hex7_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (hex7_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (hex7_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src14_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src14_valid), // .valid - .cp_data (cmd_xbar_demux_001_src14_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src14_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src14_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src14_channel), // .channel - .rf_sink_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src15_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src15_valid), // .valid - .cp_data (cmd_xbar_demux_001_src15_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src15_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src15_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src15_channel), // .channel - .rf_sink_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) lcd_on_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src16_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src16_valid), // .valid - .cp_data (cmd_xbar_demux_001_src16_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src16_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src16_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src16_channel), // .channel - .rf_sink_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) lcd_blon_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src17_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src17_valid), // .valid - .cp_data (cmd_xbar_demux_001_src17_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src17_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src17_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src17_channel), // .channel - .rf_sink_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - nios_system_addr_router addr_router ( - .sink_ready (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready - .sink_valid (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid - .sink_data (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data - .sink_startofpacket (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket - .sink_endofpacket (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (addr_router_src_ready), // src.ready - .src_valid (addr_router_src_valid), // .valid - .src_data (addr_router_src_data), // .data - .src_channel (addr_router_src_channel), // .channel - .src_startofpacket (addr_router_src_startofpacket), // .startofpacket - .src_endofpacket (addr_router_src_endofpacket) // .endofpacket - ); - - nios_system_addr_router_001 addr_router_001 ( - .sink_ready (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready - .sink_valid (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid - .sink_data (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data - .sink_startofpacket (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket - .sink_endofpacket (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (addr_router_001_src_ready), // src.ready - .src_valid (addr_router_001_src_valid), // .valid - .src_data (addr_router_001_src_data), // .data - .src_channel (addr_router_001_src_channel), // .channel - .src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket - .src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket - ); - - nios_system_id_router id_router ( - .sink_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_src_ready), // src.ready - .src_valid (id_router_src_valid), // .valid - .src_data (id_router_src_data), // .data - .src_channel (id_router_src_channel), // .channel - .src_startofpacket (id_router_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_src_endofpacket) // .endofpacket - ); - - nios_system_id_router id_router_001 ( - .sink_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_001_src_ready), // src.ready - .src_valid (id_router_001_src_valid), // .valid - .src_data (id_router_001_src_data), // .data - .src_channel (id_router_001_src_channel), // .channel - .src_startofpacket (id_router_001_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_001_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_002 ( - .sink_ready (leds_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (leds_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (leds_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_002_src_ready), // src.ready - .src_valid (id_router_002_src_valid), // .valid - .src_data (id_router_002_src_data), // .data - .src_channel (id_router_002_src_channel), // .channel - .src_startofpacket (id_router_002_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_002_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_003 ( - .sink_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_003_src_ready), // src.ready - .src_valid (id_router_003_src_valid), // .valid - .src_data (id_router_003_src_data), // .data - .src_channel (id_router_003_src_channel), // .channel - .src_startofpacket (id_router_003_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_003_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_004 ( - .sink_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_004_src_ready), // src.ready - .src_valid (id_router_004_src_valid), // .valid - .src_data (id_router_004_src_data), // .data - .src_channel (id_router_004_src_channel), // .channel - .src_startofpacket (id_router_004_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_004_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_005 ( - .sink_ready (switches_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (switches_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (switches_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_005_src_ready), // src.ready - .src_valid (id_router_005_src_valid), // .valid - .src_data (id_router_005_src_data), // .data - .src_channel (id_router_005_src_channel), // .channel - .src_startofpacket (id_router_005_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_005_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_006 ( - .sink_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_006_src_ready), // src.ready - .src_valid (id_router_006_src_valid), // .valid - .src_data (id_router_006_src_data), // .data - .src_channel (id_router_006_src_channel), // .channel - .src_startofpacket (id_router_006_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_006_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_007 ( - .sink_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (hex0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_007_src_ready), // src.ready - .src_valid (id_router_007_src_valid), // .valid - .src_data (id_router_007_src_data), // .data - .src_channel (id_router_007_src_channel), // .channel - .src_startofpacket (id_router_007_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_007_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_008 ( - .sink_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (hex1_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_008_src_ready), // src.ready - .src_valid (id_router_008_src_valid), // .valid - .src_data (id_router_008_src_data), // .data - .src_channel (id_router_008_src_channel), // .channel - .src_startofpacket (id_router_008_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_008_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_009 ( - .sink_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (hex2_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_009_src_ready), // src.ready - .src_valid (id_router_009_src_valid), // .valid - .src_data (id_router_009_src_data), // .data - .src_channel (id_router_009_src_channel), // .channel - .src_startofpacket (id_router_009_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_009_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_010 ( - .sink_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (hex3_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_010_src_ready), // src.ready - .src_valid (id_router_010_src_valid), // .valid - .src_data (id_router_010_src_data), // .data - .src_channel (id_router_010_src_channel), // .channel - .src_startofpacket (id_router_010_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_010_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_011 ( - .sink_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (hex4_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_011_src_ready), // src.ready - .src_valid (id_router_011_src_valid), // .valid - .src_data (id_router_011_src_data), // .data - .src_channel (id_router_011_src_channel), // .channel - .src_startofpacket (id_router_011_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_011_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_012 ( - .sink_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (hex5_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_012_src_ready), // src.ready - .src_valid (id_router_012_src_valid), // .valid - .src_data (id_router_012_src_data), // .data - .src_channel (id_router_012_src_channel), // .channel - .src_startofpacket (id_router_012_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_012_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_013 ( - .sink_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (hex6_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_013_src_ready), // src.ready - .src_valid (id_router_013_src_valid), // .valid - .src_data (id_router_013_src_data), // .data - .src_channel (id_router_013_src_channel), // .channel - .src_startofpacket (id_router_013_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_013_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_014 ( - .sink_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (hex7_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_014_src_ready), // src.ready - .src_valid (id_router_014_src_valid), // .valid - .src_data (id_router_014_src_data), // .data - .src_channel (id_router_014_src_channel), // .channel - .src_startofpacket (id_router_014_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_014_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_015 ( - .sink_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_015_src_ready), // src.ready - .src_valid (id_router_015_src_valid), // .valid - .src_data (id_router_015_src_data), // .data - .src_channel (id_router_015_src_channel), // .channel - .src_startofpacket (id_router_015_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_015_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_016 ( - .sink_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_016_src_ready), // src.ready - .src_valid (id_router_016_src_valid), // .valid - .src_data (id_router_016_src_data), // .data - .src_channel (id_router_016_src_channel), // .channel - .src_startofpacket (id_router_016_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_016_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_017 ( - .sink_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_017_src_ready), // src.ready - .src_valid (id_router_017_src_valid), // .valid - .src_data (id_router_017_src_data), // .data - .src_channel (id_router_017_src_channel), // .channel - .src_startofpacket (id_router_017_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_017_src_endofpacket) // .endofpacket - ); - - altera_reset_controller #( - .NUM_RESET_INPUTS (2), - .OUTPUT_RESET_SYNC_EDGES ("deassert"), - .SYNC_DEPTH (2), - .RESET_REQUEST_PRESENT (1) - ) rst_controller ( - .reset_in0 (~reset_reset_n), // reset_in0.reset - .reset_in1 (nios2_processor_jtag_debug_module_reset_reset), // reset_in1.reset - .clk (clk_clk), // clk.clk - .reset_out (rst_controller_reset_out_reset), // reset_out.reset - .reset_req (rst_controller_reset_out_reset_req), // .reset_req - .reset_in2 (1'b0), // (terminated) - .reset_in3 (1'b0), // (terminated) - .reset_in4 (1'b0), // (terminated) - .reset_in5 (1'b0), // (terminated) - .reset_in6 (1'b0), // (terminated) - .reset_in7 (1'b0), // (terminated) - .reset_in8 (1'b0), // (terminated) - .reset_in9 (1'b0), // (terminated) - .reset_in10 (1'b0), // (terminated) - .reset_in11 (1'b0), // (terminated) - .reset_in12 (1'b0), // (terminated) - .reset_in13 (1'b0), // (terminated) - .reset_in14 (1'b0), // (terminated) - .reset_in15 (1'b0) // (terminated) - ); - - nios_system_cmd_xbar_demux cmd_xbar_demux ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (addr_router_src_ready), // sink.ready - .sink_channel (addr_router_src_channel), // .channel - .sink_data (addr_router_src_data), // .data - .sink_startofpacket (addr_router_src_startofpacket), // .startofpacket - .sink_endofpacket (addr_router_src_endofpacket), // .endofpacket - .sink_valid (addr_router_src_valid), // .valid - .src0_ready (cmd_xbar_demux_src0_ready), // src0.ready - .src0_valid (cmd_xbar_demux_src0_valid), // .valid - .src0_data (cmd_xbar_demux_src0_data), // .data - .src0_channel (cmd_xbar_demux_src0_channel), // .channel - .src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket - .src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket - .src1_ready (cmd_xbar_demux_src1_ready), // src1.ready - .src1_valid (cmd_xbar_demux_src1_valid), // .valid - .src1_data (cmd_xbar_demux_src1_data), // .data - .src1_channel (cmd_xbar_demux_src1_channel), // .channel - .src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket - .src1_endofpacket (cmd_xbar_demux_src1_endofpacket) // .endofpacket - ); - - nios_system_cmd_xbar_demux_001 cmd_xbar_demux_001 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (addr_router_001_src_ready), // sink.ready - .sink_channel (addr_router_001_src_channel), // .channel - .sink_data (addr_router_001_src_data), // .data - .sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket - .sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket - .sink_valid (addr_router_001_src_valid), // .valid - .src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready - .src0_valid (cmd_xbar_demux_001_src0_valid), // .valid - .src0_data (cmd_xbar_demux_001_src0_data), // .data - .src0_channel (cmd_xbar_demux_001_src0_channel), // .channel - .src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket - .src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket - .src1_ready (cmd_xbar_demux_001_src1_ready), // src1.ready - .src1_valid (cmd_xbar_demux_001_src1_valid), // .valid - .src1_data (cmd_xbar_demux_001_src1_data), // .data - .src1_channel (cmd_xbar_demux_001_src1_channel), // .channel - .src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket - .src1_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket - .src2_ready (cmd_xbar_demux_001_src2_ready), // src2.ready - .src2_valid (cmd_xbar_demux_001_src2_valid), // .valid - .src2_data (cmd_xbar_demux_001_src2_data), // .data - .src2_channel (cmd_xbar_demux_001_src2_channel), // .channel - .src2_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket - .src2_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket - .src3_ready (cmd_xbar_demux_001_src3_ready), // src3.ready - .src3_valid (cmd_xbar_demux_001_src3_valid), // .valid - .src3_data (cmd_xbar_demux_001_src3_data), // .data - .src3_channel (cmd_xbar_demux_001_src3_channel), // .channel - .src3_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket - .src3_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket - .src4_ready (cmd_xbar_demux_001_src4_ready), // src4.ready - .src4_valid (cmd_xbar_demux_001_src4_valid), // .valid - .src4_data (cmd_xbar_demux_001_src4_data), // .data - .src4_channel (cmd_xbar_demux_001_src4_channel), // .channel - .src4_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket - .src4_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket - .src5_ready (cmd_xbar_demux_001_src5_ready), // src5.ready - .src5_valid (cmd_xbar_demux_001_src5_valid), // .valid - .src5_data (cmd_xbar_demux_001_src5_data), // .data - .src5_channel (cmd_xbar_demux_001_src5_channel), // .channel - .src5_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket - .src5_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket - .src6_ready (cmd_xbar_demux_001_src6_ready), // src6.ready - .src6_valid (cmd_xbar_demux_001_src6_valid), // .valid - .src6_data (cmd_xbar_demux_001_src6_data), // .data - .src6_channel (cmd_xbar_demux_001_src6_channel), // .channel - .src6_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket - .src6_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket - .src7_ready (cmd_xbar_demux_001_src7_ready), // src7.ready - .src7_valid (cmd_xbar_demux_001_src7_valid), // .valid - .src7_data (cmd_xbar_demux_001_src7_data), // .data - .src7_channel (cmd_xbar_demux_001_src7_channel), // .channel - .src7_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket - .src7_endofpacket (cmd_xbar_demux_001_src7_endofpacket), // .endofpacket - .src8_ready (cmd_xbar_demux_001_src8_ready), // src8.ready - .src8_valid (cmd_xbar_demux_001_src8_valid), // .valid - .src8_data (cmd_xbar_demux_001_src8_data), // .data - .src8_channel (cmd_xbar_demux_001_src8_channel), // .channel - .src8_startofpacket (cmd_xbar_demux_001_src8_startofpacket), // .startofpacket - .src8_endofpacket (cmd_xbar_demux_001_src8_endofpacket), // .endofpacket - .src9_ready (cmd_xbar_demux_001_src9_ready), // src9.ready - .src9_valid (cmd_xbar_demux_001_src9_valid), // .valid - .src9_data (cmd_xbar_demux_001_src9_data), // .data - .src9_channel (cmd_xbar_demux_001_src9_channel), // .channel - .src9_startofpacket (cmd_xbar_demux_001_src9_startofpacket), // .startofpacket - .src9_endofpacket (cmd_xbar_demux_001_src9_endofpacket), // .endofpacket - .src10_ready (cmd_xbar_demux_001_src10_ready), // src10.ready - .src10_valid (cmd_xbar_demux_001_src10_valid), // .valid - .src10_data (cmd_xbar_demux_001_src10_data), // .data - .src10_channel (cmd_xbar_demux_001_src10_channel), // .channel - .src10_startofpacket (cmd_xbar_demux_001_src10_startofpacket), // .startofpacket - .src10_endofpacket (cmd_xbar_demux_001_src10_endofpacket), // .endofpacket - .src11_ready (cmd_xbar_demux_001_src11_ready), // src11.ready - .src11_valid (cmd_xbar_demux_001_src11_valid), // .valid - .src11_data (cmd_xbar_demux_001_src11_data), // .data - .src11_channel (cmd_xbar_demux_001_src11_channel), // .channel - .src11_startofpacket (cmd_xbar_demux_001_src11_startofpacket), // .startofpacket - .src11_endofpacket (cmd_xbar_demux_001_src11_endofpacket), // .endofpacket - .src12_ready (cmd_xbar_demux_001_src12_ready), // src12.ready - .src12_valid (cmd_xbar_demux_001_src12_valid), // .valid - .src12_data (cmd_xbar_demux_001_src12_data), // .data - .src12_channel (cmd_xbar_demux_001_src12_channel), // .channel - .src12_startofpacket (cmd_xbar_demux_001_src12_startofpacket), // .startofpacket - .src12_endofpacket (cmd_xbar_demux_001_src12_endofpacket), // .endofpacket - .src13_ready (cmd_xbar_demux_001_src13_ready), // src13.ready - .src13_valid (cmd_xbar_demux_001_src13_valid), // .valid - .src13_data (cmd_xbar_demux_001_src13_data), // .data - .src13_channel (cmd_xbar_demux_001_src13_channel), // .channel - .src13_startofpacket (cmd_xbar_demux_001_src13_startofpacket), // .startofpacket - .src13_endofpacket (cmd_xbar_demux_001_src13_endofpacket), // .endofpacket - .src14_ready (cmd_xbar_demux_001_src14_ready), // src14.ready - .src14_valid (cmd_xbar_demux_001_src14_valid), // .valid - .src14_data (cmd_xbar_demux_001_src14_data), // .data - .src14_channel (cmd_xbar_demux_001_src14_channel), // .channel - .src14_startofpacket (cmd_xbar_demux_001_src14_startofpacket), // .startofpacket - .src14_endofpacket (cmd_xbar_demux_001_src14_endofpacket), // .endofpacket - .src15_ready (cmd_xbar_demux_001_src15_ready), // src15.ready - .src15_valid (cmd_xbar_demux_001_src15_valid), // .valid - .src15_data (cmd_xbar_demux_001_src15_data), // .data - .src15_channel (cmd_xbar_demux_001_src15_channel), // .channel - .src15_startofpacket (cmd_xbar_demux_001_src15_startofpacket), // .startofpacket - .src15_endofpacket (cmd_xbar_demux_001_src15_endofpacket), // .endofpacket - .src16_ready (cmd_xbar_demux_001_src16_ready), // src16.ready - .src16_valid (cmd_xbar_demux_001_src16_valid), // .valid - .src16_data (cmd_xbar_demux_001_src16_data), // .data - .src16_channel (cmd_xbar_demux_001_src16_channel), // .channel - .src16_startofpacket (cmd_xbar_demux_001_src16_startofpacket), // .startofpacket - .src16_endofpacket (cmd_xbar_demux_001_src16_endofpacket), // .endofpacket - .src17_ready (cmd_xbar_demux_001_src17_ready), // src17.ready - .src17_valid (cmd_xbar_demux_001_src17_valid), // .valid - .src17_data (cmd_xbar_demux_001_src17_data), // .data - .src17_channel (cmd_xbar_demux_001_src17_channel), // .channel - .src17_startofpacket (cmd_xbar_demux_001_src17_startofpacket), // .startofpacket - .src17_endofpacket (cmd_xbar_demux_001_src17_endofpacket) // .endofpacket - ); - - nios_system_cmd_xbar_mux cmd_xbar_mux ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (cmd_xbar_mux_src_ready), // src.ready - .src_valid (cmd_xbar_mux_src_valid), // .valid - .src_data (cmd_xbar_mux_src_data), // .data - .src_channel (cmd_xbar_mux_src_channel), // .channel - .src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket - .src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket - .sink0_ready (cmd_xbar_demux_src0_ready), // sink0.ready - .sink0_valid (cmd_xbar_demux_src0_valid), // .valid - .sink0_channel (cmd_xbar_demux_src0_channel), // .channel - .sink0_data (cmd_xbar_demux_src0_data), // .data - .sink0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket - .sink0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket - .sink1_ready (cmd_xbar_demux_001_src0_ready), // sink1.ready - .sink1_valid (cmd_xbar_demux_001_src0_valid), // .valid - .sink1_channel (cmd_xbar_demux_001_src0_channel), // .channel - .sink1_data (cmd_xbar_demux_001_src0_data), // .data - .sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket - .sink1_endofpacket (cmd_xbar_demux_001_src0_endofpacket) // .endofpacket - ); - - nios_system_cmd_xbar_mux cmd_xbar_mux_001 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (cmd_xbar_mux_001_src_ready), // src.ready - .src_valid (cmd_xbar_mux_001_src_valid), // .valid - .src_data (cmd_xbar_mux_001_src_data), // .data - .src_channel (cmd_xbar_mux_001_src_channel), // .channel - .src_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket - .src_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket - .sink0_ready (cmd_xbar_demux_src1_ready), // sink0.ready - .sink0_valid (cmd_xbar_demux_src1_valid), // .valid - .sink0_channel (cmd_xbar_demux_src1_channel), // .channel - .sink0_data (cmd_xbar_demux_src1_data), // .data - .sink0_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket - .sink0_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket - .sink1_ready (cmd_xbar_demux_001_src1_ready), // sink1.ready - .sink1_valid (cmd_xbar_demux_001_src1_valid), // .valid - .sink1_channel (cmd_xbar_demux_001_src1_channel), // .channel - .sink1_data (cmd_xbar_demux_001_src1_data), // .data - .sink1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket - .sink1_endofpacket (cmd_xbar_demux_001_src1_endofpacket) // .endofpacket - ); - - nios_system_cmd_xbar_demux rsp_xbar_demux ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_src_ready), // sink.ready - .sink_channel (id_router_src_channel), // .channel - .sink_data (id_router_src_data), // .data - .sink_startofpacket (id_router_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_src_endofpacket), // .endofpacket - .sink_valid (id_router_src_valid), // .valid - .src0_ready (rsp_xbar_demux_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_src0_valid), // .valid - .src0_data (rsp_xbar_demux_src0_data), // .data - .src0_channel (rsp_xbar_demux_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket - .src1_ready (rsp_xbar_demux_src1_ready), // src1.ready - .src1_valid (rsp_xbar_demux_src1_valid), // .valid - .src1_data (rsp_xbar_demux_src1_data), // .data - .src1_channel (rsp_xbar_demux_src1_channel), // .channel - .src1_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket - .src1_endofpacket (rsp_xbar_demux_src1_endofpacket) // .endofpacket - ); - - nios_system_cmd_xbar_demux rsp_xbar_demux_001 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_001_src_ready), // sink.ready - .sink_channel (id_router_001_src_channel), // .channel - .sink_data (id_router_001_src_data), // .data - .sink_startofpacket (id_router_001_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_001_src_endofpacket), // .endofpacket - .sink_valid (id_router_001_src_valid), // .valid - .src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_001_src0_valid), // .valid - .src0_data (rsp_xbar_demux_001_src0_data), // .data - .src0_channel (rsp_xbar_demux_001_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket - .src1_ready (rsp_xbar_demux_001_src1_ready), // src1.ready - .src1_valid (rsp_xbar_demux_001_src1_valid), // .valid - .src1_data (rsp_xbar_demux_001_src1_data), // .data - .src1_channel (rsp_xbar_demux_001_src1_channel), // .channel - .src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket - .src1_endofpacket (rsp_xbar_demux_001_src1_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_002 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_002_src_ready), // sink.ready - .sink_channel (id_router_002_src_channel), // .channel - .sink_data (id_router_002_src_data), // .data - .sink_startofpacket (id_router_002_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_002_src_endofpacket), // .endofpacket - .sink_valid (id_router_002_src_valid), // .valid - .src0_ready (rsp_xbar_demux_002_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_002_src0_valid), // .valid - .src0_data (rsp_xbar_demux_002_src0_data), // .data - .src0_channel (rsp_xbar_demux_002_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_002_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_003 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_003_src_ready), // sink.ready - .sink_channel (id_router_003_src_channel), // .channel - .sink_data (id_router_003_src_data), // .data - .sink_startofpacket (id_router_003_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_003_src_endofpacket), // .endofpacket - .sink_valid (id_router_003_src_valid), // .valid - .src0_ready (rsp_xbar_demux_003_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_003_src0_valid), // .valid - .src0_data (rsp_xbar_demux_003_src0_data), // .data - .src0_channel (rsp_xbar_demux_003_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_003_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_004 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_004_src_ready), // sink.ready - .sink_channel (id_router_004_src_channel), // .channel - .sink_data (id_router_004_src_data), // .data - .sink_startofpacket (id_router_004_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_004_src_endofpacket), // .endofpacket - .sink_valid (id_router_004_src_valid), // .valid - .src0_ready (rsp_xbar_demux_004_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_004_src0_valid), // .valid - .src0_data (rsp_xbar_demux_004_src0_data), // .data - .src0_channel (rsp_xbar_demux_004_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_004_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_005 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_005_src_ready), // sink.ready - .sink_channel (id_router_005_src_channel), // .channel - .sink_data (id_router_005_src_data), // .data - .sink_startofpacket (id_router_005_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_005_src_endofpacket), // .endofpacket - .sink_valid (id_router_005_src_valid), // .valid - .src0_ready (rsp_xbar_demux_005_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_005_src0_valid), // .valid - .src0_data (rsp_xbar_demux_005_src0_data), // .data - .src0_channel (rsp_xbar_demux_005_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_006 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_006_src_ready), // sink.ready - .sink_channel (id_router_006_src_channel), // .channel - .sink_data (id_router_006_src_data), // .data - .sink_startofpacket (id_router_006_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_006_src_endofpacket), // .endofpacket - .sink_valid (id_router_006_src_valid), // .valid - .src0_ready (rsp_xbar_demux_006_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_006_src0_valid), // .valid - .src0_data (rsp_xbar_demux_006_src0_data), // .data - .src0_channel (rsp_xbar_demux_006_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_006_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_007 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_007_src_ready), // sink.ready - .sink_channel (id_router_007_src_channel), // .channel - .sink_data (id_router_007_src_data), // .data - .sink_startofpacket (id_router_007_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_007_src_endofpacket), // .endofpacket - .sink_valid (id_router_007_src_valid), // .valid - .src0_ready (rsp_xbar_demux_007_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_007_src0_valid), // .valid - .src0_data (rsp_xbar_demux_007_src0_data), // .data - .src0_channel (rsp_xbar_demux_007_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_007_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_008 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_008_src_ready), // sink.ready - .sink_channel (id_router_008_src_channel), // .channel - .sink_data (id_router_008_src_data), // .data - .sink_startofpacket (id_router_008_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_008_src_endofpacket), // .endofpacket - .sink_valid (id_router_008_src_valid), // .valid - .src0_ready (rsp_xbar_demux_008_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_008_src0_valid), // .valid - .src0_data (rsp_xbar_demux_008_src0_data), // .data - .src0_channel (rsp_xbar_demux_008_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_008_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_009 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_009_src_ready), // sink.ready - .sink_channel (id_router_009_src_channel), // .channel - .sink_data (id_router_009_src_data), // .data - .sink_startofpacket (id_router_009_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_009_src_endofpacket), // .endofpacket - .sink_valid (id_router_009_src_valid), // .valid - .src0_ready (rsp_xbar_demux_009_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_009_src0_valid), // .valid - .src0_data (rsp_xbar_demux_009_src0_data), // .data - .src0_channel (rsp_xbar_demux_009_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_009_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_009_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_010 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_010_src_ready), // sink.ready - .sink_channel (id_router_010_src_channel), // .channel - .sink_data (id_router_010_src_data), // .data - .sink_startofpacket (id_router_010_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_010_src_endofpacket), // .endofpacket - .sink_valid (id_router_010_src_valid), // .valid - .src0_ready (rsp_xbar_demux_010_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_010_src0_valid), // .valid - .src0_data (rsp_xbar_demux_010_src0_data), // .data - .src0_channel (rsp_xbar_demux_010_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_010_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_010_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_011 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_011_src_ready), // sink.ready - .sink_channel (id_router_011_src_channel), // .channel - .sink_data (id_router_011_src_data), // .data - .sink_startofpacket (id_router_011_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_011_src_endofpacket), // .endofpacket - .sink_valid (id_router_011_src_valid), // .valid - .src0_ready (rsp_xbar_demux_011_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_011_src0_valid), // .valid - .src0_data (rsp_xbar_demux_011_src0_data), // .data - .src0_channel (rsp_xbar_demux_011_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_011_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_011_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_012 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_012_src_ready), // sink.ready - .sink_channel (id_router_012_src_channel), // .channel - .sink_data (id_router_012_src_data), // .data - .sink_startofpacket (id_router_012_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_012_src_endofpacket), // .endofpacket - .sink_valid (id_router_012_src_valid), // .valid - .src0_ready (rsp_xbar_demux_012_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_012_src0_valid), // .valid - .src0_data (rsp_xbar_demux_012_src0_data), // .data - .src0_channel (rsp_xbar_demux_012_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_012_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_012_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_013 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_013_src_ready), // sink.ready - .sink_channel (id_router_013_src_channel), // .channel - .sink_data (id_router_013_src_data), // .data - .sink_startofpacket (id_router_013_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_013_src_endofpacket), // .endofpacket - .sink_valid (id_router_013_src_valid), // .valid - .src0_ready (rsp_xbar_demux_013_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_013_src0_valid), // .valid - .src0_data (rsp_xbar_demux_013_src0_data), // .data - .src0_channel (rsp_xbar_demux_013_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_013_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_013_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_014 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_014_src_ready), // sink.ready - .sink_channel (id_router_014_src_channel), // .channel - .sink_data (id_router_014_src_data), // .data - .sink_startofpacket (id_router_014_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_014_src_endofpacket), // .endofpacket - .sink_valid (id_router_014_src_valid), // .valid - .src0_ready (rsp_xbar_demux_014_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_014_src0_valid), // .valid - .src0_data (rsp_xbar_demux_014_src0_data), // .data - .src0_channel (rsp_xbar_demux_014_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_014_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_014_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_015 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_015_src_ready), // sink.ready - .sink_channel (id_router_015_src_channel), // .channel - .sink_data (id_router_015_src_data), // .data - .sink_startofpacket (id_router_015_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_015_src_endofpacket), // .endofpacket - .sink_valid (id_router_015_src_valid), // .valid - .src0_ready (rsp_xbar_demux_015_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_015_src0_valid), // .valid - .src0_data (rsp_xbar_demux_015_src0_data), // .data - .src0_channel (rsp_xbar_demux_015_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_015_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_015_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_016 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_016_src_ready), // sink.ready - .sink_channel (id_router_016_src_channel), // .channel - .sink_data (id_router_016_src_data), // .data - .sink_startofpacket (id_router_016_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_016_src_endofpacket), // .endofpacket - .sink_valid (id_router_016_src_valid), // .valid - .src0_ready (rsp_xbar_demux_016_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_016_src0_valid), // .valid - .src0_data (rsp_xbar_demux_016_src0_data), // .data - .src0_channel (rsp_xbar_demux_016_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_016_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_016_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_017 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_017_src_ready), // sink.ready - .sink_channel (id_router_017_src_channel), // .channel - .sink_data (id_router_017_src_data), // .data - .sink_startofpacket (id_router_017_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_017_src_endofpacket), // .endofpacket - .sink_valid (id_router_017_src_valid), // .valid - .src0_ready (rsp_xbar_demux_017_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_017_src0_valid), // .valid - .src0_data (rsp_xbar_demux_017_src0_data), // .data - .src0_channel (rsp_xbar_demux_017_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_017_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_017_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_mux rsp_xbar_mux ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (rsp_xbar_mux_src_ready), // src.ready - .src_valid (rsp_xbar_mux_src_valid), // .valid - .src_data (rsp_xbar_mux_src_data), // .data - .src_channel (rsp_xbar_mux_src_channel), // .channel - .src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket - .src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket - .sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready - .sink0_valid (rsp_xbar_demux_src0_valid), // .valid - .sink0_channel (rsp_xbar_demux_src0_channel), // .channel - .sink0_data (rsp_xbar_demux_src0_data), // .data - .sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket - .sink0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket - .sink1_ready (rsp_xbar_demux_001_src0_ready), // sink1.ready - .sink1_valid (rsp_xbar_demux_001_src0_valid), // .valid - .sink1_channel (rsp_xbar_demux_001_src0_channel), // .channel - .sink1_data (rsp_xbar_demux_001_src0_data), // .data - .sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket - .sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_mux_001 rsp_xbar_mux_001 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (rsp_xbar_mux_001_src_ready), // src.ready - .src_valid (rsp_xbar_mux_001_src_valid), // .valid - .src_data (rsp_xbar_mux_001_src_data), // .data - .src_channel (rsp_xbar_mux_001_src_channel), // .channel - .src_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket - .src_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket - .sink0_ready (rsp_xbar_demux_src1_ready), // sink0.ready - .sink0_valid (rsp_xbar_demux_src1_valid), // .valid - .sink0_channel (rsp_xbar_demux_src1_channel), // .channel - .sink0_data (rsp_xbar_demux_src1_data), // .data - .sink0_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket - .sink0_endofpacket (rsp_xbar_demux_src1_endofpacket), // .endofpacket - .sink1_ready (rsp_xbar_demux_001_src1_ready), // sink1.ready - .sink1_valid (rsp_xbar_demux_001_src1_valid), // .valid - .sink1_channel (rsp_xbar_demux_001_src1_channel), // .channel - .sink1_data (rsp_xbar_demux_001_src1_data), // .data - .sink1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket - .sink1_endofpacket (rsp_xbar_demux_001_src1_endofpacket), // .endofpacket - .sink2_ready (rsp_xbar_demux_002_src0_ready), // sink2.ready - .sink2_valid (rsp_xbar_demux_002_src0_valid), // .valid - .sink2_channel (rsp_xbar_demux_002_src0_channel), // .channel - .sink2_data (rsp_xbar_demux_002_src0_data), // .data - .sink2_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket - .sink2_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket - .sink3_ready (rsp_xbar_demux_003_src0_ready), // sink3.ready - .sink3_valid (rsp_xbar_demux_003_src0_valid), // .valid - .sink3_channel (rsp_xbar_demux_003_src0_channel), // .channel - .sink3_data (rsp_xbar_demux_003_src0_data), // .data - .sink3_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket - .sink3_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket - .sink4_ready (rsp_xbar_demux_004_src0_ready), // sink4.ready - .sink4_valid (rsp_xbar_demux_004_src0_valid), // .valid - .sink4_channel (rsp_xbar_demux_004_src0_channel), // .channel - .sink4_data (rsp_xbar_demux_004_src0_data), // .data - .sink4_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket - .sink4_endofpacket (rsp_xbar_demux_004_src0_endofpacket), // .endofpacket - .sink5_ready (rsp_xbar_demux_005_src0_ready), // sink5.ready - .sink5_valid (rsp_xbar_demux_005_src0_valid), // .valid - .sink5_channel (rsp_xbar_demux_005_src0_channel), // .channel - .sink5_data (rsp_xbar_demux_005_src0_data), // .data - .sink5_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket - .sink5_endofpacket (rsp_xbar_demux_005_src0_endofpacket), // .endofpacket - .sink6_ready (rsp_xbar_demux_006_src0_ready), // sink6.ready - .sink6_valid (rsp_xbar_demux_006_src0_valid), // .valid - .sink6_channel (rsp_xbar_demux_006_src0_channel), // .channel - .sink6_data (rsp_xbar_demux_006_src0_data), // .data - .sink6_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket - .sink6_endofpacket (rsp_xbar_demux_006_src0_endofpacket), // .endofpacket - .sink7_ready (rsp_xbar_demux_007_src0_ready), // sink7.ready - .sink7_valid (rsp_xbar_demux_007_src0_valid), // .valid - .sink7_channel (rsp_xbar_demux_007_src0_channel), // .channel - .sink7_data (rsp_xbar_demux_007_src0_data), // .data - .sink7_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket - .sink7_endofpacket (rsp_xbar_demux_007_src0_endofpacket), // .endofpacket - .sink8_ready (rsp_xbar_demux_008_src0_ready), // sink8.ready - .sink8_valid (rsp_xbar_demux_008_src0_valid), // .valid - .sink8_channel (rsp_xbar_demux_008_src0_channel), // .channel - .sink8_data (rsp_xbar_demux_008_src0_data), // .data - .sink8_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket - .sink8_endofpacket (rsp_xbar_demux_008_src0_endofpacket), // .endofpacket - .sink9_ready (rsp_xbar_demux_009_src0_ready), // sink9.ready - .sink9_valid (rsp_xbar_demux_009_src0_valid), // .valid - .sink9_channel (rsp_xbar_demux_009_src0_channel), // .channel - .sink9_data (rsp_xbar_demux_009_src0_data), // .data - .sink9_startofpacket (rsp_xbar_demux_009_src0_startofpacket), // .startofpacket - .sink9_endofpacket (rsp_xbar_demux_009_src0_endofpacket), // .endofpacket - .sink10_ready (rsp_xbar_demux_010_src0_ready), // sink10.ready - .sink10_valid (rsp_xbar_demux_010_src0_valid), // .valid - .sink10_channel (rsp_xbar_demux_010_src0_channel), // .channel - .sink10_data (rsp_xbar_demux_010_src0_data), // .data - .sink10_startofpacket (rsp_xbar_demux_010_src0_startofpacket), // .startofpacket - .sink10_endofpacket (rsp_xbar_demux_010_src0_endofpacket), // .endofpacket - .sink11_ready (rsp_xbar_demux_011_src0_ready), // sink11.ready - .sink11_valid (rsp_xbar_demux_011_src0_valid), // .valid - .sink11_channel (rsp_xbar_demux_011_src0_channel), // .channel - .sink11_data (rsp_xbar_demux_011_src0_data), // .data - .sink11_startofpacket (rsp_xbar_demux_011_src0_startofpacket), // .startofpacket - .sink11_endofpacket (rsp_xbar_demux_011_src0_endofpacket), // .endofpacket - .sink12_ready (rsp_xbar_demux_012_src0_ready), // sink12.ready - .sink12_valid (rsp_xbar_demux_012_src0_valid), // .valid - .sink12_channel (rsp_xbar_demux_012_src0_channel), // .channel - .sink12_data (rsp_xbar_demux_012_src0_data), // .data - .sink12_startofpacket (rsp_xbar_demux_012_src0_startofpacket), // .startofpacket - .sink12_endofpacket (rsp_xbar_demux_012_src0_endofpacket), // .endofpacket - .sink13_ready (rsp_xbar_demux_013_src0_ready), // sink13.ready - .sink13_valid (rsp_xbar_demux_013_src0_valid), // .valid - .sink13_channel (rsp_xbar_demux_013_src0_channel), // .channel - .sink13_data (rsp_xbar_demux_013_src0_data), // .data - .sink13_startofpacket (rsp_xbar_demux_013_src0_startofpacket), // .startofpacket - .sink13_endofpacket (rsp_xbar_demux_013_src0_endofpacket), // .endofpacket - .sink14_ready (rsp_xbar_demux_014_src0_ready), // sink14.ready - .sink14_valid (rsp_xbar_demux_014_src0_valid), // .valid - .sink14_channel (rsp_xbar_demux_014_src0_channel), // .channel - .sink14_data (rsp_xbar_demux_014_src0_data), // .data - .sink14_startofpacket (rsp_xbar_demux_014_src0_startofpacket), // .startofpacket - .sink14_endofpacket (rsp_xbar_demux_014_src0_endofpacket), // .endofpacket - .sink15_ready (rsp_xbar_demux_015_src0_ready), // sink15.ready - .sink15_valid (rsp_xbar_demux_015_src0_valid), // .valid - .sink15_channel (rsp_xbar_demux_015_src0_channel), // .channel - .sink15_data (rsp_xbar_demux_015_src0_data), // .data - .sink15_startofpacket (rsp_xbar_demux_015_src0_startofpacket), // .startofpacket - .sink15_endofpacket (rsp_xbar_demux_015_src0_endofpacket), // .endofpacket - .sink16_ready (rsp_xbar_demux_016_src0_ready), // sink16.ready - .sink16_valid (rsp_xbar_demux_016_src0_valid), // .valid - .sink16_channel (rsp_xbar_demux_016_src0_channel), // .channel - .sink16_data (rsp_xbar_demux_016_src0_data), // .data - .sink16_startofpacket (rsp_xbar_demux_016_src0_startofpacket), // .startofpacket - .sink16_endofpacket (rsp_xbar_demux_016_src0_endofpacket), // .endofpacket - .sink17_ready (rsp_xbar_demux_017_src0_ready), // sink17.ready - .sink17_valid (rsp_xbar_demux_017_src0_valid), // .valid - .sink17_channel (rsp_xbar_demux_017_src0_channel), // .channel - .sink17_data (rsp_xbar_demux_017_src0_data), // .data - .sink17_startofpacket (rsp_xbar_demux_017_src0_startofpacket), // .startofpacket - .sink17_endofpacket (rsp_xbar_demux_017_src0_endofpacket) // .endofpacket - ); - - nios_system_irq_mapper irq_mapper ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq - .sender_irq (nios2_processor_d_irq_irq) // sender.irq - ); - -endmodule diff --git a/db/ip/nios_system/nios_system__report.html b/db/ip/nios_system/nios_system__report.html deleted file mode 100644 index 223f088..0000000 --- a/db/ip/nios_system/nios_system__report.html +++ /dev/null @@ -1,4862 +0,0 @@ - - - - - datasheet for nios_system - - - - - - - - -
nios_system -
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2016.12.22.10:07:17Datasheet
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Overview
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  clk_0 nios_system
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Processor -
   - nios2_processor - Nios II 13.0 -
All Components -
   - nios2_processor - altera_nios2_qsys 13.0 -
   - onchip_memory - altera_avalon_onchip_memory2 13.0.1.99.2 -
   - jtag_uart - altera_avalon_jtag_uart 13.0.1.99.2 -
   - LEDs - altera_avalon_pio 13.0.1.99.2 -
   - LEDRs - altera_avalon_pio 13.0.1.99.2 -
   - switches - altera_avalon_pio 13.0.1.99.2 -
   - push_switches - altera_avalon_pio 13.0.1.99.2 -
   - hex0 - altera_avalon_pio 13.0.1.99.2 -
   - hex1 - altera_avalon_pio 13.0.1.99.2 -
   - hex2 - altera_avalon_pio 13.0.1.99.2 -
   - hex3 - altera_avalon_pio 13.0.1.99.2 -
   - hex4 - altera_avalon_pio 13.0.1.99.2 -
   - hex5 - altera_avalon_pio 13.0.1.99.2 -
   - hex6 - altera_avalon_pio 13.0.1.99.2 -
   - hex7 - altera_avalon_pio 13.0.1.99.2 -
   - lcd_16207_0 - altera_avalon_lcd_16207 13.0.1.99.2 -
   - lcd_on - altera_avalon_pio 13.0.1.99.2 -
   - lcd_blon - altera_avalon_pio 13.0.1.99.2 -
-
-
-
Memory Map
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- nios2_processor - -
 data_master instruction_master
  - nios2_processor - -
jtag_debug_module 0x000408000x00040800
  - onchip_memory - -
s1 0x000000000x00000000
  - jtag_uart - -
avalon_jtag_slave 0x00041100
  - LEDs - -
s1 0x000410f0
  - LEDRs - -
s1 0x000410e0
  - switches - -
s1 0x000410d0
  - push_switches - -
s1 0x000410c0
  - hex0 - -
s1 0x000410b0
  - hex1 - -
s1 0x000410a0
  - hex2 - -
s1 0x00041090
  - hex3 - -
s1 0x00041080
  - hex4 - -
s1 0x00041070
  - hex5 - -
s1 0x00041060
  - hex6 - -
s1 0x00041050
  - hex7 - -
s1 0x00041040
  - lcd_16207_0 - -
control_slave 0x00041030
  - lcd_on - -
s1 0x00041010
  - lcd_blon - -
s1 0x00041020
- -
-
-

clk_0

clock_source v13.0 -
-
-
- - - - -
-

Parameters

- - - - - - - - - - - - - - - - - - - - - - - - - -
clockFrequency50000000
clockFrequencyKnowntrue
inputClockFrequency0
resetSynchronousEdgesNONE
deviceFamilyUNKNOWN
generateLegacySimfalse
-
   - - - - -
-

Software Assignments

(none)
-
- -
-
-

nios2_processor

altera_nios2_qsys v13.0 -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- clk_0 - clk  nios2_processor
  clk
clk_reset  
  reset_n
jtag_debug_module_reset   - onchip_memory -
  reset1
instruction_master  
  s1
data_master  
  s1
jtag_debug_module_reset   - jtag_uart -
  reset
d_irq  
  irq
data_master  
  avalon_jtag_slave
jtag_debug_module_reset   - LEDs -
  reset
data_master  
  s1
data_master   - LEDRs -
  s1
jtag_debug_module_reset  
  reset
jtag_debug_module_reset   - switches -
  reset
data_master  
  s1
data_master   - push_switches -
  s1
jtag_debug_module_reset  
  reset
data_master   - hex0 -
  s1
jtag_debug_module_reset  
  reset
data_master   - hex1 -
  s1
jtag_debug_module_reset  
  reset
data_master   - hex2 -
  s1
jtag_debug_module_reset  
  reset
data_master   - hex3 -
  s1
jtag_debug_module_reset  
  reset
data_master   - hex4 -
  s1
jtag_debug_module_reset  
  reset
data_master   - hex5 -
  s1
jtag_debug_module_reset  
  reset
data_master   - hex6 -
  s1
jtag_debug_module_reset  
  reset
data_master   - hex7 -
  s1
jtag_debug_module_reset  
  reset
jtag_debug_module_reset   - lcd_16207_0 -
  reset
data_master  
  control_slave
data_master   - lcd_on -
  s1
jtag_debug_module_reset  
  reset
jtag_debug_module_reset   - lcd_blon -
  reset
data_master  
  s1
-
-
-
- - - - -
-

Parameters

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
setting_showUnpublishedSettingsfalse
setting_showInternalSettingsfalse
setting_preciseSlaveAccessErrorExceptionfalse
setting_preciseIllegalMemAccessExceptionfalse
setting_preciseDivisionErrorExceptionfalse
setting_performanceCounterfalse
setting_illegalMemAccessDetectionfalse
setting_illegalInstructionsTrapfalse
setting_fullWaveformSignalsfalse
setting_extraExceptionInfofalse
setting_exportPCBfalse
setting_debugSimGenfalse
setting_clearXBitsLDNonBypasstrue
setting_bit31BypassDCachetrue
setting_bigEndianfalse
setting_export_large_RAMsfalse
setting_asic_enabledfalse
setting_asic_synopsys_translate_on_offfalse
setting_oci_export_jtag_signalsfalse
setting_bhtIndexPcOnlyfalse
setting_avalonDebugPortPresentfalse
setting_alwaysEncrypttrue
setting_allowFullAddressRangefalse
setting_activateTracetrue
setting_activateTestEndCheckerfalse
setting_activateMonitorstrue
setting_activateModelCheckerfalse
setting_HDLSimCachesClearedtrue
setting_HBreakTestfalse
muldiv_dividerfalse
mpu_useLimitfalse
mpu_enabledfalse
mmu_enabledfalse
mmu_autoAssignTlbPtrSztrue
manuallyAssignCpuIDtrue
debug_triggerArmingtrue
debug_embeddedPLLtrue
debug_debugReqSignalsfalse
debug_assignJtagInstanceIDfalse
dcache_omitDataMasterfalse
cpuResetfalse
is_hardcopy_compatiblefalse
setting_shadowRegisterSets0
mpu_numOfInstRegion8
mpu_numOfDataRegion8
mmu_TLBMissExcOffset0
debug_jtagInstanceID0
resetOffset0
exceptionOffset32
cpuID0
cpuID_stored0
breakOffset32
userDefinedSettings
resetSlaveonchip_memory.s1
mmu_TLBMissExcSlaveNone
exceptionSlaveonchip_memory.s1
breakSlavenios2_processor.jtag_debug_module
setting_perfCounterWidth32
setting_interruptControllerTypeInternal
setting_branchPredictionTypeAutomatic
setting_bhtPtrSz8
muldiv_multiplierTypeEmbeddedMulFast
mpu_minInstRegionSize12
mpu_minDataRegionSize12
mmu_uitlbNumEntries4
mmu_udtlbNumEntries6
mmu_tlbPtrSz7
mmu_tlbNumWays16
mmu_processIDNumBits8
implTiny
icache_size4096
icache_tagramBlockTypeAutomatic
icache_ramBlockTypeAutomatic
icache_numTCIM0
icache_burstTypeNone
dcache_burstsfalse
dcache_victim_buf_implram
debug_levelLevel1
debug_OCIOnchipTrace_128
dcache_size2048
dcache_tagramBlockTypeAutomatic
dcache_ramBlockTypeAutomatic
dcache_numTCDM0
dcache_lineSize32
setting_exportvectorsfalse
setting_ecc_presentfalse
regfile_ramBlockTypeAutomatic
ocimem_ramBlockTypeAutomatic
mmu_ramBlockTypeAutomatic
bht_ramBlockTypeAutomatic
resetAbsoluteAddr0
exceptionAbsoluteAddr32
breakAbsoluteAddr264224
mmu_TLBMissExcAbsAddr0
dcache_bursts_derivedfalse
dcache_size_derived2048
dcache_lineSize_derived32
translate_on "synthesis translate_on"
translate_off "synthesis translate_off"
instAddrWidth19
dataAddrWidth19
tightlyCoupledDataMaster0AddrWidth1
tightlyCoupledDataMaster1AddrWidth1
tightlyCoupledDataMaster2AddrWidth1
tightlyCoupledDataMaster3AddrWidth1
tightlyCoupledInstructionMaster0AddrWidth1
tightlyCoupledInstructionMaster1AddrWidth1
tightlyCoupledInstructionMaster2AddrWidth1
tightlyCoupledInstructionMaster3AddrWidth1
instSlaveMapParam<address-map><slave name='onchip_memory.s1' start='0x0' end='0x32000' /><slave name='nios2_processor.jtag_debug_module' start='0x40800' end='0x41000' /></address-map>
dataSlaveMapParam<address-map><slave name='onchip_memory.s1' start='0x0' end='0x32000' /><slave name='nios2_processor.jtag_debug_module' start='0x40800' end='0x41000' /><slave name='lcd_on.s1' start='0x41010' end='0x41020' /><slave name='lcd_blon.s1' start='0x41020' end='0x41030' /><slave name='lcd_16207_0.control_slave' start='0x41030' end='0x41040' /><slave name='hex7.s1' start='0x41040' end='0x41050' /><slave name='hex6.s1' start='0x41050' end='0x41060' /><slave name='hex5.s1' start='0x41060' end='0x41070' /><slave name='hex4.s1' start='0x41070' end='0x41080' /><slave name='hex3.s1' start='0x41080' end='0x41090' /><slave name='hex2.s1' start='0x41090' end='0x410A0' /><slave name='hex1.s1' start='0x410A0' end='0x410B0' /><slave name='hex0.s1' start='0x410B0' end='0x410C0' /><slave name='push_switches.s1' start='0x410C0' end='0x410D0' /><slave name='switches.s1' start='0x410D0' end='0x410E0' /><slave name='LEDRs.s1' start='0x410E0' end='0x410F0' /><slave name='LEDs.s1' start='0x410F0' end='0x41100' /><slave name='jtag_uart.avalon_jtag_slave' start='0x41100' end='0x41108' /></address-map>
clockFrequency50000000
deviceFamilyNameCYCLONEIVE
internalIrqMaskSystemInfo32
customInstSlavesSystemInfo<info/>
deviceFeaturesSystemInfoADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
tightlyCoupledDataMaster0MapParam
tightlyCoupledDataMaster1MapParam
tightlyCoupledDataMaster2MapParam
tightlyCoupledDataMaster3MapParam
tightlyCoupledInstructionMaster0MapParam
tightlyCoupledInstructionMaster1MapParam
tightlyCoupledInstructionMaster2MapParam
tightlyCoupledInstructionMaster3MapParam
deviceFamilyUNKNOWN
generateLegacySimfalse
-
   - - - - -
-

Software Assignments

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BIG_ENDIAN0
BREAK_ADDR0x00040820
CPU_FREQ50000000u
CPU_ID_SIZE1
CPU_ID_VALUE0x00000000
CPU_IMPLEMENTATION"tiny"
DATA_ADDR_WIDTH19
DCACHE_LINE_SIZE0
DCACHE_LINE_SIZE_LOG20
DCACHE_SIZE0
EXCEPTION_ADDR0x00000020
FLUSHDA_SUPPORTED
HARDWARE_DIVIDE_PRESENT0
HARDWARE_MULTIPLY_PRESENT0
HARDWARE_MULX_PRESENT0
HAS_DEBUG_CORE1
HAS_DEBUG_STUB
HAS_JMPI_INSTRUCTION
ICACHE_LINE_SIZE0
ICACHE_LINE_SIZE_LOG20
ICACHE_SIZE0
INST_ADDR_WIDTH19
RESET_ADDR0x00000000
-
-
- -
-
-

onchip_memory

altera_avalon_onchip_memory2 v13.0.1.99.2 -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- clk_0 - clk  onchip_memory
  clk1
clk_reset  
  reset1
- nios2_processor - jtag_debug_module_reset  
  reset1
instruction_master  
  s1
data_master  
  s1
-
-
-
- - - - -
-

Parameters

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
allowInSystemMemoryContentEditorfalse
blockTypeAUTO
dataWidth32
dualPortfalse
initMemContenttrue
initializationFileNameonchip_mem.hex
instanceIDNONE
memorySize204800
readDuringWriteModeDONT_CARE
simAllowMRAMContentsFilefalse
simMemInitOnlyFilename0
singleClockOperationfalse
slave1Latency1
slave2Latency1
useNonDefaultInitFilefalse
useShallowMemBlocksfalse
writabletrue
autoInitializationFileNamenios_system_onchip_memory
deviceFamilyCYCLONEIVE
deviceFeaturesADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
derived_set_addr_width16
derived_gui_ram_block_typeAutomatic
derived_is_hardcopyfalse
derived_init_file_namenios_system_onchip_memory.hex
generateLegacySimfalse
-
   - - - - -
-

Software Assignments

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE0
CONTENTS_INFO""
DUAL_PORT0
GUI_RAM_BLOCK_TYPEAUTO
INIT_CONTENTS_FILEnios_system_onchip_memory
INIT_MEM_CONTENT1
INSTANCE_IDNONE
NON_DEFAULT_INIT_FILE_ENABLED0
RAM_BLOCK_TYPEAUTO
READ_DURING_WRITE_MODEDONT_CARE
SINGLE_CLOCK_OP0
SIZE_MULTIPLE1
SIZE_VALUE204800
WRITABLE1
-
-
- -
-
-

jtag_uart

altera_avalon_jtag_uart v13.0.1.99.2 -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- nios2_processor - jtag_debug_module_reset  jtag_uart
  reset
d_irq  
  irq
data_master  
  avalon_jtag_slave
- clk_0 - clk_reset  
  reset
clk  
  clk
-
-
-
- - - - -
-

Parameters

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
allowMultipleConnectionsfalse
hubInstanceID0
readBufferDepth64
readIRQThreshold8
simInputCharacterStream
simInteractiveOptionsNO_INTERACTIVE_WINDOWS
useRegistersForReadBufferfalse
useRegistersForWriteBufferfalse
useRelativePathForSimFilefalse
writeBufferDepth64
writeIRQThreshold8
avalonSpec2.0
legacySignalAllowfalse
enableInteractiveInputfalse
enableInteractiveOutputfalse
deviceFamilyUNKNOWN
generateLegacySimfalse
-
   - - - - -
-

Software Assignments

- - - - - - - - - - - - - - - - - -
READ_DEPTH64
READ_THRESHOLD8
WRITE_DEPTH64
WRITE_THRESHOLD8
-
-
- -
-
-

LEDs

altera_avalon_pio v13.0.1.99.2 -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- clk_0 - clk  LEDs
  clk
clk_reset  
  reset
- nios2_processor - jtag_debug_module_reset  
  reset
data_master  
  s1
-
-
-
- - - - -
-

Parameters

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
bitClearingEdgeCapRegfalse
bitModifyingOutRegfalse
captureEdgefalse
directionOutput
edgeTypeRISING
generateIRQfalse
irqTypeLEVEL
resetValue0
simDoTestBenchWiringfalse
simDrivenValue0
width8
clockRate50000000
derived_has_trifalse
derived_has_outtrue
derived_has_infalse
derived_do_test_bench_wiringfalse
derived_capturefalse
derived_edge_typeNONE
derived_irq_typeNONE
derived_has_irqfalse
deviceFamilyUNKNOWN
generateLegacySimfalse
-
   - - - - -
-

Software Assignments

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BIT_CLEARING_EDGE_REGISTER0
BIT_MODIFYING_OUTPUT_REGISTER0
CAPTURE0
DATA_WIDTH8
DO_TEST_BENCH_WIRING0
DRIVEN_SIM_VALUE0
EDGE_TYPENONE
FREQ50000000
HAS_IN0
HAS_OUT1
HAS_TRI0
IRQ_TYPENONE
RESET_VALUE0
-
-
- -
-
-

LEDRs

altera_avalon_pio v13.0.1.99.2 -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- clk_0 - clk  LEDRs
  clk
clk_reset  
  reset
- nios2_processor - data_master  
  s1
jtag_debug_module_reset  
  reset
-
-
-
- - - - -
-

Parameters

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
bitClearingEdgeCapRegfalse
bitModifyingOutRegfalse
captureEdgefalse
directionOutput
edgeTypeRISING
generateIRQfalse
irqTypeLEVEL
resetValue0
simDoTestBenchWiringfalse
simDrivenValue0
width18
clockRate50000000
derived_has_trifalse
derived_has_outtrue
derived_has_infalse
derived_do_test_bench_wiringfalse
derived_capturefalse
derived_edge_typeNONE
derived_irq_typeNONE
derived_has_irqfalse
deviceFamilyUNKNOWN
generateLegacySimfalse
-
   - - - - -
-

Software Assignments

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BIT_CLEARING_EDGE_REGISTER0
BIT_MODIFYING_OUTPUT_REGISTER0
CAPTURE0
DATA_WIDTH18
DO_TEST_BENCH_WIRING0
DRIVEN_SIM_VALUE0
EDGE_TYPENONE
FREQ50000000
HAS_IN0
HAS_OUT1
HAS_TRI0
IRQ_TYPENONE
RESET_VALUE0
-
-
- -
-
-

switches

altera_avalon_pio v13.0.1.99.2 -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- clk_0 - clk  switches
  clk
clk_reset  
  reset
- nios2_processor - jtag_debug_module_reset  
  reset
data_master  
  s1
-
-
-
- - - - -
-

Parameters

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
bitClearingEdgeCapRegfalse
bitModifyingOutRegfalse
captureEdgefalse
directionInput
edgeTypeRISING
generateIRQfalse
irqTypeLEVEL
resetValue0
simDoTestBenchWiringfalse
simDrivenValue0
width18
clockRate50000000
derived_has_trifalse
derived_has_outfalse
derived_has_intrue
derived_do_test_bench_wiringfalse
derived_capturefalse
derived_edge_typeNONE
derived_irq_typeNONE
derived_has_irqfalse
deviceFamilyUNKNOWN
generateLegacySimfalse
-
   - - - - -
-

Software Assignments

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BIT_CLEARING_EDGE_REGISTER0
BIT_MODIFYING_OUTPUT_REGISTER0
CAPTURE0
DATA_WIDTH18
DO_TEST_BENCH_WIRING0
DRIVEN_SIM_VALUE0
EDGE_TYPENONE
FREQ50000000
HAS_IN1
HAS_OUT0
HAS_TRI0
IRQ_TYPENONE
RESET_VALUE0
-
-
- -
-
-

push_switches

altera_avalon_pio v13.0.1.99.2 -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- clk_0 - clk  push_switches
  clk
clk_reset  
  reset
- nios2_processor - data_master  
  s1
jtag_debug_module_reset  
  reset
-
-
-
- - - - -
-

Parameters

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
bitClearingEdgeCapRegfalse
bitModifyingOutRegfalse
captureEdgefalse
directionInput
edgeTypeRISING
generateIRQfalse
irqTypeLEVEL
resetValue0
simDoTestBenchWiringfalse
simDrivenValue0
width3
clockRate50000000
derived_has_trifalse
derived_has_outfalse
derived_has_intrue
derived_do_test_bench_wiringfalse
derived_capturefalse
derived_edge_typeNONE
derived_irq_typeNONE
derived_has_irqfalse
deviceFamilyUNKNOWN
generateLegacySimfalse
-
   - - - - -
-

Software Assignments

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BIT_CLEARING_EDGE_REGISTER0
BIT_MODIFYING_OUTPUT_REGISTER0
CAPTURE0
DATA_WIDTH3
DO_TEST_BENCH_WIRING0
DRIVEN_SIM_VALUE0
EDGE_TYPENONE
FREQ50000000
HAS_IN1
HAS_OUT0
HAS_TRI0
IRQ_TYPENONE
RESET_VALUE0
-
-
- -
-
-

hex0

altera_avalon_pio v13.0.1.99.2 -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- clk_0 - clk  hex0
  clk
clk_reset  
  reset
- nios2_processor - data_master  
  s1
jtag_debug_module_reset  
  reset
-
-
-
- - - - -
-

Parameters

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
bitClearingEdgeCapRegfalse
bitModifyingOutRegfalse
captureEdgefalse
directionOutput
edgeTypeRISING
generateIRQfalse
irqTypeLEVEL
resetValue0
simDoTestBenchWiringfalse
simDrivenValue0
width7
clockRate50000000
derived_has_trifalse
derived_has_outtrue
derived_has_infalse
derived_do_test_bench_wiringfalse
derived_capturefalse
derived_edge_typeNONE
derived_irq_typeNONE
derived_has_irqfalse
deviceFamilyUNKNOWN
generateLegacySimfalse
-
   - - - - -
-

Software Assignments

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BIT_CLEARING_EDGE_REGISTER0
BIT_MODIFYING_OUTPUT_REGISTER0
CAPTURE0
DATA_WIDTH7
DO_TEST_BENCH_WIRING0
DRIVEN_SIM_VALUE0
EDGE_TYPENONE
FREQ50000000
HAS_IN0
HAS_OUT1
HAS_TRI0
IRQ_TYPENONE
RESET_VALUE0
-
-
- -
-
-

hex1

altera_avalon_pio v13.0.1.99.2 -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- clk_0 - clk  hex1
  clk
clk_reset  
  reset
- nios2_processor - data_master  
  s1
jtag_debug_module_reset  
  reset
-
-
-
- - - - -
-

Parameters

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
bitClearingEdgeCapRegfalse
bitModifyingOutRegfalse
captureEdgefalse
directionOutput
edgeTypeRISING
generateIRQfalse
irqTypeLEVEL
resetValue0
simDoTestBenchWiringfalse
simDrivenValue0
width7
clockRate50000000
derived_has_trifalse
derived_has_outtrue
derived_has_infalse
derived_do_test_bench_wiringfalse
derived_capturefalse
derived_edge_typeNONE
derived_irq_typeNONE
derived_has_irqfalse
deviceFamilyUNKNOWN
generateLegacySimfalse
-
   - - - - -
-

Software Assignments

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BIT_CLEARING_EDGE_REGISTER0
BIT_MODIFYING_OUTPUT_REGISTER0
CAPTURE0
DATA_WIDTH7
DO_TEST_BENCH_WIRING0
DRIVEN_SIM_VALUE0
EDGE_TYPENONE
FREQ50000000
HAS_IN0
HAS_OUT1
HAS_TRI0
IRQ_TYPENONE
RESET_VALUE0
-
-
- -
-
-

hex2

altera_avalon_pio v13.0.1.99.2 -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- clk_0 - clk  hex2
  clk
clk_reset  
  reset
- nios2_processor - data_master  
  s1
jtag_debug_module_reset  
  reset
-
-
-
- - - - -
-

Parameters

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
bitClearingEdgeCapRegfalse
bitModifyingOutRegfalse
captureEdgefalse
directionOutput
edgeTypeRISING
generateIRQfalse
irqTypeLEVEL
resetValue0
simDoTestBenchWiringfalse
simDrivenValue0
width7
clockRate50000000
derived_has_trifalse
derived_has_outtrue
derived_has_infalse
derived_do_test_bench_wiringfalse
derived_capturefalse
derived_edge_typeNONE
derived_irq_typeNONE
derived_has_irqfalse
deviceFamilyUNKNOWN
generateLegacySimfalse
-
   - - - - -
-

Software Assignments

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BIT_CLEARING_EDGE_REGISTER0
BIT_MODIFYING_OUTPUT_REGISTER0
CAPTURE0
DATA_WIDTH7
DO_TEST_BENCH_WIRING0
DRIVEN_SIM_VALUE0
EDGE_TYPENONE
FREQ50000000
HAS_IN0
HAS_OUT1
HAS_TRI0
IRQ_TYPENONE
RESET_VALUE0
-
-
- -
-
-

hex3

altera_avalon_pio v13.0.1.99.2 -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- clk_0 - clk  hex3
  clk
clk_reset  
  reset
- nios2_processor - data_master  
  s1
jtag_debug_module_reset  
  reset
-
-
-
- - - - -
-

Parameters

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
bitClearingEdgeCapRegfalse
bitModifyingOutRegfalse
captureEdgefalse
directionOutput
edgeTypeRISING
generateIRQfalse
irqTypeLEVEL
resetValue0
simDoTestBenchWiringfalse
simDrivenValue0
width7
clockRate50000000
derived_has_trifalse
derived_has_outtrue
derived_has_infalse
derived_do_test_bench_wiringfalse
derived_capturefalse
derived_edge_typeNONE
derived_irq_typeNONE
derived_has_irqfalse
deviceFamilyUNKNOWN
generateLegacySimfalse
-
   - - - - -
-

Software Assignments

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BIT_CLEARING_EDGE_REGISTER0
BIT_MODIFYING_OUTPUT_REGISTER0
CAPTURE0
DATA_WIDTH7
DO_TEST_BENCH_WIRING0
DRIVEN_SIM_VALUE0
EDGE_TYPENONE
FREQ50000000
HAS_IN0
HAS_OUT1
HAS_TRI0
IRQ_TYPENONE
RESET_VALUE0
-
-
- -
-
-

hex4

altera_avalon_pio v13.0.1.99.2 -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- clk_0 - clk  hex4
  clk
clk_reset  
  reset
- nios2_processor - data_master  
  s1
jtag_debug_module_reset  
  reset
-
-
-
- - - - -
-

Parameters

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
bitClearingEdgeCapRegfalse
bitModifyingOutRegfalse
captureEdgefalse
directionOutput
edgeTypeRISING
generateIRQfalse
irqTypeLEVEL
resetValue0
simDoTestBenchWiringfalse
simDrivenValue0
width7
clockRate50000000
derived_has_trifalse
derived_has_outtrue
derived_has_infalse
derived_do_test_bench_wiringfalse
derived_capturefalse
derived_edge_typeNONE
derived_irq_typeNONE
derived_has_irqfalse
deviceFamilyUNKNOWN
generateLegacySimfalse
-
   - - - - -
-

Software Assignments

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BIT_CLEARING_EDGE_REGISTER0
BIT_MODIFYING_OUTPUT_REGISTER0
CAPTURE0
DATA_WIDTH7
DO_TEST_BENCH_WIRING0
DRIVEN_SIM_VALUE0
EDGE_TYPENONE
FREQ50000000
HAS_IN0
HAS_OUT1
HAS_TRI0
IRQ_TYPENONE
RESET_VALUE0
-
-
- -
-
-

hex5

altera_avalon_pio v13.0.1.99.2 -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- clk_0 - clk  hex5
  clk
clk_reset  
  reset
- nios2_processor - data_master  
  s1
jtag_debug_module_reset  
  reset
-
-
-
- - - - -
-

Parameters

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
bitClearingEdgeCapRegfalse
bitModifyingOutRegfalse
captureEdgefalse
directionOutput
edgeTypeRISING
generateIRQfalse
irqTypeLEVEL
resetValue0
simDoTestBenchWiringfalse
simDrivenValue0
width7
clockRate50000000
derived_has_trifalse
derived_has_outtrue
derived_has_infalse
derived_do_test_bench_wiringfalse
derived_capturefalse
derived_edge_typeNONE
derived_irq_typeNONE
derived_has_irqfalse
deviceFamilyUNKNOWN
generateLegacySimfalse
-
   - - - - -
-

Software Assignments

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BIT_CLEARING_EDGE_REGISTER0
BIT_MODIFYING_OUTPUT_REGISTER0
CAPTURE0
DATA_WIDTH7
DO_TEST_BENCH_WIRING0
DRIVEN_SIM_VALUE0
EDGE_TYPENONE
FREQ50000000
HAS_IN0
HAS_OUT1
HAS_TRI0
IRQ_TYPENONE
RESET_VALUE0
-
-
- -
-
-

hex6

altera_avalon_pio v13.0.1.99.2 -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- clk_0 - clk  hex6
  clk
clk_reset  
  reset
- nios2_processor - data_master  
  s1
jtag_debug_module_reset  
  reset
-
-
-
- - - - -
-

Parameters

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
bitClearingEdgeCapRegfalse
bitModifyingOutRegfalse
captureEdgefalse
directionOutput
edgeTypeRISING
generateIRQfalse
irqTypeLEVEL
resetValue0
simDoTestBenchWiringfalse
simDrivenValue0
width7
clockRate50000000
derived_has_trifalse
derived_has_outtrue
derived_has_infalse
derived_do_test_bench_wiringfalse
derived_capturefalse
derived_edge_typeNONE
derived_irq_typeNONE
derived_has_irqfalse
deviceFamilyUNKNOWN
generateLegacySimfalse
-
   - - - - -
-

Software Assignments

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BIT_CLEARING_EDGE_REGISTER0
BIT_MODIFYING_OUTPUT_REGISTER0
CAPTURE0
DATA_WIDTH7
DO_TEST_BENCH_WIRING0
DRIVEN_SIM_VALUE0
EDGE_TYPENONE
FREQ50000000
HAS_IN0
HAS_OUT1
HAS_TRI0
IRQ_TYPENONE
RESET_VALUE0
-
-
- -
-
-

hex7

altera_avalon_pio v13.0.1.99.2 -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- clk_0 - clk  hex7
  clk
clk_reset  
  reset
- nios2_processor - data_master  
  s1
jtag_debug_module_reset  
  reset
-
-
-
- - - - -
-

Parameters

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
bitClearingEdgeCapRegfalse
bitModifyingOutRegfalse
captureEdgefalse
directionOutput
edgeTypeRISING
generateIRQfalse
irqTypeLEVEL
resetValue0
simDoTestBenchWiringfalse
simDrivenValue0
width7
clockRate50000000
derived_has_trifalse
derived_has_outtrue
derived_has_infalse
derived_do_test_bench_wiringfalse
derived_capturefalse
derived_edge_typeNONE
derived_irq_typeNONE
derived_has_irqfalse
deviceFamilyUNKNOWN
generateLegacySimfalse
-
   - - - - -
-

Software Assignments

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BIT_CLEARING_EDGE_REGISTER0
BIT_MODIFYING_OUTPUT_REGISTER0
CAPTURE0
DATA_WIDTH7
DO_TEST_BENCH_WIRING0
DRIVEN_SIM_VALUE0
EDGE_TYPENONE
FREQ50000000
HAS_IN0
HAS_OUT1
HAS_TRI0
IRQ_TYPENONE
RESET_VALUE0
-
-
- -
-
-

lcd_16207_0

altera_avalon_lcd_16207 v13.0.1.99.2 -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- clk_0 - clk  lcd_16207_0
  clk
clk_reset  
  reset
- nios2_processor - jtag_debug_module_reset  
  reset
data_master  
  control_slave
-
-
-
- - - - -
-

Parameters

- - - - - - - - - -
deviceFamilyUNKNOWN
generateLegacySimfalse
-
   - - - - -
-

Software Assignments

(none)
-
- -
-
-

lcd_on

altera_avalon_pio v13.0.1.99.2 -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- clk_0 - clk  lcd_on
  clk
clk_reset  
  reset
- nios2_processor - data_master  
  s1
jtag_debug_module_reset  
  reset
-
-
-
- - - - -
-

Parameters

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
bitClearingEdgeCapRegfalse
bitModifyingOutRegfalse
captureEdgefalse
directionOutput
edgeTypeRISING
generateIRQfalse
irqTypeLEVEL
resetValue0
simDoTestBenchWiringfalse
simDrivenValue0
width1
clockRate50000000
derived_has_trifalse
derived_has_outtrue
derived_has_infalse
derived_do_test_bench_wiringfalse
derived_capturefalse
derived_edge_typeNONE
derived_irq_typeNONE
derived_has_irqfalse
deviceFamilyUNKNOWN
generateLegacySimfalse
-
   - - - - -
-

Software Assignments

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BIT_CLEARING_EDGE_REGISTER0
BIT_MODIFYING_OUTPUT_REGISTER0
CAPTURE0
DATA_WIDTH1
DO_TEST_BENCH_WIRING0
DRIVEN_SIM_VALUE0
EDGE_TYPENONE
FREQ50000000
HAS_IN0
HAS_OUT1
HAS_TRI0
IRQ_TYPENONE
RESET_VALUE0
-
-
- -
-
-

lcd_blon

altera_avalon_pio v13.0.1.99.2 -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- clk_0 - clk  lcd_blon
  clk
clk_reset  
  reset
- nios2_processor - jtag_debug_module_reset  
  reset
data_master  
  s1
-
-
-
- - - - -
-

Parameters

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
bitClearingEdgeCapRegfalse
bitModifyingOutRegfalse
captureEdgefalse
directionOutput
edgeTypeRISING
generateIRQfalse
irqTypeLEVEL
resetValue0
simDoTestBenchWiringfalse
simDrivenValue0
width1
clockRate50000000
derived_has_trifalse
derived_has_outtrue
derived_has_infalse
derived_do_test_bench_wiringfalse
derived_capturefalse
derived_edge_typeNONE
derived_irq_typeNONE
derived_has_irqfalse
deviceFamilyUNKNOWN
generateLegacySimfalse
-
   - - - - -
-

Software Assignments

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BIT_CLEARING_EDGE_REGISTER0
BIT_MODIFYING_OUTPUT_REGISTER0
CAPTURE0
DATA_WIDTH1
DO_TEST_BENCH_WIRING0
DRIVEN_SIM_VALUE0
EDGE_TYPENONE
FREQ50000000
HAS_IN0
HAS_OUT1
HAS_TRI0
IRQ_TYPENONE
RESET_VALUE0
-
-
- - - - - -
generation took 0.00 secondsrendering took 0.15 seconds
- - diff --git a/db/ip/nios_system/nios_system__report.xml b/db/ip/nios_system/nios_system__report.xml deleted file mode 100644 index 1cebda8..0000000 --- a/db/ip/nios_system/nios_system__report.xml +++ /dev/null @@ -1,2521 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 0 starting:nios_system "nios_system" - Transform: PipelineBridgeSwap - 19 modules, 75 connections]]> - Transform: ClockCrossingBridgeSwap - Transform: QsysBetaIPSwap - Transform: CustomInstructionTransform - No custom instruction connections, skipping transform - Transform: MMTransform - Transform: TranslatorTransform - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 39 modules, 155 connections]]> - Transform: IDPadTransform - Transform: DomainTransform - Transform merlin_domain_transform not run on matched interfaces nios2_processor.instruction_master and nios2_processor_instruction_master_translator.avalon_anti_master_0 - Transform merlin_domain_transform not run on matched interfaces nios2_processor.data_master and nios2_processor_data_master_translator.avalon_anti_master_0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Transform merlin_domain_transform not run on matched interfaces nios2_processor_jtag_debug_module_translator.avalon_anti_slave_0 and nios2_processor.jtag_debug_module - Transform merlin_domain_transform not run on matched interfaces onchip_memory_s1_translator.avalon_anti_slave_0 and onchip_memory.s1 - Transform merlin_domain_transform not run on matched interfaces LEDs_s1_translator.avalon_anti_slave_0 and LEDs.s1 - Transform merlin_domain_transform not run on matched interfaces jtag_uart_avalon_jtag_slave_translator.avalon_anti_slave_0 and jtag_uart.avalon_jtag_slave - Transform merlin_domain_transform not run on matched interfaces LEDRs_s1_translator.avalon_anti_slave_0 and LEDRs.s1 - Transform merlin_domain_transform not run on matched interfaces switches_s1_translator.avalon_anti_slave_0 and switches.s1 - Transform merlin_domain_transform not run on matched interfaces push_switches_s1_translator.avalon_anti_slave_0 and push_switches.s1 - Transform merlin_domain_transform not run on matched interfaces hex0_s1_translator.avalon_anti_slave_0 and hex0.s1 - Transform merlin_domain_transform not run on matched interfaces hex1_s1_translator.avalon_anti_slave_0 and hex1.s1 - Transform merlin_domain_transform not run on matched interfaces hex2_s1_translator.avalon_anti_slave_0 and hex2.s1 - Transform merlin_domain_transform not run on matched interfaces hex3_s1_translator.avalon_anti_slave_0 and hex3.s1 - Transform merlin_domain_transform not run on matched interfaces hex4_s1_translator.avalon_anti_slave_0 and hex4.s1 - Transform merlin_domain_transform not run on matched interfaces hex5_s1_translator.avalon_anti_slave_0 and hex5.s1 - Transform merlin_domain_transform not run on matched interfaces hex6_s1_translator.avalon_anti_slave_0 and hex6.s1 - Transform merlin_domain_transform not run on matched interfaces hex7_s1_translator.avalon_anti_slave_0 and hex7.s1 - Transform merlin_domain_transform not run on matched interfaces lcd_16207_0_control_slave_translator.avalon_anti_slave_0 and lcd_16207_0.control_slave - Transform merlin_domain_transform not run on matched interfaces lcd_on_s1_translator.avalon_anti_slave_0 and lcd_on.s1 - Transform merlin_domain_transform not run on matched interfaces lcd_blon_s1_translator.avalon_anti_slave_0 and lcd_blon.s1 - 78 modules, 423 connections]]> - Transform: RouterTransform - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 98 modules, 503 connections]]> - Transform: TrafficLimiterTransform - Transform: BurstTransform - Transform: CombinedWidthTransform - Transform: ResetAdaptation - - - - 99 modules, 390 connections]]> - Transform: NetworkToSwitchTransform - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 138 modules, 470 connections]]> - Transform: WidthTransform - Transform: RouterTableTransform - Transform: ClockCrossingTransform - Transform: PipelineTransform - Transform: TrafficLimiterUpdateTransform - 138 modules, 470 connections]]> - Transform: InterruptMapperTransform - - - - 139 modules, 473 connections]]> - Transform: InterruptSyncTransform - Transform: InterruptFanoutTransform - Transform: AvalonStreamingTransform - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - "No matching role found for rst_controller:reset_out:reset_req (reset_req)" - nios_system" reuses altera_nios2_qsys "submodules/nios_system_nios2_processor"]]> - nios_system" reuses altera_avalon_onchip_memory2 "submodules/nios_system_onchip_memory"]]> - nios_system" reuses altera_avalon_jtag_uart "submodules/nios_system_jtag_uart"]]> - nios_system" reuses altera_avalon_pio "submodules/nios_system_LEDs"]]> - nios_system" reuses altera_avalon_pio "submodules/nios_system_LEDRs"]]> - nios_system" reuses altera_avalon_pio "submodules/nios_system_switches"]]> - nios_system" reuses altera_avalon_pio "submodules/nios_system_push_switches"]]> - nios_system" reuses altera_avalon_pio "submodules/nios_system_hex0"]]> - nios_system" reuses altera_avalon_pio "submodules/nios_system_hex0"]]> - nios_system" reuses altera_avalon_pio "submodules/nios_system_hex0"]]> - nios_system" reuses altera_avalon_pio "submodules/nios_system_hex0"]]> - nios_system" reuses altera_avalon_pio "submodules/nios_system_hex0"]]> - nios_system" reuses altera_avalon_pio "submodules/nios_system_hex0"]]> - nios_system" reuses altera_avalon_pio "submodules/nios_system_hex0"]]> - nios_system" reuses altera_avalon_pio "submodules/nios_system_hex0"]]> - nios_system" reuses altera_avalon_lcd_16207 "submodules/nios_system_lcd_16207_0"]]> - nios_system" reuses altera_avalon_pio "submodules/nios_system_lcd_on"]]> - nios_system" reuses altera_avalon_pio "submodules/nios_system_lcd_on"]]> - nios_system" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> - nios_system" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> - nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> - nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> - nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> - nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> - nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> - nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> - nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> - nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> - nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> - nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> - nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> - nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> - nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> - nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> - nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> - nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> - nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> - nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> - nios_system" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> - nios_system" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> - nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> - nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> - nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> - nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> - nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> - nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> - nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> - nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> - nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> - nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> - nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> - nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> - nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> - nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> - nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> - nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> - nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> - nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> - nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> - nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> - nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> - nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> - nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> - nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> - nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> - nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> - nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> - nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> - nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> - nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> - nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> - nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> - nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> - nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> - nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> - nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> - nios_system" reuses altera_merlin_router "submodules/nios_system_addr_router"]]> - nios_system" reuses altera_merlin_router "submodules/nios_system_addr_router_001"]]> - nios_system" reuses altera_merlin_router "submodules/nios_system_id_router"]]> - nios_system" reuses altera_merlin_router "submodules/nios_system_id_router"]]> - nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> - nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> - nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> - nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> - nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> - nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> - nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> - nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> - nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> - nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> - nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> - nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> - nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> - nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> - nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> - nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> - nios_system" reuses altera_reset_controller "submodules/altera_reset_controller"]]> - nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_cmd_xbar_demux"]]> - nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_cmd_xbar_demux_001"]]> - nios_system" reuses altera_merlin_multiplexer "submodules/nios_system_cmd_xbar_mux"]]> - nios_system" reuses altera_merlin_multiplexer "submodules/nios_system_cmd_xbar_mux"]]> - nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_cmd_xbar_demux"]]> - nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_cmd_xbar_demux"]]> - nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> - nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> - nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> - nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> - nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> - nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> - nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> - nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> - nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> - nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> - nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> - nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> - nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> - nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> - nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> - nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> - nios_system" reuses altera_merlin_multiplexer "submodules/nios_system_rsp_xbar_mux"]]> - nios_system" reuses altera_merlin_multiplexer "submodules/nios_system_rsp_xbar_mux_001"]]> - nios_system" reuses altera_irq_mapper "submodules/nios_system_irq_mapper"]]> - queue size: 121 starting:altera_nios2_qsys "submodules/nios_system_nios2_processor" - Starting RTL generation for module 'nios_system_nios2_processor' - Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] - # 2016.12.22 10:07:23 (*) Starting Nios II generation - # 2016.12.22 10:07:23 (*) Checking for plaintext license. - # 2016.12.22 10:07:23 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus - # 2016.12.22 10:07:23 (*) Defaulting to contents of LM_LICENSE_FILE environment variable - # 2016.12.22 10:07:23 (*) LM_LICENSE_FILE environment variable is empty - # 2016.12.22 10:07:23 (*) Plaintext license not found. - # 2016.12.22 10:07:23 (*) No license required to generate encrypted Nios II/e. - # 2016.12.22 10:07:23 (*) Elaborating CPU configuration settings - # 2016.12.22 10:07:23 (*) Creating all objects for CPU - # 2016.12.22 10:07:24 (*) Generating RTL from CPU objects - # 2016.12.22 10:07:24 (*) Creating plain-text RTL - # 2016.12.22 10:07:26 (*) Done Nios II generation - Done RTL generation for module 'nios_system_nios2_processor' - nios_system" instantiated altera_nios2_qsys "nios2_processor"]]> - queue size: 120 starting:altera_avalon_onchip_memory2 "submodules/nios_system_onchip_memory" - Starting RTL generation for module 'nios_system_onchip_memory' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] - Done RTL generation for module 'nios_system_onchip_memory' - nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory"]]> - queue size: 119 starting:altera_avalon_jtag_uart "submodules/nios_system_jtag_uart" - Starting RTL generation for module 'nios_system_jtag_uart' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] - Done RTL generation for module 'nios_system_jtag_uart' - nios_system" instantiated altera_avalon_jtag_uart "jtag_uart"]]> - queue size: 118 starting:altera_avalon_pio "submodules/nios_system_LEDs" - Starting RTL generation for module 'nios_system_LEDs' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] - Done RTL generation for module 'nios_system_LEDs' - nios_system" instantiated altera_avalon_pio "LEDs"]]> - queue size: 117 starting:altera_avalon_pio "submodules/nios_system_LEDRs" - Starting RTL generation for module 'nios_system_LEDRs' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] - Done RTL generation for module 'nios_system_LEDRs' - nios_system" instantiated altera_avalon_pio "LEDRs"]]> - queue size: 116 starting:altera_avalon_pio "submodules/nios_system_switches" - Starting RTL generation for module 'nios_system_switches' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] - Done RTL generation for module 'nios_system_switches' - nios_system" instantiated altera_avalon_pio "switches"]]> - queue size: 115 starting:altera_avalon_pio "submodules/nios_system_push_switches" - Starting RTL generation for module 'nios_system_push_switches' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] - Done RTL generation for module 'nios_system_push_switches' - nios_system" instantiated altera_avalon_pio "push_switches"]]> - queue size: 114 starting:altera_avalon_pio "submodules/nios_system_hex0" - Starting RTL generation for module 'nios_system_hex0' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] - Done RTL generation for module 'nios_system_hex0' - nios_system" instantiated altera_avalon_pio "hex0"]]> - queue size: 106 starting:altera_avalon_lcd_16207 "submodules/nios_system_lcd_16207_0" - Starting RTL generation for module 'nios_system_lcd_16207_0' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 ] - Done RTL generation for module 'nios_system_lcd_16207_0' - nios_system" instantiated altera_avalon_lcd_16207 "lcd_16207_0"]]> - queue size: 105 starting:altera_avalon_pio "submodules/nios_system_lcd_on" - Starting RTL generation for module 'nios_system_lcd_on' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 ] - Done RTL generation for module 'nios_system_lcd_on' - nios_system" instantiated altera_avalon_pio "lcd_on"]]> - queue size: 103 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" - nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator"]]> - queue size: 101 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" - nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator"]]> - queue size: 83 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" - nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent"]]> - queue size: 81 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" - nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent"]]> - queue size: 80 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" - nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo"]]> - queue size: 45 starting:altera_merlin_router "submodules/nios_system_addr_router" - nios_system" instantiated altera_merlin_router "addr_router"]]> - queue size: 44 starting:altera_merlin_router "submodules/nios_system_addr_router_001" - nios_system" instantiated altera_merlin_router "addr_router_001"]]> - queue size: 43 starting:altera_merlin_router "submodules/nios_system_id_router" - nios_system" instantiated altera_merlin_router "id_router"]]> - queue size: 41 starting:altera_merlin_router "submodules/nios_system_id_router_002" - nios_system" instantiated altera_merlin_router "id_router_002"]]> - queue size: 25 starting:altera_reset_controller "submodules/altera_reset_controller" - nios_system" instantiated altera_reset_controller "rst_controller"]]> - queue size: 24 starting:altera_merlin_demultiplexer "submodules/nios_system_cmd_xbar_demux" - nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux"]]> - queue size: 23 starting:altera_merlin_demultiplexer "submodules/nios_system_cmd_xbar_demux_001" - nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001"]]> - queue size: 22 starting:altera_merlin_multiplexer "submodules/nios_system_cmd_xbar_mux" - nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux"]]> - queue size: 18 starting:altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002" - nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002"]]> - queue size: 2 starting:altera_merlin_multiplexer "submodules/nios_system_rsp_xbar_mux" - nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux"]]> - C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv]]> - queue size: 1 starting:altera_merlin_multiplexer "submodules/nios_system_rsp_xbar_mux_001" - nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001"]]> - C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv]]> - queue size: 0 starting:altera_irq_mapper "submodules/nios_system_irq_mapper" - nios_system" instantiated altera_irq_mapper "irq_mapper"]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 121 starting:altera_nios2_qsys "submodules/nios_system_nios2_processor" - Starting RTL generation for module 'nios_system_nios2_processor' - Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] - # 2016.12.22 10:07:23 (*) Starting Nios II generation - # 2016.12.22 10:07:23 (*) Checking for plaintext license. - # 2016.12.22 10:07:23 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus - # 2016.12.22 10:07:23 (*) Defaulting to contents of LM_LICENSE_FILE environment variable - # 2016.12.22 10:07:23 (*) LM_LICENSE_FILE environment variable is empty - # 2016.12.22 10:07:23 (*) Plaintext license not found. - # 2016.12.22 10:07:23 (*) No license required to generate encrypted Nios II/e. - # 2016.12.22 10:07:23 (*) Elaborating CPU configuration settings - # 2016.12.22 10:07:23 (*) Creating all objects for CPU - # 2016.12.22 10:07:24 (*) Generating RTL from CPU objects - # 2016.12.22 10:07:24 (*) Creating plain-text RTL - # 2016.12.22 10:07:26 (*) Done Nios II generation - Done RTL generation for module 'nios_system_nios2_processor' - nios_system" instantiated altera_nios2_qsys "nios2_processor"]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 120 starting:altera_avalon_onchip_memory2 "submodules/nios_system_onchip_memory" - Starting RTL generation for module 'nios_system_onchip_memory' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] - Done RTL generation for module 'nios_system_onchip_memory' - nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory"]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 119 starting:altera_avalon_jtag_uart "submodules/nios_system_jtag_uart" - Starting RTL generation for module 'nios_system_jtag_uart' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] - Done RTL generation for module 'nios_system_jtag_uart' - nios_system" instantiated altera_avalon_jtag_uart "jtag_uart"]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 118 starting:altera_avalon_pio "submodules/nios_system_LEDs" - Starting RTL generation for module 'nios_system_LEDs' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] - Done RTL generation for module 'nios_system_LEDs' - nios_system" instantiated altera_avalon_pio "LEDs"]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 117 starting:altera_avalon_pio "submodules/nios_system_LEDRs" - Starting RTL generation for module 'nios_system_LEDRs' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] - Done RTL generation for module 'nios_system_LEDRs' - nios_system" instantiated altera_avalon_pio "LEDRs"]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 116 starting:altera_avalon_pio "submodules/nios_system_switches" - Starting RTL generation for module 'nios_system_switches' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] - Done RTL generation for module 'nios_system_switches' - nios_system" instantiated altera_avalon_pio "switches"]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 115 starting:altera_avalon_pio "submodules/nios_system_push_switches" - Starting RTL generation for module 'nios_system_push_switches' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] - Done RTL generation for module 'nios_system_push_switches' - nios_system" instantiated altera_avalon_pio "push_switches"]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 114 starting:altera_avalon_pio "submodules/nios_system_hex0" - Starting RTL generation for module 'nios_system_hex0' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] - Done RTL generation for module 'nios_system_hex0' - nios_system" instantiated altera_avalon_pio "hex0"]]> - - - - - - - - - - - - - - queue size: 106 starting:altera_avalon_lcd_16207 "submodules/nios_system_lcd_16207_0" - Starting RTL generation for module 'nios_system_lcd_16207_0' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 ] - Done RTL generation for module 'nios_system_lcd_16207_0' - nios_system" instantiated altera_avalon_lcd_16207 "lcd_16207_0"]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 105 starting:altera_avalon_pio "submodules/nios_system_lcd_on" - Starting RTL generation for module 'nios_system_lcd_on' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 ] - Done RTL generation for module 'nios_system_lcd_on' - nios_system" instantiated altera_avalon_pio "lcd_on"]]> - - - - - - - - - - - - - - - queue size: 103 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" - nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator"]]> - - - - - - - - - - - - - - queue size: 101 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" - nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator"]]> - - - - - - - - - - - - - - - - - - - queue size: 83 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" - nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent"]]> - - - - - - - - - - - - - - - - - - - - - queue size: 81 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" - nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent"]]> - - - - - - - - - - - - - - - - queue size: 80 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" - nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo"]]> - - - - - - - - - - - - - - - queue size: 45 starting:altera_merlin_router "submodules/nios_system_addr_router" - nios_system" instantiated altera_merlin_router "addr_router"]]> - - - - - - - - - - - - - - - queue size: 44 starting:altera_merlin_router "submodules/nios_system_addr_router_001" - nios_system" instantiated altera_merlin_router "addr_router_001"]]> - - - - - - - - - - - - - - - queue size: 43 starting:altera_merlin_router "submodules/nios_system_id_router" - nios_system" instantiated altera_merlin_router "id_router"]]> - - - - - - - - - - - - - - - queue size: 41 starting:altera_merlin_router "submodules/nios_system_id_router_002" - nios_system" instantiated altera_merlin_router "id_router_002"]]> - - - - - - - - - - - - - - - - - queue size: 25 starting:altera_reset_controller "submodules/altera_reset_controller" - nios_system" instantiated altera_reset_controller "rst_controller"]]> - - - - - - - - - - - - - - - - - - - - - queue size: 24 starting:altera_merlin_demultiplexer "submodules/nios_system_cmd_xbar_demux" - nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux"]]> - - - - - - - - - - - - - - - - - - - - - queue size: 23 starting:altera_merlin_demultiplexer "submodules/nios_system_cmd_xbar_demux_001" - nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001"]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 22 starting:altera_merlin_multiplexer "submodules/nios_system_cmd_xbar_mux" - nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux"]]> - - - - - - - - - - - - - - - - - - - - - queue size: 18 starting:altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002" - nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002"]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 2 starting:altera_merlin_multiplexer "submodules/nios_system_rsp_xbar_mux" - nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux"]]> - C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 1 starting:altera_merlin_multiplexer "submodules/nios_system_rsp_xbar_mux_001" - nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001"]]> - C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv]]> - - - - - - - - - - - - - - - - - - queue size: 0 starting:altera_irq_mapper "submodules/nios_system_irq_mapper" - nios_system" instantiated altera_irq_mapper "irq_mapper"]]> - - - diff --git a/db/ip/nios_system/submodules/altera_avalon_sc_fifo.v b/db/ip/nios_system/submodules/altera_avalon_sc_fifo.v deleted file mode 100644 index 94e2787..0000000 --- a/db/ip/nios_system/submodules/altera_avalon_sc_fifo.v +++ /dev/null @@ -1,877 +0,0 @@ -// ----------------------------------------------------------- -// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your -// use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any -// output files any of the foregoing (including device programming or -// simulation files), and any associated documentation or information are -// expressly subject to the terms and conditions of the Altera Program -// License Subscription Agreement or other applicable license agreement, -// including, without limitation, that your use is for the sole purpose -// of programming logic devices manufactured by Altera and sold by Altera -// or its authorized distributors. Please refer to the applicable -// agreement for further details. -// -// Description: Single clock Avalon-ST FIFO. -// ----------------------------------------------------------- - -`timescale 1 ns / 1 ns - - -//altera message_off 10036 -module altera_avalon_sc_fifo -#( - // -------------------------------------------------- - // Parameters - // -------------------------------------------------- - parameter SYMBOLS_PER_BEAT = 1, - parameter BITS_PER_SYMBOL = 8, - parameter FIFO_DEPTH = 16, - parameter CHANNEL_WIDTH = 0, - parameter ERROR_WIDTH = 0, - parameter USE_PACKETS = 0, - parameter USE_FILL_LEVEL = 0, - parameter USE_STORE_FORWARD = 0, - parameter USE_ALMOST_FULL_IF = 0, - parameter USE_ALMOST_EMPTY_IF = 0, - - // -------------------------------------------------- - // Empty latency is defined as the number of cycles - // required for a write to deassert the empty flag. - // For example, a latency of 1 means that the empty - // flag is deasserted on the cycle after a write. - // - // Another way to think of it is the latency for a - // write to propagate to the output. - // - // An empty latency of 0 implies lookahead, which is - // only implemented for the register-based FIFO. - // -------------------------------------------------- - parameter EMPTY_LATENCY = 3, - parameter USE_MEMORY_BLOCKS = 1, - - // -------------------------------------------------- - // Internal Parameters - // -------------------------------------------------- - parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL, - parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT) -) -( - // -------------------------------------------------- - // Ports - // -------------------------------------------------- - input clk, - input reset, - - input [DATA_WIDTH-1: 0] in_data, - input in_valid, - input in_startofpacket, - input in_endofpacket, - input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty, - input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error, - input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel, - output in_ready, - - output [DATA_WIDTH-1 : 0] out_data, - output reg out_valid, - output out_startofpacket, - output out_endofpacket, - output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty, - output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error, - output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel, - input out_ready, - - input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address, - input csr_write, - input csr_read, - input [31 : 0] csr_writedata, - output reg [31 : 0] csr_readdata, - - output wire almost_full_data, - output wire almost_empty_data -); - - // -------------------------------------------------- - // Local Parameters - // -------------------------------------------------- - localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH); - localparam DEPTH = FIFO_DEPTH; - localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH; - localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ? - 2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH: - DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH; - - // -------------------------------------------------- - // Internal Signals - // -------------------------------------------------- - genvar i; - - reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0]; - reg [ADDR_WIDTH-1 : 0] wr_ptr; - reg [ADDR_WIDTH-1 : 0] rd_ptr; - reg [DEPTH-1 : 0] mem_used; - - wire [ADDR_WIDTH-1 : 0] next_wr_ptr; - wire [ADDR_WIDTH-1 : 0] next_rd_ptr; - wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr; - wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr; - - wire [ADDR_WIDTH-1 : 0] mem_rd_ptr; - - wire read; - wire write; - - reg empty; - reg next_empty; - reg full; - reg next_full; - - wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals; - wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals; - wire [PAYLOAD_WIDTH-1 : 0] in_payload; - reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload; - reg [PAYLOAD_WIDTH-1 : 0] out_payload; - - reg internal_out_valid; - wire internal_out_ready; - - reg [ADDR_WIDTH : 0] fifo_fill_level; - reg [ADDR_WIDTH : 0] fill_level; - - reg [ADDR_WIDTH-1 : 0] sop_ptr = 0; - reg [23:0] almost_full_threshold; - reg [23:0] almost_empty_threshold; - reg [23:0] cut_through_threshold; - reg [15:0] pkt_cnt; - reg [15:0] pkt_cnt_r; - reg [15:0] pkt_cnt_plusone; - reg [15:0] pkt_cnt_minusone; - reg drop_on_error_en; - reg error_in_pkt; - reg pkt_has_started; - reg sop_has_left_fifo; - reg fifo_too_small_r; - reg pkt_cnt_eq_zero; - reg pkt_cnt_eq_one; - reg pkt_cnt_changed; - - wire wait_for_threshold; - reg pkt_mode; - wire wait_for_pkt; - wire ok_to_forward; - wire in_pkt_eop_arrive; - wire out_pkt_leave; - wire in_pkt_start; - wire in_pkt_error; - wire drop_on_error; - wire fifo_too_small; - wire out_pkt_sop_leave; - wire [31:0] max_fifo_size; - reg fifo_fill_level_lt_cut_through_threshold; - - // -------------------------------------------------- - // Define Payload - // - // Icky part where we decide which signals form the - // payload to the FIFO with generate blocks. - // -------------------------------------------------- - generate - if (EMPTY_WIDTH > 0) begin - assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty}; - assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals; - end - else begin - assign out_empty = in_error; - assign in_packet_signals = {in_startofpacket, in_endofpacket}; - assign {out_startofpacket, out_endofpacket} = out_packet_signals; - end - endgenerate - - generate - if (USE_PACKETS) begin - if (ERROR_WIDTH > 0) begin - if (CHANNEL_WIDTH > 0) begin - assign in_payload = {in_packet_signals, in_data, in_error, in_channel}; - assign {out_packet_signals, out_data, out_error, out_channel} = out_payload; - end - else begin - assign out_channel = in_channel; - assign in_payload = {in_packet_signals, in_data, in_error}; - assign {out_packet_signals, out_data, out_error} = out_payload; - end - end - else begin - assign out_error = in_error; - if (CHANNEL_WIDTH > 0) begin - assign in_payload = {in_packet_signals, in_data, in_channel}; - assign {out_packet_signals, out_data, out_channel} = out_payload; - end - else begin - assign out_channel = in_channel; - assign in_payload = {in_packet_signals, in_data}; - assign {out_packet_signals, out_data} = out_payload; - end - end - end - else begin - assign out_packet_signals = 0; - if (ERROR_WIDTH > 0) begin - if (CHANNEL_WIDTH > 0) begin - assign in_payload = {in_data, in_error, in_channel}; - assign {out_data, out_error, out_channel} = out_payload; - end - else begin - assign out_channel = in_channel; - assign in_payload = {in_data, in_error}; - assign {out_data, out_error} = out_payload; - end - end - else begin - assign out_error = in_error; - if (CHANNEL_WIDTH > 0) begin - assign in_payload = {in_data, in_channel}; - assign {out_data, out_channel} = out_payload; - end - else begin - assign out_channel = in_channel; - assign in_payload = in_data; - assign out_data = out_payload; - end - end - end - endgenerate - - // -------------------------------------------------- - // Memory-based FIFO storage - // - // To allow a ready latency of 0, the read index is - // obtained from the next read pointer and memory - // outputs are unregistered. - // - // If the empty latency is 1, we infer bypass logic - // around the memory so writes propagate to the - // outputs on the next cycle. - // - // Do not change the way this is coded: Quartus needs - // a perfect match to the template, and any attempt to - // refactor the two always blocks into one will break - // memory inference. - // -------------------------------------------------- - generate if (USE_MEMORY_BLOCKS == 1) begin - - if (EMPTY_LATENCY == 1) begin - - always @(posedge clk) begin - if (in_valid && in_ready) - mem[wr_ptr] = in_payload; - - internal_out_payload = mem[mem_rd_ptr]; - end - - end else begin - - always @(posedge clk) begin - if (in_valid && in_ready) - mem[wr_ptr] <= in_payload; - - internal_out_payload <= mem[mem_rd_ptr]; - end - - end - - assign mem_rd_ptr = next_rd_ptr; - - end else begin - - // -------------------------------------------------- - // Register-based FIFO storage - // - // Uses a shift register as the storage element. Each - // shift register slot has a bit which indicates if - // the slot is occupied (credit to Sam H for the idea). - // The occupancy bits are contiguous and start from the - // lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep - // FIFO. - // - // Each slot is enabled during a read or when it - // is unoccupied. New data is always written to every - // going-to-be-empty slot (we keep track of which ones - // are actually useful with the occupancy bits). On a - // read we shift occupied slots. - // - // The exception is the last slot, which always gets - // new data when it is unoccupied. - // -------------------------------------------------- - for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg - always @(posedge clk or posedge reset) begin - if (reset) begin - mem[i] <= 0; - end - else if (read || !mem_used[i]) begin - if (!mem_used[i+1]) - mem[i] <= in_payload; - else - mem[i] <= mem[i+1]; - end - end - end - - always @(posedge clk, posedge reset) begin - if (reset) begin - mem[DEPTH-1] <= 0; - end - else begin - if (!mem_used[DEPTH-1]) - mem[DEPTH-1] <= in_payload; - - if (DEPTH == 1) begin - if (write) - mem[DEPTH-1] <= in_payload; - end - end - end - - end - endgenerate - - assign read = internal_out_ready && internal_out_valid && ok_to_forward; - assign write = in_ready && in_valid; - - // -------------------------------------------------- - // Pointer Management - // -------------------------------------------------- - generate if (USE_MEMORY_BLOCKS == 1) begin - - assign incremented_wr_ptr = wr_ptr + 1'b1; - assign incremented_rd_ptr = rd_ptr + 1'b1; - assign next_wr_ptr = drop_on_error ? sop_ptr : write ? incremented_wr_ptr : wr_ptr; - assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr; - - always @(posedge clk or posedge reset) begin - if (reset) begin - wr_ptr <= 0; - rd_ptr <= 0; - end - else begin - wr_ptr <= next_wr_ptr; - rd_ptr <= next_rd_ptr; - end - end - - end else begin - - // -------------------------------------------------- - // Shift Register Occupancy Bits - // - // Consider a 4-deep FIFO with 2 entries: 0011 - // On a read and write, do not modify the bits. - // On a write, left-shift the bits to get 0111. - // On a read, right-shift the bits to get 0001. - // - // Also, on a write we set bit0 (the head), while - // clearing the tail on a read. - // -------------------------------------------------- - always @(posedge clk or posedge reset) begin - if (reset) begin - mem_used[0] <= 0; - end - else begin - if (write ^ read) begin - if (read) begin - if (DEPTH > 1) - mem_used[0] <= mem_used[1]; - else - mem_used[0] <= 0; - end - if (write) - mem_used[0] <= 1; - end - end - end - - if (DEPTH > 1) begin - always @(posedge clk or posedge reset) begin - if (reset) begin - mem_used[DEPTH-1] <= 0; - end - else begin - if (write ^ read) begin - mem_used[DEPTH-1] <= 0; - if (write) - mem_used[DEPTH-1] <= mem_used[DEPTH-2]; - end - end - end - end - - for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic - always @(posedge clk, posedge reset) begin - if (reset) begin - mem_used[i] <= 0; - end - else begin - if (write ^ read) begin - if (read) - mem_used[i] <= mem_used[i+1]; - if (write) - mem_used[i] <= mem_used[i-1]; - end - end - end - end - - end - endgenerate - - - // -------------------------------------------------- - // Memory FIFO Status Management - // - // Generates the full and empty signals from the - // pointers. The FIFO is full when the next write - // pointer will be equal to the read pointer after - // a write. Reading from a FIFO clears full. - // - // The FIFO is empty when the next read pointer will - // be equal to the write pointer after a read. Writing - // to a FIFO clears empty. - // - // A simultaneous read and write must not change any of - // the empty or full flags unless there is a drop on error event. - // -------------------------------------------------- - generate if (USE_MEMORY_BLOCKS == 1) begin - - always @* begin - next_full = full; - next_empty = empty; - - if (read && !write) begin - next_full = 1'b0; - - if (incremented_rd_ptr == wr_ptr) - next_empty = 1'b1; - end - - if (write && !read) begin - if (!drop_on_error) - next_empty = 1'b0; - else if (sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo - next_empty = 1'b1; - - if (incremented_wr_ptr == rd_ptr && !drop_on_error) - next_full = 1'b1; - end - - if (write && read && drop_on_error) begin - if (sop_ptr == next_rd_ptr) - next_empty = 1'b1; - end - end - - always @(posedge clk or posedge reset) begin - if (reset) begin - empty <= 1; - full <= 0; - end - else begin - empty <= next_empty; - full <= next_full; - end - end - - end else begin - // -------------------------------------------------- - // Register FIFO Status Management - // - // Full when the tail occupancy bit is 1. Empty when - // the head occupancy bit is 0. - // -------------------------------------------------- - always @* begin - full = mem_used[DEPTH-1]; - empty = !mem_used[0]; - - // ------------------------------------------ - // For a single slot FIFO, reading clears the - // full status immediately. - // ------------------------------------------ - if (DEPTH == 1) - full = mem_used[0] && !read; - - internal_out_payload = mem[0]; - - // ------------------------------------------ - // Writes clear empty immediately for lookahead modes. - // Note that we use in_valid instead of write to avoid - // combinational loops (in lookahead mode, qualifying - // with in_ready is meaningless). - // - // In a 1-deep FIFO, a possible combinational loop runs - // from write -> out_valid -> out_ready -> write - // ------------------------------------------ - if (EMPTY_LATENCY == 0) begin - empty = !mem_used[0] && !in_valid; - - if (!mem_used[0] && in_valid) - internal_out_payload = in_payload; - end - end - - end - endgenerate - - // -------------------------------------------------- - // Avalon-ST Signals - // - // The in_ready signal is straightforward. - // - // To match memory latency when empty latency > 1, - // out_valid assertions must be delayed by one clock - // cycle. - // - // Note: out_valid deassertions must not be delayed or - // the FIFO will underflow. - // -------------------------------------------------- - assign in_ready = !full; - assign internal_out_ready = out_ready || !out_valid; - - generate if (EMPTY_LATENCY > 1) begin - always @(posedge clk or posedge reset) begin - if (reset) - internal_out_valid <= 0; - else begin - internal_out_valid <= !empty & ok_to_forward & ~drop_on_error; - - if (read) begin - if (incremented_rd_ptr == wr_ptr) - internal_out_valid <= 1'b0; - end - end - end - end else begin - always @* begin - internal_out_valid = !empty & ok_to_forward; - end - end - endgenerate - - // -------------------------------------------------- - // Single Output Pipeline Stage - // - // This output pipeline stage is enabled if the FIFO's - // empty latency is set to 3 (default). It is disabled - // for all other allowed latencies. - // - // Reason: The memory outputs are unregistered, so we have to - // register the output or fmax will drop if combinatorial - // logic is present on the output datapath. - // - // Q: The Avalon-ST spec says that I have to register my outputs - // But isn't the memory counted as a register? - // A: The path from the address lookup to the memory output is - // slow. Registering the memory outputs is a good idea. - // - // The registers get packed into the memory by the fitter - // which means minimal resources are consumed (the result - // is a altsyncram with registered outputs, available on - // all modern Altera devices). - // - // This output stage acts as an extra slot in the FIFO, - // and complicates the fill level. - // -------------------------------------------------- - generate if (EMPTY_LATENCY == 3) begin - always @(posedge clk or posedge reset) begin - if (reset) begin - out_valid <= 0; - out_payload <= 0; - end - else begin - if (internal_out_ready) begin - out_valid <= internal_out_valid & ok_to_forward; - out_payload <= internal_out_payload; - end - end - end - end - else begin - always @* begin - out_valid = internal_out_valid; - out_payload = internal_out_payload; - end - end - endgenerate - - // -------------------------------------------------- - // Fill Level - // - // The fill level is calculated from the next write - // and read pointers to avoid unnecessary latency. - // - // If the output pipeline is enabled, the fill level - // must account for it, or we'll always be off by one. - // This may, or may not be important depending on the - // application. - // - // For now, we'll always calculate the exact fill level - // at the cost of an extra adder when the output stage - // is enabled. - // -------------------------------------------------- - generate if (USE_FILL_LEVEL) begin - wire [31:0] depth32; - assign depth32 = DEPTH; - always @(posedge clk or posedge reset) begin - if (reset) - fifo_fill_level <= 0; - else if (next_full & !drop_on_error) - fifo_fill_level <= depth32[ADDR_WIDTH:0]; - else begin - fifo_fill_level[ADDR_WIDTH] <= 1'b0; - fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr; - end - end - - always @* begin - fill_level = fifo_fill_level; - - if (EMPTY_LATENCY == 3) - fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid}; - end - end - else begin - initial fill_level = 0; - end - endgenerate - - generate if (USE_ALMOST_FULL_IF) begin - assign almost_full_data = (fill_level >= almost_full_threshold); - end - else - assign almost_full_data = 0; - endgenerate - - generate if (USE_ALMOST_EMPTY_IF) begin - assign almost_empty_data = (fill_level <= almost_empty_threshold); - end - else - assign almost_empty_data = 0; - endgenerate - - // -------------------------------------------------- - // Avalon-MM Status & Control Connection Point - // - // Register map: - // - // | Addr | RW | 31 - 0 | - // | 0 | R | Fill level | - // - // The registering of this connection point means - // that there is a cycle of latency between - // reads/writes and the updating of the fill level. - // -------------------------------------------------- - generate if (USE_STORE_FORWARD) begin - assign max_fifo_size = FIFO_DEPTH - 1; - always @(posedge clk or posedge reset) begin - if (reset) begin - almost_full_threshold <= max_fifo_size[23 : 0]; - almost_empty_threshold <= 0; - cut_through_threshold <= 0; - drop_on_error_en <= 0; - csr_readdata <= 0; - pkt_mode <= 1'b1; - end - else begin - if (csr_write) begin - if(csr_address == 3'b010) - almost_full_threshold <= csr_writedata[23:0]; - if(csr_address == 3'b011) - almost_empty_threshold <= csr_writedata[23:0]; - if(csr_address == 3'b100) begin - cut_through_threshold <= csr_writedata[23:0]; - pkt_mode <= (csr_writedata[23:0] == 0); - end - if(csr_address == 3'b101) - drop_on_error_en <= csr_writedata[0]; - end - - if (csr_read) begin - csr_readdata <= 32'b0; - if (csr_address == 0) - csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level}; - if (csr_address == 2) - csr_readdata <= {8'b0, almost_full_threshold}; - if (csr_address == 3) - csr_readdata <= {8'b0, almost_empty_threshold}; - if (csr_address == 4) - csr_readdata <= {8'b0, cut_through_threshold}; - if (csr_address == 5) - csr_readdata <= {31'b0, drop_on_error_en}; - end - end - end - end - else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin - assign max_fifo_size = FIFO_DEPTH - 1; - always @(posedge clk or posedge reset) begin - if (reset) begin - almost_full_threshold <= max_fifo_size[23 : 0]; - almost_empty_threshold <= 0; - csr_readdata <= 0; - end - else begin - if (csr_write) begin - if(csr_address == 3'b010) - almost_full_threshold <= csr_writedata[23:0]; - if(csr_address == 3'b011) - almost_empty_threshold <= csr_writedata[23:0]; - end - - if (csr_read) begin - csr_readdata <= 32'b0; - if (csr_address == 0) - csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level}; - if (csr_address == 2) - csr_readdata <= {8'b0, almost_full_threshold}; - if (csr_address == 3) - csr_readdata <= {8'b0, almost_empty_threshold}; - end - end - end - end - else begin - always @(posedge clk or posedge reset) begin - if (reset) begin - csr_readdata <= 0; - end - else if (csr_read) begin - csr_readdata <= 0; - - if (csr_address == 0) - csr_readdata <= fill_level; - end - end - end - endgenerate - - // -------------------------------------------------- - // Store and forward logic - // -------------------------------------------------- - // if the fifo gets full before the entire packet or the - // cut-threshold condition is met then start sending out - // data in order to avoid dead-lock situation - - generate if (USE_STORE_FORWARD) begin - assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ; - assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave); - assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) : - ~wait_for_threshold) | fifo_too_small_r; - assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket; - assign in_pkt_start = in_valid & in_ready & in_startofpacket; - assign in_pkt_error = in_valid & in_ready & |in_error; - assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket; - assign out_pkt_leave = out_valid & out_ready & out_endofpacket; - assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready; - - // count packets coming and going into the fifo - always @(posedge clk or posedge reset) begin - if (reset) begin - pkt_cnt <= 0; - pkt_cnt_r <= 0; - pkt_cnt_plusone <= 1; - pkt_cnt_minusone <= 0; - pkt_cnt_changed <= 0; - pkt_has_started <= 0; - sop_has_left_fifo <= 0; - fifo_too_small_r <= 0; - pkt_cnt_eq_zero <= 1'b1; - pkt_cnt_eq_one <= 1'b0; - fifo_fill_level_lt_cut_through_threshold <= 1'b1; - end - else begin - fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold; - fifo_too_small_r <= fifo_too_small; - pkt_cnt_plusone <= pkt_cnt + 1'b1; - pkt_cnt_minusone <= pkt_cnt - 1'b1; - pkt_cnt_r <= pkt_cnt; - pkt_cnt_changed <= 1'b0; - - if( in_pkt_eop_arrive ) - sop_has_left_fifo <= 1'b0; - else if (out_pkt_sop_leave & pkt_cnt_eq_zero ) - sop_has_left_fifo <= 1'b1; - - if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin - pkt_cnt_changed <= 1'b1; - pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_plusone; - pkt_cnt_eq_zero <= 0; - if (pkt_cnt == 0) - pkt_cnt_eq_one <= 1'b1; - else - pkt_cnt_eq_one <= 1'b0; - end - else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin - pkt_cnt_changed <= 1'b1; - pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_minusone; - if (pkt_cnt == 1) - pkt_cnt_eq_zero <= 1'b1; - else - pkt_cnt_eq_zero <= 1'b0; - if (pkt_cnt == 2) - pkt_cnt_eq_one <= 1'b1; - else - pkt_cnt_eq_one <= 1'b0; - end - - if (in_pkt_start) - pkt_has_started <= 1'b1; - else if (in_pkt_eop_arrive) - pkt_has_started <= 1'b0; - end - end - - // drop on error logic - always @(posedge clk or posedge reset) begin - if (reset) begin - sop_ptr <= 0; - error_in_pkt <= 0; - end - else begin - // save the location of the SOP - if ( in_pkt_start ) - sop_ptr <= wr_ptr; - - // remember if error in pkt - // log error only if packet has already started - if (in_pkt_eop_arrive) - error_in_pkt <= 1'b0; - else if ( in_pkt_error & (pkt_has_started | in_pkt_start)) - error_in_pkt <= 1'b1; - end - end - assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive & - ~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero); - - end - else begin - assign ok_to_forward = 1'b1; - assign drop_on_error = 1'b0; - end - endgenerate - - - // -------------------------------------------------- - // Calculates the log2ceil of the input value - // -------------------------------------------------- - function integer log2ceil; - input integer val; - integer i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - -endmodule diff --git a/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv b/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv deleted file mode 100644 index 00dc788..0000000 --- a/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv +++ /dev/null @@ -1,270 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2010 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $ -// $Revision: #3 $ -// $Date: 2010/07/07 $ -// $Author: jyeap $ - -/* ----------------------------------------------------------------------- -Round-robin/fixed arbitration implementation. - -Q: how do you find the least-significant set-bit in an n-bit binary number, X? - -A: M = X & (~X + 1) - -Example: X = 101000100 - 101000100 & - 010111011 + 1 = - - 101000100 & - 010111100 = - ----------- - 000000100 - -The method can be generalized to find the first set-bit -at a bit index no lower than bit-index N, simply by adding -2**N rather than 1. - - -Q: how does this relate to round-robin arbitration? -A: -Let X be the concatenation of all request signals. -Let the number to be added to X (hereafter called the -top_priority) initialize to 1, and be assigned from the -concatenation of the previous saved-grant, left-rotated -by one position, each time arbitration occurs. The -concatenation of grants is then M. - -Problem: consider this case: - -top_priority = 010000 -request = 001001 -~request + top_priority = 000110 -next_grant = 000000 <- no one is granted! - -There was no "set bit at a bit index no lower than bit-index 4", so -the result was 0. - -We need to propagate the carry out from (~request + top_priority) to the LSB, so -that the sum becomes 000111, and next_grant is 000001. This operation could be -called a "circular add". - -A bit of experimentation on the circular add reveals a significant amount of -delay in exiting and re-entering the carry chain - this will vary with device -family. Quartus also reports a combinational loop warning. Finally, -Modelsim 6.3g has trouble with the expression, evaluating it to 'X'. But -Modelsim _doesn't_ report a combinational loop!) - -An alternate solution: concatenate the request vector with itself, and OR -corresponding bits from the top and bottom halves to determine next_grant. - -Example: - -top_priority = 010000 -{request, request} = 001001 001001 -{~request, ~request} + top_priority = 110111 000110 -result of & operation = 000001 000000 -next_grant = 000001 - -Notice that if request = 0, the sum operation will overflow, but we can ignore -this; the next_grant result is 0 (no one granted), as you might expect. -In the implementation, the last-granted value must be maintained as -a non-zero value - best probably simply not to update it when no requests -occur. - ------------------------------------------------------------------------ */ - -`timescale 1 ns / 1 ns - -module altera_merlin_arbitrator -#( - parameter NUM_REQUESTERS = 8, - // -------------------------------------- - // Implemented schemes - // "round-robin" - // "fixed-priority" - // "no-arb" - // -------------------------------------- - parameter SCHEME = "round-robin", - parameter PIPELINE = 0 -) -( - input clk, - input reset, - - // -------------------------------------- - // Requests - // -------------------------------------- - input [NUM_REQUESTERS-1:0] request, - - // -------------------------------------- - // Grants - // -------------------------------------- - output [NUM_REQUESTERS-1:0] grant, - - // -------------------------------------- - // Control Signals - // -------------------------------------- - input increment_top_priority, - input save_top_priority -); - - // -------------------------------------- - // Signals - // -------------------------------------- - wire [NUM_REQUESTERS-1:0] top_priority; - reg [NUM_REQUESTERS-1:0] top_priority_reg; - reg [NUM_REQUESTERS-1:0] last_grant; - wire [2*NUM_REQUESTERS-1:0] result; - - // -------------------------------------- - // Scheme Selection - // -------------------------------------- - generate - if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin - assign top_priority = top_priority_reg; - end - else begin - // Fixed arbitration (or single-requester corner case) - assign top_priority = 1'b1; - end - endgenerate - - // -------------------------------------- - // Decision Logic - // -------------------------------------- - altera_merlin_arb_adder - #( - .WIDTH (2 * NUM_REQUESTERS) - ) - adder - ( - .a ({ ~request, ~request }), - .b ({{NUM_REQUESTERS{1'b0}}, top_priority}), - .sum (result) - ); - - - generate if (SCHEME == "no-arb") begin - - // -------------------------------------- - // No arbitration: just wire request directly to grant - // -------------------------------------- - assign grant = request; - - end else begin - // Do the math in double-vector domain - wire [2*NUM_REQUESTERS-1:0] grant_double_vector; - assign grant_double_vector = {request, request} & result; - - // -------------------------------------- - // Extract grant from the top and bottom halves - // of the double vector. - // -------------------------------------- - assign grant = - grant_double_vector[NUM_REQUESTERS - 1 : 0] | - grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS]; - - end - endgenerate - - // -------------------------------------- - // Left-rotate the last grant vector to create top_priority. - // -------------------------------------- - always @(posedge clk or posedge reset) begin - if (reset) begin - top_priority_reg <= 1'b1; - end - else begin - if (PIPELINE) begin - if (increment_top_priority) begin - top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0], - grant[NUM_REQUESTERS-1]} : top_priority_reg; - end - end else begin - if (save_top_priority) begin - top_priority_reg <= grant; - end - if (increment_top_priority) begin - if (|request) - top_priority_reg <= { grant[NUM_REQUESTERS-2:0], - grant[NUM_REQUESTERS-1] }; - else - top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] }; - end - end - end - end - -endmodule - -// ---------------------------------------------- -// Adder for the standard arbitrator -// ---------------------------------------------- -module altera_merlin_arb_adder -#( - parameter WIDTH = 8 -) -( - input [WIDTH-1:0] a, - input [WIDTH-1:0] b, - - output [WIDTH-1:0] sum -); - - // ---------------------------------------------- - // Benchmarks indicate that for small widths, the full - // adder has higher fmax because synthesis can merge - // it with the mux, allowing partial decisions to be - // made early. - // - // The magic number is 4 requesters, which means an - // 8 bit adder. - // ---------------------------------------------- - genvar i; - generate if (WIDTH <= 8) begin : full_adder - - wire cout[WIDTH-1:0]; - - assign sum[0] = (a[0] ^ b[0]); - assign cout[0] = (a[0] & b[0]); - - for (i = 1; i < WIDTH; i = i+1) begin : arb - - assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1]; - assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i])); - - end - - end else begin : carry_chain - - assign sum = a + b; - - end - endgenerate - -endmodule diff --git a/db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv b/db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv deleted file mode 100644 index 9b49c44..0000000 --- a/db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv +++ /dev/null @@ -1,286 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2012 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_slave_agent/altera_merlin_burst_uncompressor.sv#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------ -// Merlin Burst Uncompressor -// -// Compressed read bursts -> uncompressed -// ------------------------------------------ - -`timescale 1 ns / 1 ns - -module altera_merlin_burst_uncompressor -#( - parameter ADDR_W = 16, - parameter BURSTWRAP_W = 3, - parameter BYTE_CNT_W = 4, - parameter PKT_SYMBOLS = 4, - parameter BURST_SIZE_W = 3 -) -( - input clk, - input reset, - - // sink ST signals - input sink_startofpacket, - input sink_endofpacket, - input sink_valid, - output sink_ready, - - // sink ST "data" - input [ADDR_W - 1: 0] sink_addr, - input [BURSTWRAP_W - 1 : 0] sink_burstwrap, - input [BYTE_CNT_W - 1 : 0] sink_byte_cnt, - input sink_is_compressed, - input [BURST_SIZE_W-1 : 0] sink_burstsize, - - // source ST signals - output source_startofpacket, - output source_endofpacket, - output source_valid, - input source_ready, - - // source ST "data" - output [ADDR_W - 1: 0] source_addr, - output [BURSTWRAP_W - 1 : 0] source_burstwrap, - output [BYTE_CNT_W - 1 : 0] source_byte_cnt, - - // Note: in the slave agent, the output should always be uncompressed. In - // other applications, it may be required to leave-compressed or not. How to - // control? Seems like a simple mux - pass-through if no uncompression is - // required. - output source_is_compressed, - output [BURST_SIZE_W-1 : 0] source_burstsize -); - -//---------------------------------------------------- -// AXSIZE decoding -// -// Turns the axsize value into the actual number of bytes -// being transferred. -// --------------------------------------------------- -function reg[63:0] bytes_in_transfer; - input [2:0] axsize; - case (axsize) - 3'b000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001; - 3'b001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010; - 3'b010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100; - 3'b011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000; - 3'b100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000; - 3'b101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000; - 3'b110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000; - 3'b111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000; - default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001; - endcase - -endfunction - - // num_symbols is PKT_SYMBOLS, appropriately sized. - wire [31:0] int_num_symbols = PKT_SYMBOLS; - wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0]; - - // def: Burst Compression. In a merlin network, a compressed burst is one - // which is transmitted in a single beat. Example: read burst. In - // constrast, an uncompressed burst (example: write burst) is transmitted in - // one beat per writedata item. - // - // For compressed bursts which require response packets, burst - // uncompression is required. Concrete example: a read burst of size 8 - // occupies one response-fifo position. When that fifo position reaches the - // front of the FIFO, the slave starts providing the required 8 readdatavalid - // pulses. The 8 return response beats must be provided in a single packet, - // with incrementing address and decrementing byte_cnt fields. Upon receipt - // of the final readdata item of the burst, the response FIFO item is - // retired. - // Burst uncompression logic provides: - // a) 2-state FSM (idle, busy) - // reset to idle state - // transition to busy state for 2nd and subsequent rdv pulses - // - a single-cycle burst (aka non-burst read) causes no transition to - // busy state. - // b) response startofpacket/endofpacket logic. The response FIFO item - // will have sop asserted, and may have eop asserted. (In the case of - // multiple read bursts transmit in the command fabric in a single packet, - // the eop assertion will come in a later FIFO item.) To support packet - // conservation, and emit a well-formed packet on the response fabric, - // i) response fabric startofpacket is asserted only for the first resp. - // beat; - // ii) response fabric endofpacket is asserted only for the last resp. - // beat. - // c) response address field. The response address field contains an - // incrementing sequence, such that each readdata item is associated with - // its slave-map location. N.b. a) computing the address correctly requires - // knowledge of burstwrap behavior b) there may be no clients of the address - // field, which makes this field a good target for optimization. See - // burst_uncompress_address_counter below. - // d) response byte_cnt field. The response byte_cnt field contains a - // decrementing sequence, such that each beat of the response contains the - // count of bytes to follow. In the case of sub-bursts in a single packet, - // the byte_cnt field may decrement down to num_symbols, then back up to - // some value, multiple times in the packet. - - reg burst_uncompress_busy; - reg [BYTE_CNT_W-1:0] burst_uncompress_byte_counter; - wire first_packet_beat; - wire last_packet_beat; - - assign first_packet_beat = sink_valid & ~burst_uncompress_busy; - - // First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to - // the output. - assign source_byte_cnt = - first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter; - assign source_valid = sink_valid; - - // Last packet beat is set throughout receipt of an uncompressed read burst - // from the response FIFO - this forces all the burst uncompression machinery - // idle. - assign last_packet_beat = ~sink_is_compressed | - ( - burst_uncompress_busy ? - (sink_valid & (burst_uncompress_byte_counter == num_symbols)) : - sink_valid & (sink_byte_cnt == num_symbols) - ); - - always @(posedge clk or posedge reset) begin - if (reset) begin - burst_uncompress_busy <= '0; - burst_uncompress_byte_counter <= '0; - end - else begin - if (source_valid & source_ready & sink_valid) begin - // No matter what the current state, last_packet_beat leads to - // idle. - if (last_packet_beat) begin - burst_uncompress_busy <= '0; - burst_uncompress_byte_counter <= '0; - end - else begin - if (burst_uncompress_busy) begin - burst_uncompress_byte_counter <= burst_uncompress_byte_counter ? - (burst_uncompress_byte_counter - num_symbols) : - (sink_byte_cnt - num_symbols); - end - else begin // not busy, at least one more beat to go - burst_uncompress_byte_counter <= sink_byte_cnt - num_symbols; - // To do: should busy go true for numsymbols-size compressed - // bursts? - burst_uncompress_busy <= '1; - end - end - end - end - end - - wire [ADDR_W - 1 : 0 ] addr_width_burstwrap; - reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base; - reg [ADDR_W - 1 : 0] burst_uncompress_address_offset; - - wire [63:0] decoded_burstsize_wire; - wire [ADDR_W-1:0] decoded_burstsize; - - // The input burstwrap value can be used as a mask against address values, - // but with one caveat: the address width may be (probably is) wider than - // the burstwrap width. The spec says: extend the msb of the burstwrap - // value out over the entire address width (but only if the address width - // actually is wider than the burstwrap width; otherwise it's a 0-width or - // negative range and concatenation multiplier). - assign addr_width_burstwrap[BURSTWRAP_W - 1 : 0] = sink_burstwrap; - generate - if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend - // Sign-extend, just wires: - assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] = - {(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}}; - end - endgenerate - - always @(posedge clk or posedge reset) begin - if (reset) begin - burst_uncompress_address_base <= '0; - end - else if (first_packet_beat & source_ready) begin - burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap; - end - end - - assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize); //expand it to 64 bits - assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0]; //then take the width that is needed - - wire [ADDR_W - 1 : 0] p1_burst_uncompress_address_offset = - ( - (first_packet_beat ? - sink_addr : - burst_uncompress_address_offset) + decoded_burstsize - ) & - addr_width_burstwrap; - - always @(posedge clk or posedge reset) begin - if (reset) begin - burst_uncompress_address_offset <= '0; - end - else begin - if (source_ready & source_valid) begin - burst_uncompress_address_offset <= p1_burst_uncompress_address_offset; - // if (first_packet_beat) begin - // burst_uncompress_address_offset <= - // (sink_addr + num_symbols) & addr_width_burstwrap; - // end - // else begin - // burst_uncompress_address_offset <= - // (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap; - // end - end - end - end - - // On the first packet beat, send the input address out unchanged, - // while values are computed/registered for 2nd and subsequent beats. - assign source_addr = first_packet_beat ? sink_addr : - burst_uncompress_address_base | burst_uncompress_address_offset; - assign source_burstwrap = sink_burstwrap; - assign source_burstsize = sink_burstsize; - - //------------------------------------------------------------------- - // A single (compressed) read burst will have sop/eop in the same beat. - // A sequence of read sub-bursts emitted by a burst adapter in response to a - // single read burst will have sop on the first sub-burst, eop on the last. - // Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve - // packet conservation. - assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy; - assign source_endofpacket = sink_endofpacket & last_packet_beat; - assign sink_ready = source_valid & source_ready & last_packet_beat; - - // This is correct for the slave agent usage, but won't always be true in the - // width adapter. To do: add an "please uncompress" input, and use it to - // pass-through or modify, and set source_is_compressed accordingly. - assign source_is_compressed = 1'b0; -endmodule - diff --git a/db/ip/nios_system/submodules/altera_merlin_master_agent.sv b/db/ip/nios_system/submodules/altera_merlin_master_agent.sv deleted file mode 100644 index 070f26f..0000000 --- a/db/ip/nios_system/submodules/altera_merlin_master_agent.sv +++ /dev/null @@ -1,309 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_master_agent/altera_merlin_master_agent.sv#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// -------------------------------------- -// Merlin Master Agent -// -// Converts Avalon-MM transactions into -// Merlin network packets. -// -------------------------------------- - -`timescale 1 ns / 1 ns - -module altera_merlin_master_agent -#( - // ------------------- - // Packet Format Parameters - // ------------------- - parameter PKT_QOS_H = 109, - PKT_QOS_L = 106, - PKT_DATA_SIDEBAND_H = 105, - PKT_DATA_SIDEBAND_L = 98, - PKT_ADDR_SIDEBAND_H = 97, - PKT_ADDR_SIDEBAND_L = 93, - PKT_CACHE_H = 92, - PKT_CACHE_L = 89, - PKT_THREAD_ID_H = 88, - PKT_THREAD_ID_L = 87, - PKT_BEGIN_BURST = 81, - PKT_PROTECTION_H = 80, - PKT_PROTECTION_L = 80, - PKT_BURSTWRAP_H = 79, - PKT_BURSTWRAP_L = 77, - PKT_BYTE_CNT_H = 76, - PKT_BYTE_CNT_L = 74, - PKT_ADDR_H = 73, - PKT_ADDR_L = 42, - PKT_BURST_SIZE_H = 86, - PKT_BURST_SIZE_L = 84, - PKT_BURST_TYPE_H = 94, - PKT_BURST_TYPE_L = 93, - PKT_TRANS_EXCLUSIVE = 83, - PKT_TRANS_LOCK = 82, - PKT_TRANS_COMPRESSED_READ = 41, - PKT_TRANS_POSTED = 40, - PKT_TRANS_WRITE = 39, - PKT_TRANS_READ = 38, - PKT_DATA_H = 37, - PKT_DATA_L = 6, - PKT_BYTEEN_H = 5, - PKT_BYTEEN_L = 2, - PKT_SRC_ID_H = 1, - PKT_SRC_ID_L = 1, - PKT_DEST_ID_H = 0, - PKT_DEST_ID_L = 0, - PKT_RESPONSE_STATUS_L = 110, - PKT_RESPONSE_STATUS_H = 111, - ST_DATA_W = 112, - ST_CHANNEL_W = 1, - - // ------------------- - // Agent Parameters - // ------------------- - AV_BURSTCOUNT_W = 3, - ID = 1, - SUPPRESS_0_BYTEEN_RSP = 1, - BURSTWRAP_VALUE = 4, - CACHE_VALUE = 0, - SECURE_ACCESS_BIT = 1, - USE_READRESPONSE = 0, - USE_WRITERESPONSE = 0, - - // ------------------- - // Derived Parameters - // ------------------- - PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1, - PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1, - PKT_PROTECTION_W= PKT_PROTECTION_H - PKT_PROTECTION_L + 1, - PKT_ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1, - PKT_DATA_W = PKT_DATA_H - PKT_DATA_L + 1, - PKT_BYTEEN_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, - PKT_SRC_ID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1, - PKT_DEST_ID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1 -) -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // Avalon-MM Anti-Master - // ------------------- - input [PKT_ADDR_W-1 : 0] av_address, - input av_write, - input av_read, - input [PKT_DATA_W-1 : 0] av_writedata, - output reg [PKT_DATA_W-1 : 0] av_readdata, - output reg av_waitrequest, - output reg av_readdatavalid, - input [PKT_BYTEEN_W-1 : 0] av_byteenable, - input [AV_BURSTCOUNT_W-1 : 0] av_burstcount, - input av_debugaccess, - input av_lock, - output reg [1:0] av_response, - input av_writeresponserequest, - output reg av_writeresponsevalid, - - // ------------------- - // Command Source - // ------------------- - output reg cp_valid, - output reg [ST_DATA_W-1 : 0] cp_data, - output wire cp_startofpacket, - output wire cp_endofpacket, - input cp_ready, - - // ------------------- - // Response Sink - // ------------------- - input rp_valid, - input [ST_DATA_W-1 : 0] rp_data, - input [ST_CHANNEL_W-1 : 0] rp_channel, - input rp_startofpacket, - input rp_endofpacket, - output reg rp_ready -); - // ------------------------------------------------------------ - // Utility Functions - // ------------------------------------------------------------ - function integer clogb2; - input [31:0] value; - begin - for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) - value = value >> 1; - clogb2 = clogb2 - 1; - end - endfunction // clogb2 - - localparam MAX_BURST = 1 << (AV_BURSTCOUNT_W - 1); - localparam NUMSYMBOLS = PKT_BYTEEN_W; - localparam BURSTING = (MAX_BURST > NUMSYMBOLS); - localparam BITS_TO_ZERO = clogb2(NUMSYMBOLS); - localparam BURST_SIZE = clogb2(NUMSYMBOLS); - - typedef enum bit [1:0] - { - FIXED = 2'b00, - INCR = 2'b01, - WRAP = 2'b10, - OTHER_WRAP = 2'b11 - } MerlinBurstType; - - // -------------------------------------- - // Potential optimization: compare in words to save bits? - // -------------------------------------- - wire is_burst; - assign is_burst = (BURSTING) & (av_burstcount > NUMSYMBOLS); - - wire [31:0] burstwrap_value_int = BURSTWRAP_VALUE; - wire [31:0] id_int = ID; - wire [2:0] burstsize_sig = BURST_SIZE[2:0]; - wire [1:0] bursttype_value = burstwrap_value_int[PKT_BURSTWRAP_W-1] ? INCR : WRAP; - - // -------------------------------------- - // Address alignment - // - // The packet format requires that addresses be aligned to - // the transaction size. - // -------------------------------------- - wire [PKT_ADDR_W-1 : 0] av_address_aligned; - generate - if (NUMSYMBOLS > 1) begin - assign av_address_aligned = - {av_address[PKT_ADDR_W-1 : BITS_TO_ZERO], {BITS_TO_ZERO {1'b0}}}; - end - else begin - assign av_address_aligned = av_address; - end - endgenerate - - // -------------------------------------- - // Command & Response Construction - // -------------------------------------- - always @* begin - cp_data = '0; // default assignment; override below as needed. - - cp_data[PKT_PROTECTION_L] = av_debugaccess; - cp_data[PKT_PROTECTION_L+1] = SECURE_ACCESS_BIT[0]; // Default Non-secured (AXI) - cp_data[PKT_PROTECTION_L+2] = 1'b0; // Default Data access (AXI) - cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L ] = burstwrap_value_int[PKT_BURSTWRAP_W-1:0]; - cp_data[PKT_BYTE_CNT_H :PKT_BYTE_CNT_L ] = av_burstcount; - cp_data[PKT_ADDR_H :PKT_ADDR_L ] = av_address_aligned; - cp_data[PKT_TRANS_EXCLUSIVE ] = 1'b0; - cp_data[PKT_TRANS_LOCK ] = av_lock; - cp_data[PKT_TRANS_COMPRESSED_READ ] = av_read & is_burst; - cp_data[PKT_TRANS_READ ] = av_read; - cp_data[PKT_TRANS_WRITE ] = av_write; - // posted and non-posted write avaiable now - cp_data[PKT_TRANS_POSTED ] = av_write & !av_writeresponserequest; - cp_data[PKT_DATA_H :PKT_DATA_L ] = av_writedata; - cp_data[PKT_BYTEEN_H :PKT_BYTEEN_L ] = av_byteenable; - cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = burstsize_sig; - cp_data[PKT_BURST_TYPE_H:PKT_BURST_TYPE_L] = bursttype_value; - cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L ] = id_int[PKT_SRC_ID_W-1:0]; - cp_data[PKT_THREAD_ID_H:PKT_THREAD_ID_L ] = '0; - cp_data[PKT_CACHE_H :PKT_CACHE_L ] = CACHE_VALUE[3:0]; - cp_data[PKT_QOS_H : PKT_QOS_L] = '0; - cp_data[PKT_ADDR_SIDEBAND_H:PKT_ADDR_SIDEBAND_L] = '0; - cp_data[PKT_DATA_SIDEBAND_H :PKT_DATA_SIDEBAND_L] = '0; - - av_readdata = rp_data[PKT_DATA_H : PKT_DATA_L]; - if (USE_WRITERESPONSE || USE_READRESPONSE) - av_response = rp_data[PKT_RESPONSE_STATUS_H : PKT_RESPONSE_STATUS_L]; - else - av_response = '0; - - end - - // -------------------------------------- - // Command Control - // -------------------------------------- - always @* begin - cp_valid = 0; - - if (av_write || av_read) - cp_valid = 1; - end - - generate if (BURSTING) begin - reg sop_enable; - - always @(posedge clk, posedge reset) begin - if (reset) begin - sop_enable <= 1'b1; - end - else begin - if (cp_valid && cp_ready) begin - sop_enable <= 1'b0; - if (cp_endofpacket) - sop_enable <= 1'b1; - end - end - end - - assign cp_startofpacket = sop_enable; - assign cp_endofpacket = (av_read) | (av_burstcount == NUMSYMBOLS); - - end - else begin - - assign cp_startofpacket = 1'b1; - assign cp_endofpacket = 1'b1; - - end - endgenerate - - // -------------------------------------- - // Backpressure & Readdatavalid - // -------------------------------------- - reg hold_waitrequest; - - always @ (posedge clk, posedge reset) begin - if (reset) - hold_waitrequest <= 1'b1; - else - hold_waitrequest <= 1'b0; - end - - always @* begin - rp_ready = 1; - av_readdatavalid = 0; - av_writeresponsevalid = 0; - av_waitrequest = hold_waitrequest | !cp_ready; - - // -------------------------------------- - // Currently, responses are _always_ read responses because - // this Avalon agent only issues posted writes, which do - // not have responses. -> not true for now - // Now Avalon supports response, so based on type of transaction - // return, assert correct thing - // -------------------------------------- - if (rp_data[PKT_TRANS_WRITE] == 1) - av_writeresponsevalid = rp_valid; - else - av_readdatavalid = rp_valid; - - if (SUPPRESS_0_BYTEEN_RSP) begin - if (rp_data[PKT_BYTEEN_H:PKT_BYTEEN_L] == 0) - av_readdatavalid = 0; - end - end - -endmodule diff --git a/db/ip/nios_system/submodules/altera_merlin_master_translator.sv b/db/ip/nios_system/submodules/altera_merlin_master_translator.sv deleted file mode 100644 index a43760f..0000000 --- a/db/ip/nios_system/submodules/altera_merlin_master_translator.sv +++ /dev/null @@ -1,554 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_master_translator/altera_merlin_master_translator.sv#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// -------------------------------------- -// Merlin Master Translator -// -// Converts Avalon-MM Master Interfaces into -// Avalon-MM Universal Master Interfaces -// -------------------------------------- - -`timescale 1 ns / 1 ns - - - -module altera_merlin_master_translator #( - parameter - AV_ADDRESS_W = 32, - AV_DATA_W = 32, - AV_BURSTCOUNT_W = 4, - AV_BYTEENABLE_W = 4, - - //Optional Port Declarations - - USE_BURSTCOUNT = 1, - USE_BEGINBURSTTRANSFER = 0, - USE_BEGINTRANSFER = 0, - USE_CHIPSELECT = 0, - USE_READ = 1, - USE_READDATAVALID = 1, - USE_WRITE = 1, - USE_WAITREQUEST = 1, - USE_WRITERESPONSE = 0, - USE_READRESPONSE = 0, - - AV_REGISTERINCOMINGSIGNALS = 0, - AV_SYMBOLS_PER_WORD = 4, - AV_ADDRESS_SYMBOLS = 0, - AV_CONSTANT_BURST_BEHAVIOR = 1, - AV_BURSTCOUNT_SYMBOLS = 0, - AV_LINEWRAPBURSTS = 0, - UAV_ADDRESS_W = 38, - UAV_BURSTCOUNT_W = 10, - UAV_CONSTANT_BURST_BEHAVIOR = 0 - )( - //Universal Avalon Master - input wire clk, - input wire reset, - output reg uav_write, - output reg uav_read, - output reg [UAV_ADDRESS_W -1 : 0] uav_address, - output reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount, - output wire [AV_BYTEENABLE_W -1 : 0] uav_byteenable, - output wire [AV_DATA_W -1 : 0] uav_writedata, - output wire uav_lock, - output wire uav_debugaccess, - output wire uav_clken, - - input wire [ AV_DATA_W -1 : 0] uav_readdata, - input wire uav_readdatavalid, - input wire uav_waitrequest, - input wire [1:0] uav_response, - output reg uav_writeresponserequest, - input wire uav_writeresponsevalid, - - //Avalon-MM !Master - input reg av_write, - input reg av_read, - input wire [AV_ADDRESS_W -1 : 0] av_address, - input wire [AV_BYTEENABLE_W -1 : 0] av_byteenable, - input wire [AV_BURSTCOUNT_W -1 : 0] av_burstcount, - input wire [AV_DATA_W -1 : 0] av_writedata, - input wire av_begintransfer, - input wire av_beginbursttransfer, - input wire av_lock, - input wire av_chipselect, - input wire av_debugaccess, - input wire av_clken, - - output wire [AV_DATA_W -1 : 0] av_readdata, - output wire av_readdatavalid, - output reg av_waitrequest, - output reg [1:0] av_response, - input wire av_writeresponserequest, - output reg av_writeresponsevalid - - ); - - - localparam BITS_PER_WORD = clog2(AV_SYMBOLS_PER_WORD - 1); - localparam AV_MAX_SYMBOL_BURST = flog2( pow2(AV_BURSTCOUNT_W - 1) * (AV_BURSTCOUNT_SYMBOLS ? 1 : (AV_SYMBOLS_PER_WORD)) ); - localparam AV_MAX_SYMBOL_BURST_MINUS_ONE = AV_MAX_SYMBOL_BURST ? AV_MAX_SYMBOL_BURST - 1 : 0 ; - - localparam UAV_BURSTCOUNT_W_OR_32 = UAV_BURSTCOUNT_W > 32 ? 31 : UAV_BURSTCOUNT_W -1; - localparam UAV_ADDRESS_W_OR_32 = UAV_ADDRESS_W > 32 ? 31 : UAV_ADDRESS_W -1; - - - // -1 for burstcount restriction 2^(n-1) - - localparam BITS_PER_WORD_BURSTCOUNT = UAV_BURSTCOUNT_W == 1 ? 0 : BITS_PER_WORD; - localparam BITS_PER_WORD_ADDRESS = UAV_ADDRESS_W == 1 ? 0 : BITS_PER_WORD; - - localparam ADDRESS_LOW = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD_ADDRESS; - localparam BURSTCOUNT_LOW = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD_BURSTCOUNT; - - localparam ADDRESS_HIGH = UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_LOW ? AV_ADDRESS_W : UAV_ADDRESS_W - ADDRESS_LOW; - localparam BURSTCOUNT_HIGH = UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_LOW ? AV_BURSTCOUNT_W : UAV_BURSTCOUNT_W - BURSTCOUNT_LOW; - - function integer flog2; - input [31:0] Depth; - integer i; - begin - i = Depth; - if ( i <= 0 ) flog2 = 0; - else begin - for(flog2 = -1; i > 0; flog2 = flog2 + 1) - i = i >> 1; - end - end - - endfunction // flog2 - - function integer clog2; - input [31:0] Depth; - integer i; - begin - i = Depth; - for(clog2 = 0; i > 0; clog2 = clog2 + 1) - i = i >> 1; - end - - endfunction - - function integer pow2; - input [31:0] toShift; - begin - pow2=1; - pow2= pow2 << toShift; - end - endfunction // pow2 - - // ------------------------------------------------- - // Assign some constants to appropriately-sized signals to - // avoid synthesis warnings. This also helps some simulators - // with their inferred sensitivity lists. - // ------------------------------------------------- - // Calculate the symbols per word as the power of 2 extended symbols per word - wire [31:0] symbols_per_word_int = 2**(clog2(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W_OR_32 : 0] - 1)); - wire [UAV_BURSTCOUNT_W_OR_32 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W_OR_32 : 0]; - - - reg internal_beginbursttransfer; - reg internal_begintransfer; - reg [UAV_ADDRESS_W - 1: 0 ] uav_address_pre; - reg [UAV_BURSTCOUNT_W - 1 : 0 ] uav_burstcount_pre; - - - - reg uav_read_pre; - reg uav_write_pre; - reg read_accepted; - - //Passthru assignmenst - - assign uav_writedata = av_writedata; - assign av_readdata = uav_readdata; - assign uav_byteenable = av_byteenable; - assign uav_lock = av_lock; - assign av_readdatavalid = uav_readdatavalid; - assign uav_debugaccess = av_debugaccess; - assign uav_clken = av_clken; - - //Response signals - always_comb - begin - if (!USE_READRESPONSE && !USE_WRITERESPONSE) - av_response = '0; - else - av_response = uav_response; - if (USE_WRITERESPONSE) begin - uav_writeresponserequest = av_writeresponserequest; - av_writeresponsevalid = uav_writeresponsevalid; - end else begin - uav_writeresponserequest = '0; - av_writeresponsevalid = '0; - end - end - - //address + burstcount assignment - - reg [UAV_ADDRESS_W - 1 : 0] address_register; - reg [UAV_BURSTCOUNT_W - 1 : 0] burstcount_register; - - always @* begin - uav_address=uav_address_pre; - uav_burstcount=uav_burstcount_pre; - - if(AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~internal_beginbursttransfer) begin - uav_address=address_register; - uav_burstcount=burstcount_register; - end - end - - reg first_burst_stalled; - reg burst_stalled; - - - wire[UAV_ADDRESS_W-1:0] combi_burst_addr_reg; - wire [UAV_ADDRESS_W-1:0] combi_addr_reg; - generate - if(AV_LINEWRAPBURSTS && AV_MAX_SYMBOL_BURST!=0) begin - if(AV_MAX_SYMBOL_BURST > UAV_ADDRESS_W - 1) begin - assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] }; - assign combi_addr_reg = { address_register[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] }; - end - else begin - assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], uav_address_pre[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] }; - assign combi_addr_reg = { address_register[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], address_register[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] }; - end - end - else begin - assign combi_burst_addr_reg = - uav_address_pre + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W_OR_32:0]; - assign combi_addr_reg = - address_register + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W_OR_32:0]; - end - endgenerate - - always@(posedge clk, posedge reset) begin - - if(reset) begin - address_register <= '0; - burstcount_register <= '0; - first_burst_stalled <= 1'b0; - burst_stalled <= 1'b0; - end - else begin - address_register <= address_register; - burstcount_register <= burstcount_register; - - if(internal_beginbursttransfer||first_burst_stalled) begin - - if(av_waitrequest) begin - first_burst_stalled <= 1'b1; - address_register <= uav_address_pre; - burstcount_register <= uav_burstcount_pre; - end else begin - first_burst_stalled <= 1'b0; - address_register <= combi_burst_addr_reg; - burstcount_register <= uav_burstcount_pre - symbols_per_word; - end - end - - else if(internal_begintransfer || burst_stalled) begin - if(~av_waitrequest) begin - burst_stalled <= 1'b0; - address_register <= combi_addr_reg; - burstcount_register <= burstcount_register - symbols_per_word; - end else - burst_stalled<=1'b1; - end - end - - end - - //Address - always @* begin - uav_address_pre = '0; - - if(AV_ADDRESS_SYMBOLS) - uav_address_pre=av_address[ ( ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0 ) : 0 ]; - else begin - uav_address_pre[ UAV_ADDRESS_W - 1 : ADDRESS_LOW ] = av_address[( ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0 ]; - end - end - - //Burstcount - always@* begin - uav_burstcount_pre = symbols_per_word; // default to a single transfer - - if(USE_BURSTCOUNT) begin - uav_burstcount_pre = '0; - - if(AV_BURSTCOUNT_SYMBOLS) - uav_burstcount_pre = av_burstcount[( BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0 ) :0 ]; - else begin - uav_burstcount_pre[ UAV_BURSTCOUNT_W - 1 : BURSTCOUNT_LOW] = av_burstcount[( BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0 ) : 0 ]; - end - - end - - end - - - //waitrequest translation - - always@(posedge clk, posedge reset) begin - if(reset) - read_accepted <= 1'b0; - else begin - read_accepted <= read_accepted; - - if(read_accepted == 1 && uav_readdatavalid == 1) // reset acceptance only when rdv arrives - read_accepted <= 1'b0; - - if(read_accepted == 0) - read_accepted<=av_waitrequest ? uav_read_pre & ~uav_waitrequest : 1'b0; - end - - end - - reg write_accepted = 0; - generate if (AV_REGISTERINCOMINGSIGNALS) begin - always@(posedge clk, posedge reset) begin - if(reset) - write_accepted <= 1'b0; - else begin - write_accepted <= - ~av_waitrequest ? 1'b0 : - uav_write & ~uav_waitrequest? 1'b1 : - write_accepted; - end - end - end endgenerate - - always@* begin - av_waitrequest = uav_waitrequest; - - if(USE_READDATAVALID == 0 ) begin - av_waitrequest = uav_read_pre ? ~uav_readdatavalid : uav_waitrequest; - end - - if (AV_REGISTERINCOMINGSIGNALS) begin - av_waitrequest = - uav_read_pre ? ~uav_readdatavalid : - uav_write_pre ? (internal_begintransfer | uav_waitrequest) & ~write_accepted : - 1'b1; - end - - if(USE_WAITREQUEST == 0) begin - av_waitrequest = 0; - end - end - - //read/write generation - always@* begin - - uav_write = 1'b0; - uav_write_pre = 1'b0; - uav_read = 1'b0; - uav_read_pre = 1'b0; - - if(!USE_CHIPSELECT) begin - if (USE_READ) begin - uav_read_pre=av_read; - end - - if (USE_WRITE) begin - uav_write_pre=av_write; - end - end - else begin - if(!USE_WRITE && USE_READ) begin - uav_read_pre=av_read; - uav_write_pre=av_chipselect & ~av_read; - end - else if(!USE_READ && USE_WRITE) begin - uav_write_pre=av_write; - uav_read_pre = av_chipselect & ~av_write; - end - else if (USE_READ && USE_WRITE) begin - uav_write_pre=av_write; - uav_read_pre=av_read; - end - end - - if(USE_READDATAVALID == 0) - uav_read = uav_read_pre & ~read_accepted; - else - uav_read = uav_read_pre; - - if(AV_REGISTERINCOMINGSIGNALS == 0) - uav_write=uav_write_pre; - else - uav_write=uav_write_pre & ~write_accepted; - - - end - - // ------------------- - // Begintransfer Assigment - // ------------------- - - reg end_begintransfer; - - always@* begin - if(USE_BEGINTRANSFER) begin - internal_begintransfer = av_begintransfer; - end else begin - internal_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer; - end - end - - always@ ( posedge clk or posedge reset ) begin - - if(reset) begin - end_begintransfer <= 1'b0; - end - else begin - - if(internal_begintransfer == 1 && uav_waitrequest) - end_begintransfer <= 1'b1; - else if(uav_waitrequest) - end_begintransfer <= end_begintransfer; - else - end_begintransfer <= 1'b0; - - end - - end - - // ------------------- - // Beginbursttransfer Assigment - // ------------------- - - reg end_beginbursttransfer; - wire last_burst_transfer_pre; - wire last_burst_transfer_reg; - wire last_burst_transfer; - - // compare values before the mux to shorten critical path; benchmark before changing - assign last_burst_transfer_pre = (uav_burstcount_pre == symbols_per_word); - assign last_burst_transfer_reg = (burstcount_register == symbols_per_word); - assign last_burst_transfer = (internal_beginbursttransfer) ? last_burst_transfer_pre : last_burst_transfer_reg; - - always@* begin - if(USE_BEGINBURSTTRANSFER) begin - internal_beginbursttransfer = av_beginbursttransfer; - end else begin - internal_beginbursttransfer = uav_read ? internal_begintransfer : internal_begintransfer && ~end_beginbursttransfer; - end - end - - always@ ( posedge clk or posedge reset ) begin - - if(reset) begin - end_beginbursttransfer <= 1'b0; - end - else begin - end_beginbursttransfer <= end_beginbursttransfer; - if( last_burst_transfer && internal_begintransfer || uav_read ) begin - end_beginbursttransfer <= 1'b0; - end - else if(uav_write && internal_begintransfer) begin - end_beginbursttransfer <= 1'b1; - end - end - - end - - // synthesis translate_off - - // ------------------------------------------------ - // check_1 : for waitrequest signal violation - // Ensure that when waitreqeust is asserted, the master is not allowed to change its controls - // Exception : begintransfer / beginbursttransfer - // : previously not in any transaction (idle) - // Note : Not checking clken which is not exactly part of Avalon controls/inputs - // : Not using system verilog assertions (seq/prop) since it is not supported if using Modelsim_SE - // ------------------------------------------------ - - reg av_waitrequest_r; - reg av_write_r,av_writeresponserequest_r,av_read_r,av_lock_r,av_chipselect_r,av_debugaccess_r; - reg [AV_ADDRESS_W-1:0] av_address_r; - reg [AV_BYTEENABLE_W-1:0] av_byteenable_r; - reg [AV_BURSTCOUNT_W-1:0] av_burstcount_r; - reg [AV_DATA_W-1:0] av_writedata_r; - - always @(posedge clk or posedge reset) begin - if (reset) begin - av_waitrequest_r <= '0; - av_write_r <= '0; - av_writeresponserequest_r <= '0; - av_read_r <= '0; - av_lock_r <= '0; - av_chipselect_r <= '0; - av_debugaccess_r <= '0; - av_address_r <= '0; - av_byteenable_r <= '0; - av_burstcount_r <= '0; - av_writedata_r <= '0; - - end - else begin - av_waitrequest_r <= av_waitrequest; - av_write_r <= av_write; - av_writeresponserequest_r <= av_writeresponserequest; - av_read_r <= av_read; - av_lock_r <= av_lock; - av_chipselect_r <= av_chipselect; - av_debugaccess_r <= av_debugaccess; - av_address_r <= av_address; - av_byteenable_r <= av_byteenable; - av_burstcount_r <= av_burstcount; - av_writedata_r <= av_writedata; - - if ( av_waitrequest_r && // When waitrequest is asserted - ( (av_write != av_write_r) || // Checks that : Input controls/data does not change - (av_writeresponserequest != av_writeresponserequest_r) || - (av_read != av_read_r) || - (av_lock != av_lock_r) || - (av_debugaccess != av_debugaccess_r) || - (av_address != av_address_r) || - (av_byteenable != av_byteenable_r) || - (av_burstcount != av_burstcount_r) - ) && - (av_write_r | av_read_r) && // Check only when : previously initiated a write/read - (!USE_CHIPSELECT | av_chipselect_r) // and chipselect was asserted (or unused) - ) - $display("%t: %m: Error: Input controls/data changed while av_waitrequest is asserted.\nav_address %x --> %x\nav_byteenable %x --> %x\nav_burstcount %x --> %x\nav_writedata %x --> %x\nav_writeresponserequest %x --> %x\nav_write %x --> %x\nav_read %x --> %x\nav_lock %x --> %x\nav_chipselect %x --> %x\nav_debugaccess %x --> %x ", $time(), - av_address_r , av_address, - av_byteenable_r , av_byteenable, - av_burstcount_r , av_burstcount, - av_writedata_r , av_writedata, - av_writeresponserequest_r, av_writeresponserequest, - av_write_r , av_write, - av_read_r , av_read, - av_lock_r , av_lock, - av_chipselect_r, av_chipselect, - av_debugaccess_r, av_debugaccess); - end - - // end check_1 - - end - - // synthesis translate_on - - - endmodule diff --git a/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv b/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv deleted file mode 100644 index ea599eb..0000000 --- a/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv +++ /dev/null @@ -1,588 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2011 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent.sv#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -`timescale 1 ns / 1 ns - -module altera_merlin_slave_agent -#( - // Packet parameters - parameter PKT_BEGIN_BURST = 81, - parameter PKT_DATA_H = 31, - parameter PKT_DATA_L = 0, - parameter PKT_SYMBOL_W = 8, - parameter PKT_BYTEEN_H = 71, - parameter PKT_BYTEEN_L = 68, - parameter PKT_ADDR_H = 63, - parameter PKT_ADDR_L = 32, - parameter PKT_TRANS_LOCK = 87, - parameter PKT_TRANS_COMPRESSED_READ = 67, - parameter PKT_TRANS_POSTED = 66, - parameter PKT_TRANS_WRITE = 65, - parameter PKT_TRANS_READ = 64, - parameter PKT_SRC_ID_H = 74, - parameter PKT_SRC_ID_L = 72, - parameter PKT_DEST_ID_H = 77, - parameter PKT_DEST_ID_L = 75, - parameter PKT_BURSTWRAP_H = 85, - parameter PKT_BURSTWRAP_L = 82, - parameter PKT_BYTE_CNT_H = 81, - parameter PKT_BYTE_CNT_L = 78, - parameter PKT_PROTECTION_H = 86, - parameter PKT_PROTECTION_L = 86, - parameter PKT_RESPONSE_STATUS_H = 89, - parameter PKT_RESPONSE_STATUS_L = 88, - parameter PKT_BURST_SIZE_H = 92, - parameter PKT_BURST_SIZE_L = 90, - parameter ST_DATA_W = 93, - parameter ST_CHANNEL_W = 32, - - // Slave parameters - parameter ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1, - parameter AVS_DATA_W = PKT_DATA_H - PKT_DATA_L + 1, - parameter AVS_BURSTCOUNT_W = 4, - parameter PKT_SYMBOLS = AVS_DATA_W / PKT_SYMBOL_W, - - // Slave agent parameters - parameter PREVENT_FIFO_OVERFLOW = 0, - parameter SUPPRESS_0_BYTEEN_CMD = 1, - parameter USE_READRESPONSE = 0, - parameter USE_WRITERESPONSE = 0, - - // Derived slave parameters - parameter AVS_BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, - parameter BURST_SIZE_W = 3, - - // Derived FIFO width - parameter FIFO_DATA_W = ST_DATA_W + 1 -) -( - - input clk, - input reset, - - // Universal-Avalon anti-slave - output [ADDR_W-1:0] m0_address, - output [AVS_BURSTCOUNT_W-1:0] m0_burstcount, - output [AVS_BE_W-1:0] m0_byteenable, - output m0_read, - input [AVS_DATA_W-1:0] m0_readdata, - input m0_waitrequest, - output m0_write, - output [AVS_DATA_W-1:0] m0_writedata, - input m0_readdatavalid, - output m0_debugaccess, - output m0_lock, - input [1:0] m0_response, - output m0_writeresponserequest, - input m0_writeresponsevalid, - - // Avalon-ST FIFO interfaces. - // Note: there's no need to include the "data" field here, at least for - // reads, since readdata is filled in from slave info. To keep life - // simple, have a data field, but fill it with 0s. - // Av-st response fifo source interface - output reg [FIFO_DATA_W-1:0] rf_source_data, - output rf_source_valid, - output rf_source_startofpacket, - output rf_source_endofpacket, - input rf_source_ready, - - // Av-st response fifo sink interface - input [FIFO_DATA_W-1:0] rf_sink_data, - input rf_sink_valid, - input rf_sink_startofpacket, - input rf_sink_endofpacket, - output rf_sink_ready, - - // Av-st readdata fifo src interface, data and response - // extra 2 bits for storing RESPONSE STATUS - output [AVS_DATA_W+1:0] rdata_fifo_src_data, - output rdata_fifo_src_valid, - input rdata_fifo_src_ready, - - // Av-st readdata fifo sink interface - input [AVS_DATA_W+1:0] rdata_fifo_sink_data, - input rdata_fifo_sink_valid, - output rdata_fifo_sink_ready, - - // Av-st sink command packet interface - output cp_ready, - input cp_valid, - input [ST_DATA_W-1:0] cp_data, - input [ST_CHANNEL_W-1:0] cp_channel, - input cp_startofpacket, - input cp_endofpacket, - - // Av-st source response packet interface - input rp_ready, - output reg rp_valid, - output reg [ST_DATA_W-1:0] rp_data, - output rp_startofpacket, - output rp_endofpacket -); - - // -------------------------------------------------- - // Ceil(log2()) function log2ceil of 4 = 2 - // -------------------------------------------------- - function integer log2ceil; - input reg[63:0] val; - reg [63:0] i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - - // ------------------------------------------------ - // Local Parameters - // ------------------------------------------------ - localparam DATA_W = PKT_DATA_H - PKT_DATA_L + 1; - localparam BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1; - localparam MID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1; - localparam SID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1; - localparam BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1; - localparam BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1; - localparam BURSTSIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1; - localparam BITS_TO_MASK = log2ceil(PKT_SYMBOLS); - - // ------------------------------------------------ - // Signals - // ------------------------------------------------ - wire [DATA_W-1:0] cmd_data; - wire [BE_W-1:0] cmd_byteen; - wire [ADDR_W-1:0] cmd_addr; - wire [MID_W-1:0] cmd_mid; - wire [SID_W-1:0] cmd_sid; - wire cmd_read; - wire cmd_write; - wire cmd_compressed; - wire cmd_posted; - wire [BYTE_CNT_W-1:0] cmd_byte_cnt; - wire [BURSTWRAP_W-1:0] cmd_burstwrap; - wire [BURSTSIZE_W-1:0] cmd_burstsize; - wire cmd_debugaccess; - - wire byteen_asserted; - wire needs_response_synthesis; - wire generate_response; - - // Assign command fields - assign cmd_data = cp_data[PKT_DATA_H :PKT_DATA_L ]; - assign cmd_byteen = cp_data[PKT_BYTEEN_H:PKT_BYTEEN_L]; - assign cmd_addr = cp_data[PKT_ADDR_H :PKT_ADDR_L ]; - assign cmd_compressed = cp_data[PKT_TRANS_COMPRESSED_READ]; - assign cmd_posted = cp_data[PKT_TRANS_POSTED]; - assign cmd_write = cp_data[PKT_TRANS_WRITE]; - assign cmd_read = cp_data[PKT_TRANS_READ]; - assign cmd_mid = cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L]; - assign cmd_sid = cp_data[PKT_DEST_ID_H:PKT_DEST_ID_L]; - assign cmd_byte_cnt = cp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]; - assign cmd_burstwrap = cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]; - assign cmd_burstsize = cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]; - assign cmd_debugaccess = cp_data[PKT_PROTECTION_L]; - - // Local "ready_for_command" signal: deasserted when the agent is unable to accept - // another command, e.g. rdv FIFO is full, (local readdata storage is full && - // ~rp_ready), ... - // Say, this could depend on the type of command, for example, even if the - // rdv FIFO is full, a write request can be accepted. For later. - wire ready_for_command; - - wire local_lock = cp_valid & cp_data[PKT_TRANS_LOCK]; - wire local_write = cp_valid & cp_data[PKT_TRANS_WRITE]; - wire local_read = cp_valid & cp_data[PKT_TRANS_READ]; - wire local_compressed_read = cp_valid & cp_data[PKT_TRANS_COMPRESSED_READ]; - wire nonposted_write_endofpacket = ~cp_data[PKT_TRANS_POSTED] & local_write & cp_endofpacket; - - // num_symbols is PKT_SYMBOLS, appropriately sized. - wire [31:0] int_num_symbols = PKT_SYMBOLS; - wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0]; - - generate - if (PREVENT_FIFO_OVERFLOW) begin : prevent_fifo_overflow - // --------------------------------------------------- - // Backpressure if the slave says to, or if FIFO overflow may occur. - // - // All commands are backpressured once the FIFO is full - // even if they don't need storage. This breaks a long - // combinatorial path from the master read/write through - // this logic and back to the master via the backpressure - // path. - // - // To avoid a loss of throughput the FIFO will be parameterized - // one slot deeper. The extra slot should never be used in normal - // operation, but should a slave misbehave and accept one more - // read than it should then backpressure will kick in. - // - // An example: assume a slave with MPRT = 2. It can accept a - // command sequence RRWW without backpressuring. If the FIFO is - // only 2 deep, we'd backpressure the writes leading to loss of - // throughput. If the FIFO is 3 deep, we'll only backpressure when - // RRR... which is an illegal condition anyway. - // --------------------------------------------------- - - assign ready_for_command = rf_source_ready; - assign cp_ready = (~m0_waitrequest | ~byteen_asserted) && ready_for_command; - - end else begin : no_prevent_fifo_overflow - - // Do not suppress the command or the slave will - // not be able to waitrequest - assign ready_for_command = 1'b1; - // Backpressure only if the slave says to. - assign cp_ready = ~m0_waitrequest | ~byteen_asserted; - - end - endgenerate - - generate if (SUPPRESS_0_BYTEEN_CMD) begin : suppress_0_byteen_cmd - assign byteen_asserted = |cmd_byteen; - end else begin : no_suppress_0_byteen_cmd - assign byteen_asserted = 1'b1; - end - endgenerate - - // ------------------------------------------------------------------- - // Extract avalon signals from command packet. - // ------------------------------------------------------------------- - // Mask off the lower bits of address. - // The burst adapter before this component will break narrow sized packets - // into sub-bursts of length 1. However, the packet addresses are preserved, - // which means this component may see size-aligned addresses. - // - // Masking ensures that the addresses seen by an Avalon slave are aligned to - // the full data width instead of the size. - // - // Example: - // output from burst adapter (datawidth=4, size=2 bytes): - // subburst1 addr=0, subburst2 addr=2, subburst3 addr=4, subburst4 addr=6 - // expected output from slave agent: - // subburst1 addr=0, subburst2 addr=0, subburst3 addr=4, subburst4 addr=4 - generate - if (BITS_TO_MASK > 0) begin : mask_address - - assign m0_address = { cmd_addr[ADDR_W-1:BITS_TO_MASK], {BITS_TO_MASK{1'b0}} }; - - end else begin : no_mask_address - - assign m0_address = cmd_addr; - - end - endgenerate - - assign m0_byteenable = cmd_byteen; - assign m0_writedata = cmd_data; - - // Note: no Avalon-MM slave in existence accepts uncompressed read bursts - - // this sort of burst exists only in merlin fabric ST packets. What to do - // if we see such a burst? All beats in that burst need to be transmitted - // to the slave so we have enough space-time for byteenable expression. - // - // There can be multiple bursts in a packet, but only one beat per burst - // in cases. The exception is when we've decided not to insert a - // burst adapter for efficiency reasons, in which case this agent is also - // responsible for driving burstcount to 1 on each beat of an uncompressed - // read burst. - - assign m0_read = ready_for_command & byteen_asserted & - (local_compressed_read | local_read); - - generate - begin : m0_burstcount_zero_pad - // AVS_BURSTCOUNT_W and BYTE_CNT_W may not be equal. Assign m0_burstcount - // from a sub-range, or 0-pad, as appropriate. - if (AVS_BURSTCOUNT_W > BYTE_CNT_W) begin - wire [AVS_BURSTCOUNT_W - BYTE_CNT_W - 1 : 0] zero_pad = - {(AVS_BURSTCOUNT_W - BYTE_CNT_W) {1'b0}}; - assign m0_burstcount = (local_read & ~local_compressed_read) ? - {zero_pad, num_symbols} : - {zero_pad, cmd_byte_cnt}; - end - else begin : m0_burstcount_no_pad - assign m0_burstcount = (local_read & ~local_compressed_read) ? - num_symbols[AVS_BURSTCOUNT_W-1:0] : - cmd_byte_cnt[AVS_BURSTCOUNT_W-1:0]; - end - end - endgenerate - - assign m0_write = ready_for_command & local_write & byteen_asserted; - assign m0_lock = ready_for_command & local_lock & (m0_read | m0_write); - assign m0_debugaccess = cmd_debugaccess; - // For now, to support write response - assign m0_writeresponserequest = ready_for_command & local_write & byteen_asserted & !cmd_posted; - //assign m0_writeresponserequest = '0; - - // ------------------------------------------------------------------- - // Indirection layer for response packet values. Some may always wire - // directly from the slave translator; others will no doubt emerge from - // various FIFOs. - // What to put in resp_data when a write occured? Answer: it does not - // matter, because only response status is needed for non-posted writes, - // and the packet already has a field for that. - - // tgngo:Use the rdata_fifo to store write response as well - // So that we wont lost response if master can back-pressured - // as well as it needs for write response merging - assign rdata_fifo_src_valid = m0_readdatavalid | m0_writeresponsevalid; - //assign rdata_fifo_src_valid = m0_readdatavalid; - assign rdata_fifo_src_data = {m0_response,m0_readdata}; - - // ------------------------------------------------------------------ - // Generate a token when read commands are suppressed. The token - // is stored in the response FIFO, and will be used to synthesize - // a read response. The same token is used for non-posted write - // response synthesis. - // - // Note: this token is not generated for suppressed uncompressed read cycles; - // the burst uncompression logic at the read side of the response FIFO - // generates the correct number of responses. - // ------------------------------------------------------------------ - // When the slave can return the response, let it does its works. Dont generate sysnthesis response - assign needs_response_synthesis = ((local_read | local_compressed_read) & !byteen_asserted) | (nonposted_write_endofpacket && !USE_WRITERESPONSE); - - // Avalon-ST interfaces to external response fifo: - // tgngo:Currently, with "generate response synthesis", only one write command is allowed to write in at eop of non-posted write - // To support response from slave, we need to store each sub-burst of write command into fifo. - // Each sub-burst will return a response and these two command and response are popped out together - // Resposne merging will happen and at end_of_packet of the command - the last sub-burst write - // the slave agent will send out the final merged response - - wire internal_cp_endofburst; - wire [31:0] minimum_bytecount_wire = PKT_SYMBOLS; // to solve qis warning - wire [AVS_BURSTCOUNT_W-1:0] minimum_bytecount; - assign minimum_bytecount = minimum_bytecount_wire[AVS_BURSTCOUNT_W-1:0]; - assign internal_cp_endofburst = (cmd_byte_cnt == minimum_bytecount); - wire local_nonposted_write = ~cp_data[PKT_TRANS_POSTED] & local_write; - wire nonposted_end_of_subburst = local_nonposted_write & internal_cp_endofburst; - - assign rf_source_valid = (local_read | local_compressed_read | (nonposted_write_endofpacket && !USE_WRITERESPONSE) | (USE_WRITERESPONSE && nonposted_end_of_subburst)) - & ready_for_command & cp_ready; - assign rf_source_startofpacket = cp_startofpacket; - assign rf_source_endofpacket = cp_endofpacket; - always @* begin - // default: assign every command packet field to the response FIFO... - rf_source_data = {1'b0, cp_data}; - - // ... and override select fields as needed. - rf_source_data[FIFO_DATA_W-1] = needs_response_synthesis; - rf_source_data[PKT_DATA_H :PKT_DATA_L] = {DATA_W {1'b0}}; - rf_source_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = cmd_byteen; - rf_source_data[PKT_ADDR_H :PKT_ADDR_L] = cmd_addr; - //rf_source_data[PKT_ADDR_H :PKT_ADDR_L] = m0_address; - rf_source_data[PKT_TRANS_COMPRESSED_READ] = cmd_compressed; - rf_source_data[PKT_TRANS_POSTED] = cmd_posted; - rf_source_data[PKT_TRANS_WRITE] = cmd_write; - rf_source_data[PKT_TRANS_READ] = cmd_read; - rf_source_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = cmd_mid; - rf_source_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = cmd_sid; - rf_source_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = cmd_byte_cnt; - rf_source_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = cmd_burstwrap; - rf_source_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = cmd_burstsize; - rf_source_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = '0; - rf_source_data[PKT_PROTECTION_L] = cmd_debugaccess; - end - - wire uncompressor_source_valid; - wire [BURSTSIZE_W-1:0] uncompressor_burstsize; - - //assign rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; - // tgngo: last_write_response indicates the last response of the burst (incase need sub-burst) - // at this time, the final response merged will send out, and rp_valid is only asserted - // for one response for whole burst - generate - if (USE_READRESPONSE & USE_WRITERESPONSE) begin - wire last_write_response = rf_sink_data[PKT_TRANS_WRITE] & !rf_sink_data[PKT_TRANS_POSTED] & rf_sink_endofpacket; - always @* begin - if (rf_sink_data[PKT_TRANS_WRITE] == 1) - rp_valid = rdata_fifo_sink_valid & last_write_response; - else - rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; - end - end else begin - always @* begin - rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; - end - end - endgenerate - // ------------------------------------------------------------------ - // Response merging - // ------------------------------------------------------------------ - wire [1:0] current_response = rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W]; - reg [1:0] response_merged; - generate - begin: response_merging - if (USE_READRESPONSE & USE_WRITERESPONSE) begin - reg first_write_response; - reg reset_merged_output; - reg [1:0] previous_response_in; - reg [1:0] previous_response; - - always_ff @(posedge clk, posedge reset) begin - if (reset) begin - first_write_response <= 1'b1; - end - else begin // Merging work for write response, for read: previous_response_in = current_response - if (rf_sink_valid & rdata_fifo_sink_valid & rf_sink_data[PKT_TRANS_WRITE]) begin - first_write_response <= 1'b0; - if (rf_sink_endofpacket) - first_write_response <= 1'b1; - end - end - end - - always_comb begin - reset_merged_output = first_write_response && rdata_fifo_sink_valid; - previous_response_in = reset_merged_output ? current_response : previous_response; - response_merged = current_response >= previous_response ? current_response: previous_response_in; - end - - always_ff @(posedge clk or posedge reset) begin - if (reset) begin - previous_response <= 2'b00; - end - else begin - if (rf_sink_valid & rdata_fifo_sink_valid) begin - previous_response <= response_merged; - end - end - end - end else begin - always @* begin - response_merged = current_response; - end - end - end - endgenerate - - assign generate_response = rf_sink_data[FIFO_DATA_W-1]; - - wire [BYTE_CNT_W-1:0] rf_sink_byte_cnt = rf_sink_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]; - wire rf_sink_compressed = rf_sink_data[PKT_TRANS_COMPRESSED_READ]; - wire [BURSTWRAP_W-1:0] rf_sink_burstwrap = rf_sink_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]; - wire [BURSTSIZE_W-1:0] rf_sink_burstsize = rf_sink_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]; - wire [ADDR_W-1:0] rf_sink_addr = rf_sink_data[PKT_ADDR_H:PKT_ADDR_L]; - // a non posted write response is always completed in 1 cycle. Modify the startofpacket signal to 1'b1 instead of taking whatever is in the rf_fifo - wire rf_sink_startofpacket_wire = rf_sink_data[PKT_TRANS_WRITE] ? 1'b1 : rf_sink_startofpacket; - - wire [BYTE_CNT_W-1:0] burst_byte_cnt; - wire [BURSTWRAP_W-1:0] rp_burstwrap; - wire [ADDR_W-1:0] rp_address; - wire rp_is_compressed; - - // ------------------------------------------------------------------ - // Backpressure the readdata fifo if we're supposed to synthesize a response. - // This may be a read response (for suppressed reads) or a write response - // (for non-posted writes). - // ------------------------------------------------------------------ - assign rdata_fifo_sink_ready = rdata_fifo_sink_valid & rp_ready & ~(rf_sink_valid & generate_response); - - always @* begin - // By default, return all fields... - rp_data = rf_sink_data[ST_DATA_W - 1 : 0]; - - // ... and override specific fields. - rp_data[PKT_DATA_H :PKT_DATA_L] = rdata_fifo_sink_data[AVS_DATA_W-1:0]; - // Assignments directly from the response fifo. - rp_data[PKT_TRANS_POSTED] = rf_sink_data[PKT_TRANS_POSTED]; - rp_data[PKT_TRANS_WRITE] = rf_sink_data[PKT_TRANS_WRITE]; - rp_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = rf_sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; - rp_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = rf_sink_data[PKT_SRC_ID_H : PKT_SRC_ID_L]; - rp_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = rf_sink_data[PKT_BYTEEN_H : PKT_BYTEEN_L]; - rp_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = rf_sink_data[PKT_PROTECTION_H:PKT_PROTECTION_L]; - - // Burst uncompressor assignments - rp_data[PKT_ADDR_H :PKT_ADDR_L] = rp_address; - rp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = rp_burstwrap; - rp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = burst_byte_cnt; - rp_data[PKT_TRANS_READ] = rf_sink_data[PKT_TRANS_READ] | rf_sink_data[PKT_TRANS_COMPRESSED_READ]; - rp_data[PKT_TRANS_COMPRESSED_READ] = rp_is_compressed; - - // avalon slaves always respond with "okay" -> not true for now - //rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L] = {RESPONSE_W{ 1'b0 }}; - rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L] = response_merged; - rp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = uncompressor_burstsize; - end - - // ------------------------------------------------------------------ - // Note: the burst uncompressor may be asked to generate responses for - // write packets; these are treated the same as single-cycle uncompressed - // reads. - // ------------------------------------------------------------------ - altera_merlin_burst_uncompressor #( - .ADDR_W (ADDR_W), - .BURSTWRAP_W (BURSTWRAP_W), - .BYTE_CNT_W (BYTE_CNT_W), - .PKT_SYMBOLS (PKT_SYMBOLS) - ) uncompressor - ( - .clk (clk), - .reset (reset), - .sink_startofpacket (rf_sink_startofpacket_wire), - .sink_endofpacket (rf_sink_endofpacket), - .sink_valid (rf_sink_valid & (rdata_fifo_sink_valid | generate_response)), - .sink_ready (rf_sink_ready), - .sink_addr (rf_sink_addr), - .sink_burstwrap (rf_sink_burstwrap), - .sink_byte_cnt (rf_sink_byte_cnt), - .sink_is_compressed (rf_sink_compressed), - .sink_burstsize (rf_sink_burstsize), - - .source_startofpacket (rp_startofpacket), - .source_endofpacket (rp_endofpacket), - .source_valid (uncompressor_source_valid), - .source_ready (rp_ready), - .source_addr (rp_address), - .source_burstwrap (rp_burstwrap), - .source_byte_cnt (burst_byte_cnt), - .source_is_compressed (rp_is_compressed), - .source_burstsize (uncompressor_burstsize) - ); - -//-------------------------------------- -// Assertion: In case slave support response. Yhe slave needs return response in order -// Ex: non-posted write followed by a read: write response must complete before read data -//-------------------------------------- -// synthesis translate_off -ERROR_write_response_and_read_response_cannot_happen_same_time: - assert property ( @(posedge clk) - disable iff (reset) !(m0_writeresponsevalid && m0_readdatavalid) - ); - -// synthesis translate_on -endmodule - diff --git a/db/ip/nios_system/submodules/altera_merlin_slave_translator.sv b/db/ip/nios_system/submodules/altera_merlin_slave_translator.sv deleted file mode 100644 index bcb2311..0000000 --- a/db/ip/nios_system/submodules/altera_merlin_slave_translator.sv +++ /dev/null @@ -1,533 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------- -// Merlin Slave Translator -// -// Translates Universal Avalon MM Slave -// to any Avalon MM Slave -// ------------------------------------- -// -//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one -//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero -//The key feature here is that no same cycle turnaround data is processed through the fabric. - -//import avalon_utilities_pkg::*; - -`timescale 1 ns / 1 ns - -module altera_merlin_slave_translator - #( - parameter - //Widths - AV_ADDRESS_W = 32, - AV_DATA_W = 32, - AV_BURSTCOUNT_W = 4, - AV_BYTEENABLE_W = 4, - UAV_BYTEENABLE_W = 4, - - //Read Latency - AV_READLATENCY = 1, - - //Timing - AV_READ_WAIT_CYCLES = 0, - AV_WRITE_WAIT_CYCLES = 0, - AV_SETUP_WAIT_CYCLES = 0, - AV_DATA_HOLD_CYCLES = 0, - - //Optional Port Declarations - USE_READDATAVALID = 1, - USE_WAITREQUEST = 1, - USE_READRESPONSE = 0, - USE_WRITERESPONSE = 0, - - //Variable Addressing - AV_SYMBOLS_PER_WORD = 4, - AV_ADDRESS_SYMBOLS = 0, - AV_BURSTCOUNT_SYMBOLS = 0, - BITS_PER_WORD = clog2_plusone(AV_SYMBOLS_PER_WORD - 1), - UAV_ADDRESS_W = 38, - UAV_BURSTCOUNT_W = 10, - UAV_DATA_W = 32, - - AV_CONSTANT_BURST_BEHAVIOR = 0, - UAV_CONSTANT_BURST_BEHAVIOR = 0, - CHIPSELECT_THROUGH_READLATENCY = 0, - - // Tightly-Coupled Options - USE_UAV_CLKEN = 0, - AV_REQUIRE_UNALIGNED_ADDRESSES = 0 - ) - ( - - // ------------------- - // Clock & Reset - // ------------------- - input wire clk, - input wire reset, - - // ------------------- - // Universal Avalon Slave - // ------------------- - - input wire [UAV_ADDRESS_W - 1 : 0] uav_address, - input wire [UAV_DATA_W - 1 : 0] uav_writedata, - input wire uav_write, - input wire uav_read, - input wire [UAV_BURSTCOUNT_W - 1 : 0] uav_burstcount, - input wire [UAV_BYTEENABLE_W - 1 : 0] uav_byteenable, - input wire uav_lock, - input wire uav_debugaccess, - input wire uav_clken, - - output logic uav_readdatavalid, - output logic uav_waitrequest, - output logic [UAV_DATA_W - 1 : 0] uav_readdata, - output logic [1:0] uav_response, - input wire uav_writeresponserequest, - output logic uav_writeresponsevalid, - - // ------------------- - // Customizable Avalon Master - // ------------------- - output logic [AV_ADDRESS_W - 1 : 0] av_address, - output logic [AV_DATA_W - 1 : 0] av_writedata, - output logic av_write, - output logic av_read, - output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount, - output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable, - output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable, - output logic av_begintransfer, - output wire av_chipselect, - output logic av_beginbursttransfer, - output logic av_lock, - output wire av_clken, - output wire av_debugaccess, - output wire av_outputenable, - - input logic [AV_DATA_W - 1 : 0] av_readdata, - input logic av_readdatavalid, - input logic av_waitrequest, - - input logic [1:0] av_response, - output logic av_writeresponserequest, - input wire av_writeresponsevalid - - ); - - function integer clog2_plusone; - input [31:0] Depth; - integer i; - begin - i = Depth; - for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1) - i = i >> 1; - end - - endfunction - - function integer max; - //returns the larger of two passed arguments - input [31:0] one; - input [31:0] two; - - if(one > two) - max=one; - else - max=two; - endfunction // int - - localparam AV_READ_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES); - localparam AV_WRITE_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES); - localparam AV_DATA_HOLD_INDEXED = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES); - localparam LOG2_OF_LATENCY_SUM = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1)); - localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD; - localparam ADDRESS_SHIFT_SELECTOR = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD; - - localparam ADDRESS_HIGH = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ? - AV_ADDRESS_W : - UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR; - - localparam BURSTCOUNT_HIGH = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ? - AV_BURSTCOUNT_W : - UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR; - localparam BYTEENABLE_ADDRESS_BITS = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1; - - - // Calculate the symbols per word as the power of 2 extended symbols per word - wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1)); - wire [UAV_BURSTCOUNT_W : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W : 0]; - - // +-------------------------------- - // |Backwards Compatibility Signals - // +-------------------------------- - assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1; - assign av_debugaccess = uav_debugaccess; - - // +------------------- - // |Passthru Signals - // +------------------- - always_comb - begin - if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin - uav_response = '0; - end else begin - uav_response = av_response; - end - end - assign av_writeresponserequest = uav_writeresponserequest; - assign uav_writeresponsevalid = av_writeresponsevalid; - - //------------------------- - //Writedata and Byteenable - //------------------------- - - always@* begin - av_byteenable = '0; - av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0]; - end - - always@* begin - av_writedata = '0; - av_writedata = uav_writedata[AV_DATA_W - 1 : 0]; - end - - // +------------------- - // |Calculated Signals - // +------------------- - - logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address; - - function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable; - input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable; - - for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin - if(byteenable[i] == 1) begin - return i; - end - end - - return '0; - - endfunction - - reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg; - reg [AV_ADDRESS_W - 1 : 0] address_reg; - - - always@(posedge clk, posedge reset) begin - if(reset) begin - burstcount_reg <= '0; - address_reg <= '0; - end - else begin - burstcount_reg <= burstcount_reg; - address_reg <= address_reg; - - if(av_beginbursttransfer) begin - burstcount_reg <= uav_burstcount [BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ]; - address_reg <= real_uav_address [ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ]; - - end - end - end - - - logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire; - - always@* begin - if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin - temp_wire = decode_byteenable(uav_byteenable); - - real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] }; - end - else begin - real_uav_address = uav_address; - end - - av_address = real_uav_address[ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ]; - - if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer ) - av_address = address_reg; - end - - always@* begin - av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ]; - - if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer ) - av_burstcount = burstcount_reg; - end - - always@* begin - av_lock = uav_lock; - end - - // ------------------- - // Writebyteenable Assignment - // ------------------- - -always@* begin - av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0]; -end - - // ------------------- - // Waitrequest Assignment - // ------------------- - - reg av_waitrequest_generated; - reg av_waitrequest_generated_read; - reg av_waitrequest_generated_write; - reg waitrequest_reset_override; - - reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter; - - always@(posedge reset, posedge clk) begin - - if(reset) begin - wait_latency_counter <= '0; - waitrequest_reset_override <= 1'h1; - end - else begin - waitrequest_reset_override <= 1'h0; - - wait_latency_counter <= '0; - - if( uav_read | uav_write ) - wait_latency_counter <= wait_latency_counter + 1'h1; - - if( ~uav_waitrequest | waitrequest_reset_override ) - wait_latency_counter <= '0; - - end - - end - - - always @* begin - - av_read = uav_read; - av_write = uav_write; - - av_waitrequest_generated = 1'h1; - av_waitrequest_generated_read = 1'h1; - av_waitrequest_generated_write = 1'h1; - - if(LOG2_OF_LATENCY_SUM == 1) - av_waitrequest_generated = 0; - - if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin - av_read = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read; - av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED; - - av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED; - av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED; - - if(uav_write) - av_waitrequest_generated = av_waitrequest_generated_write; - else - av_waitrequest_generated = av_waitrequest_generated_read; - - end - - if(USE_WAITREQUEST) begin - uav_waitrequest = av_waitrequest; - end - else begin - uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override; - end - - end - - // -------------- - // Readdata Assignment - // -------------- - - reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre; - - always@(posedge clk, posedge reset) begin - if(reset) - av_readdata_pre <= 'b0; - else - av_readdata_pre <= av_readdata; - end - - always@* begin - uav_readdata = '0; - - if( AV_READLATENCY != 0 || USE_READDATAVALID ) begin - uav_readdata = av_readdata; - end - else begin - uav_readdata = av_readdata_pre; - end - end - // ------------------- - // Readdatavalid Assigment - // ------------------- - - reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg; - reg top_read_latency_shift_reg; - - - - always@* begin - - uav_readdatavalid=top_read_latency_shift_reg; - - if(USE_READDATAVALID) begin - uav_readdatavalid = av_readdatavalid; - end - - end - - always@* begin - - top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override; - - if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin - top_read_latency_shift_reg=read_latency_shift_reg; - end - - if (AV_READLATENCY > 1) begin - top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)]; - end - - end - - always@(posedge reset, posedge clk) begin - - if (reset) begin - read_latency_shift_reg <= '0; - end - else if (av_clken) begin - - read_latency_shift_reg <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override; - - for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin - read_latency_shift_reg[i+1] <= read_latency_shift_reg[i]; - end - - end - - end - - // ------------ - // Chipselect and OutputEnable - // ------------ - - reg av_chipselect_pre; - wire cs_extension; - reg av_outputenable_pre; - - - assign av_chipselect = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre; - assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg)); - - assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre; - - always@(posedge reset, posedge clk) begin - if(reset) - av_outputenable_pre <= 1'b0; - else if( AV_READLATENCY == 0 && AV_READ_WAIT_INDEXED != 0 ) - av_outputenable_pre <= 0; - else - av_outputenable_pre <= cs_extension | uav_read; - end - - always@(posedge reset, posedge clk) begin - if(reset) begin - av_chipselect_pre <= 1'b0; - end - else begin - av_chipselect_pre <= 1'b0; - - if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin - //The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall. - //There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator. - if(uav_read) begin - av_chipselect_pre <= 1'b1; - end - else if(cs_extension == 1) begin - av_chipselect_pre <= 1'b1; - end - - end - end - end - - // ------------------- - // Begintransfer Assigment - // ------------------- - - reg end_begintransfer; - - always@* begin - av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer; - end - - always@ ( posedge clk or posedge reset ) begin - - if(reset) begin - end_begintransfer <= 1'b0; - end - else begin - - if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override) - end_begintransfer <= 1'b1; - else if(uav_waitrequest) - end_begintransfer <= end_begintransfer; - else - end_begintransfer <= 1'b0; - - end - - end - - // ------------------- - // Beginbursttransfer Assigment - // ------------------- - - reg end_beginbursttransfer; - reg in_transfer; - - - - always@* begin - av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer); - end - - always@ ( posedge clk or posedge reset ) begin - if(reset) begin - end_beginbursttransfer <= 1'b0; - in_transfer <= 1'b0; - end - else begin - - end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word ); - - if(uav_write && uav_burstcount == symbols_per_word) - in_transfer <=1'b0; - else if(uav_write) - in_transfer <=1'b1; - - end - - end - -endmodule diff --git a/db/ip/nios_system/submodules/altera_reset_controller.sdc b/db/ip/nios_system/submodules/altera_reset_controller.sdc deleted file mode 100644 index d58dd05..0000000 --- a/db/ip/nios_system/submodules/altera_reset_controller.sdc +++ /dev/null @@ -1,33 +0,0 @@ -# (C) 2001-2013 Altera Corporation. All rights reserved. -# Your use of Altera Corporation's design tools, logic functions and other -# software and tools, and its AMPP partner logic functions, and any output -# files any of the foregoing (including device programming or simulation -# files), and any associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License Subscription -# Agreement, Altera MegaCore Function License Agreement, or other applicable -# license agreement, including, without limitation, that your use is for the -# sole purpose of programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the applicable -# agreement for further details. - - -# +--------------------------------------------------- -# | Cut the async clear paths -# +--------------------------------------------------- -set aclr_counter 0 -set clrn_counter 0 -set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] -set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] -foreach_in_collection aclr_pin $aclr_collection { - set aclr_counter [expr $aclr_counter + 1] -} -foreach_in_collection clrn_pin $clrn_collection { - set clrn_counter [expr $clrn_counter + 1] -} -if {$aclr_counter > 0} { - set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] -} - -if {$clrn_counter > 0} { - set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] -} diff --git a/db/ip/nios_system/submodules/altera_reset_controller.v b/db/ip/nios_system/submodules/altera_reset_controller.v deleted file mode 100644 index 7c250c7..0000000 --- a/db/ip/nios_system/submodules/altera_reset_controller.v +++ /dev/null @@ -1,206 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_reset_controller/altera_reset_controller.v#2 $ -// $Revision: #2 $ -// $Date: 2013/06/03 $ -// $Author: wkleong $ - -// -------------------------------------- -// Reset controller -// -// Combines all the input resets and synchronizes -// the result to the clk. -// ACDS13.1 - Added reset request as part of reset sequencing -// -------------------------------------- - -`timescale 1 ns / 1 ns - -module altera_reset_controller -#( - parameter NUM_RESET_INPUTS = 6, - parameter OUTPUT_RESET_SYNC_EDGES = "deassert", - parameter SYNC_DEPTH = 2, - parameter RESET_REQUEST_PRESENT = 0 -) -( - // -------------------------------------- - // We support up to 16 reset inputs, for now - // -------------------------------------- - input reset_in0, - input reset_in1, - input reset_in2, - input reset_in3, - input reset_in4, - input reset_in5, - input reset_in6, - input reset_in7, - input reset_in8, - input reset_in9, - input reset_in10, - input reset_in11, - input reset_in12, - input reset_in13, - input reset_in14, - input reset_in15, - - input clk, - output reg reset_out, - output reg reset_req -); - - localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert"); - - localparam DEPTH = 2; - localparam CLKEN_LAGS_RESET = 0; - localparam EARLY_RST_TAP = (CLKEN_LAGS_RESET != 0) ? 0 : 1; - - wire merged_reset; - wire reset_out_pre; - - // Registers and Interconnect - (*preserve*) reg [SYNC_DEPTH: 0] altera_reset_synchronizer_int_chain; - reg [(SYNC_DEPTH-1): 0] r_sync_rst_chain; - reg r_sync_rst_dly; - reg r_sync_rst; - reg r_early_rst; - - // -------------------------------------- - // "Or" all the input resets together - // -------------------------------------- - assign merged_reset = ( - reset_in0 | - reset_in1 | - reset_in2 | - reset_in3 | - reset_in4 | - reset_in5 | - reset_in6 | - reset_in7 | - reset_in8 | - reset_in9 | - reset_in10 | - reset_in11 | - reset_in12 | - reset_in13 | - reset_in14 | - reset_in15 - ); - - // -------------------------------------- - // And if required, synchronize it to the required clock domain, - // with the correct synchronization type - // -------------------------------------- - generate if (OUTPUT_RESET_SYNC_EDGES == "none") begin - - assign reset_out_pre = merged_reset; - - end else begin - - altera_reset_synchronizer - #( - .DEPTH (SYNC_DEPTH), - .ASYNC_RESET(ASYNC_RESET) - ) - alt_rst_sync_uq1 - ( - .clk (clk), - .reset_in (merged_reset), - .reset_out (reset_out_pre) - ); - - end - endgenerate - - generate if (RESET_REQUEST_PRESENT == 0) begin - always @* begin - reset_out = reset_out_pre; - reset_req = 1'b0; - end - end - else begin - - // 3-FF Metastability Synchronizer - initial - begin - altera_reset_synchronizer_int_chain <= 3'b111; - end - - always @(posedge clk) - begin - altera_reset_synchronizer_int_chain[2:0] <= {altera_reset_synchronizer_int_chain[1:0], reset_out_pre}; - end - - - // Synchronous reset pipe - initial - begin - r_sync_rst_chain <= {DEPTH{1'b1}}; - end - - always @(posedge clk) - begin - if (altera_reset_synchronizer_int_chain[2] == 1'b1) - begin - r_sync_rst_chain <= {DEPTH{1'b1}}; - end - else - begin - r_sync_rst_chain <= {1'b0, r_sync_rst_chain[DEPTH-1:1]}; - end - end - - // Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition - // matches the early input. - initial - begin - r_sync_rst_dly <= 1'b1; - r_sync_rst <= 1'b1; - r_early_rst <= 1'b1; - end - - always @(posedge clk) - begin - // Delayed reset pipeline register - r_sync_rst_dly <= r_sync_rst_chain[DEPTH-1]; - - case ({r_sync_rst_dly, r_sync_rst_chain[1], r_sync_rst}) - 3'b000: r_sync_rst <= 1'b0; // Not reset - 3'b001: r_sync_rst <= 1'b0; - 3'b010: r_sync_rst <= 1'b0; - 3'b011: r_sync_rst <= 1'b1; - 3'b100: r_sync_rst <= 1'b1; - 3'b101: r_sync_rst <= 1'b1; - 3'b110: r_sync_rst <= 1'b1; - 3'b111: r_sync_rst <= 1'b1; // In Reset - default: r_sync_rst <= 1'b1; - endcase - - case ({r_sync_rst_chain[DEPTH-1], r_sync_rst_chain[EARLY_RST_TAP]}) - 2'b00: r_early_rst <= 1'b0; // Not reset - 2'b01: r_early_rst <= 1'b1; // Coming out of reset - 2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design. - 2'b11: r_early_rst <= 1'b1; // Held in reset - default: r_early_rst <= 1'b1; - endcase - end - - always @* begin - reset_out = r_sync_rst; - reset_req = r_early_rst; - end - - end - endgenerate - -endmodule diff --git a/db/ip/nios_system/submodules/altera_reset_synchronizer.v b/db/ip/nios_system/submodules/altera_reset_synchronizer.v deleted file mode 100644 index 14936c3..0000000 --- a/db/ip/nios_system/submodules/altera_reset_synchronizer.v +++ /dev/null @@ -1,87 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ----------------------------------------------- -// Reset Synchronizer -// ----------------------------------------------- -`timescale 1 ns / 1 ns - -module altera_reset_synchronizer -#( - parameter ASYNC_RESET = 1, - parameter DEPTH = 2 -) -( - input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, - - input clk, - output reset_out -); - - // ----------------------------------------------- - // Synchronizer register chain. We cannot reuse the - // standard synchronizer in this implementation - // because our timing constraints are different. - // - // Instead of cutting the timing path to the d-input - // on the first flop we need to cut the aclr input. - // - // We omit the "preserve" attribute on the final - // output register, so that the synthesis tool can - // duplicate it where needed. - // ----------------------------------------------- - (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; - reg altera_reset_synchronizer_int_chain_out; - - generate if (ASYNC_RESET) begin - - // ----------------------------------------------- - // Assert asynchronously, deassert synchronously. - // ----------------------------------------------- - always @(posedge clk or posedge reset_in) begin - if (reset_in) begin - altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; - altera_reset_synchronizer_int_chain_out <= 1'b1; - end - else begin - altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; - altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; - altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; - end - end - - assign reset_out = altera_reset_synchronizer_int_chain_out; - - end else begin - - // ----------------------------------------------- - // Assert synchronously, deassert synchronously. - // ----------------------------------------------- - always @(posedge clk) begin - altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; - altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; - altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; - end - - assign reset_out = altera_reset_synchronizer_int_chain_out; - - end - endgenerate - -endmodule - diff --git a/db/ip/nios_system/submodules/nios_system_LEDRs.v b/db/ip/nios_system/submodules/nios_system_LEDRs.v deleted file mode 100644 index 63ed909..0000000 --- a/db/ip/nios_system/submodules/nios_system_LEDRs.v +++ /dev/null @@ -1,66 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_LEDRs ( - // inputs: - address, - chipselect, - clk, - reset_n, - write_n, - writedata, - - // outputs: - out_port, - readdata - ) -; - - output [ 17: 0] out_port; - output [ 31: 0] readdata; - input [ 1: 0] address; - input chipselect; - input clk; - input reset_n; - input write_n; - input [ 31: 0] writedata; - - wire clk_en; - reg [ 17: 0] data_out; - wire [ 17: 0] out_port; - wire [ 17: 0] read_mux_out; - wire [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {18 {(address == 0)}} & data_out; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - data_out <= 0; - else if (chipselect && ~write_n && (address == 0)) - data_out <= writedata[17 : 0]; - end - - - assign readdata = {32'b0 | read_mux_out}; - assign out_port = data_out; - -endmodule - diff --git a/db/ip/nios_system/submodules/nios_system_LEDs.v b/db/ip/nios_system/submodules/nios_system_LEDs.v deleted file mode 100644 index 4e22fe4..0000000 --- a/db/ip/nios_system/submodules/nios_system_LEDs.v +++ /dev/null @@ -1,66 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_LEDs ( - // inputs: - address, - chipselect, - clk, - reset_n, - write_n, - writedata, - - // outputs: - out_port, - readdata - ) -; - - output [ 7: 0] out_port; - output [ 31: 0] readdata; - input [ 1: 0] address; - input chipselect; - input clk; - input reset_n; - input write_n; - input [ 31: 0] writedata; - - wire clk_en; - reg [ 7: 0] data_out; - wire [ 7: 0] out_port; - wire [ 7: 0] read_mux_out; - wire [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {8 {(address == 0)}} & data_out; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - data_out <= 0; - else if (chipselect && ~write_n && (address == 0)) - data_out <= writedata[7 : 0]; - end - - - assign readdata = {32'b0 | read_mux_out}; - assign out_port = data_out; - -endmodule - diff --git a/db/ip/nios_system/submodules/nios_system_addr_router.sv b/db/ip/nios_system/submodules/nios_system_addr_router.sv deleted file mode 100644 index 3c8760e..0000000 --- a/db/ip/nios_system/submodules/nios_system_addr_router.sv +++ /dev/null @@ -1,224 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------------------- -// Merlin Router -// -// Asserts the appropriate one-hot encoded channel based on -// either (a) the address or (b) the dest id. The DECODER_TYPE -// parameter controls this behaviour. 0 means address decoder, -// 1 means dest id decoder. -// -// In the case of (a), it also sets the destination id. -// ------------------------------------------------------- - -`timescale 1 ns / 1 ns - -module nios_system_addr_router_default_decode - #( - parameter DEFAULT_CHANNEL = 1, - DEFAULT_WR_CHANNEL = -1, - DEFAULT_RD_CHANNEL = -1, - DEFAULT_DESTID = 15 - ) - (output [85 - 81 : 0] default_destination_id, - output [18-1 : 0] default_wr_channel, - output [18-1 : 0] default_rd_channel, - output [18-1 : 0] default_src_channel - ); - - assign default_destination_id = - DEFAULT_DESTID[85 - 81 : 0]; - - generate begin : default_decode - if (DEFAULT_CHANNEL == -1) begin - assign default_src_channel = '0; - end - else begin - assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; - end - end - endgenerate - - generate begin : default_decode_rw - if (DEFAULT_RD_CHANNEL == -1) begin - assign default_wr_channel = '0; - assign default_rd_channel = '0; - end - else begin - assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; - assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; - end - end - endgenerate - -endmodule - - -module nios_system_addr_router -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // Command Sink (Input) - // ------------------- - input sink_valid, - input [96-1 : 0] sink_data, - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Command Source (Output) - // ------------------- - output src_valid, - output reg [96-1 : 0] src_data, - output reg [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready -); - - // ------------------------------------------------------- - // Local parameters and variables - // ------------------------------------------------------- - localparam PKT_ADDR_H = 54; - localparam PKT_ADDR_L = 36; - localparam PKT_DEST_ID_H = 85; - localparam PKT_DEST_ID_L = 81; - localparam PKT_PROTECTION_H = 89; - localparam PKT_PROTECTION_L = 87; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam DECODER_TYPE = 0; - - localparam PKT_TRANS_WRITE = 57; - localparam PKT_TRANS_READ = 58; - - localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; - localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; - - - - // ------------------------------------------------------- - // Figure out the number of bits to mask off for each slave span - // during address decoding - // ------------------------------------------------------- - localparam PAD0 = log2ceil(64'h40000 - 64'h0); - localparam PAD1 = log2ceil(64'h41000 - 64'h40800); - // ------------------------------------------------------- - // Work out which address bits are significant based on the - // address range of the slaves. If the required width is too - // large or too small, we use the address field width instead. - // ------------------------------------------------------- - localparam ADDR_RANGE = 64'h41000; - localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); - localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || - (RANGE_ADDR_WIDTH == 0) ? - PKT_ADDR_H : - PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; - - localparam RG = RANGE_ADDR_WIDTH-1; - - wire [PKT_ADDR_W-1 : 0] address = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L]; - - // ------------------------------------------------------- - // Pass almost everything through, untouched - // ------------------------------------------------------- - assign sink_ready = src_ready; - assign src_valid = sink_valid; - assign src_startofpacket = sink_startofpacket; - assign src_endofpacket = sink_endofpacket; - - wire [PKT_DEST_ID_W-1:0] default_destid; - wire [18-1 : 0] default_src_channel; - - - - - - nios_system_addr_router_default_decode the_default_decode( - .default_destination_id (default_destid), - .default_wr_channel (), - .default_rd_channel (), - .default_src_channel (default_src_channel) - ); - - always @* begin - src_data = sink_data; - src_channel = default_src_channel; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid; - - // -------------------------------------------------- - // Address Decoder - // Sets the channel and destination ID based on the address - // -------------------------------------------------- - - // ( 0x0 .. 0x40000 ) - if ( {address[RG:PAD0],{PAD0{1'b0}}} == 19'h0 ) begin - src_channel = 18'b10; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 15; - end - - // ( 0x40800 .. 0x41000 ) - if ( {address[RG:PAD1],{PAD1{1'b0}}} == 19'h40800 ) begin - src_channel = 18'b01; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 14; - end - -end - - - // -------------------------------------------------- - // Ceil(log2()) function - // -------------------------------------------------- - function integer log2ceil; - input reg[65:0] val; - reg [65:0] i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - -endmodule - - diff --git a/db/ip/nios_system/submodules/nios_system_addr_router_001.sv b/db/ip/nios_system/submodules/nios_system_addr_router_001.sv deleted file mode 100644 index 7b8c2d0..0000000 --- a/db/ip/nios_system/submodules/nios_system_addr_router_001.sv +++ /dev/null @@ -1,336 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------------------- -// Merlin Router -// -// Asserts the appropriate one-hot encoded channel based on -// either (a) the address or (b) the dest id. The DECODER_TYPE -// parameter controls this behaviour. 0 means address decoder, -// 1 means dest id decoder. -// -// In the case of (a), it also sets the destination id. -// ------------------------------------------------------- - -`timescale 1 ns / 1 ns - -module nios_system_addr_router_001_default_decode - #( - parameter DEFAULT_CHANNEL = 1, - DEFAULT_WR_CHANNEL = -1, - DEFAULT_RD_CHANNEL = -1, - DEFAULT_DESTID = 15 - ) - (output [85 - 81 : 0] default_destination_id, - output [18-1 : 0] default_wr_channel, - output [18-1 : 0] default_rd_channel, - output [18-1 : 0] default_src_channel - ); - - assign default_destination_id = - DEFAULT_DESTID[85 - 81 : 0]; - - generate begin : default_decode - if (DEFAULT_CHANNEL == -1) begin - assign default_src_channel = '0; - end - else begin - assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; - end - end - endgenerate - - generate begin : default_decode_rw - if (DEFAULT_RD_CHANNEL == -1) begin - assign default_wr_channel = '0; - assign default_rd_channel = '0; - end - else begin - assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; - assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; - end - end - endgenerate - -endmodule - - -module nios_system_addr_router_001 -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // Command Sink (Input) - // ------------------- - input sink_valid, - input [96-1 : 0] sink_data, - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Command Source (Output) - // ------------------- - output src_valid, - output reg [96-1 : 0] src_data, - output reg [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready -); - - // ------------------------------------------------------- - // Local parameters and variables - // ------------------------------------------------------- - localparam PKT_ADDR_H = 54; - localparam PKT_ADDR_L = 36; - localparam PKT_DEST_ID_H = 85; - localparam PKT_DEST_ID_L = 81; - localparam PKT_PROTECTION_H = 89; - localparam PKT_PROTECTION_L = 87; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam DECODER_TYPE = 0; - - localparam PKT_TRANS_WRITE = 57; - localparam PKT_TRANS_READ = 58; - - localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; - localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; - - - - // ------------------------------------------------------- - // Figure out the number of bits to mask off for each slave span - // during address decoding - // ------------------------------------------------------- - localparam PAD0 = log2ceil(64'h40000 - 64'h0); - localparam PAD1 = log2ceil(64'h41000 - 64'h40800); - localparam PAD2 = log2ceil(64'h41020 - 64'h41010); - localparam PAD3 = log2ceil(64'h41030 - 64'h41020); - localparam PAD4 = log2ceil(64'h41040 - 64'h41030); - localparam PAD5 = log2ceil(64'h41050 - 64'h41040); - localparam PAD6 = log2ceil(64'h41060 - 64'h41050); - localparam PAD7 = log2ceil(64'h41070 - 64'h41060); - localparam PAD8 = log2ceil(64'h41080 - 64'h41070); - localparam PAD9 = log2ceil(64'h41090 - 64'h41080); - localparam PAD10 = log2ceil(64'h410a0 - 64'h41090); - localparam PAD11 = log2ceil(64'h410b0 - 64'h410a0); - localparam PAD12 = log2ceil(64'h410c0 - 64'h410b0); - localparam PAD13 = log2ceil(64'h410d0 - 64'h410c0); - localparam PAD14 = log2ceil(64'h410e0 - 64'h410d0); - localparam PAD15 = log2ceil(64'h410f0 - 64'h410e0); - localparam PAD16 = log2ceil(64'h41100 - 64'h410f0); - localparam PAD17 = log2ceil(64'h41108 - 64'h41100); - // ------------------------------------------------------- - // Work out which address bits are significant based on the - // address range of the slaves. If the required width is too - // large or too small, we use the address field width instead. - // ------------------------------------------------------- - localparam ADDR_RANGE = 64'h41108; - localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); - localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || - (RANGE_ADDR_WIDTH == 0) ? - PKT_ADDR_H : - PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; - - localparam RG = RANGE_ADDR_WIDTH-1; - - wire [PKT_ADDR_W-1 : 0] address = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L]; - - // ------------------------------------------------------- - // Pass almost everything through, untouched - // ------------------------------------------------------- - assign sink_ready = src_ready; - assign src_valid = sink_valid; - assign src_startofpacket = sink_startofpacket; - assign src_endofpacket = sink_endofpacket; - - wire [PKT_DEST_ID_W-1:0] default_destid; - wire [18-1 : 0] default_src_channel; - - - - - - nios_system_addr_router_001_default_decode the_default_decode( - .default_destination_id (default_destid), - .default_wr_channel (), - .default_rd_channel (), - .default_src_channel (default_src_channel) - ); - - always @* begin - src_data = sink_data; - src_channel = default_src_channel; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid; - - // -------------------------------------------------- - // Address Decoder - // Sets the channel and destination ID based on the address - // -------------------------------------------------- - - // ( 0x0 .. 0x40000 ) - if ( {address[RG:PAD0],{PAD0{1'b0}}} == 19'h0 ) begin - src_channel = 18'b000000000000000010; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 15; - end - - // ( 0x40800 .. 0x41000 ) - if ( {address[RG:PAD1],{PAD1{1'b0}}} == 19'h40800 ) begin - src_channel = 18'b000000000000000001; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 14; - end - - // ( 0x41010 .. 0x41020 ) - if ( {address[RG:PAD2],{PAD2{1'b0}}} == 19'h41010 ) begin - src_channel = 18'b010000000000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 13; - end - - // ( 0x41020 .. 0x41030 ) - if ( {address[RG:PAD3],{PAD3{1'b0}}} == 19'h41020 ) begin - src_channel = 18'b100000000000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 12; - end - - // ( 0x41030 .. 0x41040 ) - if ( {address[RG:PAD4],{PAD4{1'b0}}} == 19'h41030 ) begin - src_channel = 18'b001000000000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 11; - end - - // ( 0x41040 .. 0x41050 ) - if ( {address[RG:PAD5],{PAD5{1'b0}}} == 19'h41040 ) begin - src_channel = 18'b000100000000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 9; - end - - // ( 0x41050 .. 0x41060 ) - if ( {address[RG:PAD6],{PAD6{1'b0}}} == 19'h41050 ) begin - src_channel = 18'b000010000000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8; - end - - // ( 0x41060 .. 0x41070 ) - if ( {address[RG:PAD7],{PAD7{1'b0}}} == 19'h41060 ) begin - src_channel = 18'b000001000000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7; - end - - // ( 0x41070 .. 0x41080 ) - if ( {address[RG:PAD8],{PAD8{1'b0}}} == 19'h41070 ) begin - src_channel = 18'b000000100000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6; - end - - // ( 0x41080 .. 0x41090 ) - if ( {address[RG:PAD9],{PAD9{1'b0}}} == 19'h41080 ) begin - src_channel = 18'b000000010000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5; - end - - // ( 0x41090 .. 0x410a0 ) - if ( {address[RG:PAD10],{PAD10{1'b0}}} == 19'h41090 ) begin - src_channel = 18'b000000001000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4; - end - - // ( 0x410a0 .. 0x410b0 ) - if ( {address[RG:PAD11],{PAD11{1'b0}}} == 19'h410a0 ) begin - src_channel = 18'b000000000100000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3; - end - - // ( 0x410b0 .. 0x410c0 ) - if ( {address[RG:PAD12],{PAD12{1'b0}}} == 19'h410b0 ) begin - src_channel = 18'b000000000010000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2; - end - - // ( 0x410c0 .. 0x410d0 ) - if ( {address[RG:PAD13],{PAD13{1'b0}}} == 19'h410c0 ) begin - src_channel = 18'b000000000001000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 16; - end - - // ( 0x410d0 .. 0x410e0 ) - if ( {address[RG:PAD14],{PAD14{1'b0}}} == 19'h410d0 ) begin - src_channel = 18'b000000000000100000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 17; - end - - // ( 0x410e0 .. 0x410f0 ) - if ( {address[RG:PAD15],{PAD15{1'b0}}} == 19'h410e0 ) begin - src_channel = 18'b000000000000010000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0; - end - - // ( 0x410f0 .. 0x41100 ) - if ( {address[RG:PAD16],{PAD16{1'b0}}} == 19'h410f0 ) begin - src_channel = 18'b000000000000000100; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1; - end - - // ( 0x41100 .. 0x41108 ) - if ( {address[RG:PAD17],{PAD17{1'b0}}} == 19'h41100 ) begin - src_channel = 18'b000000000000001000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 10; - end - -end - - - // -------------------------------------------------- - // Ceil(log2()) function - // -------------------------------------------------- - function integer log2ceil; - input reg[65:0] val; - reg [65:0] i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - -endmodule - - diff --git a/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv b/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv deleted file mode 100644 index 0aef300..0000000 --- a/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv +++ /dev/null @@ -1,116 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------- -// Merlin Demultiplexer -// -// Asserts valid on the appropriate output -// given a one-hot channel signal. -// ------------------------------------- - -`timescale 1 ns / 1 ns - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_cmd_xbar_demux -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// NUM_OUTPUTS: 2 -// VALID_WIDTH: 1 -// ------------------------------------------ - -//------------------------------------------ -// Message Supression Used -// QIS Warnings -// 15610 - Warning: Design contains x input pin(s) that do not drive logic -//------------------------------------------ - -module nios_system_cmd_xbar_demux -( - // ------------------- - // Sink - // ------------------- - input [1-1 : 0] sink_valid, - input [96-1 : 0] sink_data, // ST_DATA_W=96 - input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Sources - // ------------------- - output reg src0_valid, - output reg [96-1 : 0] src0_data, // ST_DATA_W=96 - output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 - output reg src0_startofpacket, - output reg src0_endofpacket, - input src0_ready, - - output reg src1_valid, - output reg [96-1 : 0] src1_data, // ST_DATA_W=96 - output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18 - output reg src1_startofpacket, - output reg src1_endofpacket, - input src1_ready, - - - // ------------------- - // Clock & Reset - // ------------------- - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk - input clk, - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset - input reset - -); - - localparam NUM_OUTPUTS = 2; - wire [NUM_OUTPUTS - 1 : 0] ready_vector; - - // ------------------- - // Demux - // ------------------- - always @* begin - src0_data = sink_data; - src0_startofpacket = sink_startofpacket; - src0_endofpacket = sink_endofpacket; - src0_channel = sink_channel >> NUM_OUTPUTS; - - src0_valid = sink_channel[0] && sink_valid; - - src1_data = sink_data; - src1_startofpacket = sink_startofpacket; - src1_endofpacket = sink_endofpacket; - src1_channel = sink_channel >> NUM_OUTPUTS; - - src1_valid = sink_channel[1] && sink_valid; - - end - - // ------------------- - // Backpressure - // ------------------- - assign ready_vector[0] = src0_ready; - assign ready_vector[1] = src1_ready; - - assign sink_ready = |(sink_channel & {{16{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); - -endmodule - - diff --git a/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv b/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv deleted file mode 100644 index 433e8d0..0000000 --- a/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv +++ /dev/null @@ -1,356 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------- -// Merlin Demultiplexer -// -// Asserts valid on the appropriate output -// given a one-hot channel signal. -// ------------------------------------- - -`timescale 1 ns / 1 ns - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_cmd_xbar_demux_001 -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// NUM_OUTPUTS: 18 -// VALID_WIDTH: 1 -// ------------------------------------------ - -//------------------------------------------ -// Message Supression Used -// QIS Warnings -// 15610 - Warning: Design contains x input pin(s) that do not drive logic -//------------------------------------------ - -module nios_system_cmd_xbar_demux_001 -( - // ------------------- - // Sink - // ------------------- - input [1-1 : 0] sink_valid, - input [96-1 : 0] sink_data, // ST_DATA_W=96 - input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Sources - // ------------------- - output reg src0_valid, - output reg [96-1 : 0] src0_data, // ST_DATA_W=96 - output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 - output reg src0_startofpacket, - output reg src0_endofpacket, - input src0_ready, - - output reg src1_valid, - output reg [96-1 : 0] src1_data, // ST_DATA_W=96 - output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18 - output reg src1_startofpacket, - output reg src1_endofpacket, - input src1_ready, - - output reg src2_valid, - output reg [96-1 : 0] src2_data, // ST_DATA_W=96 - output reg [18-1 : 0] src2_channel, // ST_CHANNEL_W=18 - output reg src2_startofpacket, - output reg src2_endofpacket, - input src2_ready, - - output reg src3_valid, - output reg [96-1 : 0] src3_data, // ST_DATA_W=96 - output reg [18-1 : 0] src3_channel, // ST_CHANNEL_W=18 - output reg src3_startofpacket, - output reg src3_endofpacket, - input src3_ready, - - output reg src4_valid, - output reg [96-1 : 0] src4_data, // ST_DATA_W=96 - output reg [18-1 : 0] src4_channel, // ST_CHANNEL_W=18 - output reg src4_startofpacket, - output reg src4_endofpacket, - input src4_ready, - - output reg src5_valid, - output reg [96-1 : 0] src5_data, // ST_DATA_W=96 - output reg [18-1 : 0] src5_channel, // ST_CHANNEL_W=18 - output reg src5_startofpacket, - output reg src5_endofpacket, - input src5_ready, - - output reg src6_valid, - output reg [96-1 : 0] src6_data, // ST_DATA_W=96 - output reg [18-1 : 0] src6_channel, // ST_CHANNEL_W=18 - output reg src6_startofpacket, - output reg src6_endofpacket, - input src6_ready, - - output reg src7_valid, - output reg [96-1 : 0] src7_data, // ST_DATA_W=96 - output reg [18-1 : 0] src7_channel, // ST_CHANNEL_W=18 - output reg src7_startofpacket, - output reg src7_endofpacket, - input src7_ready, - - output reg src8_valid, - output reg [96-1 : 0] src8_data, // ST_DATA_W=96 - output reg [18-1 : 0] src8_channel, // ST_CHANNEL_W=18 - output reg src8_startofpacket, - output reg src8_endofpacket, - input src8_ready, - - output reg src9_valid, - output reg [96-1 : 0] src9_data, // ST_DATA_W=96 - output reg [18-1 : 0] src9_channel, // ST_CHANNEL_W=18 - output reg src9_startofpacket, - output reg src9_endofpacket, - input src9_ready, - - output reg src10_valid, - output reg [96-1 : 0] src10_data, // ST_DATA_W=96 - output reg [18-1 : 0] src10_channel, // ST_CHANNEL_W=18 - output reg src10_startofpacket, - output reg src10_endofpacket, - input src10_ready, - - output reg src11_valid, - output reg [96-1 : 0] src11_data, // ST_DATA_W=96 - output reg [18-1 : 0] src11_channel, // ST_CHANNEL_W=18 - output reg src11_startofpacket, - output reg src11_endofpacket, - input src11_ready, - - output reg src12_valid, - output reg [96-1 : 0] src12_data, // ST_DATA_W=96 - output reg [18-1 : 0] src12_channel, // ST_CHANNEL_W=18 - output reg src12_startofpacket, - output reg src12_endofpacket, - input src12_ready, - - output reg src13_valid, - output reg [96-1 : 0] src13_data, // ST_DATA_W=96 - output reg [18-1 : 0] src13_channel, // ST_CHANNEL_W=18 - output reg src13_startofpacket, - output reg src13_endofpacket, - input src13_ready, - - output reg src14_valid, - output reg [96-1 : 0] src14_data, // ST_DATA_W=96 - output reg [18-1 : 0] src14_channel, // ST_CHANNEL_W=18 - output reg src14_startofpacket, - output reg src14_endofpacket, - input src14_ready, - - output reg src15_valid, - output reg [96-1 : 0] src15_data, // ST_DATA_W=96 - output reg [18-1 : 0] src15_channel, // ST_CHANNEL_W=18 - output reg src15_startofpacket, - output reg src15_endofpacket, - input src15_ready, - - output reg src16_valid, - output reg [96-1 : 0] src16_data, // ST_DATA_W=96 - output reg [18-1 : 0] src16_channel, // ST_CHANNEL_W=18 - output reg src16_startofpacket, - output reg src16_endofpacket, - input src16_ready, - - output reg src17_valid, - output reg [96-1 : 0] src17_data, // ST_DATA_W=96 - output reg [18-1 : 0] src17_channel, // ST_CHANNEL_W=18 - output reg src17_startofpacket, - output reg src17_endofpacket, - input src17_ready, - - - // ------------------- - // Clock & Reset - // ------------------- - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk - input clk, - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset - input reset - -); - - localparam NUM_OUTPUTS = 18; - wire [NUM_OUTPUTS - 1 : 0] ready_vector; - - // ------------------- - // Demux - // ------------------- - always @* begin - src0_data = sink_data; - src0_startofpacket = sink_startofpacket; - src0_endofpacket = sink_endofpacket; - src0_channel = sink_channel >> NUM_OUTPUTS; - - src0_valid = sink_channel[0] && sink_valid; - - src1_data = sink_data; - src1_startofpacket = sink_startofpacket; - src1_endofpacket = sink_endofpacket; - src1_channel = sink_channel >> NUM_OUTPUTS; - - src1_valid = sink_channel[1] && sink_valid; - - src2_data = sink_data; - src2_startofpacket = sink_startofpacket; - src2_endofpacket = sink_endofpacket; - src2_channel = sink_channel >> NUM_OUTPUTS; - - src2_valid = sink_channel[2] && sink_valid; - - src3_data = sink_data; - src3_startofpacket = sink_startofpacket; - src3_endofpacket = sink_endofpacket; - src3_channel = sink_channel >> NUM_OUTPUTS; - - src3_valid = sink_channel[3] && sink_valid; - - src4_data = sink_data; - src4_startofpacket = sink_startofpacket; - src4_endofpacket = sink_endofpacket; - src4_channel = sink_channel >> NUM_OUTPUTS; - - src4_valid = sink_channel[4] && sink_valid; - - src5_data = sink_data; - src5_startofpacket = sink_startofpacket; - src5_endofpacket = sink_endofpacket; - src5_channel = sink_channel >> NUM_OUTPUTS; - - src5_valid = sink_channel[5] && sink_valid; - - src6_data = sink_data; - src6_startofpacket = sink_startofpacket; - src6_endofpacket = sink_endofpacket; - src6_channel = sink_channel >> NUM_OUTPUTS; - - src6_valid = sink_channel[6] && sink_valid; - - src7_data = sink_data; - src7_startofpacket = sink_startofpacket; - src7_endofpacket = sink_endofpacket; - src7_channel = sink_channel >> NUM_OUTPUTS; - - src7_valid = sink_channel[7] && sink_valid; - - src8_data = sink_data; - src8_startofpacket = sink_startofpacket; - src8_endofpacket = sink_endofpacket; - src8_channel = sink_channel >> NUM_OUTPUTS; - - src8_valid = sink_channel[8] && sink_valid; - - src9_data = sink_data; - src9_startofpacket = sink_startofpacket; - src9_endofpacket = sink_endofpacket; - src9_channel = sink_channel >> NUM_OUTPUTS; - - src9_valid = sink_channel[9] && sink_valid; - - src10_data = sink_data; - src10_startofpacket = sink_startofpacket; - src10_endofpacket = sink_endofpacket; - src10_channel = sink_channel >> NUM_OUTPUTS; - - src10_valid = sink_channel[10] && sink_valid; - - src11_data = sink_data; - src11_startofpacket = sink_startofpacket; - src11_endofpacket = sink_endofpacket; - src11_channel = sink_channel >> NUM_OUTPUTS; - - src11_valid = sink_channel[11] && sink_valid; - - src12_data = sink_data; - src12_startofpacket = sink_startofpacket; - src12_endofpacket = sink_endofpacket; - src12_channel = sink_channel >> NUM_OUTPUTS; - - src12_valid = sink_channel[12] && sink_valid; - - src13_data = sink_data; - src13_startofpacket = sink_startofpacket; - src13_endofpacket = sink_endofpacket; - src13_channel = sink_channel >> NUM_OUTPUTS; - - src13_valid = sink_channel[13] && sink_valid; - - src14_data = sink_data; - src14_startofpacket = sink_startofpacket; - src14_endofpacket = sink_endofpacket; - src14_channel = sink_channel >> NUM_OUTPUTS; - - src14_valid = sink_channel[14] && sink_valid; - - src15_data = sink_data; - src15_startofpacket = sink_startofpacket; - src15_endofpacket = sink_endofpacket; - src15_channel = sink_channel >> NUM_OUTPUTS; - - src15_valid = sink_channel[15] && sink_valid; - - src16_data = sink_data; - src16_startofpacket = sink_startofpacket; - src16_endofpacket = sink_endofpacket; - src16_channel = sink_channel >> NUM_OUTPUTS; - - src16_valid = sink_channel[16] && sink_valid; - - src17_data = sink_data; - src17_startofpacket = sink_startofpacket; - src17_endofpacket = sink_endofpacket; - src17_channel = sink_channel >> NUM_OUTPUTS; - - src17_valid = sink_channel[17] && sink_valid; - - end - - // ------------------- - // Backpressure - // ------------------- - assign ready_vector[0] = src0_ready; - assign ready_vector[1] = src1_ready; - assign ready_vector[2] = src2_ready; - assign ready_vector[3] = src3_ready; - assign ready_vector[4] = src4_ready; - assign ready_vector[5] = src5_ready; - assign ready_vector[6] = src6_ready; - assign ready_vector[7] = src7_ready; - assign ready_vector[8] = src8_ready; - assign ready_vector[9] = src9_ready; - assign ready_vector[10] = src10_ready; - assign ready_vector[11] = src11_ready; - assign ready_vector[12] = src12_ready; - assign ready_vector[13] = src13_ready; - assign ready_vector[14] = src14_ready; - assign ready_vector[15] = src15_ready; - assign ready_vector[16] = src16_ready; - assign ready_vector[17] = src17_ready; - - assign sink_ready = |(sink_channel & ready_vector); - -endmodule - - diff --git a/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv b/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv deleted file mode 100644 index 76ec5b4..0000000 --- a/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv +++ /dev/null @@ -1,308 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------ -// Merlin Multiplexer -// ------------------------------------------ - -`timescale 1 ns / 1 ns - - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_cmd_xbar_mux -// NUM_INPUTS: 2 -// ARBITRATION_SHARES: 1 1 -// ARBITRATION_SCHEME "round-robin" -// PIPELINE_ARB: 1 -// PKT_TRANS_LOCK: 59 (arbitration locking enabled) -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// ------------------------------------------ - -module nios_system_cmd_xbar_mux -( - // ---------------------- - // Sinks - // ---------------------- - input sink0_valid, - input [96-1 : 0] sink0_data, - input [18-1: 0] sink0_channel, - input sink0_startofpacket, - input sink0_endofpacket, - output sink0_ready, - - input sink1_valid, - input [96-1 : 0] sink1_data, - input [18-1: 0] sink1_channel, - input sink1_startofpacket, - input sink1_endofpacket, - output sink1_ready, - - - // ---------------------- - // Source - // ---------------------- - output src_valid, - output [96-1 : 0] src_data, - output [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready, - - // ---------------------- - // Clock & Reset - // ---------------------- - input clk, - input reset -); - localparam PAYLOAD_W = 96 + 18 + 2; - localparam NUM_INPUTS = 2; - localparam SHARE_COUNTER_W = 1; - localparam PIPELINE_ARB = 1; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam PKT_TRANS_LOCK = 59; - - // ------------------------------------------ - // Signals - // ------------------------------------------ - wire [NUM_INPUTS - 1 : 0] request; - wire [NUM_INPUTS - 1 : 0] valid; - wire [NUM_INPUTS - 1 : 0] grant; - wire [NUM_INPUTS - 1 : 0] next_grant; - reg [NUM_INPUTS - 1 : 0] saved_grant; - reg [PAYLOAD_W - 1 : 0] src_payload; - wire last_cycle; - reg packet_in_progress; - reg update_grant; - - wire [PAYLOAD_W - 1 : 0] sink0_payload; - wire [PAYLOAD_W - 1 : 0] sink1_payload; - - assign valid[0] = sink0_valid; - assign valid[1] = sink1_valid; - - wire [NUM_INPUTS - 1 : 0] eop; - assign eop[0] = sink0_endofpacket; - assign eop[1] = sink1_endofpacket; - - // ------------------------------------------ - // ------------------------------------------ - // Grant Logic & Updates - // ------------------------------------------ - // ------------------------------------------ - reg [NUM_INPUTS - 1 : 0] lock; - always @* begin - lock[0] = sink0_data[59]; - lock[1] = sink1_data[59]; - end - reg [NUM_INPUTS - 1 : 0] locked = '0; - always @(posedge clk or posedge reset) begin - if (reset) begin - locked <= '0; - end - else begin - locked <= next_grant & lock; - end - end - - assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); - - // ------------------------------------------ - // We're working on a packet at any time valid is high, except - // when this is the endofpacket. - // ------------------------------------------ - always @(posedge clk or posedge reset) begin - if (reset) begin - packet_in_progress <= 1'b0; - end - else begin - if (src_valid) - packet_in_progress <= 1'b1; - if (last_cycle) - packet_in_progress <= 1'b0; - end - end - - - // ------------------------------------------ - // Shares - // - // Special case: all-equal shares _should_ be optimized into assigning a - // constant to next_grant_share. - // Special case: all-1's shares _should_ result in the share counter - // being optimized away. - // ------------------------------------------ - // Input | arb shares | counter load value - // 0 | 1 | 0 - // 1 | 1 | 0 - wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; - - // ------------------------------------------ - // Choose the share value corresponding to the grant. - // ------------------------------------------ - reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; - always @* begin - next_grant_share = - share_0 & { SHARE_COUNTER_W {next_grant[0]} } | - share_1 & { SHARE_COUNTER_W {next_grant[1]} }; - end - - // ------------------------------------------ - // Flag to indicate first packet of an arb sequence. - // ------------------------------------------ - - // ------------------------------------------ - // Compute the next share-count value. - // ------------------------------------------ - reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; - reg [SHARE_COUNTER_W - 1 : 0] share_count; - reg share_count_zero_flag; - - always @* begin - // Update the counter, but don't decrement below 0. - p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; - end - - // ------------------------------------------ - // Update the share counter and share-counter=zero flag. - // ------------------------------------------ - always @(posedge clk or posedge reset) begin - if (reset) begin - share_count <= '0; - share_count_zero_flag <= 1'b1; - end - else begin - if (update_grant) begin - share_count <= next_grant_share; - share_count_zero_flag <= (next_grant_share == '0); - end - else if (last_cycle) begin - share_count <= p1_share_count; - share_count_zero_flag <= (p1_share_count == '0); - end - end - end - - - always @* begin - update_grant = 0; - - // ------------------------------------------ - // The pipeline delays grant by one cycle, so - // we have to calculate the update_grant signal - // one cycle ahead of time. - // - // Possible optimization: omit the first clause - // "if (!packet_in_progress & ~src_valid) ..." - // cost: one idle cycle at the the beginning of each - // grant cycle. - // benefit: save a small amount of logic. - // ------------------------------------------ - if (!packet_in_progress & !src_valid) - update_grant = 1; - if (last_cycle && share_count_zero_flag) - update_grant = 1; - end - - wire save_grant; - assign save_grant = update_grant; - assign grant = saved_grant; - - always @(posedge clk, posedge reset) begin - if (reset) - saved_grant <= '0; - else if (save_grant) - saved_grant <= next_grant; - end - - // ------------------------------------------ - // ------------------------------------------ - // Arbitrator - // ------------------------------------------ - // ------------------------------------------ - - // ------------------------------------------ - // Create a request vector that stays high during - // the packet for unpipelined arbitration. - // - // The pipelined arbitration scheme does not require - // request to be held high during the packet. - // ------------------------------------------ - reg [NUM_INPUTS - 1 : 0] prev_request; - always @(posedge clk, posedge reset) begin - if (reset) - prev_request <= '0; - else - prev_request <= request & ~(valid & eop); - end - - assign request = (PIPELINE_ARB == 1) ? valid | locked : - prev_request | valid | locked; - - - altera_merlin_arbitrator - #( - .NUM_REQUESTERS(NUM_INPUTS), - .SCHEME ("round-robin"), - .PIPELINE (1) - ) arb ( - .clk (clk), - .reset (reset), - .request (request), - .grant (next_grant), - .save_top_priority (src_valid), - .increment_top_priority (update_grant) - ); - - // ------------------------------------------ - // ------------------------------------------ - // Mux - // - // Implemented as a sum of products. - // ------------------------------------------ - // ------------------------------------------ - - assign sink0_ready = src_ready && grant[0]; - assign sink1_ready = src_ready && grant[1]; - - assign src_valid = |(grant & valid); - - always @* begin - src_payload = - sink0_payload & {PAYLOAD_W {grant[0]} } | - sink1_payload & {PAYLOAD_W {grant[1]} }; - end - - // ------------------------------------------ - // Mux Payload Mapping - // ------------------------------------------ - - assign sink0_payload = {sink0_channel,sink0_data, - sink0_startofpacket,sink0_endofpacket}; - assign sink1_payload = {sink1_channel,sink1_data, - sink1_startofpacket,sink1_endofpacket}; - - assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; - -endmodule - - - diff --git a/db/ip/nios_system/submodules/nios_system_hex0.v b/db/ip/nios_system/submodules/nios_system_hex0.v deleted file mode 100644 index 365eed9..0000000 --- a/db/ip/nios_system/submodules/nios_system_hex0.v +++ /dev/null @@ -1,66 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_hex0 ( - // inputs: - address, - chipselect, - clk, - reset_n, - write_n, - writedata, - - // outputs: - out_port, - readdata - ) -; - - output [ 6: 0] out_port; - output [ 31: 0] readdata; - input [ 1: 0] address; - input chipselect; - input clk; - input reset_n; - input write_n; - input [ 31: 0] writedata; - - wire clk_en; - reg [ 6: 0] data_out; - wire [ 6: 0] out_port; - wire [ 6: 0] read_mux_out; - wire [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {7 {(address == 0)}} & data_out; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - data_out <= 0; - else if (chipselect && ~write_n && (address == 0)) - data_out <= writedata[6 : 0]; - end - - - assign readdata = {32'b0 | read_mux_out}; - assign out_port = data_out; - -endmodule - diff --git a/db/ip/nios_system/submodules/nios_system_id_router.sv b/db/ip/nios_system/submodules/nios_system_id_router.sv deleted file mode 100644 index 90937e8..0000000 --- a/db/ip/nios_system/submodules/nios_system_id_router.sv +++ /dev/null @@ -1,221 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------------------- -// Merlin Router -// -// Asserts the appropriate one-hot encoded channel based on -// either (a) the address or (b) the dest id. The DECODER_TYPE -// parameter controls this behaviour. 0 means address decoder, -// 1 means dest id decoder. -// -// In the case of (a), it also sets the destination id. -// ------------------------------------------------------- - -`timescale 1 ns / 1 ns - -module nios_system_id_router_default_decode - #( - parameter DEFAULT_CHANNEL = 0, - DEFAULT_WR_CHANNEL = -1, - DEFAULT_RD_CHANNEL = -1, - DEFAULT_DESTID = 1 - ) - (output [85 - 81 : 0] default_destination_id, - output [18-1 : 0] default_wr_channel, - output [18-1 : 0] default_rd_channel, - output [18-1 : 0] default_src_channel - ); - - assign default_destination_id = - DEFAULT_DESTID[85 - 81 : 0]; - - generate begin : default_decode - if (DEFAULT_CHANNEL == -1) begin - assign default_src_channel = '0; - end - else begin - assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; - end - end - endgenerate - - generate begin : default_decode_rw - if (DEFAULT_RD_CHANNEL == -1) begin - assign default_wr_channel = '0; - assign default_rd_channel = '0; - end - else begin - assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; - assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; - end - end - endgenerate - -endmodule - - -module nios_system_id_router -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // Command Sink (Input) - // ------------------- - input sink_valid, - input [96-1 : 0] sink_data, - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Command Source (Output) - // ------------------- - output src_valid, - output reg [96-1 : 0] src_data, - output reg [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready -); - - // ------------------------------------------------------- - // Local parameters and variables - // ------------------------------------------------------- - localparam PKT_ADDR_H = 54; - localparam PKT_ADDR_L = 36; - localparam PKT_DEST_ID_H = 85; - localparam PKT_DEST_ID_L = 81; - localparam PKT_PROTECTION_H = 89; - localparam PKT_PROTECTION_L = 87; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam DECODER_TYPE = 1; - - localparam PKT_TRANS_WRITE = 57; - localparam PKT_TRANS_READ = 58; - - localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; - localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; - - - - // ------------------------------------------------------- - // Figure out the number of bits to mask off for each slave span - // during address decoding - // ------------------------------------------------------- - // ------------------------------------------------------- - // Work out which address bits are significant based on the - // address range of the slaves. If the required width is too - // large or too small, we use the address field width instead. - // ------------------------------------------------------- - localparam ADDR_RANGE = 64'h0; - localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); - localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || - (RANGE_ADDR_WIDTH == 0) ? - PKT_ADDR_H : - PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; - - localparam RG = RANGE_ADDR_WIDTH; - - reg [PKT_DEST_ID_W-1 : 0] destid; - - // ------------------------------------------------------- - // Pass almost everything through, untouched - // ------------------------------------------------------- - assign sink_ready = src_ready; - assign src_valid = sink_valid; - assign src_startofpacket = sink_startofpacket; - assign src_endofpacket = sink_endofpacket; - - wire [PKT_DEST_ID_W-1:0] default_destid; - wire [18-1 : 0] default_src_channel; - - - - - - nios_system_id_router_default_decode the_default_decode( - .default_destination_id (default_destid), - .default_wr_channel (), - .default_rd_channel (), - .default_src_channel (default_src_channel) - ); - - always @* begin - src_data = sink_data; - src_channel = default_src_channel; - - // -------------------------------------------------- - // DestinationID Decoder - // Sets the channel based on the destination ID. - // -------------------------------------------------- - destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; - - - - if (destid == 1 ) begin - src_channel = 18'b01; - end - - if (destid == 0 ) begin - src_channel = 18'b10; - end - - -end - - - // -------------------------------------------------- - // Ceil(log2()) function - // -------------------------------------------------- - function integer log2ceil; - input reg[65:0] val; - reg [65:0] i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - -endmodule - - diff --git a/db/ip/nios_system/submodules/nios_system_id_router_002.sv b/db/ip/nios_system/submodules/nios_system_id_router_002.sv deleted file mode 100644 index a80e831..0000000 --- a/db/ip/nios_system/submodules/nios_system_id_router_002.sv +++ /dev/null @@ -1,217 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------------------- -// Merlin Router -// -// Asserts the appropriate one-hot encoded channel based on -// either (a) the address or (b) the dest id. The DECODER_TYPE -// parameter controls this behaviour. 0 means address decoder, -// 1 means dest id decoder. -// -// In the case of (a), it also sets the destination id. -// ------------------------------------------------------- - -`timescale 1 ns / 1 ns - -module nios_system_id_router_002_default_decode - #( - parameter DEFAULT_CHANNEL = 0, - DEFAULT_WR_CHANNEL = -1, - DEFAULT_RD_CHANNEL = -1, - DEFAULT_DESTID = 0 - ) - (output [85 - 81 : 0] default_destination_id, - output [18-1 : 0] default_wr_channel, - output [18-1 : 0] default_rd_channel, - output [18-1 : 0] default_src_channel - ); - - assign default_destination_id = - DEFAULT_DESTID[85 - 81 : 0]; - - generate begin : default_decode - if (DEFAULT_CHANNEL == -1) begin - assign default_src_channel = '0; - end - else begin - assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; - end - end - endgenerate - - generate begin : default_decode_rw - if (DEFAULT_RD_CHANNEL == -1) begin - assign default_wr_channel = '0; - assign default_rd_channel = '0; - end - else begin - assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; - assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; - end - end - endgenerate - -endmodule - - -module nios_system_id_router_002 -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // Command Sink (Input) - // ------------------- - input sink_valid, - input [96-1 : 0] sink_data, - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Command Source (Output) - // ------------------- - output src_valid, - output reg [96-1 : 0] src_data, - output reg [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready -); - - // ------------------------------------------------------- - // Local parameters and variables - // ------------------------------------------------------- - localparam PKT_ADDR_H = 54; - localparam PKT_ADDR_L = 36; - localparam PKT_DEST_ID_H = 85; - localparam PKT_DEST_ID_L = 81; - localparam PKT_PROTECTION_H = 89; - localparam PKT_PROTECTION_L = 87; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam DECODER_TYPE = 1; - - localparam PKT_TRANS_WRITE = 57; - localparam PKT_TRANS_READ = 58; - - localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; - localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; - - - - // ------------------------------------------------------- - // Figure out the number of bits to mask off for each slave span - // during address decoding - // ------------------------------------------------------- - // ------------------------------------------------------- - // Work out which address bits are significant based on the - // address range of the slaves. If the required width is too - // large or too small, we use the address field width instead. - // ------------------------------------------------------- - localparam ADDR_RANGE = 64'h0; - localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); - localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || - (RANGE_ADDR_WIDTH == 0) ? - PKT_ADDR_H : - PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; - - localparam RG = RANGE_ADDR_WIDTH; - - reg [PKT_DEST_ID_W-1 : 0] destid; - - // ------------------------------------------------------- - // Pass almost everything through, untouched - // ------------------------------------------------------- - assign sink_ready = src_ready; - assign src_valid = sink_valid; - assign src_startofpacket = sink_startofpacket; - assign src_endofpacket = sink_endofpacket; - - wire [PKT_DEST_ID_W-1:0] default_destid; - wire [18-1 : 0] default_src_channel; - - - - - - nios_system_id_router_002_default_decode the_default_decode( - .default_destination_id (default_destid), - .default_wr_channel (), - .default_rd_channel (), - .default_src_channel (default_src_channel) - ); - - always @* begin - src_data = sink_data; - src_channel = default_src_channel; - - // -------------------------------------------------- - // DestinationID Decoder - // Sets the channel based on the destination ID. - // -------------------------------------------------- - destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; - - - - if (destid == 0 ) begin - src_channel = 18'b1; - end - - -end - - - // -------------------------------------------------- - // Ceil(log2()) function - // -------------------------------------------------- - function integer log2ceil; - input reg[65:0] val; - reg [65:0] i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - -endmodule - - diff --git a/db/ip/nios_system/submodules/nios_system_id_router_003.sv b/db/ip/nios_system/submodules/nios_system_id_router_003.sv deleted file mode 100644 index 5eb343c..0000000 --- a/db/ip/nios_system/submodules/nios_system_id_router_003.sv +++ /dev/null @@ -1,217 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------------------- -// Merlin Router -// -// Asserts the appropriate one-hot encoded channel based on -// either (a) the address or (b) the dest id. The DECODER_TYPE -// parameter controls this behaviour. 0 means address decoder, -// 1 means dest id decoder. -// -// In the case of (a), it also sets the destination id. -// ------------------------------------------------------- - -`timescale 1 ns / 1 ns - -module nios_system_id_router_003_default_decode - #( - parameter DEFAULT_CHANNEL = 0, - DEFAULT_WR_CHANNEL = -1, - DEFAULT_RD_CHANNEL = -1, - DEFAULT_DESTID = 0 - ) - (output [85 - 81 : 0] default_destination_id, - output [18-1 : 0] default_wr_channel, - output [18-1 : 0] default_rd_channel, - output [18-1 : 0] default_src_channel - ); - - assign default_destination_id = - DEFAULT_DESTID[85 - 81 : 0]; - - generate begin : default_decode - if (DEFAULT_CHANNEL == -1) begin - assign default_src_channel = '0; - end - else begin - assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; - end - end - endgenerate - - generate begin : default_decode_rw - if (DEFAULT_RD_CHANNEL == -1) begin - assign default_wr_channel = '0; - assign default_rd_channel = '0; - end - else begin - assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; - assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; - end - end - endgenerate - -endmodule - - -module nios_system_id_router_003 -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // Command Sink (Input) - // ------------------- - input sink_valid, - input [96-1 : 0] sink_data, - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Command Source (Output) - // ------------------- - output src_valid, - output reg [96-1 : 0] src_data, - output reg [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready -); - - // ------------------------------------------------------- - // Local parameters and variables - // ------------------------------------------------------- - localparam PKT_ADDR_H = 54; - localparam PKT_ADDR_L = 36; - localparam PKT_DEST_ID_H = 85; - localparam PKT_DEST_ID_L = 81; - localparam PKT_PROTECTION_H = 89; - localparam PKT_PROTECTION_L = 87; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam DECODER_TYPE = 1; - - localparam PKT_TRANS_WRITE = 57; - localparam PKT_TRANS_READ = 58; - - localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; - localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; - - - - // ------------------------------------------------------- - // Figure out the number of bits to mask off for each slave span - // during address decoding - // ------------------------------------------------------- - // ------------------------------------------------------- - // Work out which address bits are significant based on the - // address range of the slaves. If the required width is too - // large or too small, we use the address field width instead. - // ------------------------------------------------------- - localparam ADDR_RANGE = 64'h0; - localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); - localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || - (RANGE_ADDR_WIDTH == 0) ? - PKT_ADDR_H : - PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; - - localparam RG = RANGE_ADDR_WIDTH; - - reg [PKT_DEST_ID_W-1 : 0] destid; - - // ------------------------------------------------------- - // Pass almost everything through, untouched - // ------------------------------------------------------- - assign sink_ready = src_ready; - assign src_valid = sink_valid; - assign src_startofpacket = sink_startofpacket; - assign src_endofpacket = sink_endofpacket; - - wire [PKT_DEST_ID_W-1:0] default_destid; - wire [18-1 : 0] default_src_channel; - - - - - - nios_system_id_router_003_default_decode the_default_decode( - .default_destination_id (default_destid), - .default_wr_channel (), - .default_rd_channel (), - .default_src_channel (default_src_channel) - ); - - always @* begin - src_data = sink_data; - src_channel = default_src_channel; - - // -------------------------------------------------- - // DestinationID Decoder - // Sets the channel based on the destination ID. - // -------------------------------------------------- - destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; - - - - if (destid == 0 ) begin - src_channel = 18'b1; - end - - -end - - - // -------------------------------------------------- - // Ceil(log2()) function - // -------------------------------------------------- - function integer log2ceil; - input reg[65:0] val; - reg [65:0] i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - -endmodule - - diff --git a/db/ip/nios_system/submodules/nios_system_irq_mapper.sv b/db/ip/nios_system/submodules/nios_system_irq_mapper.sv deleted file mode 100644 index cc0a8bb..0000000 --- a/db/ip/nios_system/submodules/nios_system_irq_mapper.sv +++ /dev/null @@ -1,59 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------------------- -// Altera IRQ Mapper -// -// Parameters -// NUM_RCVRS : 1 -// SENDER_IRW_WIDTH : 32 -// IRQ_MAP : 0:5 -// -// ------------------------------------------------------- - -`timescale 1 ns / 1 ns - -module nios_system_irq_mapper -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // IRQ Receivers - // ------------------- - input receiver0_irq, - - // ------------------- - // Command Source (Output) - // ------------------- - output reg [31 : 0] sender_irq -); - - - always @* begin - sender_irq = 0; - - sender_irq[5] = receiver0_irq; - end - -endmodule - - diff --git a/db/ip/nios_system/submodules/nios_system_jtag_uart.v b/db/ip/nios_system/submodules/nios_system_jtag_uart.v deleted file mode 100644 index 0d02445..0000000 --- a/db/ip/nios_system/submodules/nios_system_jtag_uart.v +++ /dev/null @@ -1,583 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_jtag_uart_sim_scfifo_w ( - // inputs: - clk, - fifo_wdata, - fifo_wr, - - // outputs: - fifo_FF, - r_dat, - wfifo_empty, - wfifo_used - ) -; - - output fifo_FF; - output [ 7: 0] r_dat; - output wfifo_empty; - output [ 5: 0] wfifo_used; - input clk; - input [ 7: 0] fifo_wdata; - input fifo_wr; - - wire fifo_FF; - wire [ 7: 0] r_dat; - wire wfifo_empty; - wire [ 5: 0] wfifo_used; - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - always @(posedge clk) - begin - if (fifo_wr) - $write("%c", fifo_wdata); - end - - - assign wfifo_used = {6{1'b0}}; - assign r_dat = {8{1'b0}}; - assign fifo_FF = 1'b0; - assign wfifo_empty = 1'b1; - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_jtag_uart_scfifo_w ( - // inputs: - clk, - fifo_clear, - fifo_wdata, - fifo_wr, - rd_wfifo, - - // outputs: - fifo_FF, - r_dat, - wfifo_empty, - wfifo_used - ) -; - - output fifo_FF; - output [ 7: 0] r_dat; - output wfifo_empty; - output [ 5: 0] wfifo_used; - input clk; - input fifo_clear; - input [ 7: 0] fifo_wdata; - input fifo_wr; - input rd_wfifo; - - wire fifo_FF; - wire [ 7: 0] r_dat; - wire wfifo_empty; - wire [ 5: 0] wfifo_used; - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - nios_system_jtag_uart_sim_scfifo_w the_nios_system_jtag_uart_sim_scfifo_w - ( - .clk (clk), - .fifo_FF (fifo_FF), - .fifo_wdata (fifo_wdata), - .fifo_wr (fifo_wr), - .r_dat (r_dat), - .wfifo_empty (wfifo_empty), - .wfifo_used (wfifo_used) - ); - - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on -//synthesis read_comments_as_HDL on -// scfifo wfifo -// ( -// .aclr (fifo_clear), -// .clock (clk), -// .data (fifo_wdata), -// .empty (wfifo_empty), -// .full (fifo_FF), -// .q (r_dat), -// .rdreq (rd_wfifo), -// .usedw (wfifo_used), -// .wrreq (fifo_wr) -// ); -// -// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO", -// wfifo.lpm_numwords = 64, -// wfifo.lpm_showahead = "OFF", -// wfifo.lpm_type = "scfifo", -// wfifo.lpm_width = 8, -// wfifo.lpm_widthu = 6, -// wfifo.overflow_checking = "OFF", -// wfifo.underflow_checking = "OFF", -// wfifo.use_eab = "ON"; -// -//synthesis read_comments_as_HDL off - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_jtag_uart_sim_scfifo_r ( - // inputs: - clk, - fifo_rd, - rst_n, - - // outputs: - fifo_EF, - fifo_rdata, - rfifo_full, - rfifo_used - ) -; - - output fifo_EF; - output [ 7: 0] fifo_rdata; - output rfifo_full; - output [ 5: 0] rfifo_used; - input clk; - input fifo_rd; - input rst_n; - - reg [ 31: 0] bytes_left; - wire fifo_EF; - reg fifo_rd_d; - wire [ 7: 0] fifo_rdata; - wire new_rom; - wire [ 31: 0] num_bytes; - wire [ 6: 0] rfifo_entries; - wire rfifo_full; - wire [ 5: 0] rfifo_used; - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - // Generate rfifo_entries for simulation - always @(posedge clk or negedge rst_n) - begin - if (rst_n == 0) - begin - bytes_left <= 32'h0; - fifo_rd_d <= 1'b0; - end - else - begin - fifo_rd_d <= fifo_rd; - // decrement on read - if (fifo_rd_d) - bytes_left <= bytes_left - 1'b1; - // catch new contents - if (new_rom) - bytes_left <= num_bytes; - end - end - - - assign fifo_EF = bytes_left == 32'b0; - assign rfifo_full = bytes_left > 7'h40; - assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left; - assign rfifo_used = rfifo_entries[5 : 0]; - assign new_rom = 1'b0; - assign num_bytes = 32'b0; - assign fifo_rdata = 8'b0; - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_jtag_uart_scfifo_r ( - // inputs: - clk, - fifo_clear, - fifo_rd, - rst_n, - t_dat, - wr_rfifo, - - // outputs: - fifo_EF, - fifo_rdata, - rfifo_full, - rfifo_used - ) -; - - output fifo_EF; - output [ 7: 0] fifo_rdata; - output rfifo_full; - output [ 5: 0] rfifo_used; - input clk; - input fifo_clear; - input fifo_rd; - input rst_n; - input [ 7: 0] t_dat; - input wr_rfifo; - - wire fifo_EF; - wire [ 7: 0] fifo_rdata; - wire rfifo_full; - wire [ 5: 0] rfifo_used; - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - nios_system_jtag_uart_sim_scfifo_r the_nios_system_jtag_uart_sim_scfifo_r - ( - .clk (clk), - .fifo_EF (fifo_EF), - .fifo_rd (fifo_rd), - .fifo_rdata (fifo_rdata), - .rfifo_full (rfifo_full), - .rfifo_used (rfifo_used), - .rst_n (rst_n) - ); - - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on -//synthesis read_comments_as_HDL on -// scfifo rfifo -// ( -// .aclr (fifo_clear), -// .clock (clk), -// .data (t_dat), -// .empty (fifo_EF), -// .full (rfifo_full), -// .q (fifo_rdata), -// .rdreq (fifo_rd), -// .usedw (rfifo_used), -// .wrreq (wr_rfifo) -// ); -// -// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO", -// rfifo.lpm_numwords = 64, -// rfifo.lpm_showahead = "OFF", -// rfifo.lpm_type = "scfifo", -// rfifo.lpm_width = 8, -// rfifo.lpm_widthu = 6, -// rfifo.overflow_checking = "OFF", -// rfifo.underflow_checking = "OFF", -// rfifo.use_eab = "ON"; -// -//synthesis read_comments_as_HDL off - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_jtag_uart ( - // inputs: - av_address, - av_chipselect, - av_read_n, - av_write_n, - av_writedata, - clk, - rst_n, - - // outputs: - av_irq, - av_readdata, - av_waitrequest, - dataavailable, - readyfordata - ) - /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ; - - output av_irq; - output [ 31: 0] av_readdata; - output av_waitrequest; - output dataavailable; - output readyfordata; - input av_address; - input av_chipselect; - input av_read_n; - input av_write_n; - input [ 31: 0] av_writedata; - input clk; - input rst_n; - - reg ac; - wire activity; - wire av_irq; - wire [ 31: 0] av_readdata; - reg av_waitrequest; - reg dataavailable; - reg fifo_AE; - reg fifo_AF; - wire fifo_EF; - wire fifo_FF; - wire fifo_clear; - wire fifo_rd; - wire [ 7: 0] fifo_rdata; - wire [ 7: 0] fifo_wdata; - reg fifo_wr; - reg ien_AE; - reg ien_AF; - wire ipen_AE; - wire ipen_AF; - reg pause_irq; - wire [ 7: 0] r_dat; - wire r_ena; - reg r_val; - wire rd_wfifo; - reg read_0; - reg readyfordata; - wire rfifo_full; - wire [ 5: 0] rfifo_used; - reg rvalid; - reg sim_r_ena; - reg sim_t_dat; - reg sim_t_ena; - reg sim_t_pause; - wire [ 7: 0] t_dat; - reg t_dav; - wire t_ena; - wire t_pause; - wire wfifo_empty; - wire [ 5: 0] wfifo_used; - reg woverflow; - wire wr_rfifo; - //avalon_jtag_slave, which is an e_avalon_slave - assign rd_wfifo = r_ena & ~wfifo_empty; - assign wr_rfifo = t_ena & ~rfifo_full; - assign fifo_clear = ~rst_n; - nios_system_jtag_uart_scfifo_w the_nios_system_jtag_uart_scfifo_w - ( - .clk (clk), - .fifo_FF (fifo_FF), - .fifo_clear (fifo_clear), - .fifo_wdata (fifo_wdata), - .fifo_wr (fifo_wr), - .r_dat (r_dat), - .rd_wfifo (rd_wfifo), - .wfifo_empty (wfifo_empty), - .wfifo_used (wfifo_used) - ); - - nios_system_jtag_uart_scfifo_r the_nios_system_jtag_uart_scfifo_r - ( - .clk (clk), - .fifo_EF (fifo_EF), - .fifo_clear (fifo_clear), - .fifo_rd (fifo_rd), - .fifo_rdata (fifo_rdata), - .rfifo_full (rfifo_full), - .rfifo_used (rfifo_used), - .rst_n (rst_n), - .t_dat (t_dat), - .wr_rfifo (wr_rfifo) - ); - - assign ipen_AE = ien_AE & fifo_AE; - assign ipen_AF = ien_AF & (pause_irq | fifo_AF); - assign av_irq = ipen_AE | ipen_AF; - assign activity = t_pause | t_ena; - always @(posedge clk or negedge rst_n) - begin - if (rst_n == 0) - pause_irq <= 1'b0; - else // only if fifo is not empty... - if (t_pause & ~fifo_EF) - pause_irq <= 1'b1; - else if (read_0) - pause_irq <= 1'b0; - end - - - always @(posedge clk or negedge rst_n) - begin - if (rst_n == 0) - begin - r_val <= 1'b0; - t_dav <= 1'b1; - end - else - begin - r_val <= r_ena & ~wfifo_empty; - t_dav <= ~rfifo_full; - end - end - - - always @(posedge clk or negedge rst_n) - begin - if (rst_n == 0) - begin - fifo_AE <= 1'b0; - fifo_AF <= 1'b0; - fifo_wr <= 1'b0; - rvalid <= 1'b0; - read_0 <= 1'b0; - ien_AE <= 1'b0; - ien_AF <= 1'b0; - ac <= 1'b0; - woverflow <= 1'b0; - av_waitrequest <= 1'b1; - end - else - begin - fifo_AE <= {fifo_FF,wfifo_used} <= 8; - fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8; - fifo_wr <= 1'b0; - read_0 <= 1'b0; - av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest); - if (activity) - ac <= 1'b1; - // write - if (av_chipselect & ~av_write_n & av_waitrequest) - // addr 1 is control; addr 0 is data - if (av_address) - begin - ien_AF <= av_writedata[0]; - ien_AE <= av_writedata[1]; - if (av_writedata[10] & ~activity) - ac <= 1'b0; - end - else - begin - fifo_wr <= ~fifo_FF; - woverflow <= fifo_FF; - end - // read - if (av_chipselect & ~av_read_n & av_waitrequest) - begin - // addr 1 is interrupt; addr 0 is data - if (~av_address) - rvalid <= ~fifo_EF; - read_0 <= ~av_address; - end - end - end - - - assign fifo_wdata = av_writedata[7 : 0]; - assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0; - assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF }; - always @(posedge clk or negedge rst_n) - begin - if (rst_n == 0) - readyfordata <= 0; - else - readyfordata <= ~fifo_FF; - end - - - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - // Tie off Atlantic Interface signals not used for simulation - always @(posedge clk) - begin - sim_t_pause <= 1'b0; - sim_t_ena <= 1'b0; - sim_t_dat <= t_dav ? r_dat : {8{r_val}}; - sim_r_ena <= 1'b0; - end - - - assign r_ena = sim_r_ena; - assign t_ena = sim_t_ena; - assign t_dat = sim_t_dat; - assign t_pause = sim_t_pause; - always @(fifo_EF) - begin - dataavailable = ~fifo_EF; - end - - - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on -//synthesis read_comments_as_HDL on -// alt_jtag_atlantic nios_system_jtag_uart_alt_jtag_atlantic -// ( -// .clk (clk), -// .r_dat (r_dat), -// .r_ena (r_ena), -// .r_val (r_val), -// .rst_n (rst_n), -// .t_dat (t_dat), -// .t_dav (t_dav), -// .t_ena (t_ena), -// .t_pause (t_pause) -// ); -// -// defparam nios_system_jtag_uart_alt_jtag_atlantic.INSTANCE_ID = 0, -// nios_system_jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6, -// nios_system_jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6, -// nios_system_jtag_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES"; -// -// always @(posedge clk or negedge rst_n) -// begin -// if (rst_n == 0) -// dataavailable <= 0; -// else -// dataavailable <= ~fifo_EF; -// end -// -// -//synthesis read_comments_as_HDL off - -endmodule - diff --git a/db/ip/nios_system/submodules/nios_system_lcd.v b/db/ip/nios_system/submodules/nios_system_lcd.v deleted file mode 100644 index 18c2d15..0000000 --- a/db/ip/nios_system/submodules/nios_system_lcd.v +++ /dev/null @@ -1,66 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_lcd ( - // inputs: - address, - begintransfer, - clk, - read, - reset_n, - write, - writedata, - - // outputs: - LCD_E, - LCD_RS, - LCD_RW, - LCD_data, - readdata - ) -; - - output LCD_E; - output LCD_RS; - output LCD_RW; - inout [ 7: 0] LCD_data; - output [ 7: 0] readdata; - input [ 1: 0] address; - input begintransfer; - input clk; - input read; - input reset_n; - input write; - input [ 7: 0] writedata; - - wire LCD_E; - wire LCD_RS; - wire LCD_RW; - wire [ 7: 0] LCD_data; - wire [ 7: 0] readdata; - assign LCD_RW = address[0]; - assign LCD_RS = address[1]; - assign LCD_E = read | write; - assign LCD_data = (address[0]) ? {8{1'bz}} : writedata; - assign readdata = LCD_data; - //control_slave, which is an e_avalon_slave - -endmodule - diff --git a/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v b/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v deleted file mode 100644 index f58d30f..0000000 --- a/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v +++ /dev/null @@ -1,66 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_lcd_16207_0 ( - // inputs: - address, - begintransfer, - clk, - read, - reset_n, - write, - writedata, - - // outputs: - LCD_E, - LCD_RS, - LCD_RW, - LCD_data, - readdata - ) -; - - output LCD_E; - output LCD_RS; - output LCD_RW; - inout [ 7: 0] LCD_data; - output [ 7: 0] readdata; - input [ 1: 0] address; - input begintransfer; - input clk; - input read; - input reset_n; - input write; - input [ 7: 0] writedata; - - wire LCD_E; - wire LCD_RS; - wire LCD_RW; - wire [ 7: 0] LCD_data; - wire [ 7: 0] readdata; - assign LCD_RW = address[0]; - assign LCD_RS = address[1]; - assign LCD_E = read | write; - assign LCD_data = (address[0]) ? {8{1'bz}} : writedata; - assign readdata = LCD_data; - //control_slave, which is an e_avalon_slave - -endmodule - diff --git a/db/ip/nios_system/submodules/nios_system_lcd_E.v b/db/ip/nios_system/submodules/nios_system_lcd_E.v deleted file mode 100644 index c5680d0..0000000 --- a/db/ip/nios_system/submodules/nios_system_lcd_E.v +++ /dev/null @@ -1,66 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_lcd_E ( - // inputs: - address, - chipselect, - clk, - reset_n, - write_n, - writedata, - - // outputs: - out_port, - readdata - ) -; - - output out_port; - output [ 31: 0] readdata; - input [ 1: 0] address; - input chipselect; - input clk; - input reset_n; - input write_n; - input [ 31: 0] writedata; - - wire clk_en; - reg data_out; - wire out_port; - wire read_mux_out; - wire [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {1 {(address == 0)}} & data_out; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - data_out <= 0; - else if (chipselect && ~write_n && (address == 0)) - data_out <= writedata; - end - - - assign readdata = {32'b0 | read_mux_out}; - assign out_port = data_out; - -endmodule - diff --git a/db/ip/nios_system/submodules/nios_system_lcd_on.v b/db/ip/nios_system/submodules/nios_system_lcd_on.v deleted file mode 100644 index 4e9a8dc..0000000 --- a/db/ip/nios_system/submodules/nios_system_lcd_on.v +++ /dev/null @@ -1,66 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_lcd_on ( - // inputs: - address, - chipselect, - clk, - reset_n, - write_n, - writedata, - - // outputs: - out_port, - readdata - ) -; - - output out_port; - output [ 31: 0] readdata; - input [ 1: 0] address; - input chipselect; - input clk; - input reset_n; - input write_n; - input [ 31: 0] writedata; - - wire clk_en; - reg data_out; - wire out_port; - wire read_mux_out; - wire [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {1 {(address == 0)}} & data_out; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - data_out <= 0; - else if (chipselect && ~write_n && (address == 0)) - data_out <= writedata; - end - - - assign readdata = {32'b0 | read_mux_out}; - assign out_port = data_out; - -endmodule - diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor.sdc b/db/ip/nios_system/submodules/nios_system_nios2_processor.sdc deleted file mode 100644 index 4848c5a..0000000 --- a/db/ip/nios_system/submodules/nios_system_nios2_processor.sdc +++ /dev/null @@ -1,53 +0,0 @@ -# Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -# use of Altera Corporation's design tools, logic functions and other -# software and tools, and its AMPP partner logic functions, and any -# output files any of the foregoing (including device programming or -# simulation files), and any associated documentation or information are -# expressly subject to the terms and conditions of the Altera Program -# License Subscription Agreement or other applicable license agreement, -# including, without limitation, that your use is for the sole purpose -# of programming logic devices manufactured by Altera and sold by Altera -# or its authorized distributors. Please refer to the applicable -# agreement for further details. - -#************************************************************** -# Timequest JTAG clock definition -# Uncommenting the following lines will define the JTAG -# clock in TimeQuest Timing Analyzer -#************************************************************** - -#create_clock -period 10MHz {altera_reserved_tck} -#set_clock_groups -asynchronous -group {altera_reserved_tck} - -#************************************************************** -# Set TCL Path Variables -#************************************************************** - -set nios_system_nios2_processor nios_system_nios2_processor:* -set nios_system_nios2_processor_oci nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci -set nios_system_nios2_processor_oci_break nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break -set nios_system_nios2_processor_ocimem nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem -set nios_system_nios2_processor_oci_debug nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug -set nios_system_nios2_processor_wrapper nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper -set nios_system_nios2_processor_jtag_tck nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck -set nios_system_nios2_processor_jtag_sysclk nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk -set nios_system_nios2_processor_oci_path [format "%s|%s" $nios_system_nios2_processor $nios_system_nios2_processor_oci] -set nios_system_nios2_processor_oci_break_path [format "%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_oci_break] -set nios_system_nios2_processor_ocimem_path [format "%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_ocimem] -set nios_system_nios2_processor_oci_debug_path [format "%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_oci_debug] -set nios_system_nios2_processor_jtag_tck_path [format "%s|%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_wrapper $nios_system_nios2_processor_jtag_tck] -set nios_system_nios2_processor_jtag_sysclk_path [format "%s|%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_wrapper $nios_system_nios2_processor_jtag_sysclk] -set nios_system_nios2_processor_jtag_sr [format "%s|*sr" $nios_system_nios2_processor_jtag_tck_path] - -#************************************************************** -# Set False Paths -#************************************************************** - -set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_break_path|break_readreg*] -to [get_keepers *$nios_system_nios2_processor_jtag_sr*] -set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_debug_path|*resetlatch] -to [get_keepers *$nios_system_nios2_processor_jtag_sr[33]] -set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_debug_path|monitor_ready] -to [get_keepers *$nios_system_nios2_processor_jtag_sr[0]] -set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_debug_path|monitor_error] -to [get_keepers *$nios_system_nios2_processor_jtag_sr[34]] -set_false_path -from [get_keepers *$nios_system_nios2_processor_ocimem_path|*MonDReg*] -to [get_keepers *$nios_system_nios2_processor_jtag_sr*] -set_false_path -from *$nios_system_nios2_processor_jtag_sr* -to *$nios_system_nios2_processor_jtag_sysclk_path|*jdo* -set_false_path -from sld_hub:*|irf_reg* -to *$nios_system_nios2_processor_jtag_sysclk_path|ir* -set_false_path -from sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1] -to *$nios_system_nios2_processor_oci_debug_path|monitor_go diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor.v b/db/ip/nios_system/submodules/nios_system_nios2_processor.v deleted file mode 100644 index 7e8e063..0000000 --- a/db/ip/nios_system/submodules/nios_system_nios2_processor.v +++ /dev/null @@ -1,5672 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_register_bank_a_module ( - // inputs: - clock, - data, - rdaddress, - wraddress, - wren, - - // outputs: - q - ) -; - - parameter lpm_file = "UNUSED"; - - - output [ 31: 0] q; - input clock; - input [ 31: 0] data; - input [ 4: 0] rdaddress; - input [ 4: 0] wraddress; - input wren; - - wire [ 31: 0] q; - wire [ 31: 0] ram_q; - assign q = ram_q; - altsyncram the_altsyncram - ( - .address_a (wraddress), - .address_b (rdaddress), - .clock0 (clock), - .data_a (data), - .q_b (ram_q), - .wren_a (wren) - ); - - defparam the_altsyncram.address_reg_b = "CLOCK0", - the_altsyncram.init_file = lpm_file, - the_altsyncram.maximum_depth = 0, - the_altsyncram.numwords_a = 32, - the_altsyncram.numwords_b = 32, - the_altsyncram.operation_mode = "DUAL_PORT", - the_altsyncram.outdata_reg_b = "UNREGISTERED", - the_altsyncram.ram_block_type = "AUTO", - the_altsyncram.rdcontrol_reg_b = "CLOCK0", - the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", - the_altsyncram.width_a = 32, - the_altsyncram.width_b = 32, - the_altsyncram.widthad_a = 5, - the_altsyncram.widthad_b = 5; - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_register_bank_b_module ( - // inputs: - clock, - data, - rdaddress, - wraddress, - wren, - - // outputs: - q - ) -; - - parameter lpm_file = "UNUSED"; - - - output [ 31: 0] q; - input clock; - input [ 31: 0] data; - input [ 4: 0] rdaddress; - input [ 4: 0] wraddress; - input wren; - - wire [ 31: 0] q; - wire [ 31: 0] ram_q; - assign q = ram_q; - altsyncram the_altsyncram - ( - .address_a (wraddress), - .address_b (rdaddress), - .clock0 (clock), - .data_a (data), - .q_b (ram_q), - .wren_a (wren) - ); - - defparam the_altsyncram.address_reg_b = "CLOCK0", - the_altsyncram.init_file = lpm_file, - the_altsyncram.maximum_depth = 0, - the_altsyncram.numwords_a = 32, - the_altsyncram.numwords_b = 32, - the_altsyncram.operation_mode = "DUAL_PORT", - the_altsyncram.outdata_reg_b = "UNREGISTERED", - the_altsyncram.ram_block_type = "AUTO", - the_altsyncram.rdcontrol_reg_b = "CLOCK0", - the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", - the_altsyncram.width_a = 32, - the_altsyncram.width_b = 32, - the_altsyncram.widthad_a = 5, - the_altsyncram.widthad_b = 5; - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_debug ( - // inputs: - clk, - dbrk_break, - debugreq, - hbreak_enabled, - jdo, - jrst_n, - ocireg_ers, - ocireg_mrs, - reset, - st_ready_test_idle, - take_action_ocimem_a, - take_action_ocireg, - xbrk_break, - - // outputs: - debugack, - monitor_error, - monitor_go, - monitor_ready, - oci_hbreak_req, - resetlatch, - resetrequest - ) -; - - output debugack; - output monitor_error; - output monitor_go; - output monitor_ready; - output oci_hbreak_req; - output resetlatch; - output resetrequest; - input clk; - input dbrk_break; - input debugreq; - input hbreak_enabled; - input [ 37: 0] jdo; - input jrst_n; - input ocireg_ers; - input ocireg_mrs; - input reset; - input st_ready_test_idle; - input take_action_ocimem_a; - input take_action_ocireg; - input xbrk_break; - - reg break_on_reset /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - wire debugack; - reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; - reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; - reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; - wire oci_hbreak_req; - wire reset_sync; - reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - wire unxcomplemented_resetxx0; - assign unxcomplemented_resetxx0 = jrst_n; - altera_std_synchronizer the_altera_std_synchronizer - ( - .clk (clk), - .din (reset), - .dout (reset_sync), - .reset_n (unxcomplemented_resetxx0) - ); - - defparam the_altera_std_synchronizer.depth = 2; - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - break_on_reset <= 1'b0; - resetrequest <= 1'b0; - jtag_break <= 1'b0; - end - else if (take_action_ocimem_a) - begin - resetrequest <= jdo[22]; - jtag_break <= jdo[21] ? 1 - : jdo[20] ? 0 - : jtag_break; - - break_on_reset <= jdo[19] ? 1 - : jdo[18] ? 0 - : break_on_reset; - - resetlatch <= jdo[24] ? 0 : resetlatch; - end - else if (reset_sync) - begin - jtag_break <= break_on_reset; - resetlatch <= 1; - end - else if (debugreq & ~debugack & break_on_reset) - jtag_break <= 1'b1; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - monitor_ready <= 1'b0; - monitor_error <= 1'b0; - monitor_go <= 1'b0; - end - else - begin - if (take_action_ocimem_a && jdo[25]) - monitor_ready <= 1'b0; - else if (take_action_ocireg && ocireg_mrs) - monitor_ready <= 1'b1; - if (take_action_ocimem_a && jdo[25]) - monitor_error <= 1'b0; - else if (take_action_ocireg && ocireg_ers) - monitor_error <= 1'b1; - if (take_action_ocimem_a && jdo[23]) - monitor_go <= 1'b1; - else if (st_ready_test_idle) - monitor_go <= 1'b0; - end - end - - - assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq; - assign debugack = ~hbreak_enabled; - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_ociram_sp_ram_module ( - // inputs: - address, - byteenable, - clock, - data, - wren, - - // outputs: - q - ) -; - - parameter lpm_file = "UNUSED"; - - - output [ 31: 0] q; - input [ 7: 0] address; - input [ 3: 0] byteenable; - input clock; - input [ 31: 0] data; - input wren; - - wire [ 31: 0] q; - wire [ 31: 0] ram_q; - assign q = ram_q; - altsyncram the_altsyncram - ( - .address_a (address), - .byteena_a (byteenable), - .clock0 (clock), - .data_a (data), - .q_a (ram_q), - .wren_a (wren) - ); - - defparam the_altsyncram.init_file = lpm_file, - the_altsyncram.maximum_depth = 0, - the_altsyncram.numwords_a = 256, - the_altsyncram.operation_mode = "SINGLE_PORT", - the_altsyncram.outdata_reg_a = "UNREGISTERED", - the_altsyncram.ram_block_type = "AUTO", - the_altsyncram.width_a = 32, - the_altsyncram.width_byteena_a = 4, - the_altsyncram.widthad_a = 8; - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_ocimem ( - // inputs: - address, - byteenable, - clk, - debugaccess, - jdo, - jrst_n, - read, - take_action_ocimem_a, - take_action_ocimem_b, - take_no_action_ocimem_a, - write, - writedata, - - // outputs: - MonDReg, - ociram_readdata, - waitrequest - ) -; - - output [ 31: 0] MonDReg; - output [ 31: 0] ociram_readdata; - output waitrequest; - input [ 8: 0] address; - input [ 3: 0] byteenable; - input clk; - input debugaccess; - input [ 37: 0] jdo; - input jrst_n; - input read; - input take_action_ocimem_a; - input take_action_ocimem_b; - input take_no_action_ocimem_a; - input write; - input [ 31: 0] writedata; - - reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire [ 8: 0] MonARegAddrInc; - wire MonARegAddrIncAccessingRAM; - reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - reg avalon_ociram_readdata_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire avalon_ram_wr; - wire [ 31: 0] cfgrom_readdata; - reg jtag_ram_access /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - reg jtag_ram_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - reg jtag_ram_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - reg jtag_ram_wr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - reg jtag_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - reg jtag_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire [ 7: 0] ociram_addr; - wire [ 3: 0] ociram_byteenable; - wire [ 31: 0] ociram_readdata; - wire [ 31: 0] ociram_wr_data; - wire ociram_wr_en; - reg waitrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - jtag_rd <= 1'b0; - jtag_rd_d1 <= 1'b0; - jtag_ram_wr <= 1'b0; - jtag_ram_rd <= 1'b0; - jtag_ram_rd_d1 <= 1'b0; - jtag_ram_access <= 1'b0; - MonAReg <= 0; - MonDReg <= 0; - waitrequest <= 1'b1; - avalon_ociram_readdata_ready <= 1'b0; - end - else - begin - if (take_no_action_ocimem_a) - begin - MonAReg[10 : 2] <= MonARegAddrInc; - jtag_rd <= 1'b1; - jtag_ram_rd <= MonARegAddrIncAccessingRAM; - jtag_ram_access <= MonARegAddrIncAccessingRAM; - end - else if (take_action_ocimem_a) - begin - MonAReg[10 : 2] <= { jdo[17], - jdo[33 : 26] }; - - jtag_rd <= 1'b1; - jtag_ram_rd <= ~jdo[17]; - jtag_ram_access <= ~jdo[17]; - end - else if (take_action_ocimem_b) - begin - MonAReg[10 : 2] <= MonARegAddrInc; - MonDReg <= jdo[34 : 3]; - jtag_ram_wr <= MonARegAddrIncAccessingRAM; - jtag_ram_access <= MonARegAddrIncAccessingRAM; - end - else - begin - jtag_rd <= 0; - jtag_ram_wr <= 0; - jtag_ram_rd <= 0; - jtag_ram_access <= 0; - if (jtag_rd_d1) - MonDReg <= jtag_ram_rd_d1 ? ociram_readdata : cfgrom_readdata; - end - jtag_rd_d1 <= jtag_rd; - jtag_ram_rd_d1 <= jtag_ram_rd; - if (~waitrequest) - begin - waitrequest <= 1'b1; - avalon_ociram_readdata_ready <= 1'b0; - end - else if (write) - waitrequest <= ~address[8] & jtag_ram_access; - else if (read) - begin - avalon_ociram_readdata_ready <= ~(~address[8] & jtag_ram_access); - waitrequest <= ~avalon_ociram_readdata_ready; - end - else - begin - waitrequest <= 1'b1; - avalon_ociram_readdata_ready <= 1'b0; - end - end - end - - - assign MonARegAddrInc = MonAReg[10 : 2]+1; - assign MonARegAddrIncAccessingRAM = ~MonARegAddrInc[8]; - assign avalon_ram_wr = write & ~address[8] & debugaccess; - assign ociram_addr = jtag_ram_access ? MonAReg[9 : 2] : address[7 : 0]; - assign ociram_wr_data = jtag_ram_access ? MonDReg[31 : 0] : writedata; - assign ociram_byteenable = jtag_ram_access ? 4'b1111 : byteenable; - assign ociram_wr_en = jtag_ram_wr | avalon_ram_wr; -//nios_system_nios2_processor_ociram_sp_ram, which is an nios_sp_ram -nios_system_nios2_processor_ociram_sp_ram_module nios_system_nios2_processor_ociram_sp_ram - ( - .address (ociram_addr), - .byteenable (ociram_byteenable), - .clock (clk), - .data (ociram_wr_data), - .q (ociram_readdata), - .wren (ociram_wr_en) - ); - -//synthesis translate_off -`ifdef NO_PLI -defparam nios_system_nios2_processor_ociram_sp_ram.lpm_file = "nios_system_nios2_processor_ociram_default_contents.dat"; -`else -defparam nios_system_nios2_processor_ociram_sp_ram.lpm_file = "nios_system_nios2_processor_ociram_default_contents.hex"; -`endif -//synthesis translate_on -//synthesis read_comments_as_HDL on -//defparam nios_system_nios2_processor_ociram_sp_ram.lpm_file = "nios_system_nios2_processor_ociram_default_contents.mif"; -//synthesis read_comments_as_HDL off - assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h00000020 : - (MonAReg[4 : 2] == 3'd1)? 32'h00001313 : - (MonAReg[4 : 2] == 3'd2)? 32'h00040000 : - (MonAReg[4 : 2] == 3'd3)? 32'h00000000 : - (MonAReg[4 : 2] == 3'd4)? 32'h20000000 : - (MonAReg[4 : 2] == 3'd5)? 32'h00000000 : - (MonAReg[4 : 2] == 3'd6)? 32'h00000000 : - 32'h00000000; - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_avalon_reg ( - // inputs: - address, - clk, - debugaccess, - monitor_error, - monitor_go, - monitor_ready, - reset_n, - write, - writedata, - - // outputs: - oci_ienable, - oci_reg_readdata, - oci_single_step_mode, - ocireg_ers, - ocireg_mrs, - take_action_ocireg - ) -; - - output [ 31: 0] oci_ienable; - output [ 31: 0] oci_reg_readdata; - output oci_single_step_mode; - output ocireg_ers; - output ocireg_mrs; - output take_action_ocireg; - input [ 8: 0] address; - input clk; - input debugaccess; - input monitor_error; - input monitor_go; - input monitor_ready; - input reset_n; - input write; - input [ 31: 0] writedata; - - reg [ 31: 0] oci_ienable; - wire oci_reg_00_addressed; - wire oci_reg_01_addressed; - wire [ 31: 0] oci_reg_readdata; - reg oci_single_step_mode; - wire ocireg_ers; - wire ocireg_mrs; - wire ocireg_sstep; - wire take_action_oci_intr_mask_reg; - wire take_action_ocireg; - wire write_strobe; - assign oci_reg_00_addressed = address == 9'h100; - assign oci_reg_01_addressed = address == 9'h101; - assign write_strobe = write & debugaccess; - assign take_action_ocireg = write_strobe & oci_reg_00_addressed; - assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed; - assign ocireg_ers = writedata[1]; - assign ocireg_mrs = writedata[0]; - assign ocireg_sstep = writedata[3]; - assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go, - monitor_ready, monitor_error} : - oci_reg_01_addressed ? oci_ienable : - 32'b0; - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - oci_single_step_mode <= 1'b0; - else if (take_action_ocireg) - oci_single_step_mode <= ocireg_sstep; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - oci_ienable <= 32'b00000000000000000000000000100000; - else if (take_action_oci_intr_mask_reg) - oci_ienable <= writedata | ~(32'b00000000000000000000000000100000); - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_break ( - // inputs: - clk, - dbrk_break, - dbrk_goto0, - dbrk_goto1, - jdo, - jrst_n, - reset_n, - take_action_break_a, - take_action_break_b, - take_action_break_c, - take_no_action_break_a, - take_no_action_break_b, - take_no_action_break_c, - xbrk_goto0, - xbrk_goto1, - - // outputs: - break_readreg, - dbrk_hit0_latch, - dbrk_hit1_latch, - dbrk_hit2_latch, - dbrk_hit3_latch, - trigbrktype, - trigger_state_0, - trigger_state_1, - xbrk_ctrl0, - xbrk_ctrl1, - xbrk_ctrl2, - xbrk_ctrl3 - ) -; - - output [ 31: 0] break_readreg; - output dbrk_hit0_latch; - output dbrk_hit1_latch; - output dbrk_hit2_latch; - output dbrk_hit3_latch; - output trigbrktype; - output trigger_state_0; - output trigger_state_1; - output [ 7: 0] xbrk_ctrl0; - output [ 7: 0] xbrk_ctrl1; - output [ 7: 0] xbrk_ctrl2; - output [ 7: 0] xbrk_ctrl3; - input clk; - input dbrk_break; - input dbrk_goto0; - input dbrk_goto1; - input [ 37: 0] jdo; - input jrst_n; - input reset_n; - input take_action_break_a; - input take_action_break_b; - input take_action_break_c; - input take_no_action_break_a; - input take_no_action_break_b; - input take_no_action_break_c; - input xbrk_goto0; - input xbrk_goto1; - - wire [ 3: 0] break_a_wpr; - wire [ 1: 0] break_a_wpr_high_bits; - wire [ 1: 0] break_a_wpr_low_bits; - wire [ 1: 0] break_b_rr; - wire [ 1: 0] break_c_rr; - reg [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - wire dbrk0_high_value; - wire dbrk0_low_value; - wire dbrk1_high_value; - wire dbrk1_low_value; - wire dbrk2_high_value; - wire dbrk2_low_value; - wire dbrk3_high_value; - wire dbrk3_low_value; - wire dbrk_hit0_latch; - wire dbrk_hit1_latch; - wire dbrk_hit2_latch; - wire dbrk_hit3_latch; - wire take_action_any_break; - reg trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg trigger_state; - wire trigger_state_0; - wire trigger_state_1; - wire [ 31: 0] xbrk0_value; - wire [ 31: 0] xbrk1_value; - wire [ 31: 0] xbrk2_value; - wire [ 31: 0] xbrk3_value; - reg [ 7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg [ 7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg [ 7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg [ 7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - assign break_a_wpr = jdo[35 : 32]; - assign break_a_wpr_high_bits = break_a_wpr[3 : 2]; - assign break_a_wpr_low_bits = break_a_wpr[1 : 0]; - assign break_b_rr = jdo[33 : 32]; - assign break_c_rr = jdo[33 : 32]; - assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - xbrk_ctrl0 <= 0; - xbrk_ctrl1 <= 0; - xbrk_ctrl2 <= 0; - xbrk_ctrl3 <= 0; - trigbrktype <= 0; - end - else - begin - if (take_action_any_break) - trigbrktype <= 0; - else if (dbrk_break) - trigbrktype <= 1; - if (take_action_break_b) - begin - if ((break_b_rr == 2'b00) && (0 >= 1)) - begin - xbrk_ctrl0[0] <= jdo[27]; - xbrk_ctrl0[1] <= jdo[28]; - xbrk_ctrl0[2] <= jdo[29]; - xbrk_ctrl0[3] <= jdo[30]; - xbrk_ctrl0[4] <= jdo[21]; - xbrk_ctrl0[5] <= jdo[20]; - xbrk_ctrl0[6] <= jdo[19]; - xbrk_ctrl0[7] <= jdo[18]; - end - if ((break_b_rr == 2'b01) && (0 >= 2)) - begin - xbrk_ctrl1[0] <= jdo[27]; - xbrk_ctrl1[1] <= jdo[28]; - xbrk_ctrl1[2] <= jdo[29]; - xbrk_ctrl1[3] <= jdo[30]; - xbrk_ctrl1[4] <= jdo[21]; - xbrk_ctrl1[5] <= jdo[20]; - xbrk_ctrl1[6] <= jdo[19]; - xbrk_ctrl1[7] <= jdo[18]; - end - if ((break_b_rr == 2'b10) && (0 >= 3)) - begin - xbrk_ctrl2[0] <= jdo[27]; - xbrk_ctrl2[1] <= jdo[28]; - xbrk_ctrl2[2] <= jdo[29]; - xbrk_ctrl2[3] <= jdo[30]; - xbrk_ctrl2[4] <= jdo[21]; - xbrk_ctrl2[5] <= jdo[20]; - xbrk_ctrl2[6] <= jdo[19]; - xbrk_ctrl2[7] <= jdo[18]; - end - if ((break_b_rr == 2'b11) && (0 >= 4)) - begin - xbrk_ctrl3[0] <= jdo[27]; - xbrk_ctrl3[1] <= jdo[28]; - xbrk_ctrl3[2] <= jdo[29]; - xbrk_ctrl3[3] <= jdo[30]; - xbrk_ctrl3[4] <= jdo[21]; - xbrk_ctrl3[5] <= jdo[20]; - xbrk_ctrl3[6] <= jdo[19]; - xbrk_ctrl3[7] <= jdo[18]; - end - end - end - end - - - assign dbrk_hit0_latch = 1'b0; - assign dbrk0_low_value = 0; - assign dbrk0_high_value = 0; - assign dbrk_hit1_latch = 1'b0; - assign dbrk1_low_value = 0; - assign dbrk1_high_value = 0; - assign dbrk_hit2_latch = 1'b0; - assign dbrk2_low_value = 0; - assign dbrk2_high_value = 0; - assign dbrk_hit3_latch = 1'b0; - assign dbrk3_low_value = 0; - assign dbrk3_high_value = 0; - assign xbrk0_value = 32'b0; - assign xbrk1_value = 32'b0; - assign xbrk2_value = 32'b0; - assign xbrk3_value = 32'b0; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - break_readreg <= 32'b0; - else if (take_action_any_break) - break_readreg <= jdo[31 : 0]; - else if (take_no_action_break_a) - case (break_a_wpr_high_bits) - - 2'd0: begin - case (break_a_wpr_low_bits) // synthesis full_case - - 2'd0: begin - break_readreg <= xbrk0_value; - end // 2'd0 - - 2'd1: begin - break_readreg <= xbrk1_value; - end // 2'd1 - - 2'd2: begin - break_readreg <= xbrk2_value; - end // 2'd2 - - 2'd3: begin - break_readreg <= xbrk3_value; - end // 2'd3 - - endcase // break_a_wpr_low_bits - end // 2'd0 - - 2'd1: begin - break_readreg <= 32'b0; - end // 2'd1 - - 2'd2: begin - case (break_a_wpr_low_bits) // synthesis full_case - - 2'd0: begin - break_readreg <= dbrk0_low_value; - end // 2'd0 - - 2'd1: begin - break_readreg <= dbrk1_low_value; - end // 2'd1 - - 2'd2: begin - break_readreg <= dbrk2_low_value; - end // 2'd2 - - 2'd3: begin - break_readreg <= dbrk3_low_value; - end // 2'd3 - - endcase // break_a_wpr_low_bits - end // 2'd2 - - 2'd3: begin - case (break_a_wpr_low_bits) // synthesis full_case - - 2'd0: begin - break_readreg <= dbrk0_high_value; - end // 2'd0 - - 2'd1: begin - break_readreg <= dbrk1_high_value; - end // 2'd1 - - 2'd2: begin - break_readreg <= dbrk2_high_value; - end // 2'd2 - - 2'd3: begin - break_readreg <= dbrk3_high_value; - end // 2'd3 - - endcase // break_a_wpr_low_bits - end // 2'd3 - - endcase // break_a_wpr_high_bits - else if (take_no_action_break_b) - break_readreg <= jdo[31 : 0]; - else if (take_no_action_break_c) - break_readreg <= jdo[31 : 0]; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - trigger_state <= 0; - else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0)) - trigger_state <= 0; - else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1)) - trigger_state <= -1; - end - - - assign trigger_state_0 = ~trigger_state; - assign trigger_state_1 = trigger_state; - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_xbrk ( - // inputs: - D_valid, - E_valid, - F_pc, - clk, - reset_n, - trigger_state_0, - trigger_state_1, - xbrk_ctrl0, - xbrk_ctrl1, - xbrk_ctrl2, - xbrk_ctrl3, - - // outputs: - xbrk_break, - xbrk_goto0, - xbrk_goto1, - xbrk_traceoff, - xbrk_traceon, - xbrk_trigout - ) -; - - output xbrk_break; - output xbrk_goto0; - output xbrk_goto1; - output xbrk_traceoff; - output xbrk_traceon; - output xbrk_trigout; - input D_valid; - input E_valid; - input [ 16: 0] F_pc; - input clk; - input reset_n; - input trigger_state_0; - input trigger_state_1; - input [ 7: 0] xbrk_ctrl0; - input [ 7: 0] xbrk_ctrl1; - input [ 7: 0] xbrk_ctrl2; - input [ 7: 0] xbrk_ctrl3; - - wire D_cpu_addr_en; - wire E_cpu_addr_en; - reg E_xbrk_goto0; - reg E_xbrk_goto1; - reg E_xbrk_traceoff; - reg E_xbrk_traceon; - reg E_xbrk_trigout; - wire [ 18: 0] cpu_i_address; - wire xbrk0_armed; - wire xbrk0_break_hit; - wire xbrk0_goto0_hit; - wire xbrk0_goto1_hit; - wire xbrk0_toff_hit; - wire xbrk0_ton_hit; - wire xbrk0_tout_hit; - wire xbrk1_armed; - wire xbrk1_break_hit; - wire xbrk1_goto0_hit; - wire xbrk1_goto1_hit; - wire xbrk1_toff_hit; - wire xbrk1_ton_hit; - wire xbrk1_tout_hit; - wire xbrk2_armed; - wire xbrk2_break_hit; - wire xbrk2_goto0_hit; - wire xbrk2_goto1_hit; - wire xbrk2_toff_hit; - wire xbrk2_ton_hit; - wire xbrk2_tout_hit; - wire xbrk3_armed; - wire xbrk3_break_hit; - wire xbrk3_goto0_hit; - wire xbrk3_goto1_hit; - wire xbrk3_toff_hit; - wire xbrk3_ton_hit; - wire xbrk3_tout_hit; - reg xbrk_break; - wire xbrk_break_hit; - wire xbrk_goto0; - wire xbrk_goto0_hit; - wire xbrk_goto1; - wire xbrk_goto1_hit; - wire xbrk_toff_hit; - wire xbrk_ton_hit; - wire xbrk_tout_hit; - wire xbrk_traceoff; - wire xbrk_traceon; - wire xbrk_trigout; - assign cpu_i_address = {F_pc, 2'b00}; - assign D_cpu_addr_en = D_valid; - assign E_cpu_addr_en = E_valid; - assign xbrk0_break_hit = 0; - assign xbrk0_ton_hit = 0; - assign xbrk0_toff_hit = 0; - assign xbrk0_tout_hit = 0; - assign xbrk0_goto0_hit = 0; - assign xbrk0_goto1_hit = 0; - assign xbrk1_break_hit = 0; - assign xbrk1_ton_hit = 0; - assign xbrk1_toff_hit = 0; - assign xbrk1_tout_hit = 0; - assign xbrk1_goto0_hit = 0; - assign xbrk1_goto1_hit = 0; - assign xbrk2_break_hit = 0; - assign xbrk2_ton_hit = 0; - assign xbrk2_toff_hit = 0; - assign xbrk2_tout_hit = 0; - assign xbrk2_goto0_hit = 0; - assign xbrk2_goto1_hit = 0; - assign xbrk3_break_hit = 0; - assign xbrk3_ton_hit = 0; - assign xbrk3_toff_hit = 0; - assign xbrk3_tout_hit = 0; - assign xbrk3_goto0_hit = 0; - assign xbrk3_goto1_hit = 0; - assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit); - assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit); - assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit); - assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit); - assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit); - assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - xbrk_break <= 0; - else if (E_cpu_addr_en) - xbrk_break <= xbrk_break_hit; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_xbrk_traceon <= 0; - else if (E_cpu_addr_en) - E_xbrk_traceon <= xbrk_ton_hit; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_xbrk_traceoff <= 0; - else if (E_cpu_addr_en) - E_xbrk_traceoff <= xbrk_toff_hit; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_xbrk_trigout <= 0; - else if (E_cpu_addr_en) - E_xbrk_trigout <= xbrk_tout_hit; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_xbrk_goto0 <= 0; - else if (E_cpu_addr_en) - E_xbrk_goto0 <= xbrk_goto0_hit; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_xbrk_goto1 <= 0; - else if (E_cpu_addr_en) - E_xbrk_goto1 <= xbrk_goto1_hit; - end - - - assign xbrk_traceon = 1'b0; - assign xbrk_traceoff = 1'b0; - assign xbrk_trigout = 1'b0; - assign xbrk_goto0 = 1'b0; - assign xbrk_goto1 = 1'b0; - assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) || - (xbrk_ctrl0[5] & trigger_state_1); - - assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) || - (xbrk_ctrl1[5] & trigger_state_1); - - assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) || - (xbrk_ctrl2[5] & trigger_state_1); - - assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) || - (xbrk_ctrl3[5] & trigger_state_1); - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_dbrk ( - // inputs: - E_st_data, - av_ld_data_aligned_filtered, - clk, - d_address, - d_read, - d_waitrequest, - d_write, - debugack, - reset_n, - - // outputs: - cpu_d_address, - cpu_d_read, - cpu_d_readdata, - cpu_d_wait, - cpu_d_write, - cpu_d_writedata, - dbrk_break, - dbrk_goto0, - dbrk_goto1, - dbrk_traceme, - dbrk_traceoff, - dbrk_traceon, - dbrk_trigout - ) -; - - output [ 18: 0] cpu_d_address; - output cpu_d_read; - output [ 31: 0] cpu_d_readdata; - output cpu_d_wait; - output cpu_d_write; - output [ 31: 0] cpu_d_writedata; - output dbrk_break; - output dbrk_goto0; - output dbrk_goto1; - output dbrk_traceme; - output dbrk_traceoff; - output dbrk_traceon; - output dbrk_trigout; - input [ 31: 0] E_st_data; - input [ 31: 0] av_ld_data_aligned_filtered; - input clk; - input [ 18: 0] d_address; - input d_read; - input d_waitrequest; - input d_write; - input debugack; - input reset_n; - - wire [ 18: 0] cpu_d_address; - wire cpu_d_read; - wire [ 31: 0] cpu_d_readdata; - wire cpu_d_wait; - wire cpu_d_write; - wire [ 31: 0] cpu_d_writedata; - wire dbrk0_armed; - wire dbrk0_break_pulse; - wire dbrk0_goto0; - wire dbrk0_goto1; - wire dbrk0_traceme; - wire dbrk0_traceoff; - wire dbrk0_traceon; - wire dbrk0_trigout; - wire dbrk1_armed; - wire dbrk1_break_pulse; - wire dbrk1_goto0; - wire dbrk1_goto1; - wire dbrk1_traceme; - wire dbrk1_traceoff; - wire dbrk1_traceon; - wire dbrk1_trigout; - wire dbrk2_armed; - wire dbrk2_break_pulse; - wire dbrk2_goto0; - wire dbrk2_goto1; - wire dbrk2_traceme; - wire dbrk2_traceoff; - wire dbrk2_traceon; - wire dbrk2_trigout; - wire dbrk3_armed; - wire dbrk3_break_pulse; - wire dbrk3_goto0; - wire dbrk3_goto1; - wire dbrk3_traceme; - wire dbrk3_traceoff; - wire dbrk3_traceon; - wire dbrk3_trigout; - reg dbrk_break; - reg dbrk_break_pulse; - wire [ 31: 0] dbrk_data; - reg dbrk_goto0; - reg dbrk_goto1; - reg dbrk_traceme; - reg dbrk_traceoff; - reg dbrk_traceon; - reg dbrk_trigout; - assign cpu_d_address = d_address; - assign cpu_d_readdata = av_ld_data_aligned_filtered; - assign cpu_d_read = d_read; - assign cpu_d_writedata = E_st_data; - assign cpu_d_write = d_write; - assign cpu_d_wait = d_waitrequest; - assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - dbrk_break <= 0; - else - dbrk_break <= dbrk_break ? ~debugack - : dbrk_break_pulse; - - end - - - assign dbrk0_armed = 1'b0; - assign dbrk0_trigout = 1'b0; - assign dbrk0_break_pulse = 1'b0; - assign dbrk0_traceoff = 1'b0; - assign dbrk0_traceon = 1'b0; - assign dbrk0_traceme = 1'b0; - assign dbrk0_goto0 = 1'b0; - assign dbrk0_goto1 = 1'b0; - assign dbrk1_armed = 1'b0; - assign dbrk1_trigout = 1'b0; - assign dbrk1_break_pulse = 1'b0; - assign dbrk1_traceoff = 1'b0; - assign dbrk1_traceon = 1'b0; - assign dbrk1_traceme = 1'b0; - assign dbrk1_goto0 = 1'b0; - assign dbrk1_goto1 = 1'b0; - assign dbrk2_armed = 1'b0; - assign dbrk2_trigout = 1'b0; - assign dbrk2_break_pulse = 1'b0; - assign dbrk2_traceoff = 1'b0; - assign dbrk2_traceon = 1'b0; - assign dbrk2_traceme = 1'b0; - assign dbrk2_goto0 = 1'b0; - assign dbrk2_goto1 = 1'b0; - assign dbrk3_armed = 1'b0; - assign dbrk3_trigout = 1'b0; - assign dbrk3_break_pulse = 1'b0; - assign dbrk3_traceoff = 1'b0; - assign dbrk3_traceon = 1'b0; - assign dbrk3_traceme = 1'b0; - assign dbrk3_goto0 = 1'b0; - assign dbrk3_goto1 = 1'b0; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - dbrk_trigout <= 0; - dbrk_break_pulse <= 0; - dbrk_traceoff <= 0; - dbrk_traceon <= 0; - dbrk_traceme <= 0; - dbrk_goto0 <= 0; - dbrk_goto1 <= 0; - end - else - begin - dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout; - dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse; - dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff; - dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon; - dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme; - dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0; - dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1; - end - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_itrace ( - // inputs: - clk, - dbrk_traceoff, - dbrk_traceon, - jdo, - jrst_n, - take_action_tracectrl, - trc_enb, - xbrk_traceoff, - xbrk_traceon, - xbrk_wrap_traceoff, - - // outputs: - dct_buffer, - dct_count, - itm, - trc_ctrl, - trc_on - ) -; - - output [ 29: 0] dct_buffer; - output [ 3: 0] dct_count; - output [ 35: 0] itm; - output [ 15: 0] trc_ctrl; - output trc_on; - input clk; - input dbrk_traceoff; - input dbrk_traceon; - input [ 15: 0] jdo; - input jrst_n; - input take_action_tracectrl; - input trc_enb; - input xbrk_traceoff; - input xbrk_traceon; - input xbrk_wrap_traceoff; - - wire curr_pid; - reg [ 29: 0] dct_buffer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 1: 0] dct_code; - reg [ 3: 0] dct_count /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire dct_is_taken; - wire [ 31: 0] excaddr; - wire instr_retired; - wire is_advanced_exception; - wire is_cond_dct; - wire is_dct; - wire is_exception_no_break; - wire is_fast_tlb_miss_exception; - wire is_idct; - reg [ 35: 0] itm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire not_in_debug_mode; - reg pending_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg [ 31: 0] pending_excaddr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg pending_exctype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg [ 3: 0] pending_frametype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg pending_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg prev_pid_valid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire record_dct_outcome_in_sync; - wire record_itrace; - wire [ 31: 0] retired_pcb; - reg snapped_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg snapped_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg snapped_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 1: 0] sync_code; - wire [ 6: 0] sync_interval; - wire sync_pending; - reg [ 6: 0] sync_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 6: 0] sync_timer_next; - reg trc_clear /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; - wire [ 15: 0] trc_ctrl; - reg [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire trc_on; - assign is_cond_dct = 1'b0; - assign is_dct = 1'b0; - assign dct_is_taken = 1'b0; - assign is_idct = 1'b0; - assign retired_pcb = 32'b0; - assign not_in_debug_mode = 1'b0; - assign instr_retired = 1'b0; - assign is_advanced_exception = 1'b0; - assign is_exception_no_break = 1'b0; - assign is_fast_tlb_miss_exception = 1'b0; - assign curr_pid = 1'b0; - assign excaddr = 32'b0; - assign sync_code = trc_ctrl[3 : 2]; - assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 }; - assign sync_pending = sync_timer == 0; - assign record_dct_outcome_in_sync = dct_is_taken & sync_pending; - assign sync_timer_next = sync_pending ? sync_timer : (sync_timer - 1); - assign record_itrace = trc_on & trc_ctrl[4]; - assign dct_code = {is_cond_dct, dct_is_taken}; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - trc_clear <= 0; - else - trc_clear <= ~trc_enb & - take_action_tracectrl & jdo[4]; - - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - itm <= 0; - dct_buffer <= 0; - dct_count <= 0; - sync_timer <= 0; - pending_frametype <= 4'b0000; - pending_exctype <= 1'b0; - pending_excaddr <= 0; - prev_pid <= 0; - prev_pid_valid <= 0; - snapped_pid <= 0; - snapped_curr_pid <= 0; - snapped_prev_pid <= 0; - pending_curr_pid <= 0; - pending_prev_pid <= 0; - end - else if (trc_clear || (!0 && !0)) - begin - itm <= 0; - dct_buffer <= 0; - dct_count <= 0; - sync_timer <= 0; - pending_frametype <= 4'b0000; - pending_exctype <= 1'b0; - pending_excaddr <= 0; - prev_pid <= 0; - prev_pid_valid <= 0; - snapped_pid <= 0; - snapped_curr_pid <= 0; - snapped_prev_pid <= 0; - pending_curr_pid <= 0; - pending_prev_pid <= 0; - end - else - begin - if (!prev_pid_valid) - begin - prev_pid <= curr_pid; - prev_pid_valid <= 1; - end - if ((curr_pid != prev_pid) & prev_pid_valid & !snapped_pid) - begin - snapped_pid <= 1; - snapped_curr_pid <= curr_pid; - snapped_prev_pid <= prev_pid; - prev_pid <= curr_pid; - prev_pid_valid <= 1; - end - if (instr_retired | is_advanced_exception) - begin - if (~record_itrace) - pending_frametype <= 4'b1010; - else if (is_exception_no_break) - begin - pending_frametype <= 4'b0010; - pending_excaddr <= excaddr; - if (is_fast_tlb_miss_exception) - pending_exctype <= 1'b1; - else - pending_exctype <= 1'b0; - end - else if (is_idct) - pending_frametype <= 4'b1001; - else if (record_dct_outcome_in_sync) - pending_frametype <= 4'b1000; - else if (!is_dct & snapped_pid) - begin - pending_frametype <= 4'b0011; - pending_curr_pid <= snapped_curr_pid; - pending_prev_pid <= snapped_prev_pid; - snapped_pid <= 0; - end - else - pending_frametype <= 4'b0000; - if ((dct_count != 0) & - (~record_itrace | - is_exception_no_break | - is_idct | - record_dct_outcome_in_sync | - (!is_dct & snapped_pid))) - begin - itm <= {4'b0001, dct_buffer, 2'b00}; - dct_buffer <= 0; - dct_count <= 0; - sync_timer <= sync_timer_next; - end - else - begin - if (record_itrace & (is_dct & (dct_count != 4'd15)) & ~record_dct_outcome_in_sync & ~is_advanced_exception) - begin - dct_buffer <= {dct_code, dct_buffer[29 : 2]}; - dct_count <= dct_count + 1; - end - if (record_itrace & (pending_frametype == 4'b0010)) - itm <= {4'b0010, pending_excaddr[31 : 1], pending_exctype}; - else if (record_itrace & ( - (pending_frametype == 4'b1000) | - (pending_frametype == 4'b1010) | - (pending_frametype == 4'b1001))) - begin - itm <= {pending_frametype, retired_pcb}; - sync_timer <= sync_interval; - if (0 & - ((pending_frametype == 4'b1000) | (pending_frametype == 4'b1010)) & - !snapped_pid & prev_pid_valid) - begin - snapped_pid <= 1; - snapped_curr_pid <= curr_pid; - snapped_prev_pid <= prev_pid; - end - end - else if (record_itrace & - 0 & (pending_frametype == 4'b0011)) - itm <= {4'b0011, 2'b00, pending_prev_pid, 2'b00, pending_curr_pid}; - else if (record_itrace & is_dct) - begin - if (dct_count == 4'd15) - begin - itm <= {4'b0001, dct_code, dct_buffer}; - dct_buffer <= 0; - dct_count <= 0; - sync_timer <= sync_timer_next; - end - else - itm <= 4'b0000; - end - else - itm <= {4'b0000, 32'b0}; - end - end - else - itm <= {4'b0000, 32'b0}; - end - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - trc_ctrl_reg[0] <= 1'b0; - trc_ctrl_reg[1] <= 1'b0; - trc_ctrl_reg[3 : 2] <= 2'b00; - trc_ctrl_reg[4] <= 1'b0; - trc_ctrl_reg[7 : 5] <= 3'b000; - trc_ctrl_reg[8] <= 0; - trc_ctrl_reg[9] <= 1'b0; - trc_ctrl_reg[10] <= 1'b0; - end - else if (take_action_tracectrl) - begin - trc_ctrl_reg[0] <= jdo[5]; - trc_ctrl_reg[1] <= jdo[6]; - trc_ctrl_reg[3 : 2] <= jdo[8 : 7]; - trc_ctrl_reg[4] <= jdo[9]; - trc_ctrl_reg[9] <= jdo[14]; - trc_ctrl_reg[10] <= jdo[2]; - if (0) - trc_ctrl_reg[7 : 5] <= jdo[12 : 10]; - if (0 & 0) - trc_ctrl_reg[8] <= jdo[13]; - end - else if (xbrk_wrap_traceoff) - begin - trc_ctrl_reg[1] <= 0; - trc_ctrl_reg[0] <= 0; - end - else if (dbrk_traceoff | xbrk_traceoff) - trc_ctrl_reg[1] <= 0; - else if (trc_ctrl_reg[0] & - (dbrk_traceon | xbrk_traceon)) - trc_ctrl_reg[1] <= 1; - end - - - assign trc_ctrl = (0 || 0) ? {6'b000000, trc_ctrl_reg} : 0; - assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode); - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_td_mode ( - // inputs: - ctrl, - - // outputs: - td_mode - ) -; - - output [ 3: 0] td_mode; - input [ 8: 0] ctrl; - - wire [ 2: 0] ctrl_bits_for_mux; - reg [ 3: 0] td_mode; - assign ctrl_bits_for_mux = ctrl[7 : 5]; - always @(ctrl_bits_for_mux) - begin - case (ctrl_bits_for_mux) - - 3'b000: begin - td_mode = 4'b0000; - end // 3'b000 - - 3'b001: begin - td_mode = 4'b1000; - end // 3'b001 - - 3'b010: begin - td_mode = 4'b0100; - end // 3'b010 - - 3'b011: begin - td_mode = 4'b1100; - end // 3'b011 - - 3'b100: begin - td_mode = 4'b0010; - end // 3'b100 - - 3'b101: begin - td_mode = 4'b1010; - end // 3'b101 - - 3'b110: begin - td_mode = 4'b0101; - end // 3'b110 - - 3'b111: begin - td_mode = 4'b1111; - end // 3'b111 - - endcase // ctrl_bits_for_mux - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_dtrace ( - // inputs: - clk, - cpu_d_address, - cpu_d_read, - cpu_d_readdata, - cpu_d_wait, - cpu_d_write, - cpu_d_writedata, - jrst_n, - trc_ctrl, - - // outputs: - atm, - dtm - ) -; - - output [ 35: 0] atm; - output [ 35: 0] dtm; - input clk; - input [ 18: 0] cpu_d_address; - input cpu_d_read; - input [ 31: 0] cpu_d_readdata; - input cpu_d_wait; - input cpu_d_write; - input [ 31: 0] cpu_d_writedata; - input jrst_n; - input [ 15: 0] trc_ctrl; - - reg [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 31: 0] cpu_d_address_0_padded; - wire [ 31: 0] cpu_d_readdata_0_padded; - wire [ 31: 0] cpu_d_writedata_0_padded; - reg [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire record_load_addr; - wire record_load_data; - wire record_store_addr; - wire record_store_data; - wire [ 3: 0] td_mode_trc_ctrl; - assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0; - assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0; - assign cpu_d_address_0_padded = cpu_d_address | 32'b0; - //nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode, which is an e_instance - nios_system_nios2_processor_nios2_oci_td_mode nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode - ( - .ctrl (trc_ctrl[8 : 0]), - .td_mode (td_mode_trc_ctrl) - ); - - assign {record_load_addr, record_store_addr, - record_load_data, record_store_data} = td_mode_trc_ctrl; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - atm <= 0; - dtm <= 0; - end - else if (0) - begin - if (cpu_d_write & ~cpu_d_wait & record_store_addr) - atm <= {4'b0101, cpu_d_address_0_padded}; - else if (cpu_d_read & ~cpu_d_wait & record_load_addr) - atm <= {4'b0100, cpu_d_address_0_padded}; - else - atm <= {4'b0000, cpu_d_address_0_padded}; - if (cpu_d_write & ~cpu_d_wait & record_store_data) - dtm <= {4'b0111, cpu_d_writedata_0_padded}; - else if (cpu_d_read & ~cpu_d_wait & record_load_data) - dtm <= {4'b0110, cpu_d_readdata_0_padded}; - else - dtm <= {4'b0000, cpu_d_readdata_0_padded}; - end - else - begin - atm <= 0; - dtm <= 0; - end - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_compute_tm_count ( - // inputs: - atm_valid, - dtm_valid, - itm_valid, - - // outputs: - compute_tm_count - ) -; - - output [ 1: 0] compute_tm_count; - input atm_valid; - input dtm_valid; - input itm_valid; - - reg [ 1: 0] compute_tm_count; - wire [ 2: 0] switch_for_mux; - assign switch_for_mux = {itm_valid, atm_valid, dtm_valid}; - always @(switch_for_mux) - begin - case (switch_for_mux) - - 3'b000: begin - compute_tm_count = 0; - end // 3'b000 - - 3'b001: begin - compute_tm_count = 1; - end // 3'b001 - - 3'b010: begin - compute_tm_count = 1; - end // 3'b010 - - 3'b011: begin - compute_tm_count = 2; - end // 3'b011 - - 3'b100: begin - compute_tm_count = 1; - end // 3'b100 - - 3'b101: begin - compute_tm_count = 2; - end // 3'b101 - - 3'b110: begin - compute_tm_count = 2; - end // 3'b110 - - 3'b111: begin - compute_tm_count = 3; - end // 3'b111 - - endcase // switch_for_mux - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_fifowp_inc ( - // inputs: - free2, - free3, - tm_count, - - // outputs: - fifowp_inc - ) -; - - output [ 3: 0] fifowp_inc; - input free2; - input free3; - input [ 1: 0] tm_count; - - reg [ 3: 0] fifowp_inc; - always @(free2 or free3 or tm_count) - begin - if (free3 & (tm_count == 3)) - fifowp_inc = 3; - else if (free2 & (tm_count >= 2)) - fifowp_inc = 2; - else if (tm_count >= 1) - fifowp_inc = 1; - else - fifowp_inc = 0; - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_fifocount_inc ( - // inputs: - empty, - free2, - free3, - tm_count, - - // outputs: - fifocount_inc - ) -; - - output [ 4: 0] fifocount_inc; - input empty; - input free2; - input free3; - input [ 1: 0] tm_count; - - reg [ 4: 0] fifocount_inc; - always @(empty or free2 or free3 or tm_count) - begin - if (empty) - fifocount_inc = tm_count[1 : 0]; - else if (free3 & (tm_count == 3)) - fifocount_inc = 2; - else if (free2 & (tm_count >= 2)) - fifocount_inc = 1; - else if (tm_count >= 1) - fifocount_inc = 0; - else - fifocount_inc = {5{1'b1}}; - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_fifo ( - // inputs: - atm, - clk, - dbrk_traceme, - dbrk_traceoff, - dbrk_traceon, - dct_buffer, - dct_count, - dtm, - itm, - jrst_n, - reset_n, - test_ending, - test_has_ended, - trc_on, - - // outputs: - tw - ) -; - - output [ 35: 0] tw; - input [ 35: 0] atm; - input clk; - input dbrk_traceme; - input dbrk_traceoff; - input dbrk_traceon; - input [ 29: 0] dct_buffer; - input [ 3: 0] dct_count; - input [ 35: 0] dtm; - input [ 35: 0] itm; - input jrst_n; - input reset_n; - input test_ending; - input test_has_ended; - input trc_on; - - wire atm_valid; - wire [ 1: 0] compute_tm_count_tm_count; - wire dtm_valid; - wire empty; - reg [ 35: 0] fifo_0; - wire fifo_0_enable; - wire [ 35: 0] fifo_0_mux; - reg [ 35: 0] fifo_1; - reg [ 35: 0] fifo_10; - wire fifo_10_enable; - wire [ 35: 0] fifo_10_mux; - reg [ 35: 0] fifo_11; - wire fifo_11_enable; - wire [ 35: 0] fifo_11_mux; - reg [ 35: 0] fifo_12; - wire fifo_12_enable; - wire [ 35: 0] fifo_12_mux; - reg [ 35: 0] fifo_13; - wire fifo_13_enable; - wire [ 35: 0] fifo_13_mux; - reg [ 35: 0] fifo_14; - wire fifo_14_enable; - wire [ 35: 0] fifo_14_mux; - reg [ 35: 0] fifo_15; - wire fifo_15_enable; - wire [ 35: 0] fifo_15_mux; - wire fifo_1_enable; - wire [ 35: 0] fifo_1_mux; - reg [ 35: 0] fifo_2; - wire fifo_2_enable; - wire [ 35: 0] fifo_2_mux; - reg [ 35: 0] fifo_3; - wire fifo_3_enable; - wire [ 35: 0] fifo_3_mux; - reg [ 35: 0] fifo_4; - wire fifo_4_enable; - wire [ 35: 0] fifo_4_mux; - reg [ 35: 0] fifo_5; - wire fifo_5_enable; - wire [ 35: 0] fifo_5_mux; - reg [ 35: 0] fifo_6; - wire fifo_6_enable; - wire [ 35: 0] fifo_6_mux; - reg [ 35: 0] fifo_7; - wire fifo_7_enable; - wire [ 35: 0] fifo_7_mux; - reg [ 35: 0] fifo_8; - wire fifo_8_enable; - wire [ 35: 0] fifo_8_mux; - reg [ 35: 0] fifo_9; - wire fifo_9_enable; - wire [ 35: 0] fifo_9_mux; - wire [ 35: 0] fifo_read_mux; - reg [ 4: 0] fifocount /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 4: 0] fifocount_inc_fifocount; - wire [ 35: 0] fifohead; - reg [ 3: 0] fiforp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg [ 3: 0] fifowp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 3: 0] fifowp1; - wire [ 3: 0] fifowp2; - wire [ 3: 0] fifowp_inc_fifowp; - wire free2; - wire free3; - wire itm_valid; - reg ovf_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 35: 0] ovr_pending_atm; - wire [ 35: 0] ovr_pending_dtm; - wire [ 1: 0] tm_count; - wire tm_count_ge1; - wire tm_count_ge2; - wire tm_count_ge3; - wire trc_this; - wire [ 35: 0] tw; - assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme; - assign itm_valid = |itm[35 : 32]; - assign atm_valid = |atm[35 : 32] & trc_this; - assign dtm_valid = |dtm[35 : 32] & trc_this; - assign free2 = ~fifocount[4]; - assign free3 = ~fifocount[4] & ~&fifocount[3 : 0]; - assign empty = ~|fifocount; - assign fifowp1 = fifowp + 1; - assign fifowp2 = fifowp + 2; - //nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count, which is an e_instance - nios_system_nios2_processor_nios2_oci_compute_tm_count nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count - ( - .atm_valid (atm_valid), - .compute_tm_count (compute_tm_count_tm_count), - .dtm_valid (dtm_valid), - .itm_valid (itm_valid) - ); - - assign tm_count = compute_tm_count_tm_count; - //nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp, which is an e_instance - nios_system_nios2_processor_nios2_oci_fifowp_inc nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp - ( - .fifowp_inc (fifowp_inc_fifowp), - .free2 (free2), - .free3 (free3), - .tm_count (tm_count) - ); - - //nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount, which is an e_instance - nios_system_nios2_processor_nios2_oci_fifocount_inc nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount - ( - .empty (empty), - .fifocount_inc (fifocount_inc_fifocount), - .free2 (free2), - .free3 (free3), - .tm_count (tm_count) - ); - - //the_nios_system_nios2_processor_oci_test_bench, which is an e_instance - nios_system_nios2_processor_oci_test_bench the_nios_system_nios2_processor_oci_test_bench - ( - .dct_buffer (dct_buffer), - .dct_count (dct_count), - .test_ending (test_ending), - .test_has_ended (test_has_ended) - ); - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - fiforp <= 0; - fifowp <= 0; - fifocount <= 0; - ovf_pending <= 1; - end - else - begin - fifowp <= fifowp + fifowp_inc_fifowp; - fifocount <= fifocount + fifocount_inc_fifocount; - if (~empty) - fiforp <= fiforp + 1; - if (~trc_this || (~free2 & tm_count[1]) || (~free3 & (&tm_count))) - ovf_pending <= 1; - else if (atm_valid | dtm_valid) - ovf_pending <= 0; - end - end - - - assign fifohead = fifo_read_mux; - assign tw = 0 ? { (empty ? 4'h0 : fifohead[35 : 32]), fifohead[31 : 0]} : itm; - assign fifo_0_enable = ((fifowp == 4'd0) && tm_count_ge1) || (free2 && (fifowp1== 4'd0) && tm_count_ge2) ||(free3 && (fifowp2== 4'd0) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_0 <= 0; - else if (fifo_0_enable) - fifo_0 <= fifo_0_mux; - end - - - assign fifo_0_mux = (((fifowp == 4'd0) && itm_valid))? itm : - (((fifowp == 4'd0) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd0) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd0) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd0) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd0) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_1_enable = ((fifowp == 4'd1) && tm_count_ge1) || (free2 && (fifowp1== 4'd1) && tm_count_ge2) ||(free3 && (fifowp2== 4'd1) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_1 <= 0; - else if (fifo_1_enable) - fifo_1 <= fifo_1_mux; - end - - - assign fifo_1_mux = (((fifowp == 4'd1) && itm_valid))? itm : - (((fifowp == 4'd1) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd1) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd1) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd1) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd1) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_2_enable = ((fifowp == 4'd2) && tm_count_ge1) || (free2 && (fifowp1== 4'd2) && tm_count_ge2) ||(free3 && (fifowp2== 4'd2) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_2 <= 0; - else if (fifo_2_enable) - fifo_2 <= fifo_2_mux; - end - - - assign fifo_2_mux = (((fifowp == 4'd2) && itm_valid))? itm : - (((fifowp == 4'd2) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd2) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd2) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd2) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd2) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_3_enable = ((fifowp == 4'd3) && tm_count_ge1) || (free2 && (fifowp1== 4'd3) && tm_count_ge2) ||(free3 && (fifowp2== 4'd3) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_3 <= 0; - else if (fifo_3_enable) - fifo_3 <= fifo_3_mux; - end - - - assign fifo_3_mux = (((fifowp == 4'd3) && itm_valid))? itm : - (((fifowp == 4'd3) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd3) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd3) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd3) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd3) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_4_enable = ((fifowp == 4'd4) && tm_count_ge1) || (free2 && (fifowp1== 4'd4) && tm_count_ge2) ||(free3 && (fifowp2== 4'd4) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_4 <= 0; - else if (fifo_4_enable) - fifo_4 <= fifo_4_mux; - end - - - assign fifo_4_mux = (((fifowp == 4'd4) && itm_valid))? itm : - (((fifowp == 4'd4) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd4) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd4) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd4) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd4) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_5_enable = ((fifowp == 4'd5) && tm_count_ge1) || (free2 && (fifowp1== 4'd5) && tm_count_ge2) ||(free3 && (fifowp2== 4'd5) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_5 <= 0; - else if (fifo_5_enable) - fifo_5 <= fifo_5_mux; - end - - - assign fifo_5_mux = (((fifowp == 4'd5) && itm_valid))? itm : - (((fifowp == 4'd5) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd5) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd5) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd5) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd5) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_6_enable = ((fifowp == 4'd6) && tm_count_ge1) || (free2 && (fifowp1== 4'd6) && tm_count_ge2) ||(free3 && (fifowp2== 4'd6) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_6 <= 0; - else if (fifo_6_enable) - fifo_6 <= fifo_6_mux; - end - - - assign fifo_6_mux = (((fifowp == 4'd6) && itm_valid))? itm : - (((fifowp == 4'd6) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd6) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd6) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd6) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd6) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_7_enable = ((fifowp == 4'd7) && tm_count_ge1) || (free2 && (fifowp1== 4'd7) && tm_count_ge2) ||(free3 && (fifowp2== 4'd7) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_7 <= 0; - else if (fifo_7_enable) - fifo_7 <= fifo_7_mux; - end - - - assign fifo_7_mux = (((fifowp == 4'd7) && itm_valid))? itm : - (((fifowp == 4'd7) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd7) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd7) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd7) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd7) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_8_enable = ((fifowp == 4'd8) && tm_count_ge1) || (free2 && (fifowp1== 4'd8) && tm_count_ge2) ||(free3 && (fifowp2== 4'd8) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_8 <= 0; - else if (fifo_8_enable) - fifo_8 <= fifo_8_mux; - end - - - assign fifo_8_mux = (((fifowp == 4'd8) && itm_valid))? itm : - (((fifowp == 4'd8) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd8) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd8) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd8) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd8) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_9_enable = ((fifowp == 4'd9) && tm_count_ge1) || (free2 && (fifowp1== 4'd9) && tm_count_ge2) ||(free3 && (fifowp2== 4'd9) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_9 <= 0; - else if (fifo_9_enable) - fifo_9 <= fifo_9_mux; - end - - - assign fifo_9_mux = (((fifowp == 4'd9) && itm_valid))? itm : - (((fifowp == 4'd9) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd9) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd9) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd9) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd9) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_10_enable = ((fifowp == 4'd10) && tm_count_ge1) || (free2 && (fifowp1== 4'd10) && tm_count_ge2) ||(free3 && (fifowp2== 4'd10) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_10 <= 0; - else if (fifo_10_enable) - fifo_10 <= fifo_10_mux; - end - - - assign fifo_10_mux = (((fifowp == 4'd10) && itm_valid))? itm : - (((fifowp == 4'd10) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd10) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd10) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd10) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd10) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_11_enable = ((fifowp == 4'd11) && tm_count_ge1) || (free2 && (fifowp1== 4'd11) && tm_count_ge2) ||(free3 && (fifowp2== 4'd11) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_11 <= 0; - else if (fifo_11_enable) - fifo_11 <= fifo_11_mux; - end - - - assign fifo_11_mux = (((fifowp == 4'd11) && itm_valid))? itm : - (((fifowp == 4'd11) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd11) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd11) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd11) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd11) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_12_enable = ((fifowp == 4'd12) && tm_count_ge1) || (free2 && (fifowp1== 4'd12) && tm_count_ge2) ||(free3 && (fifowp2== 4'd12) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_12 <= 0; - else if (fifo_12_enable) - fifo_12 <= fifo_12_mux; - end - - - assign fifo_12_mux = (((fifowp == 4'd12) && itm_valid))? itm : - (((fifowp == 4'd12) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd12) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd12) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd12) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd12) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_13_enable = ((fifowp == 4'd13) && tm_count_ge1) || (free2 && (fifowp1== 4'd13) && tm_count_ge2) ||(free3 && (fifowp2== 4'd13) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_13 <= 0; - else if (fifo_13_enable) - fifo_13 <= fifo_13_mux; - end - - - assign fifo_13_mux = (((fifowp == 4'd13) && itm_valid))? itm : - (((fifowp == 4'd13) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd13) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd13) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd13) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd13) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_14_enable = ((fifowp == 4'd14) && tm_count_ge1) || (free2 && (fifowp1== 4'd14) && tm_count_ge2) ||(free3 && (fifowp2== 4'd14) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_14 <= 0; - else if (fifo_14_enable) - fifo_14 <= fifo_14_mux; - end - - - assign fifo_14_mux = (((fifowp == 4'd14) && itm_valid))? itm : - (((fifowp == 4'd14) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd14) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd14) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd14) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd14) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_15_enable = ((fifowp == 4'd15) && tm_count_ge1) || (free2 && (fifowp1== 4'd15) && tm_count_ge2) ||(free3 && (fifowp2== 4'd15) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_15 <= 0; - else if (fifo_15_enable) - fifo_15 <= fifo_15_mux; - end - - - assign fifo_15_mux = (((fifowp == 4'd15) && itm_valid))? itm : - (((fifowp == 4'd15) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd15) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd15) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd15) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd15) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign tm_count_ge1 = |tm_count; - assign tm_count_ge2 = tm_count[1]; - assign tm_count_ge3 = &tm_count; - assign ovr_pending_atm = {ovf_pending, atm[34 : 0]}; - assign ovr_pending_dtm = {ovf_pending, dtm[34 : 0]}; - assign fifo_read_mux = (fiforp == 4'd0)? fifo_0 : - (fiforp == 4'd1)? fifo_1 : - (fiforp == 4'd2)? fifo_2 : - (fiforp == 4'd3)? fifo_3 : - (fiforp == 4'd4)? fifo_4 : - (fiforp == 4'd5)? fifo_5 : - (fiforp == 4'd6)? fifo_6 : - (fiforp == 4'd7)? fifo_7 : - (fiforp == 4'd8)? fifo_8 : - (fiforp == 4'd9)? fifo_9 : - (fiforp == 4'd10)? fifo_10 : - (fiforp == 4'd11)? fifo_11 : - (fiforp == 4'd12)? fifo_12 : - (fiforp == 4'd13)? fifo_13 : - (fiforp == 4'd14)? fifo_14 : - fifo_15; - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_pib ( - // inputs: - clk, - clkx2, - jrst_n, - tw, - - // outputs: - tr_clk, - tr_data - ) -; - - output tr_clk; - output [ 17: 0] tr_data; - input clk; - input clkx2; - input jrst_n; - input [ 35: 0] tw; - - wire phase; - wire tr_clk; - reg tr_clk_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 17: 0] tr_data; - reg [ 17: 0] tr_data_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg x1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg x2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - assign phase = x1^x2; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - x1 <= 0; - else - x1 <= ~x1; - end - - - always @(posedge clkx2 or negedge jrst_n) - begin - if (jrst_n == 0) - begin - x2 <= 0; - tr_clk_reg <= 0; - tr_data_reg <= 0; - end - else - begin - x2 <= x1; - tr_clk_reg <= ~phase; - tr_data_reg <= phase ? tw[17 : 0] : tw[35 : 18]; - end - end - - - assign tr_clk = 0 ? tr_clk_reg : 0; - assign tr_data = 0 ? tr_data_reg : 0; - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_im ( - // inputs: - clk, - jdo, - jrst_n, - reset_n, - take_action_tracectrl, - take_action_tracemem_a, - take_action_tracemem_b, - take_no_action_tracemem_a, - trc_ctrl, - tw, - - // outputs: - tracemem_on, - tracemem_trcdata, - tracemem_tw, - trc_enb, - trc_im_addr, - trc_wrap, - xbrk_wrap_traceoff - ) -; - - output tracemem_on; - output [ 35: 0] tracemem_trcdata; - output tracemem_tw; - output trc_enb; - output [ 6: 0] trc_im_addr; - output trc_wrap; - output xbrk_wrap_traceoff; - input clk; - input [ 37: 0] jdo; - input jrst_n; - input reset_n; - input take_action_tracectrl; - input take_action_tracemem_a; - input take_action_tracemem_b; - input take_no_action_tracemem_a; - input [ 15: 0] trc_ctrl; - input [ 35: 0] tw; - - wire tracemem_on; - wire [ 35: 0] tracemem_trcdata; - wire tracemem_tw; - wire trc_enb; - reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire [ 35: 0] trc_im_data; - reg [ 16: 0] trc_jtag_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; - wire trc_on_chip; - reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire tw_valid; - wire xbrk_wrap_traceoff; - assign trc_im_data = tw; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - trc_im_addr <= 0; - trc_wrap <= 0; - end - else if (!0) - begin - trc_im_addr <= 0; - trc_wrap <= 0; - end - else if (take_action_tracectrl && - (jdo[4] | jdo[3])) - begin - if (jdo[4]) - trc_im_addr <= 0; - if (jdo[3]) - trc_wrap <= 0; - end - else if (trc_enb & trc_on_chip & tw_valid) - begin - trc_im_addr <= trc_im_addr+1; - if (&trc_im_addr) - trc_wrap <= 1; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - trc_jtag_addr <= 0; - else if (take_action_tracemem_a || - take_no_action_tracemem_a || - take_action_tracemem_b) - trc_jtag_addr <= take_action_tracemem_a ? - jdo[35 : 19] : - trc_jtag_addr + 1; - - end - - - assign trc_enb = trc_ctrl[0]; - assign trc_on_chip = ~trc_ctrl[8]; - assign tw_valid = |trc_im_data[35 : 32]; - assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap; - assign tracemem_tw = trc_wrap; - assign tracemem_on = trc_enb; - assign tracemem_trcdata = 0; - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_performance_monitors -; - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci ( - // inputs: - D_valid, - E_st_data, - E_valid, - F_pc, - address_nxt, - av_ld_data_aligned_filtered, - byteenable_nxt, - clk, - d_address, - d_read, - d_waitrequest, - d_write, - debugaccess_nxt, - hbreak_enabled, - read_nxt, - reset, - reset_n, - test_ending, - test_has_ended, - write_nxt, - writedata_nxt, - - // outputs: - jtag_debug_module_debugaccess_to_roms, - oci_hbreak_req, - oci_ienable, - oci_single_step_mode, - readdata, - resetrequest, - waitrequest - ) -; - - output jtag_debug_module_debugaccess_to_roms; - output oci_hbreak_req; - output [ 31: 0] oci_ienable; - output oci_single_step_mode; - output [ 31: 0] readdata; - output resetrequest; - output waitrequest; - input D_valid; - input [ 31: 0] E_st_data; - input E_valid; - input [ 16: 0] F_pc; - input [ 8: 0] address_nxt; - input [ 31: 0] av_ld_data_aligned_filtered; - input [ 3: 0] byteenable_nxt; - input clk; - input [ 18: 0] d_address; - input d_read; - input d_waitrequest; - input d_write; - input debugaccess_nxt; - input hbreak_enabled; - input read_nxt; - input reset; - input reset_n; - input test_ending; - input test_has_ended; - input write_nxt; - input [ 31: 0] writedata_nxt; - - wire [ 31: 0] MonDReg; - reg [ 8: 0] address; - wire [ 35: 0] atm; - wire [ 31: 0] break_readreg; - reg [ 3: 0] byteenable; - wire clkx2; - wire [ 18: 0] cpu_d_address; - wire cpu_d_read; - wire [ 31: 0] cpu_d_readdata; - wire cpu_d_wait; - wire cpu_d_write; - wire [ 31: 0] cpu_d_writedata; - wire dbrk_break; - wire dbrk_goto0; - wire dbrk_goto1; - wire dbrk_hit0_latch; - wire dbrk_hit1_latch; - wire dbrk_hit2_latch; - wire dbrk_hit3_latch; - wire dbrk_traceme; - wire dbrk_traceoff; - wire dbrk_traceon; - wire dbrk_trigout; - wire [ 29: 0] dct_buffer; - wire [ 3: 0] dct_count; - reg debugaccess; - wire debugack; - wire debugreq; - wire [ 35: 0] dtm; - wire dummy_sink; - wire [ 35: 0] itm; - wire [ 37: 0] jdo; - wire jrst_n; - wire jtag_debug_module_debugaccess_to_roms; - wire monitor_error; - wire monitor_go; - wire monitor_ready; - wire oci_hbreak_req; - wire [ 31: 0] oci_ienable; - wire [ 31: 0] oci_reg_readdata; - wire oci_single_step_mode; - wire [ 31: 0] ociram_readdata; - wire ocireg_ers; - wire ocireg_mrs; - reg read; - reg [ 31: 0] readdata; - wire resetlatch; - wire resetrequest; - wire st_ready_test_idle; - wire take_action_break_a; - wire take_action_break_b; - wire take_action_break_c; - wire take_action_ocimem_a; - wire take_action_ocimem_b; - wire take_action_ocireg; - wire take_action_tracectrl; - wire take_action_tracemem_a; - wire take_action_tracemem_b; - wire take_no_action_break_a; - wire take_no_action_break_b; - wire take_no_action_break_c; - wire take_no_action_ocimem_a; - wire take_no_action_tracemem_a; - wire tr_clk; - wire [ 17: 0] tr_data; - wire tracemem_on; - wire [ 35: 0] tracemem_trcdata; - wire tracemem_tw; - wire [ 15: 0] trc_ctrl; - wire trc_enb; - wire [ 6: 0] trc_im_addr; - wire trc_on; - wire trc_wrap; - wire trigbrktype; - wire trigger_state_0; - wire trigger_state_1; - wire trigout; - wire [ 35: 0] tw; - wire waitrequest; - reg write; - reg [ 31: 0] writedata; - wire xbrk_break; - wire [ 7: 0] xbrk_ctrl0; - wire [ 7: 0] xbrk_ctrl1; - wire [ 7: 0] xbrk_ctrl2; - wire [ 7: 0] xbrk_ctrl3; - wire xbrk_goto0; - wire xbrk_goto1; - wire xbrk_traceoff; - wire xbrk_traceon; - wire xbrk_trigout; - wire xbrk_wrap_traceoff; - nios_system_nios2_processor_nios2_oci_debug the_nios_system_nios2_processor_nios2_oci_debug - ( - .clk (clk), - .dbrk_break (dbrk_break), - .debugack (debugack), - .debugreq (debugreq), - .hbreak_enabled (hbreak_enabled), - .jdo (jdo), - .jrst_n (jrst_n), - .monitor_error (monitor_error), - .monitor_go (monitor_go), - .monitor_ready (monitor_ready), - .oci_hbreak_req (oci_hbreak_req), - .ocireg_ers (ocireg_ers), - .ocireg_mrs (ocireg_mrs), - .reset (reset), - .resetlatch (resetlatch), - .resetrequest (resetrequest), - .st_ready_test_idle (st_ready_test_idle), - .take_action_ocimem_a (take_action_ocimem_a), - .take_action_ocireg (take_action_ocireg), - .xbrk_break (xbrk_break) - ); - - nios_system_nios2_processor_nios2_ocimem the_nios_system_nios2_processor_nios2_ocimem - ( - .MonDReg (MonDReg), - .address (address), - .byteenable (byteenable), - .clk (clk), - .debugaccess (debugaccess), - .jdo (jdo), - .jrst_n (jrst_n), - .ociram_readdata (ociram_readdata), - .read (read), - .take_action_ocimem_a (take_action_ocimem_a), - .take_action_ocimem_b (take_action_ocimem_b), - .take_no_action_ocimem_a (take_no_action_ocimem_a), - .waitrequest (waitrequest), - .write (write), - .writedata (writedata) - ); - - nios_system_nios2_processor_nios2_avalon_reg the_nios_system_nios2_processor_nios2_avalon_reg - ( - .address (address), - .clk (clk), - .debugaccess (debugaccess), - .monitor_error (monitor_error), - .monitor_go (monitor_go), - .monitor_ready (monitor_ready), - .oci_ienable (oci_ienable), - .oci_reg_readdata (oci_reg_readdata), - .oci_single_step_mode (oci_single_step_mode), - .ocireg_ers (ocireg_ers), - .ocireg_mrs (ocireg_mrs), - .reset_n (reset_n), - .take_action_ocireg (take_action_ocireg), - .write (write), - .writedata (writedata) - ); - - nios_system_nios2_processor_nios2_oci_break the_nios_system_nios2_processor_nios2_oci_break - ( - .break_readreg (break_readreg), - .clk (clk), - .dbrk_break (dbrk_break), - .dbrk_goto0 (dbrk_goto0), - .dbrk_goto1 (dbrk_goto1), - .dbrk_hit0_latch (dbrk_hit0_latch), - .dbrk_hit1_latch (dbrk_hit1_latch), - .dbrk_hit2_latch (dbrk_hit2_latch), - .dbrk_hit3_latch (dbrk_hit3_latch), - .jdo (jdo), - .jrst_n (jrst_n), - .reset_n (reset_n), - .take_action_break_a (take_action_break_a), - .take_action_break_b (take_action_break_b), - .take_action_break_c (take_action_break_c), - .take_no_action_break_a (take_no_action_break_a), - .take_no_action_break_b (take_no_action_break_b), - .take_no_action_break_c (take_no_action_break_c), - .trigbrktype (trigbrktype), - .trigger_state_0 (trigger_state_0), - .trigger_state_1 (trigger_state_1), - .xbrk_ctrl0 (xbrk_ctrl0), - .xbrk_ctrl1 (xbrk_ctrl1), - .xbrk_ctrl2 (xbrk_ctrl2), - .xbrk_ctrl3 (xbrk_ctrl3), - .xbrk_goto0 (xbrk_goto0), - .xbrk_goto1 (xbrk_goto1) - ); - - nios_system_nios2_processor_nios2_oci_xbrk the_nios_system_nios2_processor_nios2_oci_xbrk - ( - .D_valid (D_valid), - .E_valid (E_valid), - .F_pc (F_pc), - .clk (clk), - .reset_n (reset_n), - .trigger_state_0 (trigger_state_0), - .trigger_state_1 (trigger_state_1), - .xbrk_break (xbrk_break), - .xbrk_ctrl0 (xbrk_ctrl0), - .xbrk_ctrl1 (xbrk_ctrl1), - .xbrk_ctrl2 (xbrk_ctrl2), - .xbrk_ctrl3 (xbrk_ctrl3), - .xbrk_goto0 (xbrk_goto0), - .xbrk_goto1 (xbrk_goto1), - .xbrk_traceoff (xbrk_traceoff), - .xbrk_traceon (xbrk_traceon), - .xbrk_trigout (xbrk_trigout) - ); - - nios_system_nios2_processor_nios2_oci_dbrk the_nios_system_nios2_processor_nios2_oci_dbrk - ( - .E_st_data (E_st_data), - .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), - .clk (clk), - .cpu_d_address (cpu_d_address), - .cpu_d_read (cpu_d_read), - .cpu_d_readdata (cpu_d_readdata), - .cpu_d_wait (cpu_d_wait), - .cpu_d_write (cpu_d_write), - .cpu_d_writedata (cpu_d_writedata), - .d_address (d_address), - .d_read (d_read), - .d_waitrequest (d_waitrequest), - .d_write (d_write), - .dbrk_break (dbrk_break), - .dbrk_goto0 (dbrk_goto0), - .dbrk_goto1 (dbrk_goto1), - .dbrk_traceme (dbrk_traceme), - .dbrk_traceoff (dbrk_traceoff), - .dbrk_traceon (dbrk_traceon), - .dbrk_trigout (dbrk_trigout), - .debugack (debugack), - .reset_n (reset_n) - ); - - nios_system_nios2_processor_nios2_oci_itrace the_nios_system_nios2_processor_nios2_oci_itrace - ( - .clk (clk), - .dbrk_traceoff (dbrk_traceoff), - .dbrk_traceon (dbrk_traceon), - .dct_buffer (dct_buffer), - .dct_count (dct_count), - .itm (itm), - .jdo (jdo), - .jrst_n (jrst_n), - .take_action_tracectrl (take_action_tracectrl), - .trc_ctrl (trc_ctrl), - .trc_enb (trc_enb), - .trc_on (trc_on), - .xbrk_traceoff (xbrk_traceoff), - .xbrk_traceon (xbrk_traceon), - .xbrk_wrap_traceoff (xbrk_wrap_traceoff) - ); - - nios_system_nios2_processor_nios2_oci_dtrace the_nios_system_nios2_processor_nios2_oci_dtrace - ( - .atm (atm), - .clk (clk), - .cpu_d_address (cpu_d_address), - .cpu_d_read (cpu_d_read), - .cpu_d_readdata (cpu_d_readdata), - .cpu_d_wait (cpu_d_wait), - .cpu_d_write (cpu_d_write), - .cpu_d_writedata (cpu_d_writedata), - .dtm (dtm), - .jrst_n (jrst_n), - .trc_ctrl (trc_ctrl) - ); - - nios_system_nios2_processor_nios2_oci_fifo the_nios_system_nios2_processor_nios2_oci_fifo - ( - .atm (atm), - .clk (clk), - .dbrk_traceme (dbrk_traceme), - .dbrk_traceoff (dbrk_traceoff), - .dbrk_traceon (dbrk_traceon), - .dct_buffer (dct_buffer), - .dct_count (dct_count), - .dtm (dtm), - .itm (itm), - .jrst_n (jrst_n), - .reset_n (reset_n), - .test_ending (test_ending), - .test_has_ended (test_has_ended), - .trc_on (trc_on), - .tw (tw) - ); - - nios_system_nios2_processor_nios2_oci_pib the_nios_system_nios2_processor_nios2_oci_pib - ( - .clk (clk), - .clkx2 (clkx2), - .jrst_n (jrst_n), - .tr_clk (tr_clk), - .tr_data (tr_data), - .tw (tw) - ); - - nios_system_nios2_processor_nios2_oci_im the_nios_system_nios2_processor_nios2_oci_im - ( - .clk (clk), - .jdo (jdo), - .jrst_n (jrst_n), - .reset_n (reset_n), - .take_action_tracectrl (take_action_tracectrl), - .take_action_tracemem_a (take_action_tracemem_a), - .take_action_tracemem_b (take_action_tracemem_b), - .take_no_action_tracemem_a (take_no_action_tracemem_a), - .tracemem_on (tracemem_on), - .tracemem_trcdata (tracemem_trcdata), - .tracemem_tw (tracemem_tw), - .trc_ctrl (trc_ctrl), - .trc_enb (trc_enb), - .trc_im_addr (trc_im_addr), - .trc_wrap (trc_wrap), - .tw (tw), - .xbrk_wrap_traceoff (xbrk_wrap_traceoff) - ); - - assign trigout = dbrk_trigout | xbrk_trigout; - assign jtag_debug_module_debugaccess_to_roms = debugack; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - address <= 0; - else - address <= address_nxt; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - byteenable <= 0; - else - byteenable <= byteenable_nxt; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - writedata <= 0; - else - writedata <= writedata_nxt; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - debugaccess <= 0; - else - debugaccess <= debugaccess_nxt; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - read <= 0; - else - read <= read ? waitrequest : read_nxt; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - write <= 0; - else - write <= write ? waitrequest : write_nxt; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - readdata <= 0; - else - readdata <= address[8] ? oci_reg_readdata : ociram_readdata; - end - - - nios_system_nios2_processor_jtag_debug_module_wrapper the_nios_system_nios2_processor_jtag_debug_module_wrapper - ( - .MonDReg (MonDReg), - .break_readreg (break_readreg), - .clk (clk), - .dbrk_hit0_latch (dbrk_hit0_latch), - .dbrk_hit1_latch (dbrk_hit1_latch), - .dbrk_hit2_latch (dbrk_hit2_latch), - .dbrk_hit3_latch (dbrk_hit3_latch), - .debugack (debugack), - .jdo (jdo), - .jrst_n (jrst_n), - .monitor_error (monitor_error), - .monitor_ready (monitor_ready), - .reset_n (reset_n), - .resetlatch (resetlatch), - .st_ready_test_idle (st_ready_test_idle), - .take_action_break_a (take_action_break_a), - .take_action_break_b (take_action_break_b), - .take_action_break_c (take_action_break_c), - .take_action_ocimem_a (take_action_ocimem_a), - .take_action_ocimem_b (take_action_ocimem_b), - .take_action_tracectrl (take_action_tracectrl), - .take_action_tracemem_a (take_action_tracemem_a), - .take_action_tracemem_b (take_action_tracemem_b), - .take_no_action_break_a (take_no_action_break_a), - .take_no_action_break_b (take_no_action_break_b), - .take_no_action_break_c (take_no_action_break_c), - .take_no_action_ocimem_a (take_no_action_ocimem_a), - .take_no_action_tracemem_a (take_no_action_tracemem_a), - .tracemem_on (tracemem_on), - .tracemem_trcdata (tracemem_trcdata), - .tracemem_tw (tracemem_tw), - .trc_im_addr (trc_im_addr), - .trc_on (trc_on), - .trc_wrap (trc_wrap), - .trigbrktype (trigbrktype), - .trigger_state_1 (trigger_state_1) - ); - - //dummy sink, which is an e_mux - assign dummy_sink = tr_clk | - tr_data | - trigout | - debugack; - - assign debugreq = 0; - assign clkx2 = 0; - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor ( - // inputs: - clk, - d_irq, - d_readdata, - d_waitrequest, - i_readdata, - i_waitrequest, - jtag_debug_module_address, - jtag_debug_module_byteenable, - jtag_debug_module_debugaccess, - jtag_debug_module_read, - jtag_debug_module_write, - jtag_debug_module_writedata, - reset_n, - - // outputs: - d_address, - d_byteenable, - d_read, - d_write, - d_writedata, - i_address, - i_read, - jtag_debug_module_debugaccess_to_roms, - jtag_debug_module_readdata, - jtag_debug_module_resetrequest, - jtag_debug_module_waitrequest, - no_ci_readra - ) -; - - output [ 18: 0] d_address; - output [ 3: 0] d_byteenable; - output d_read; - output d_write; - output [ 31: 0] d_writedata; - output [ 18: 0] i_address; - output i_read; - output jtag_debug_module_debugaccess_to_roms; - output [ 31: 0] jtag_debug_module_readdata; - output jtag_debug_module_resetrequest; - output jtag_debug_module_waitrequest; - output no_ci_readra; - input clk; - input [ 31: 0] d_irq; - input [ 31: 0] d_readdata; - input d_waitrequest; - input [ 31: 0] i_readdata; - input i_waitrequest; - input [ 8: 0] jtag_debug_module_address; - input [ 3: 0] jtag_debug_module_byteenable; - input jtag_debug_module_debugaccess; - input jtag_debug_module_read; - input jtag_debug_module_write; - input [ 31: 0] jtag_debug_module_writedata; - input reset_n; - - wire [ 1: 0] D_compare_op; - wire D_ctrl_alu_force_xor; - wire D_ctrl_alu_signed_comparison; - wire D_ctrl_alu_subtract; - wire D_ctrl_b_is_dst; - wire D_ctrl_br; - wire D_ctrl_br_cmp; - wire D_ctrl_br_uncond; - wire D_ctrl_break; - wire D_ctrl_crst; - wire D_ctrl_custom; - wire D_ctrl_custom_multi; - wire D_ctrl_exception; - wire D_ctrl_force_src2_zero; - wire D_ctrl_hi_imm16; - wire D_ctrl_ignore_dst; - wire D_ctrl_implicit_dst_eretaddr; - wire D_ctrl_implicit_dst_retaddr; - wire D_ctrl_jmp_direct; - wire D_ctrl_jmp_indirect; - wire D_ctrl_ld; - wire D_ctrl_ld_io; - wire D_ctrl_ld_non_io; - wire D_ctrl_ld_signed; - wire D_ctrl_logic; - wire D_ctrl_rdctl_inst; - wire D_ctrl_retaddr; - wire D_ctrl_rot_right; - wire D_ctrl_shift_logical; - wire D_ctrl_shift_right_arith; - wire D_ctrl_shift_rot; - wire D_ctrl_shift_rot_right; - wire D_ctrl_src2_choose_imm; - wire D_ctrl_st; - wire D_ctrl_uncond_cti_non_br; - wire D_ctrl_unsigned_lo_imm16; - wire D_ctrl_wrctl_inst; - wire [ 4: 0] D_dst_regnum; - wire [ 55: 0] D_inst; - reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; - wire [ 4: 0] D_iw_a; - wire [ 4: 0] D_iw_b; - wire [ 4: 0] D_iw_c; - wire [ 2: 0] D_iw_control_regnum; - wire [ 7: 0] D_iw_custom_n; - wire D_iw_custom_readra; - wire D_iw_custom_readrb; - wire D_iw_custom_writerc; - wire [ 15: 0] D_iw_imm16; - wire [ 25: 0] D_iw_imm26; - wire [ 4: 0] D_iw_imm5; - wire [ 1: 0] D_iw_memsz; - wire [ 5: 0] D_iw_op; - wire [ 5: 0] D_iw_opx; - wire [ 4: 0] D_iw_shift_imm5; - wire [ 4: 0] D_iw_trap_break_imm5; - wire [ 16: 0] D_jmp_direct_target_waddr; - wire [ 1: 0] D_logic_op; - wire [ 1: 0] D_logic_op_raw; - wire D_mem16; - wire D_mem32; - wire D_mem8; - wire D_op_add; - wire D_op_addi; - wire D_op_and; - wire D_op_andhi; - wire D_op_andi; - wire D_op_beq; - wire D_op_bge; - wire D_op_bgeu; - wire D_op_blt; - wire D_op_bltu; - wire D_op_bne; - wire D_op_br; - wire D_op_break; - wire D_op_bret; - wire D_op_call; - wire D_op_callr; - wire D_op_cmpeq; - wire D_op_cmpeqi; - wire D_op_cmpge; - wire D_op_cmpgei; - wire D_op_cmpgeu; - wire D_op_cmpgeui; - wire D_op_cmplt; - wire D_op_cmplti; - wire D_op_cmpltu; - wire D_op_cmpltui; - wire D_op_cmpne; - wire D_op_cmpnei; - wire D_op_crst; - wire D_op_custom; - wire D_op_div; - wire D_op_divu; - wire D_op_eret; - wire D_op_flushd; - wire D_op_flushda; - wire D_op_flushi; - wire D_op_flushp; - wire D_op_hbreak; - wire D_op_initd; - wire D_op_initda; - wire D_op_initi; - wire D_op_intr; - wire D_op_jmp; - wire D_op_jmpi; - wire D_op_ldb; - wire D_op_ldbio; - wire D_op_ldbu; - wire D_op_ldbuio; - wire D_op_ldh; - wire D_op_ldhio; - wire D_op_ldhu; - wire D_op_ldhuio; - wire D_op_ldl; - wire D_op_ldw; - wire D_op_ldwio; - wire D_op_mul; - wire D_op_muli; - wire D_op_mulxss; - wire D_op_mulxsu; - wire D_op_mulxuu; - wire D_op_nextpc; - wire D_op_nor; - wire D_op_opx; - wire D_op_or; - wire D_op_orhi; - wire D_op_ori; - wire D_op_rdctl; - wire D_op_rdprs; - wire D_op_ret; - wire D_op_rol; - wire D_op_roli; - wire D_op_ror; - wire D_op_rsv02; - wire D_op_rsv09; - wire D_op_rsv10; - wire D_op_rsv17; - wire D_op_rsv18; - wire D_op_rsv25; - wire D_op_rsv26; - wire D_op_rsv33; - wire D_op_rsv34; - wire D_op_rsv41; - wire D_op_rsv42; - wire D_op_rsv49; - wire D_op_rsv57; - wire D_op_rsv61; - wire D_op_rsv62; - wire D_op_rsv63; - wire D_op_rsvx00; - wire D_op_rsvx10; - wire D_op_rsvx15; - wire D_op_rsvx17; - wire D_op_rsvx21; - wire D_op_rsvx25; - wire D_op_rsvx33; - wire D_op_rsvx34; - wire D_op_rsvx35; - wire D_op_rsvx42; - wire D_op_rsvx43; - wire D_op_rsvx44; - wire D_op_rsvx47; - wire D_op_rsvx50; - wire D_op_rsvx51; - wire D_op_rsvx55; - wire D_op_rsvx56; - wire D_op_rsvx60; - wire D_op_rsvx63; - wire D_op_sll; - wire D_op_slli; - wire D_op_sra; - wire D_op_srai; - wire D_op_srl; - wire D_op_srli; - wire D_op_stb; - wire D_op_stbio; - wire D_op_stc; - wire D_op_sth; - wire D_op_sthio; - wire D_op_stw; - wire D_op_stwio; - wire D_op_sub; - wire D_op_sync; - wire D_op_trap; - wire D_op_wrctl; - wire D_op_wrprs; - wire D_op_xor; - wire D_op_xorhi; - wire D_op_xori; - reg D_valid; - wire [ 55: 0] D_vinst; - wire D_wr_dst_reg; - wire [ 31: 0] E_alu_result; - reg E_alu_sub; - wire [ 32: 0] E_arith_result; - wire [ 31: 0] E_arith_src1; - wire [ 31: 0] E_arith_src2; - wire E_ci_multi_stall; - wire [ 31: 0] E_ci_result; - wire E_cmp_result; - wire [ 31: 0] E_control_rd_data; - wire E_eq; - reg E_invert_arith_src_msb; - wire E_ld_stall; - wire [ 31: 0] E_logic_result; - wire E_logic_result_is_0; - wire E_lt; - wire [ 18: 0] E_mem_baddr; - wire [ 3: 0] E_mem_byte_en; - reg E_new_inst; - reg [ 4: 0] E_shift_rot_cnt; - wire [ 4: 0] E_shift_rot_cnt_nxt; - wire E_shift_rot_done; - wire E_shift_rot_fill_bit; - reg [ 31: 0] E_shift_rot_result; - wire [ 31: 0] E_shift_rot_result_nxt; - wire E_shift_rot_stall; - reg [ 31: 0] E_src1; - reg [ 31: 0] E_src2; - wire [ 31: 0] E_st_data; - wire E_st_stall; - wire E_stall; - reg E_valid; - wire [ 55: 0] E_vinst; - wire E_wrctl_bstatus; - wire E_wrctl_estatus; - wire E_wrctl_ienable; - wire E_wrctl_status; - wire [ 31: 0] F_av_iw; - wire [ 4: 0] F_av_iw_a; - wire [ 4: 0] F_av_iw_b; - wire [ 4: 0] F_av_iw_c; - wire [ 2: 0] F_av_iw_control_regnum; - wire [ 7: 0] F_av_iw_custom_n; - wire F_av_iw_custom_readra; - wire F_av_iw_custom_readrb; - wire F_av_iw_custom_writerc; - wire [ 15: 0] F_av_iw_imm16; - wire [ 25: 0] F_av_iw_imm26; - wire [ 4: 0] F_av_iw_imm5; - wire [ 1: 0] F_av_iw_memsz; - wire [ 5: 0] F_av_iw_op; - wire [ 5: 0] F_av_iw_opx; - wire [ 4: 0] F_av_iw_shift_imm5; - wire [ 4: 0] F_av_iw_trap_break_imm5; - wire F_av_mem16; - wire F_av_mem32; - wire F_av_mem8; - wire [ 55: 0] F_inst; - wire [ 31: 0] F_iw; - wire [ 4: 0] F_iw_a; - wire [ 4: 0] F_iw_b; - wire [ 4: 0] F_iw_c; - wire [ 2: 0] F_iw_control_regnum; - wire [ 7: 0] F_iw_custom_n; - wire F_iw_custom_readra; - wire F_iw_custom_readrb; - wire F_iw_custom_writerc; - wire [ 15: 0] F_iw_imm16; - wire [ 25: 0] F_iw_imm26; - wire [ 4: 0] F_iw_imm5; - wire [ 1: 0] F_iw_memsz; - wire [ 5: 0] F_iw_op; - wire [ 5: 0] F_iw_opx; - wire [ 4: 0] F_iw_shift_imm5; - wire [ 4: 0] F_iw_trap_break_imm5; - wire F_mem16; - wire F_mem32; - wire F_mem8; - wire F_op_add; - wire F_op_addi; - wire F_op_and; - wire F_op_andhi; - wire F_op_andi; - wire F_op_beq; - wire F_op_bge; - wire F_op_bgeu; - wire F_op_blt; - wire F_op_bltu; - wire F_op_bne; - wire F_op_br; - wire F_op_break; - wire F_op_bret; - wire F_op_call; - wire F_op_callr; - wire F_op_cmpeq; - wire F_op_cmpeqi; - wire F_op_cmpge; - wire F_op_cmpgei; - wire F_op_cmpgeu; - wire F_op_cmpgeui; - wire F_op_cmplt; - wire F_op_cmplti; - wire F_op_cmpltu; - wire F_op_cmpltui; - wire F_op_cmpne; - wire F_op_cmpnei; - wire F_op_crst; - wire F_op_custom; - wire F_op_div; - wire F_op_divu; - wire F_op_eret; - wire F_op_flushd; - wire F_op_flushda; - wire F_op_flushi; - wire F_op_flushp; - wire F_op_hbreak; - wire F_op_initd; - wire F_op_initda; - wire F_op_initi; - wire F_op_intr; - wire F_op_jmp; - wire F_op_jmpi; - wire F_op_ldb; - wire F_op_ldbio; - wire F_op_ldbu; - wire F_op_ldbuio; - wire F_op_ldh; - wire F_op_ldhio; - wire F_op_ldhu; - wire F_op_ldhuio; - wire F_op_ldl; - wire F_op_ldw; - wire F_op_ldwio; - wire F_op_mul; - wire F_op_muli; - wire F_op_mulxss; - wire F_op_mulxsu; - wire F_op_mulxuu; - wire F_op_nextpc; - wire F_op_nor; - wire F_op_opx; - wire F_op_or; - wire F_op_orhi; - wire F_op_ori; - wire F_op_rdctl; - wire F_op_rdprs; - wire F_op_ret; - wire F_op_rol; - wire F_op_roli; - wire F_op_ror; - wire F_op_rsv02; - wire F_op_rsv09; - wire F_op_rsv10; - wire F_op_rsv17; - wire F_op_rsv18; - wire F_op_rsv25; - wire F_op_rsv26; - wire F_op_rsv33; - wire F_op_rsv34; - wire F_op_rsv41; - wire F_op_rsv42; - wire F_op_rsv49; - wire F_op_rsv57; - wire F_op_rsv61; - wire F_op_rsv62; - wire F_op_rsv63; - wire F_op_rsvx00; - wire F_op_rsvx10; - wire F_op_rsvx15; - wire F_op_rsvx17; - wire F_op_rsvx21; - wire F_op_rsvx25; - wire F_op_rsvx33; - wire F_op_rsvx34; - wire F_op_rsvx35; - wire F_op_rsvx42; - wire F_op_rsvx43; - wire F_op_rsvx44; - wire F_op_rsvx47; - wire F_op_rsvx50; - wire F_op_rsvx51; - wire F_op_rsvx55; - wire F_op_rsvx56; - wire F_op_rsvx60; - wire F_op_rsvx63; - wire F_op_sll; - wire F_op_slli; - wire F_op_sra; - wire F_op_srai; - wire F_op_srl; - wire F_op_srli; - wire F_op_stb; - wire F_op_stbio; - wire F_op_stc; - wire F_op_sth; - wire F_op_sthio; - wire F_op_stw; - wire F_op_stwio; - wire F_op_sub; - wire F_op_sync; - wire F_op_trap; - wire F_op_wrctl; - wire F_op_wrprs; - wire F_op_xor; - wire F_op_xorhi; - wire F_op_xori; - reg [ 16: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; - wire F_pc_en; - wire [ 16: 0] F_pc_no_crst_nxt; - wire [ 16: 0] F_pc_nxt; - wire [ 16: 0] F_pc_plus_one; - wire [ 1: 0] F_pc_sel_nxt; - wire [ 18: 0] F_pcb; - wire [ 18: 0] F_pcb_nxt; - wire [ 18: 0] F_pcb_plus_four; - wire F_valid; - wire [ 55: 0] F_vinst; - reg [ 1: 0] R_compare_op; - reg R_ctrl_alu_force_xor; - wire R_ctrl_alu_force_xor_nxt; - reg R_ctrl_alu_signed_comparison; - wire R_ctrl_alu_signed_comparison_nxt; - reg R_ctrl_alu_subtract; - wire R_ctrl_alu_subtract_nxt; - reg R_ctrl_b_is_dst; - wire R_ctrl_b_is_dst_nxt; - reg R_ctrl_br; - reg R_ctrl_br_cmp; - wire R_ctrl_br_cmp_nxt; - wire R_ctrl_br_nxt; - reg R_ctrl_br_uncond; - wire R_ctrl_br_uncond_nxt; - reg R_ctrl_break; - wire R_ctrl_break_nxt; - reg R_ctrl_crst; - wire R_ctrl_crst_nxt; - reg R_ctrl_custom; - reg R_ctrl_custom_multi; - wire R_ctrl_custom_multi_nxt; - wire R_ctrl_custom_nxt; - reg R_ctrl_exception; - wire R_ctrl_exception_nxt; - reg R_ctrl_force_src2_zero; - wire R_ctrl_force_src2_zero_nxt; - reg R_ctrl_hi_imm16; - wire R_ctrl_hi_imm16_nxt; - reg R_ctrl_ignore_dst; - wire R_ctrl_ignore_dst_nxt; - reg R_ctrl_implicit_dst_eretaddr; - wire R_ctrl_implicit_dst_eretaddr_nxt; - reg R_ctrl_implicit_dst_retaddr; - wire R_ctrl_implicit_dst_retaddr_nxt; - reg R_ctrl_jmp_direct; - wire R_ctrl_jmp_direct_nxt; - reg R_ctrl_jmp_indirect; - wire R_ctrl_jmp_indirect_nxt; - reg R_ctrl_ld; - reg R_ctrl_ld_io; - wire R_ctrl_ld_io_nxt; - reg R_ctrl_ld_non_io; - wire R_ctrl_ld_non_io_nxt; - wire R_ctrl_ld_nxt; - reg R_ctrl_ld_signed; - wire R_ctrl_ld_signed_nxt; - reg R_ctrl_logic; - wire R_ctrl_logic_nxt; - reg R_ctrl_rdctl_inst; - wire R_ctrl_rdctl_inst_nxt; - reg R_ctrl_retaddr; - wire R_ctrl_retaddr_nxt; - reg R_ctrl_rot_right; - wire R_ctrl_rot_right_nxt; - reg R_ctrl_shift_logical; - wire R_ctrl_shift_logical_nxt; - reg R_ctrl_shift_right_arith; - wire R_ctrl_shift_right_arith_nxt; - reg R_ctrl_shift_rot; - wire R_ctrl_shift_rot_nxt; - reg R_ctrl_shift_rot_right; - wire R_ctrl_shift_rot_right_nxt; - reg R_ctrl_src2_choose_imm; - wire R_ctrl_src2_choose_imm_nxt; - reg R_ctrl_st; - wire R_ctrl_st_nxt; - reg R_ctrl_uncond_cti_non_br; - wire R_ctrl_uncond_cti_non_br_nxt; - reg R_ctrl_unsigned_lo_imm16; - wire R_ctrl_unsigned_lo_imm16_nxt; - reg R_ctrl_wrctl_inst; - wire R_ctrl_wrctl_inst_nxt; - reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; - wire R_en; - reg [ 1: 0] R_logic_op; - wire [ 31: 0] R_rf_a; - wire [ 31: 0] R_rf_b; - wire [ 31: 0] R_src1; - wire [ 31: 0] R_src2; - wire [ 15: 0] R_src2_hi; - wire [ 15: 0] R_src2_lo; - reg R_src2_use_imm; - wire [ 7: 0] R_stb_data; - wire [ 15: 0] R_sth_data; - reg R_valid; - wire [ 55: 0] R_vinst; - reg R_wr_dst_reg; - reg [ 31: 0] W_alu_result; - wire W_br_taken; - reg W_bstatus_reg; - wire W_bstatus_reg_inst_nxt; - wire W_bstatus_reg_nxt; - reg W_cmp_result; - reg [ 31: 0] W_control_rd_data; - reg W_estatus_reg; - wire W_estatus_reg_inst_nxt; - wire W_estatus_reg_nxt; - reg [ 31: 0] W_ienable_reg; - wire [ 31: 0] W_ienable_reg_nxt; - reg [ 31: 0] W_ipending_reg; - wire [ 31: 0] W_ipending_reg_nxt; - wire [ 18: 0] W_mem_baddr; - wire [ 31: 0] W_rf_wr_data; - wire W_rf_wren; - wire W_status_reg; - reg W_status_reg_pie; - wire W_status_reg_pie_inst_nxt; - wire W_status_reg_pie_nxt; - reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; - wire [ 55: 0] W_vinst; - wire [ 31: 0] W_wr_data; - wire [ 31: 0] W_wr_data_non_zero; - wire av_fill_bit; - reg [ 1: 0] av_ld_align_cycle; - wire [ 1: 0] av_ld_align_cycle_nxt; - wire av_ld_align_one_more_cycle; - reg av_ld_aligning_data; - wire av_ld_aligning_data_nxt; - reg [ 7: 0] av_ld_byte0_data; - wire [ 7: 0] av_ld_byte0_data_nxt; - reg [ 7: 0] av_ld_byte1_data; - wire av_ld_byte1_data_en; - wire [ 7: 0] av_ld_byte1_data_nxt; - reg [ 7: 0] av_ld_byte2_data; - wire [ 7: 0] av_ld_byte2_data_nxt; - reg [ 7: 0] av_ld_byte3_data; - wire [ 7: 0] av_ld_byte3_data_nxt; - wire [ 31: 0] av_ld_data_aligned_filtered; - wire [ 31: 0] av_ld_data_aligned_unfiltered; - wire av_ld_done; - wire av_ld_extend; - wire av_ld_getting_data; - wire av_ld_rshift8; - reg av_ld_waiting_for_data; - wire av_ld_waiting_for_data_nxt; - wire av_sign_bit; - wire [ 18: 0] d_address; - reg [ 3: 0] d_byteenable; - reg d_read; - wire d_read_nxt; - wire d_write; - wire d_write_nxt; - reg [ 31: 0] d_writedata; - reg hbreak_enabled; - reg hbreak_pending; - wire hbreak_pending_nxt; - wire hbreak_req; - wire [ 18: 0] i_address; - reg i_read; - wire i_read_nxt; - wire [ 31: 0] iactive; - wire intr_req; - wire jtag_debug_module_clk; - wire jtag_debug_module_debugaccess_to_roms; - wire [ 31: 0] jtag_debug_module_readdata; - wire jtag_debug_module_reset; - wire jtag_debug_module_resetrequest; - wire jtag_debug_module_waitrequest; - wire no_ci_readra; - wire oci_hbreak_req; - wire [ 31: 0] oci_ienable; - wire oci_single_step_mode; - wire oci_tb_hbreak_req; - wire test_ending; - wire test_has_ended; - reg wait_for_one_post_bret_inst; - //the_nios_system_nios2_processor_test_bench, which is an e_instance - nios_system_nios2_processor_test_bench the_nios_system_nios2_processor_test_bench - ( - .D_iw (D_iw), - .D_iw_op (D_iw_op), - .D_iw_opx (D_iw_opx), - .D_valid (D_valid), - .E_valid (E_valid), - .F_pcb (F_pcb), - .F_valid (F_valid), - .R_ctrl_ld (R_ctrl_ld), - .R_ctrl_ld_non_io (R_ctrl_ld_non_io), - .R_dst_regnum (R_dst_regnum), - .R_wr_dst_reg (R_wr_dst_reg), - .W_valid (W_valid), - .W_vinst (W_vinst), - .W_wr_data (W_wr_data), - .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), - .av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered), - .clk (clk), - .d_address (d_address), - .d_byteenable (d_byteenable), - .d_read (d_read), - .d_write (d_write), - .d_write_nxt (d_write_nxt), - .i_address (i_address), - .i_read (i_read), - .i_readdata (i_readdata), - .i_waitrequest (i_waitrequest), - .reset_n (reset_n), - .test_has_ended (test_has_ended) - ); - - assign F_av_iw_a = F_av_iw[31 : 27]; - assign F_av_iw_b = F_av_iw[26 : 22]; - assign F_av_iw_c = F_av_iw[21 : 17]; - assign F_av_iw_custom_n = F_av_iw[13 : 6]; - assign F_av_iw_custom_readra = F_av_iw[16]; - assign F_av_iw_custom_readrb = F_av_iw[15]; - assign F_av_iw_custom_writerc = F_av_iw[14]; - assign F_av_iw_opx = F_av_iw[16 : 11]; - assign F_av_iw_op = F_av_iw[5 : 0]; - assign F_av_iw_shift_imm5 = F_av_iw[10 : 6]; - assign F_av_iw_trap_break_imm5 = F_av_iw[10 : 6]; - assign F_av_iw_imm5 = F_av_iw[10 : 6]; - assign F_av_iw_imm16 = F_av_iw[21 : 6]; - assign F_av_iw_imm26 = F_av_iw[31 : 6]; - assign F_av_iw_memsz = F_av_iw[4 : 3]; - assign F_av_iw_control_regnum = F_av_iw[8 : 6]; - assign F_av_mem8 = F_av_iw_memsz == 2'b00; - assign F_av_mem16 = F_av_iw_memsz == 2'b01; - assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1; - assign F_iw_a = F_iw[31 : 27]; - assign F_iw_b = F_iw[26 : 22]; - assign F_iw_c = F_iw[21 : 17]; - assign F_iw_custom_n = F_iw[13 : 6]; - assign F_iw_custom_readra = F_iw[16]; - assign F_iw_custom_readrb = F_iw[15]; - assign F_iw_custom_writerc = F_iw[14]; - assign F_iw_opx = F_iw[16 : 11]; - assign F_iw_op = F_iw[5 : 0]; - assign F_iw_shift_imm5 = F_iw[10 : 6]; - assign F_iw_trap_break_imm5 = F_iw[10 : 6]; - assign F_iw_imm5 = F_iw[10 : 6]; - assign F_iw_imm16 = F_iw[21 : 6]; - assign F_iw_imm26 = F_iw[31 : 6]; - assign F_iw_memsz = F_iw[4 : 3]; - assign F_iw_control_regnum = F_iw[8 : 6]; - assign F_mem8 = F_iw_memsz == 2'b00; - assign F_mem16 = F_iw_memsz == 2'b01; - assign F_mem32 = F_iw_memsz[1] == 1'b1; - assign D_iw_a = D_iw[31 : 27]; - assign D_iw_b = D_iw[26 : 22]; - assign D_iw_c = D_iw[21 : 17]; - assign D_iw_custom_n = D_iw[13 : 6]; - assign D_iw_custom_readra = D_iw[16]; - assign D_iw_custom_readrb = D_iw[15]; - assign D_iw_custom_writerc = D_iw[14]; - assign D_iw_opx = D_iw[16 : 11]; - assign D_iw_op = D_iw[5 : 0]; - assign D_iw_shift_imm5 = D_iw[10 : 6]; - assign D_iw_trap_break_imm5 = D_iw[10 : 6]; - assign D_iw_imm5 = D_iw[10 : 6]; - assign D_iw_imm16 = D_iw[21 : 6]; - assign D_iw_imm26 = D_iw[31 : 6]; - assign D_iw_memsz = D_iw[4 : 3]; - assign D_iw_control_regnum = D_iw[8 : 6]; - assign D_mem8 = D_iw_memsz == 2'b00; - assign D_mem16 = D_iw_memsz == 2'b01; - assign D_mem32 = D_iw_memsz[1] == 1'b1; - assign F_op_call = F_iw_op == 0; - assign F_op_jmpi = F_iw_op == 1; - assign F_op_ldbu = F_iw_op == 3; - assign F_op_addi = F_iw_op == 4; - assign F_op_stb = F_iw_op == 5; - assign F_op_br = F_iw_op == 6; - assign F_op_ldb = F_iw_op == 7; - assign F_op_cmpgei = F_iw_op == 8; - assign F_op_ldhu = F_iw_op == 11; - assign F_op_andi = F_iw_op == 12; - assign F_op_sth = F_iw_op == 13; - assign F_op_bge = F_iw_op == 14; - assign F_op_ldh = F_iw_op == 15; - assign F_op_cmplti = F_iw_op == 16; - assign F_op_initda = F_iw_op == 19; - assign F_op_ori = F_iw_op == 20; - assign F_op_stw = F_iw_op == 21; - assign F_op_blt = F_iw_op == 22; - assign F_op_ldw = F_iw_op == 23; - assign F_op_cmpnei = F_iw_op == 24; - assign F_op_flushda = F_iw_op == 27; - assign F_op_xori = F_iw_op == 28; - assign F_op_stc = F_iw_op == 29; - assign F_op_bne = F_iw_op == 30; - assign F_op_ldl = F_iw_op == 31; - assign F_op_cmpeqi = F_iw_op == 32; - assign F_op_ldbuio = F_iw_op == 35; - assign F_op_muli = F_iw_op == 36; - assign F_op_stbio = F_iw_op == 37; - assign F_op_beq = F_iw_op == 38; - assign F_op_ldbio = F_iw_op == 39; - assign F_op_cmpgeui = F_iw_op == 40; - assign F_op_ldhuio = F_iw_op == 43; - assign F_op_andhi = F_iw_op == 44; - assign F_op_sthio = F_iw_op == 45; - assign F_op_bgeu = F_iw_op == 46; - assign F_op_ldhio = F_iw_op == 47; - assign F_op_cmpltui = F_iw_op == 48; - assign F_op_initd = F_iw_op == 51; - assign F_op_orhi = F_iw_op == 52; - assign F_op_stwio = F_iw_op == 53; - assign F_op_bltu = F_iw_op == 54; - assign F_op_ldwio = F_iw_op == 55; - assign F_op_rdprs = F_iw_op == 56; - assign F_op_flushd = F_iw_op == 59; - assign F_op_xorhi = F_iw_op == 60; - assign F_op_rsv02 = F_iw_op == 2; - assign F_op_rsv09 = F_iw_op == 9; - assign F_op_rsv10 = F_iw_op == 10; - assign F_op_rsv17 = F_iw_op == 17; - assign F_op_rsv18 = F_iw_op == 18; - assign F_op_rsv25 = F_iw_op == 25; - assign F_op_rsv26 = F_iw_op == 26; - assign F_op_rsv33 = F_iw_op == 33; - assign F_op_rsv34 = F_iw_op == 34; - assign F_op_rsv41 = F_iw_op == 41; - assign F_op_rsv42 = F_iw_op == 42; - assign F_op_rsv49 = F_iw_op == 49; - assign F_op_rsv57 = F_iw_op == 57; - assign F_op_rsv61 = F_iw_op == 61; - assign F_op_rsv62 = F_iw_op == 62; - assign F_op_rsv63 = F_iw_op == 63; - assign F_op_eret = F_op_opx & (F_iw_opx == 1); - assign F_op_roli = F_op_opx & (F_iw_opx == 2); - assign F_op_rol = F_op_opx & (F_iw_opx == 3); - assign F_op_flushp = F_op_opx & (F_iw_opx == 4); - assign F_op_ret = F_op_opx & (F_iw_opx == 5); - assign F_op_nor = F_op_opx & (F_iw_opx == 6); - assign F_op_mulxuu = F_op_opx & (F_iw_opx == 7); - assign F_op_cmpge = F_op_opx & (F_iw_opx == 8); - assign F_op_bret = F_op_opx & (F_iw_opx == 9); - assign F_op_ror = F_op_opx & (F_iw_opx == 11); - assign F_op_flushi = F_op_opx & (F_iw_opx == 12); - assign F_op_jmp = F_op_opx & (F_iw_opx == 13); - assign F_op_and = F_op_opx & (F_iw_opx == 14); - assign F_op_cmplt = F_op_opx & (F_iw_opx == 16); - assign F_op_slli = F_op_opx & (F_iw_opx == 18); - assign F_op_sll = F_op_opx & (F_iw_opx == 19); - assign F_op_wrprs = F_op_opx & (F_iw_opx == 20); - assign F_op_or = F_op_opx & (F_iw_opx == 22); - assign F_op_mulxsu = F_op_opx & (F_iw_opx == 23); - assign F_op_cmpne = F_op_opx & (F_iw_opx == 24); - assign F_op_srli = F_op_opx & (F_iw_opx == 26); - assign F_op_srl = F_op_opx & (F_iw_opx == 27); - assign F_op_nextpc = F_op_opx & (F_iw_opx == 28); - assign F_op_callr = F_op_opx & (F_iw_opx == 29); - assign F_op_xor = F_op_opx & (F_iw_opx == 30); - assign F_op_mulxss = F_op_opx & (F_iw_opx == 31); - assign F_op_cmpeq = F_op_opx & (F_iw_opx == 32); - assign F_op_divu = F_op_opx & (F_iw_opx == 36); - assign F_op_div = F_op_opx & (F_iw_opx == 37); - assign F_op_rdctl = F_op_opx & (F_iw_opx == 38); - assign F_op_mul = F_op_opx & (F_iw_opx == 39); - assign F_op_cmpgeu = F_op_opx & (F_iw_opx == 40); - assign F_op_initi = F_op_opx & (F_iw_opx == 41); - assign F_op_trap = F_op_opx & (F_iw_opx == 45); - assign F_op_wrctl = F_op_opx & (F_iw_opx == 46); - assign F_op_cmpltu = F_op_opx & (F_iw_opx == 48); - assign F_op_add = F_op_opx & (F_iw_opx == 49); - assign F_op_break = F_op_opx & (F_iw_opx == 52); - assign F_op_hbreak = F_op_opx & (F_iw_opx == 53); - assign F_op_sync = F_op_opx & (F_iw_opx == 54); - assign F_op_sub = F_op_opx & (F_iw_opx == 57); - assign F_op_srai = F_op_opx & (F_iw_opx == 58); - assign F_op_sra = F_op_opx & (F_iw_opx == 59); - assign F_op_intr = F_op_opx & (F_iw_opx == 61); - assign F_op_crst = F_op_opx & (F_iw_opx == 62); - assign F_op_rsvx00 = F_op_opx & (F_iw_opx == 0); - assign F_op_rsvx10 = F_op_opx & (F_iw_opx == 10); - assign F_op_rsvx15 = F_op_opx & (F_iw_opx == 15); - assign F_op_rsvx17 = F_op_opx & (F_iw_opx == 17); - assign F_op_rsvx21 = F_op_opx & (F_iw_opx == 21); - assign F_op_rsvx25 = F_op_opx & (F_iw_opx == 25); - assign F_op_rsvx33 = F_op_opx & (F_iw_opx == 33); - assign F_op_rsvx34 = F_op_opx & (F_iw_opx == 34); - assign F_op_rsvx35 = F_op_opx & (F_iw_opx == 35); - assign F_op_rsvx42 = F_op_opx & (F_iw_opx == 42); - assign F_op_rsvx43 = F_op_opx & (F_iw_opx == 43); - assign F_op_rsvx44 = F_op_opx & (F_iw_opx == 44); - assign F_op_rsvx47 = F_op_opx & (F_iw_opx == 47); - assign F_op_rsvx50 = F_op_opx & (F_iw_opx == 50); - assign F_op_rsvx51 = F_op_opx & (F_iw_opx == 51); - assign F_op_rsvx55 = F_op_opx & (F_iw_opx == 55); - assign F_op_rsvx56 = F_op_opx & (F_iw_opx == 56); - assign F_op_rsvx60 = F_op_opx & (F_iw_opx == 60); - assign F_op_rsvx63 = F_op_opx & (F_iw_opx == 63); - assign F_op_opx = F_iw_op == 58; - assign F_op_custom = F_iw_op == 50; - assign D_op_call = D_iw_op == 0; - assign D_op_jmpi = D_iw_op == 1; - assign D_op_ldbu = D_iw_op == 3; - assign D_op_addi = D_iw_op == 4; - assign D_op_stb = D_iw_op == 5; - assign D_op_br = D_iw_op == 6; - assign D_op_ldb = D_iw_op == 7; - assign D_op_cmpgei = D_iw_op == 8; - assign D_op_ldhu = D_iw_op == 11; - assign D_op_andi = D_iw_op == 12; - assign D_op_sth = D_iw_op == 13; - assign D_op_bge = D_iw_op == 14; - assign D_op_ldh = D_iw_op == 15; - assign D_op_cmplti = D_iw_op == 16; - assign D_op_initda = D_iw_op == 19; - assign D_op_ori = D_iw_op == 20; - assign D_op_stw = D_iw_op == 21; - assign D_op_blt = D_iw_op == 22; - assign D_op_ldw = D_iw_op == 23; - assign D_op_cmpnei = D_iw_op == 24; - assign D_op_flushda = D_iw_op == 27; - assign D_op_xori = D_iw_op == 28; - assign D_op_stc = D_iw_op == 29; - assign D_op_bne = D_iw_op == 30; - assign D_op_ldl = D_iw_op == 31; - assign D_op_cmpeqi = D_iw_op == 32; - assign D_op_ldbuio = D_iw_op == 35; - assign D_op_muli = D_iw_op == 36; - assign D_op_stbio = D_iw_op == 37; - assign D_op_beq = D_iw_op == 38; - assign D_op_ldbio = D_iw_op == 39; - assign D_op_cmpgeui = D_iw_op == 40; - assign D_op_ldhuio = D_iw_op == 43; - assign D_op_andhi = D_iw_op == 44; - assign D_op_sthio = D_iw_op == 45; - assign D_op_bgeu = D_iw_op == 46; - assign D_op_ldhio = D_iw_op == 47; - assign D_op_cmpltui = D_iw_op == 48; - assign D_op_initd = D_iw_op == 51; - assign D_op_orhi = D_iw_op == 52; - assign D_op_stwio = D_iw_op == 53; - assign D_op_bltu = D_iw_op == 54; - assign D_op_ldwio = D_iw_op == 55; - assign D_op_rdprs = D_iw_op == 56; - assign D_op_flushd = D_iw_op == 59; - assign D_op_xorhi = D_iw_op == 60; - assign D_op_rsv02 = D_iw_op == 2; - assign D_op_rsv09 = D_iw_op == 9; - assign D_op_rsv10 = D_iw_op == 10; - assign D_op_rsv17 = D_iw_op == 17; - assign D_op_rsv18 = D_iw_op == 18; - assign D_op_rsv25 = D_iw_op == 25; - assign D_op_rsv26 = D_iw_op == 26; - assign D_op_rsv33 = D_iw_op == 33; - assign D_op_rsv34 = D_iw_op == 34; - assign D_op_rsv41 = D_iw_op == 41; - assign D_op_rsv42 = D_iw_op == 42; - assign D_op_rsv49 = D_iw_op == 49; - assign D_op_rsv57 = D_iw_op == 57; - assign D_op_rsv61 = D_iw_op == 61; - assign D_op_rsv62 = D_iw_op == 62; - assign D_op_rsv63 = D_iw_op == 63; - assign D_op_eret = D_op_opx & (D_iw_opx == 1); - assign D_op_roli = D_op_opx & (D_iw_opx == 2); - assign D_op_rol = D_op_opx & (D_iw_opx == 3); - assign D_op_flushp = D_op_opx & (D_iw_opx == 4); - assign D_op_ret = D_op_opx & (D_iw_opx == 5); - assign D_op_nor = D_op_opx & (D_iw_opx == 6); - assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7); - assign D_op_cmpge = D_op_opx & (D_iw_opx == 8); - assign D_op_bret = D_op_opx & (D_iw_opx == 9); - assign D_op_ror = D_op_opx & (D_iw_opx == 11); - assign D_op_flushi = D_op_opx & (D_iw_opx == 12); - assign D_op_jmp = D_op_opx & (D_iw_opx == 13); - assign D_op_and = D_op_opx & (D_iw_opx == 14); - assign D_op_cmplt = D_op_opx & (D_iw_opx == 16); - assign D_op_slli = D_op_opx & (D_iw_opx == 18); - assign D_op_sll = D_op_opx & (D_iw_opx == 19); - assign D_op_wrprs = D_op_opx & (D_iw_opx == 20); - assign D_op_or = D_op_opx & (D_iw_opx == 22); - assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23); - assign D_op_cmpne = D_op_opx & (D_iw_opx == 24); - assign D_op_srli = D_op_opx & (D_iw_opx == 26); - assign D_op_srl = D_op_opx & (D_iw_opx == 27); - assign D_op_nextpc = D_op_opx & (D_iw_opx == 28); - assign D_op_callr = D_op_opx & (D_iw_opx == 29); - assign D_op_xor = D_op_opx & (D_iw_opx == 30); - assign D_op_mulxss = D_op_opx & (D_iw_opx == 31); - assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32); - assign D_op_divu = D_op_opx & (D_iw_opx == 36); - assign D_op_div = D_op_opx & (D_iw_opx == 37); - assign D_op_rdctl = D_op_opx & (D_iw_opx == 38); - assign D_op_mul = D_op_opx & (D_iw_opx == 39); - assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40); - assign D_op_initi = D_op_opx & (D_iw_opx == 41); - assign D_op_trap = D_op_opx & (D_iw_opx == 45); - assign D_op_wrctl = D_op_opx & (D_iw_opx == 46); - assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48); - assign D_op_add = D_op_opx & (D_iw_opx == 49); - assign D_op_break = D_op_opx & (D_iw_opx == 52); - assign D_op_hbreak = D_op_opx & (D_iw_opx == 53); - assign D_op_sync = D_op_opx & (D_iw_opx == 54); - assign D_op_sub = D_op_opx & (D_iw_opx == 57); - assign D_op_srai = D_op_opx & (D_iw_opx == 58); - assign D_op_sra = D_op_opx & (D_iw_opx == 59); - assign D_op_intr = D_op_opx & (D_iw_opx == 61); - assign D_op_crst = D_op_opx & (D_iw_opx == 62); - assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0); - assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10); - assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15); - assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17); - assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21); - assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25); - assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33); - assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34); - assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35); - assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42); - assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43); - assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44); - assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47); - assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50); - assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51); - assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55); - assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56); - assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60); - assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63); - assign D_op_opx = D_iw_op == 58; - assign D_op_custom = D_iw_op == 50; - assign R_en = 1'b1; - assign E_ci_result = 0; - //custom_instruction_master, which is an e_custom_instruction_master - assign no_ci_readra = 1'b0; - assign E_ci_multi_stall = 1'b0; - assign iactive = d_irq[31 : 0] & 32'b00000000000000000000000000100000; - assign F_pc_sel_nxt = R_ctrl_exception ? 2'b00 : - R_ctrl_break ? 2'b01 : - (W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 : - 2'b11; - - assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 8 : - (F_pc_sel_nxt == 2'b01)? 66056 : - (F_pc_sel_nxt == 2'b10)? E_arith_result[18 : 2] : - F_pc_plus_one; - - assign F_pc_nxt = F_pc_no_crst_nxt; - assign F_pcb_nxt = {F_pc_nxt, 2'b00}; - assign F_pc_en = W_valid; - assign F_pc_plus_one = F_pc + 1; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - F_pc <= 0; - else if (F_pc_en) - F_pc <= F_pc_nxt; - end - - - assign F_pcb = {F_pc, 2'b00}; - assign F_pcb_plus_four = {F_pc_plus_one, 2'b00}; - assign F_valid = i_read & ~i_waitrequest; - assign i_read_nxt = W_valid | (i_read & i_waitrequest); - assign i_address = {F_pc, 2'b00}; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - i_read <= 1'b1; - else - i_read <= i_read_nxt; - end - - - assign oci_tb_hbreak_req = oci_hbreak_req; - assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled & ~(wait_for_one_post_bret_inst & ~W_valid); - assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled - : hbreak_req; - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - wait_for_one_post_bret_inst <= 1'b0; - else - wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 : (F_valid | ~oci_single_step_mode) ? 1'b0 : wait_for_one_post_bret_inst; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - hbreak_pending <= 1'b0; - else - hbreak_pending <= hbreak_pending_nxt; - end - - - assign intr_req = W_status_reg_pie & (W_ipending_reg != 0); - assign F_av_iw = i_readdata; - assign F_iw = hbreak_req ? 4040762 : - 1'b0 ? 127034 : - intr_req ? 3926074 : - F_av_iw; - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - D_iw <= 0; - else if (F_valid) - D_iw <= F_iw; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - D_valid <= 0; - else - D_valid <= F_valid; - end - - - assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 : - D_ctrl_implicit_dst_eretaddr ? 5'd29 : - D_ctrl_b_is_dst ? D_iw_b : - D_iw_c; - - assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst; - assign D_logic_op_raw = D_op_opx ? D_iw_opx[4 : 3] : - D_iw_op[4 : 3]; - - assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 : D_logic_op_raw; - assign D_compare_op = D_op_opx ? D_iw_opx[4 : 3] : - D_iw_op[4 : 3]; - - assign D_jmp_direct_target_waddr = D_iw[31 : 6]; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_valid <= 0; - else - R_valid <= D_valid; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_wr_dst_reg <= 0; - else - R_wr_dst_reg <= D_wr_dst_reg; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_dst_regnum <= 0; - else - R_dst_regnum <= D_dst_regnum; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_logic_op <= 0; - else - R_logic_op <= D_logic_op; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_compare_op <= 0; - else - R_compare_op <= D_compare_op; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_src2_use_imm <= 0; - else - R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid); - end - - - assign W_rf_wren = (R_wr_dst_reg & W_valid) | ~reset_n; - assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data; -//nios_system_nios2_processor_register_bank_a, which is an nios_sdp_ram -nios_system_nios2_processor_register_bank_a_module nios_system_nios2_processor_register_bank_a - ( - .clock (clk), - .data (W_rf_wr_data), - .q (R_rf_a), - .rdaddress (D_iw_a), - .wraddress (R_dst_regnum), - .wren (W_rf_wren) - ); - -//synthesis translate_off -`ifdef NO_PLI -defparam nios_system_nios2_processor_register_bank_a.lpm_file = "nios_system_nios2_processor_rf_ram_a.dat"; -`else -defparam nios_system_nios2_processor_register_bank_a.lpm_file = "nios_system_nios2_processor_rf_ram_a.hex"; -`endif -//synthesis translate_on -//synthesis read_comments_as_HDL on -//defparam nios_system_nios2_processor_register_bank_a.lpm_file = "nios_system_nios2_processor_rf_ram_a.mif"; -//synthesis read_comments_as_HDL off -//nios_system_nios2_processor_register_bank_b, which is an nios_sdp_ram -nios_system_nios2_processor_register_bank_b_module nios_system_nios2_processor_register_bank_b - ( - .clock (clk), - .data (W_rf_wr_data), - .q (R_rf_b), - .rdaddress (D_iw_b), - .wraddress (R_dst_regnum), - .wren (W_rf_wren) - ); - -//synthesis translate_off -`ifdef NO_PLI -defparam nios_system_nios2_processor_register_bank_b.lpm_file = "nios_system_nios2_processor_rf_ram_b.dat"; -`else -defparam nios_system_nios2_processor_register_bank_b.lpm_file = "nios_system_nios2_processor_rf_ram_b.hex"; -`endif -//synthesis translate_on -//synthesis read_comments_as_HDL on -//defparam nios_system_nios2_processor_register_bank_b.lpm_file = "nios_system_nios2_processor_rf_ram_b.mif"; -//synthesis read_comments_as_HDL off - assign R_src1 = (((R_ctrl_br & E_valid) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} : - ((R_ctrl_jmp_direct & E_valid))? {D_jmp_direct_target_waddr, 2'b00} : - R_rf_a; - - assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? 16'b0 : - (R_src2_use_imm)? D_iw_imm16 : - R_rf_b[15 : 0]; - - assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? 16'b0 : - (R_ctrl_hi_imm16)? D_iw_imm16 : - (R_src2_use_imm)? {16 {D_iw_imm16[15]}} : - R_rf_b[31 : 16]; - - assign R_src2 = {R_src2_hi, R_src2_lo}; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_valid <= 0; - else - E_valid <= R_valid | E_stall; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_new_inst <= 0; - else - E_new_inst <= R_valid; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_src1 <= 0; - else - E_src1 <= R_src1; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_src2 <= 0; - else - E_src2 <= R_src2; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_invert_arith_src_msb <= 0; - else - E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_alu_sub <= 0; - else - E_alu_sub <= D_ctrl_alu_subtract & R_valid; - end - - - assign E_stall = E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall; - assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb, - E_src1[30 : 0]}; - - assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb, - E_src2[30 : 0]}; - - assign E_arith_result = E_alu_sub ? - E_arith_src1 - E_arith_src2 : - E_arith_src1 + E_arith_src2; - - assign E_mem_baddr = E_arith_result[18 : 0]; - assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) : - (R_logic_op == 2'b01)? (E_src1 & E_src2) : - (R_logic_op == 2'b10)? (E_src1 | E_src2) : - (E_src1 ^ E_src2); - - assign E_logic_result_is_0 = E_logic_result == 0; - assign E_eq = E_logic_result_is_0; - assign E_lt = E_arith_result[32]; - assign E_cmp_result = (R_compare_op == 2'b00)? E_eq : - (R_compare_op == 2'b01)? ~E_lt : - (R_compare_op == 2'b10)? E_lt : - ~E_eq; - - assign E_shift_rot_cnt_nxt = E_new_inst ? E_src2[4 : 0] : E_shift_rot_cnt-1; - assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst; - assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done; - assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 : - (R_ctrl_rot_right ? E_shift_rot_result[0] : - E_shift_rot_result[31]); - - assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 : - (R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} : - {E_shift_rot_result[30 : 0], E_shift_rot_fill_bit}; - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_shift_rot_result <= 0; - else - E_shift_rot_result <= E_shift_rot_result_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_shift_rot_cnt <= 0; - else - E_shift_rot_cnt <= E_shift_rot_cnt_nxt; - end - - - assign E_control_rd_data = (D_iw_control_regnum == 3'd0)? W_status_reg : - (D_iw_control_regnum == 3'd1)? W_estatus_reg : - (D_iw_control_regnum == 3'd2)? W_bstatus_reg : - (D_iw_control_regnum == 3'd3)? W_ienable_reg : - (D_iw_control_regnum == 3'd4)? W_ipending_reg : - 0; - - assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rdctl_inst))? 0 : - (R_ctrl_shift_rot)? E_shift_rot_result : - (R_ctrl_logic)? E_logic_result : - (R_ctrl_custom)? E_ci_result : - E_arith_result; - - assign R_stb_data = R_rf_b[7 : 0]; - assign R_sth_data = R_rf_b[15 : 0]; - assign E_st_data = (D_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} : - (D_mem16)? {R_sth_data, R_sth_data} : - R_rf_b; - - assign E_mem_byte_en = ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b00})? 4'b0001 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b01})? 4'b0010 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b10})? 4'b0100 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b11})? 4'b1000 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0011 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0011 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b1100 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1100 : - 4'b1111; - - assign d_read_nxt = (R_ctrl_ld & E_new_inst) | (d_read & d_waitrequest); - assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst); - assign d_write_nxt = (R_ctrl_st & E_new_inst) | (d_write & d_waitrequest); - assign E_st_stall = d_write_nxt; - assign d_address = W_mem_baddr; - assign av_ld_getting_data = d_read & ~d_waitrequest; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - d_read <= 0; - else - d_read <= d_read_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - d_writedata <= 0; - else - d_writedata <= E_st_data; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - d_byteenable <= 0; - else - d_byteenable <= E_mem_byte_en; - end - - - assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1); - assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_mem16 ? 2 : 3); - assign av_ld_aligning_data_nxt = av_ld_aligning_data ? - ~av_ld_align_one_more_cycle : - (~D_mem32 & av_ld_getting_data); - - assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ? - ~av_ld_getting_data : - (R_ctrl_ld & E_new_inst); - - assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_mem32 | ~av_ld_aligning_data_nxt); - assign av_ld_rshift8 = av_ld_aligning_data & - (av_ld_align_cycle < (W_mem_baddr[1 : 0])); - - assign av_ld_extend = av_ld_aligning_data; - assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data : - av_ld_extend ? av_ld_byte0_data : - d_readdata[7 : 0]; - - assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data : - av_ld_extend ? {8 {av_fill_bit}} : - d_readdata[15 : 8]; - - assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data : - av_ld_extend ? {8 {av_fill_bit}} : - d_readdata[23 : 16]; - - assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data : - av_ld_extend ? {8 {av_fill_bit}} : - d_readdata[31 : 24]; - - assign av_ld_byte1_data_en = ~(av_ld_extend & D_mem16 & ~av_ld_rshift8); - assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data, - av_ld_byte1_data, av_ld_byte0_data}; - - assign av_sign_bit = D_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7]; - assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_align_cycle <= 0; - else - av_ld_align_cycle <= av_ld_align_cycle_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_waiting_for_data <= 0; - else - av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_aligning_data <= 0; - else - av_ld_aligning_data <= av_ld_aligning_data_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_byte0_data <= 0; - else - av_ld_byte0_data <= av_ld_byte0_data_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_byte1_data <= 0; - else if (av_ld_byte1_data_en) - av_ld_byte1_data <= av_ld_byte1_data_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_byte2_data <= 0; - else - av_ld_byte2_data <= av_ld_byte2_data_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_byte3_data <= 0; - else - av_ld_byte3_data <= av_ld_byte3_data_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_valid <= 0; - else - W_valid <= E_valid & ~E_stall; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_control_rd_data <= 0; - else - W_control_rd_data <= E_control_rd_data; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_cmp_result <= 0; - else - W_cmp_result <= E_cmp_result; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_alu_result <= 0; - else - W_alu_result <= E_alu_result; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_status_reg_pie <= 0; - else - W_status_reg_pie <= W_status_reg_pie_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_estatus_reg <= 0; - else - W_estatus_reg <= W_estatus_reg_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_bstatus_reg <= 0; - else - W_bstatus_reg <= W_bstatus_reg_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_ienable_reg <= 0; - else - W_ienable_reg <= W_ienable_reg_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_ipending_reg <= 0; - else - W_ipending_reg <= W_ipending_reg_nxt; - end - - - assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result : - R_ctrl_rdctl_inst ? W_control_rd_data : - W_alu_result[31 : 0]; - - assign W_wr_data = W_wr_data_non_zero; - assign W_br_taken = R_ctrl_br & W_cmp_result; - assign W_mem_baddr = W_alu_result[18 : 0]; - assign W_status_reg = W_status_reg_pie; - assign E_wrctl_status = R_ctrl_wrctl_inst & - (D_iw_control_regnum == 3'd0); - - assign E_wrctl_estatus = R_ctrl_wrctl_inst & - (D_iw_control_regnum == 3'd1); - - assign E_wrctl_bstatus = R_ctrl_wrctl_inst & - (D_iw_control_regnum == 3'd2); - - assign E_wrctl_ienable = R_ctrl_wrctl_inst & - (D_iw_control_regnum == 3'd3); - - assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst) ? 1'b0 : - (D_op_eret) ? W_estatus_reg : - (D_op_bret) ? W_bstatus_reg : - (E_wrctl_status) ? E_src1[0] : - W_status_reg_pie; - - assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie; - assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 : - (R_ctrl_exception) ? W_status_reg : - (E_wrctl_estatus) ? E_src1[0] : - W_estatus_reg; - - assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg; - assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg : - (E_wrctl_bstatus) ? E_src1[0] : - W_bstatus_reg; - - assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg; - assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ? - E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000000100000; - - assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000000100000; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - hbreak_enabled <= 1'b1; - else if (E_valid) - hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled; - end - - - nios_system_nios2_processor_nios2_oci the_nios_system_nios2_processor_nios2_oci - ( - .D_valid (D_valid), - .E_st_data (E_st_data), - .E_valid (E_valid), - .F_pc (F_pc), - .address_nxt (jtag_debug_module_address), - .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), - .byteenable_nxt (jtag_debug_module_byteenable), - .clk (jtag_debug_module_clk), - .d_address (d_address), - .d_read (d_read), - .d_waitrequest (d_waitrequest), - .d_write (d_write), - .debugaccess_nxt (jtag_debug_module_debugaccess), - .hbreak_enabled (hbreak_enabled), - .jtag_debug_module_debugaccess_to_roms (jtag_debug_module_debugaccess_to_roms), - .oci_hbreak_req (oci_hbreak_req), - .oci_ienable (oci_ienable), - .oci_single_step_mode (oci_single_step_mode), - .read_nxt (jtag_debug_module_read), - .readdata (jtag_debug_module_readdata), - .reset (jtag_debug_module_reset), - .reset_n (reset_n), - .resetrequest (jtag_debug_module_resetrequest), - .test_ending (test_ending), - .test_has_ended (test_has_ended), - .waitrequest (jtag_debug_module_waitrequest), - .write_nxt (jtag_debug_module_write), - .writedata_nxt (jtag_debug_module_writedata) - ); - - //jtag_debug_module, which is an e_avalon_slave - assign jtag_debug_module_clk = clk; - assign jtag_debug_module_reset = ~reset_n; - assign D_ctrl_custom = 1'b0; - assign R_ctrl_custom_nxt = D_ctrl_custom; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_custom <= 0; - else if (R_en) - R_ctrl_custom <= R_ctrl_custom_nxt; - end - - - assign D_ctrl_custom_multi = 1'b0; - assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_custom_multi <= 0; - else if (R_en) - R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt; - end - - - assign D_ctrl_jmp_indirect = D_op_eret| - D_op_bret| - D_op_rsvx17| - D_op_rsvx25| - D_op_ret| - D_op_jmp| - D_op_rsvx21| - D_op_callr; - - assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_jmp_indirect <= 0; - else if (R_en) - R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt; - end - - - assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi; - assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_jmp_direct <= 0; - else if (R_en) - R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt; - end - - - assign D_ctrl_implicit_dst_retaddr = D_op_call|D_op_rsv02; - assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_implicit_dst_retaddr <= 0; - else if (R_en) - R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt; - end - - - assign D_ctrl_implicit_dst_eretaddr = D_op_div|D_op_divu|D_op_mul|D_op_muli|D_op_mulxss|D_op_mulxsu|D_op_mulxuu; - assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_implicit_dst_eretaddr <= 0; - else if (R_en) - R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt; - end - - - assign D_ctrl_exception = D_op_trap| - D_op_rsvx44| - D_op_div| - D_op_divu| - D_op_mul| - D_op_muli| - D_op_mulxss| - D_op_mulxsu| - D_op_mulxuu| - D_op_intr| - D_op_rsvx60; - - assign R_ctrl_exception_nxt = D_ctrl_exception; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_exception <= 0; - else if (R_en) - R_ctrl_exception <= R_ctrl_exception_nxt; - end - - - assign D_ctrl_break = D_op_break|D_op_hbreak; - assign R_ctrl_break_nxt = D_ctrl_break; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_break <= 0; - else if (R_en) - R_ctrl_break <= R_ctrl_break_nxt; - end - - - assign D_ctrl_crst = D_op_crst|D_op_rsvx63; - assign R_ctrl_crst_nxt = D_ctrl_crst; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_crst <= 0; - else if (R_en) - R_ctrl_crst <= R_ctrl_crst_nxt; - end - - - assign D_ctrl_uncond_cti_non_br = D_op_call| - D_op_jmpi| - D_op_eret| - D_op_bret| - D_op_rsvx17| - D_op_rsvx25| - D_op_ret| - D_op_jmp| - D_op_rsvx21| - D_op_callr; - - assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_uncond_cti_non_br <= 0; - else if (R_en) - R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt; - end - - - assign D_ctrl_retaddr = D_op_call| - D_op_rsv02| - D_op_nextpc| - D_op_callr| - D_op_trap| - D_op_rsvx44| - D_op_div| - D_op_divu| - D_op_mul| - D_op_muli| - D_op_mulxss| - D_op_mulxsu| - D_op_mulxuu| - D_op_intr| - D_op_rsvx60| - D_op_break| - D_op_hbreak; - - assign R_ctrl_retaddr_nxt = D_ctrl_retaddr; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_retaddr <= 0; - else if (R_en) - R_ctrl_retaddr <= R_ctrl_retaddr_nxt; - end - - - assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl; - assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_shift_logical <= 0; - else if (R_en) - R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt; - end - - - assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra; - assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_shift_right_arith <= 0; - else if (R_en) - R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt; - end - - - assign D_ctrl_rot_right = D_op_rsvx10|D_op_ror|D_op_rsvx42|D_op_rsvx43; - assign R_ctrl_rot_right_nxt = D_ctrl_rot_right; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_rot_right <= 0; - else if (R_en) - R_ctrl_rot_right <= R_ctrl_rot_right_nxt; - end - - - assign D_ctrl_shift_rot_right = D_op_srli| - D_op_srl| - D_op_srai| - D_op_sra| - D_op_rsvx10| - D_op_ror| - D_op_rsvx42| - D_op_rsvx43; - - assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_shift_rot_right <= 0; - else if (R_en) - R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt; - end - - - assign D_ctrl_shift_rot = D_op_slli| - D_op_rsvx50| - D_op_sll| - D_op_rsvx51| - D_op_roli| - D_op_rsvx34| - D_op_rol| - D_op_rsvx35| - D_op_srli| - D_op_srl| - D_op_srai| - D_op_sra| - D_op_rsvx10| - D_op_ror| - D_op_rsvx42| - D_op_rsvx43; - - assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_shift_rot <= 0; - else if (R_en) - R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt; - end - - - assign D_ctrl_logic = D_op_and| - D_op_or| - D_op_xor| - D_op_nor| - D_op_andhi| - D_op_orhi| - D_op_xorhi| - D_op_andi| - D_op_ori| - D_op_xori; - - assign R_ctrl_logic_nxt = D_ctrl_logic; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_logic <= 0; - else if (R_en) - R_ctrl_logic <= R_ctrl_logic_nxt; - end - - - assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi; - assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_hi_imm16 <= 0; - else if (R_en) - R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt; - end - - - assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui| - D_op_cmpltui| - D_op_andi| - D_op_ori| - D_op_xori| - D_op_roli| - D_op_rsvx10| - D_op_slli| - D_op_srli| - D_op_rsvx34| - D_op_rsvx42| - D_op_rsvx50| - D_op_srai; - - assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_unsigned_lo_imm16 <= 0; - else if (R_en) - R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt; - end - - - assign D_ctrl_br_uncond = D_op_br|D_op_rsv02; - assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_br_uncond <= 0; - else if (R_en) - R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt; - end - - - assign D_ctrl_br = D_op_br| - D_op_bge| - D_op_blt| - D_op_bne| - D_op_beq| - D_op_bgeu| - D_op_bltu| - D_op_rsv62; - - assign R_ctrl_br_nxt = D_ctrl_br; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_br <= 0; - else if (R_en) - R_ctrl_br <= R_ctrl_br_nxt; - end - - - assign D_ctrl_alu_subtract = D_op_sub| - D_op_rsvx25| - D_op_cmplti| - D_op_cmpltui| - D_op_cmplt| - D_op_cmpltu| - D_op_blt| - D_op_bltu| - D_op_cmpgei| - D_op_cmpgeui| - D_op_cmpge| - D_op_cmpgeu| - D_op_bge| - D_op_rsv10| - D_op_bgeu| - D_op_rsv42; - - assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_alu_subtract <= 0; - else if (R_en) - R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt; - end - - - assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt; - assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_alu_signed_comparison <= 0; - else if (R_en) - R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt; - end - - - assign D_ctrl_br_cmp = D_op_br| - D_op_bge| - D_op_blt| - D_op_bne| - D_op_beq| - D_op_bgeu| - D_op_bltu| - D_op_rsv62| - D_op_cmpgei| - D_op_cmplti| - D_op_cmpnei| - D_op_cmpgeui| - D_op_cmpltui| - D_op_cmpeqi| - D_op_rsvx00| - D_op_cmpge| - D_op_cmplt| - D_op_cmpne| - D_op_cmpgeu| - D_op_cmpltu| - D_op_cmpeq| - D_op_rsvx56; - - assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_br_cmp <= 0; - else if (R_en) - R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt; - end - - - assign D_ctrl_ld_signed = D_op_ldb| - D_op_ldh| - D_op_ldl| - D_op_ldw| - D_op_ldbio| - D_op_ldhio| - D_op_ldwio| - D_op_rsv63; - - assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_ld_signed <= 0; - else if (R_en) - R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt; - end - - - assign D_ctrl_ld = D_op_ldb| - D_op_ldh| - D_op_ldl| - D_op_ldw| - D_op_ldbio| - D_op_ldhio| - D_op_ldwio| - D_op_rsv63| - D_op_ldbu| - D_op_ldhu| - D_op_ldbuio| - D_op_ldhuio; - - assign R_ctrl_ld_nxt = D_ctrl_ld; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_ld <= 0; - else if (R_en) - R_ctrl_ld <= R_ctrl_ld_nxt; - end - - - assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldl; - assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_ld_non_io <= 0; - else if (R_en) - R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt; - end - - - assign D_ctrl_st = D_op_stb| - D_op_sth| - D_op_stw| - D_op_stc| - D_op_stbio| - D_op_sthio| - D_op_stwio| - D_op_rsv61; - - assign R_ctrl_st_nxt = D_ctrl_st; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_st <= 0; - else if (R_en) - R_ctrl_st <= R_ctrl_st_nxt; - end - - - assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio|D_op_rsv63; - assign R_ctrl_ld_io_nxt = D_ctrl_ld_io; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_ld_io <= 0; - else if (R_en) - R_ctrl_ld_io <= R_ctrl_ld_io_nxt; - end - - - assign D_ctrl_b_is_dst = D_op_addi| - D_op_andhi| - D_op_orhi| - D_op_xorhi| - D_op_andi| - D_op_ori| - D_op_xori| - D_op_call| - D_op_rdprs| - D_op_cmpgei| - D_op_cmplti| - D_op_cmpnei| - D_op_cmpgeui| - D_op_cmpltui| - D_op_cmpeqi| - D_op_jmpi| - D_op_rsv09| - D_op_rsv17| - D_op_rsv25| - D_op_rsv33| - D_op_rsv41| - D_op_rsv49| - D_op_rsv57| - D_op_ldb| - D_op_ldh| - D_op_ldl| - D_op_ldw| - D_op_ldbio| - D_op_ldhio| - D_op_ldwio| - D_op_rsv63| - D_op_ldbu| - D_op_ldhu| - D_op_ldbuio| - D_op_ldhuio| - D_op_initd| - D_op_initda| - D_op_flushd| - D_op_flushda; - - assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_b_is_dst <= 0; - else if (R_en) - R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt; - end - - - assign D_ctrl_ignore_dst = D_op_br| - D_op_bge| - D_op_blt| - D_op_bne| - D_op_beq| - D_op_bgeu| - D_op_bltu| - D_op_rsv62| - D_op_stb| - D_op_sth| - D_op_stw| - D_op_stc| - D_op_stbio| - D_op_sthio| - D_op_stwio| - D_op_rsv61| - D_op_jmpi| - D_op_rsv09| - D_op_rsv17| - D_op_rsv25| - D_op_rsv33| - D_op_rsv41| - D_op_rsv49| - D_op_rsv57; - - assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_ignore_dst <= 0; - else if (R_en) - R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt; - end - - - assign D_ctrl_src2_choose_imm = D_op_addi| - D_op_andhi| - D_op_orhi| - D_op_xorhi| - D_op_andi| - D_op_ori| - D_op_xori| - D_op_call| - D_op_rdprs| - D_op_cmpgei| - D_op_cmplti| - D_op_cmpnei| - D_op_cmpgeui| - D_op_cmpltui| - D_op_cmpeqi| - D_op_jmpi| - D_op_rsv09| - D_op_rsv17| - D_op_rsv25| - D_op_rsv33| - D_op_rsv41| - D_op_rsv49| - D_op_rsv57| - D_op_ldb| - D_op_ldh| - D_op_ldl| - D_op_ldw| - D_op_ldbio| - D_op_ldhio| - D_op_ldwio| - D_op_rsv63| - D_op_ldbu| - D_op_ldhu| - D_op_ldbuio| - D_op_ldhuio| - D_op_initd| - D_op_initda| - D_op_flushd| - D_op_flushda| - D_op_stb| - D_op_sth| - D_op_stw| - D_op_stc| - D_op_stbio| - D_op_sthio| - D_op_stwio| - D_op_rsv61| - D_op_roli| - D_op_rsvx10| - D_op_slli| - D_op_srli| - D_op_rsvx34| - D_op_rsvx42| - D_op_rsvx50| - D_op_srai; - - assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_src2_choose_imm <= 0; - else if (R_en) - R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt; - end - - - assign D_ctrl_wrctl_inst = D_op_wrctl; - assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_wrctl_inst <= 0; - else if (R_en) - R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt; - end - - - assign D_ctrl_rdctl_inst = D_op_rdctl; - assign R_ctrl_rdctl_inst_nxt = D_ctrl_rdctl_inst; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_rdctl_inst <= 0; - else if (R_en) - R_ctrl_rdctl_inst <= R_ctrl_rdctl_inst_nxt; - end - - - assign D_ctrl_force_src2_zero = D_op_call| - D_op_rsv02| - D_op_nextpc| - D_op_callr| - D_op_trap| - D_op_rsvx44| - D_op_intr| - D_op_rsvx60| - D_op_break| - D_op_hbreak| - D_op_eret| - D_op_bret| - D_op_rsvx17| - D_op_rsvx25| - D_op_ret| - D_op_jmp| - D_op_rsvx21| - D_op_jmpi; - - assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_force_src2_zero <= 0; - else if (R_en) - R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt; - end - - - assign D_ctrl_alu_force_xor = D_op_cmpgei| - D_op_cmpgeui| - D_op_cmpeqi| - D_op_cmpge| - D_op_cmpgeu| - D_op_cmpeq| - D_op_cmpnei| - D_op_cmpne| - D_op_bge| - D_op_rsv10| - D_op_bgeu| - D_op_rsv42| - D_op_beq| - D_op_rsv34| - D_op_bne| - D_op_rsv62| - D_op_br| - D_op_rsv02; - - assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_alu_force_xor <= 0; - else if (R_en) - R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt; - end - - - //data_master, which is an e_avalon_master - //instruction_master, which is an e_avalon_master - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - assign F_inst = (F_op_call)? 56'h20202063616c6c : - (F_op_jmpi)? 56'h2020206a6d7069 : - (F_op_ldbu)? 56'h2020206c646275 : - (F_op_addi)? 56'h20202061646469 : - (F_op_stb)? 56'h20202020737462 : - (F_op_br)? 56'h20202020206272 : - (F_op_ldb)? 56'h202020206c6462 : - (F_op_cmpgei)? 56'h20636d70676569 : - (F_op_ldhu)? 56'h2020206c646875 : - (F_op_andi)? 56'h202020616e6469 : - (F_op_sth)? 56'h20202020737468 : - (F_op_bge)? 56'h20202020626765 : - (F_op_ldh)? 56'h202020206c6468 : - (F_op_cmplti)? 56'h20636d706c7469 : - (F_op_initda)? 56'h20696e69746461 : - (F_op_ori)? 56'h202020206f7269 : - (F_op_stw)? 56'h20202020737477 : - (F_op_blt)? 56'h20202020626c74 : - (F_op_ldw)? 56'h202020206c6477 : - (F_op_cmpnei)? 56'h20636d706e6569 : - (F_op_flushda)? 56'h666c7573686461 : - (F_op_xori)? 56'h202020786f7269 : - (F_op_bne)? 56'h20202020626e65 : - (F_op_cmpeqi)? 56'h20636d70657169 : - (F_op_ldbuio)? 56'h206c646275696f : - (F_op_muli)? 56'h2020206d756c69 : - (F_op_stbio)? 56'h2020737462696f : - (F_op_beq)? 56'h20202020626571 : - (F_op_ldbio)? 56'h20206c6462696f : - (F_op_cmpgeui)? 56'h636d7067657569 : - (F_op_ldhuio)? 56'h206c646875696f : - (F_op_andhi)? 56'h2020616e646869 : - (F_op_sthio)? 56'h2020737468696f : - (F_op_bgeu)? 56'h20202062676575 : - (F_op_ldhio)? 56'h20206c6468696f : - (F_op_cmpltui)? 56'h636d706c747569 : - (F_op_initd)? 56'h2020696e697464 : - (F_op_orhi)? 56'h2020206f726869 : - (F_op_stwio)? 56'h2020737477696f : - (F_op_bltu)? 56'h202020626c7475 : - (F_op_ldwio)? 56'h20206c6477696f : - (F_op_flushd)? 56'h20666c75736864 : - (F_op_xorhi)? 56'h2020786f726869 : - (F_op_eret)? 56'h20202065726574 : - (F_op_roli)? 56'h202020726f6c69 : - (F_op_rol)? 56'h20202020726f6c : - (F_op_flushp)? 56'h20666c75736870 : - (F_op_ret)? 56'h20202020726574 : - (F_op_nor)? 56'h202020206e6f72 : - (F_op_mulxuu)? 56'h206d756c787575 : - (F_op_cmpge)? 56'h2020636d706765 : - (F_op_bret)? 56'h20202062726574 : - (F_op_ror)? 56'h20202020726f72 : - (F_op_flushi)? 56'h20666c75736869 : - (F_op_jmp)? 56'h202020206a6d70 : - (F_op_and)? 56'h20202020616e64 : - (F_op_cmplt)? 56'h2020636d706c74 : - (F_op_slli)? 56'h202020736c6c69 : - (F_op_sll)? 56'h20202020736c6c : - (F_op_or)? 56'h20202020206f72 : - (F_op_mulxsu)? 56'h206d756c787375 : - (F_op_cmpne)? 56'h2020636d706e65 : - (F_op_srli)? 56'h20202073726c69 : - (F_op_srl)? 56'h2020202073726c : - (F_op_nextpc)? 56'h206e6578747063 : - (F_op_callr)? 56'h202063616c6c72 : - (F_op_xor)? 56'h20202020786f72 : - (F_op_mulxss)? 56'h206d756c787373 : - (F_op_cmpeq)? 56'h2020636d706571 : - (F_op_divu)? 56'h20202064697675 : - (F_op_div)? 56'h20202020646976 : - (F_op_rdctl)? 56'h2020726463746c : - (F_op_mul)? 56'h202020206d756c : - (F_op_cmpgeu)? 56'h20636d70676575 : - (F_op_initi)? 56'h2020696e697469 : - (F_op_trap)? 56'h20202074726170 : - (F_op_wrctl)? 56'h2020777263746c : - (F_op_cmpltu)? 56'h20636d706c7475 : - (F_op_add)? 56'h20202020616464 : - (F_op_break)? 56'h2020627265616b : - (F_op_hbreak)? 56'h2068627265616b : - (F_op_sync)? 56'h20202073796e63 : - (F_op_sub)? 56'h20202020737562 : - (F_op_srai)? 56'h20202073726169 : - (F_op_sra)? 56'h20202020737261 : - (F_op_intr)? 56'h202020696e7472 : - 56'h20202020424144; - - assign D_inst = (D_op_call)? 56'h20202063616c6c : - (D_op_jmpi)? 56'h2020206a6d7069 : - (D_op_ldbu)? 56'h2020206c646275 : - (D_op_addi)? 56'h20202061646469 : - (D_op_stb)? 56'h20202020737462 : - (D_op_br)? 56'h20202020206272 : - (D_op_ldb)? 56'h202020206c6462 : - (D_op_cmpgei)? 56'h20636d70676569 : - (D_op_ldhu)? 56'h2020206c646875 : - (D_op_andi)? 56'h202020616e6469 : - (D_op_sth)? 56'h20202020737468 : - (D_op_bge)? 56'h20202020626765 : - (D_op_ldh)? 56'h202020206c6468 : - (D_op_cmplti)? 56'h20636d706c7469 : - (D_op_initda)? 56'h20696e69746461 : - (D_op_ori)? 56'h202020206f7269 : - (D_op_stw)? 56'h20202020737477 : - (D_op_blt)? 56'h20202020626c74 : - (D_op_ldw)? 56'h202020206c6477 : - (D_op_cmpnei)? 56'h20636d706e6569 : - (D_op_flushda)? 56'h666c7573686461 : - (D_op_xori)? 56'h202020786f7269 : - (D_op_bne)? 56'h20202020626e65 : - (D_op_cmpeqi)? 56'h20636d70657169 : - (D_op_ldbuio)? 56'h206c646275696f : - (D_op_muli)? 56'h2020206d756c69 : - (D_op_stbio)? 56'h2020737462696f : - (D_op_beq)? 56'h20202020626571 : - (D_op_ldbio)? 56'h20206c6462696f : - (D_op_cmpgeui)? 56'h636d7067657569 : - (D_op_ldhuio)? 56'h206c646875696f : - (D_op_andhi)? 56'h2020616e646869 : - (D_op_sthio)? 56'h2020737468696f : - (D_op_bgeu)? 56'h20202062676575 : - (D_op_ldhio)? 56'h20206c6468696f : - (D_op_cmpltui)? 56'h636d706c747569 : - (D_op_initd)? 56'h2020696e697464 : - (D_op_orhi)? 56'h2020206f726869 : - (D_op_stwio)? 56'h2020737477696f : - (D_op_bltu)? 56'h202020626c7475 : - (D_op_ldwio)? 56'h20206c6477696f : - (D_op_flushd)? 56'h20666c75736864 : - (D_op_xorhi)? 56'h2020786f726869 : - (D_op_eret)? 56'h20202065726574 : - (D_op_roli)? 56'h202020726f6c69 : - (D_op_rol)? 56'h20202020726f6c : - (D_op_flushp)? 56'h20666c75736870 : - (D_op_ret)? 56'h20202020726574 : - (D_op_nor)? 56'h202020206e6f72 : - (D_op_mulxuu)? 56'h206d756c787575 : - (D_op_cmpge)? 56'h2020636d706765 : - (D_op_bret)? 56'h20202062726574 : - (D_op_ror)? 56'h20202020726f72 : - (D_op_flushi)? 56'h20666c75736869 : - (D_op_jmp)? 56'h202020206a6d70 : - (D_op_and)? 56'h20202020616e64 : - (D_op_cmplt)? 56'h2020636d706c74 : - (D_op_slli)? 56'h202020736c6c69 : - (D_op_sll)? 56'h20202020736c6c : - (D_op_or)? 56'h20202020206f72 : - (D_op_mulxsu)? 56'h206d756c787375 : - (D_op_cmpne)? 56'h2020636d706e65 : - (D_op_srli)? 56'h20202073726c69 : - (D_op_srl)? 56'h2020202073726c : - (D_op_nextpc)? 56'h206e6578747063 : - (D_op_callr)? 56'h202063616c6c72 : - (D_op_xor)? 56'h20202020786f72 : - (D_op_mulxss)? 56'h206d756c787373 : - (D_op_cmpeq)? 56'h2020636d706571 : - (D_op_divu)? 56'h20202064697675 : - (D_op_div)? 56'h20202020646976 : - (D_op_rdctl)? 56'h2020726463746c : - (D_op_mul)? 56'h202020206d756c : - (D_op_cmpgeu)? 56'h20636d70676575 : - (D_op_initi)? 56'h2020696e697469 : - (D_op_trap)? 56'h20202074726170 : - (D_op_wrctl)? 56'h2020777263746c : - (D_op_cmpltu)? 56'h20636d706c7475 : - (D_op_add)? 56'h20202020616464 : - (D_op_break)? 56'h2020627265616b : - (D_op_hbreak)? 56'h2068627265616b : - (D_op_sync)? 56'h20202073796e63 : - (D_op_sub)? 56'h20202020737562 : - (D_op_srai)? 56'h20202073726169 : - (D_op_sra)? 56'h20202020737261 : - (D_op_intr)? 56'h202020696e7472 : - 56'h20202020424144; - - assign F_vinst = F_valid ? F_inst : {7{8'h2d}}; - assign D_vinst = D_valid ? D_inst : {7{8'h2d}}; - assign R_vinst = R_valid ? D_inst : {7{8'h2d}}; - assign E_vinst = E_valid ? D_inst : {7{8'h2d}}; - assign W_vinst = W_valid ? D_inst : {7{8'h2d}}; - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on - -endmodule - diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v b/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v deleted file mode 100644 index 7daaec7..0000000 --- a/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v +++ /dev/null @@ -1,181 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_jtag_debug_module_sysclk ( - // inputs: - clk, - ir_in, - sr, - vs_udr, - vs_uir, - - // outputs: - jdo, - take_action_break_a, - take_action_break_b, - take_action_break_c, - take_action_ocimem_a, - take_action_ocimem_b, - take_action_tracectrl, - take_action_tracemem_a, - take_action_tracemem_b, - take_no_action_break_a, - take_no_action_break_b, - take_no_action_break_c, - take_no_action_ocimem_a, - take_no_action_tracemem_a - ) -; - - output [ 37: 0] jdo; - output take_action_break_a; - output take_action_break_b; - output take_action_break_c; - output take_action_ocimem_a; - output take_action_ocimem_b; - output take_action_tracectrl; - output take_action_tracemem_a; - output take_action_tracemem_b; - output take_no_action_break_a; - output take_no_action_break_b; - output take_no_action_break_c; - output take_no_action_ocimem_a; - output take_no_action_tracemem_a; - input clk; - input [ 1: 0] ir_in; - input [ 37: 0] sr; - input vs_udr; - input vs_uir; - - reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; - reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; - reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; - reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; - wire sync_udr; - wire sync_uir; - wire take_action_break_a; - wire take_action_break_b; - wire take_action_break_c; - wire take_action_ocimem_a; - wire take_action_ocimem_b; - wire take_action_tracectrl; - wire take_action_tracemem_a; - wire take_action_tracemem_b; - wire take_no_action_break_a; - wire take_no_action_break_b; - wire take_no_action_break_c; - wire take_no_action_ocimem_a; - wire take_no_action_tracemem_a; - wire unxunused_resetxx3; - wire unxunused_resetxx4; - reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; - assign unxunused_resetxx3 = 1'b1; - altera_std_synchronizer the_altera_std_synchronizer3 - ( - .clk (clk), - .din (vs_udr), - .dout (sync_udr), - .reset_n (unxunused_resetxx3) - ); - - defparam the_altera_std_synchronizer3.depth = 2; - - assign unxunused_resetxx4 = 1'b1; - altera_std_synchronizer the_altera_std_synchronizer4 - ( - .clk (clk), - .din (vs_uir), - .dout (sync_uir), - .reset_n (unxunused_resetxx4) - ); - - defparam the_altera_std_synchronizer4.depth = 2; - - always @(posedge clk) - begin - sync2_udr <= sync_udr; - update_jdo_strobe <= sync_udr & ~sync2_udr; - enable_action_strobe <= update_jdo_strobe; - sync2_uir <= sync_uir; - jxuir <= sync_uir & ~sync2_uir; - end - - - assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && - ~jdo[35] && jdo[34]; - - assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && - ~jdo[35] && ~jdo[34]; - - assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) && - jdo[35]; - - assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) && - ~jdo[37] && - jdo[36]; - - assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) && - ~jdo[37] && - ~jdo[36]; - - assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) && - jdo[37]; - - assign take_action_break_a = enable_action_strobe && (ir == 2'b10) && - ~jdo[36] && - jdo[37]; - - assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) && - ~jdo[36] && - ~jdo[37]; - - assign take_action_break_b = enable_action_strobe && (ir == 2'b10) && - jdo[36] && ~jdo[35] && - jdo[37]; - - assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) && - jdo[36] && ~jdo[35] && - ~jdo[37]; - - assign take_action_break_c = enable_action_strobe && (ir == 2'b10) && - jdo[36] && jdo[35] && - jdo[37]; - - assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) && - jdo[36] && jdo[35] && - ~jdo[37]; - - assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) && - jdo[15]; - - always @(posedge clk) - begin - if (jxuir) - ir <= ir_in; - if (update_jdo_strobe) - jdo <= sr; - end - - - -endmodule - diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v b/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v deleted file mode 100644 index 8e3a593..0000000 --- a/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v +++ /dev/null @@ -1,239 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_jtag_debug_module_tck ( - // inputs: - MonDReg, - break_readreg, - dbrk_hit0_latch, - dbrk_hit1_latch, - dbrk_hit2_latch, - dbrk_hit3_latch, - debugack, - ir_in, - jtag_state_rti, - monitor_error, - monitor_ready, - reset_n, - resetlatch, - tck, - tdi, - tracemem_on, - tracemem_trcdata, - tracemem_tw, - trc_im_addr, - trc_on, - trc_wrap, - trigbrktype, - trigger_state_1, - vs_cdr, - vs_sdr, - vs_uir, - - // outputs: - ir_out, - jrst_n, - sr, - st_ready_test_idle, - tdo - ) -; - - output [ 1: 0] ir_out; - output jrst_n; - output [ 37: 0] sr; - output st_ready_test_idle; - output tdo; - input [ 31: 0] MonDReg; - input [ 31: 0] break_readreg; - input dbrk_hit0_latch; - input dbrk_hit1_latch; - input dbrk_hit2_latch; - input dbrk_hit3_latch; - input debugack; - input [ 1: 0] ir_in; - input jtag_state_rti; - input monitor_error; - input monitor_ready; - input reset_n; - input resetlatch; - input tck; - input tdi; - input tracemem_on; - input [ 35: 0] tracemem_trcdata; - input tracemem_tw; - input [ 6: 0] trc_im_addr; - input trc_on; - input trc_wrap; - input trigbrktype; - input trigger_state_1; - input vs_cdr; - input vs_sdr; - input vs_uir; - - reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire debugack_sync; - reg [ 1: 0] ir_out; - wire jrst_n; - wire monitor_ready_sync; - reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire st_ready_test_idle; - wire tdo; - wire unxcomplemented_resetxx1; - wire unxcomplemented_resetxx2; - always @(posedge tck) - begin - if (vs_cdr) - case (ir_in) - - 2'b00: begin - sr[35] <= debugack_sync; - sr[34] <= monitor_error; - sr[33] <= resetlatch; - sr[32 : 1] <= MonDReg; - sr[0] <= monitor_ready_sync; - end // 2'b00 - - 2'b01: begin - sr[35 : 0] <= tracemem_trcdata; - sr[37] <= tracemem_tw; - sr[36] <= tracemem_on; - end // 2'b01 - - 2'b10: begin - sr[37] <= trigger_state_1; - sr[36] <= dbrk_hit3_latch; - sr[35] <= dbrk_hit2_latch; - sr[34] <= dbrk_hit1_latch; - sr[33] <= dbrk_hit0_latch; - sr[32 : 1] <= break_readreg; - sr[0] <= trigbrktype; - end // 2'b10 - - 2'b11: begin - sr[15 : 12] <= 1'b0; - sr[11 : 2] <= trc_im_addr; - sr[1] <= trc_wrap; - sr[0] <= trc_on; - end // 2'b11 - - endcase // ir_in - if (vs_sdr) - case (DRsize) - - 3'b000: begin - sr <= {tdi, sr[37 : 2], tdi}; - end // 3'b000 - - 3'b001: begin - sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]}; - end // 3'b001 - - 3'b010: begin - sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]}; - end // 3'b010 - - 3'b011: begin - sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]}; - end // 3'b011 - - 3'b100: begin - sr <= {tdi, sr[37], tdi, sr[35 : 1]}; - end // 3'b100 - - 3'b101: begin - sr <= {tdi, sr[37 : 1]}; - end // 3'b101 - - default: begin - sr <= {tdi, sr[37 : 2], tdi}; - end // default - - endcase // DRsize - if (vs_uir) - case (ir_in) - - 2'b00: begin - DRsize <= 3'b100; - end // 2'b00 - - 2'b01: begin - DRsize <= 3'b101; - end // 2'b01 - - 2'b10: begin - DRsize <= 3'b101; - end // 2'b10 - - 2'b11: begin - DRsize <= 3'b010; - end // 2'b11 - - endcase // ir_in - end - - - assign tdo = sr[0]; - assign st_ready_test_idle = jtag_state_rti; - assign unxcomplemented_resetxx1 = jrst_n; - altera_std_synchronizer the_altera_std_synchronizer1 - ( - .clk (tck), - .din (debugack), - .dout (debugack_sync), - .reset_n (unxcomplemented_resetxx1) - ); - - defparam the_altera_std_synchronizer1.depth = 2; - - assign unxcomplemented_resetxx2 = jrst_n; - altera_std_synchronizer the_altera_std_synchronizer2 - ( - .clk (tck), - .din (monitor_ready), - .dout (monitor_ready_sync), - .reset_n (unxcomplemented_resetxx2) - ); - - defparam the_altera_std_synchronizer2.depth = 2; - - always @(posedge tck or negedge jrst_n) - begin - if (jrst_n == 0) - ir_out <= 2'b0; - else - ir_out <= {debugack_sync, monitor_ready_sync}; - end - - - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - assign jrst_n = reset_n; - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on -//synthesis read_comments_as_HDL on -// assign jrst_n = 1; -//synthesis read_comments_as_HDL off - -endmodule - diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v b/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v deleted file mode 100644 index 1fd5cb7..0000000 --- a/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v +++ /dev/null @@ -1,233 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_jtag_debug_module_wrapper ( - // inputs: - MonDReg, - break_readreg, - clk, - dbrk_hit0_latch, - dbrk_hit1_latch, - dbrk_hit2_latch, - dbrk_hit3_latch, - debugack, - monitor_error, - monitor_ready, - reset_n, - resetlatch, - tracemem_on, - tracemem_trcdata, - tracemem_tw, - trc_im_addr, - trc_on, - trc_wrap, - trigbrktype, - trigger_state_1, - - // outputs: - jdo, - jrst_n, - st_ready_test_idle, - take_action_break_a, - take_action_break_b, - take_action_break_c, - take_action_ocimem_a, - take_action_ocimem_b, - take_action_tracectrl, - take_action_tracemem_a, - take_action_tracemem_b, - take_no_action_break_a, - take_no_action_break_b, - take_no_action_break_c, - take_no_action_ocimem_a, - take_no_action_tracemem_a - ) -; - - output [ 37: 0] jdo; - output jrst_n; - output st_ready_test_idle; - output take_action_break_a; - output take_action_break_b; - output take_action_break_c; - output take_action_ocimem_a; - output take_action_ocimem_b; - output take_action_tracectrl; - output take_action_tracemem_a; - output take_action_tracemem_b; - output take_no_action_break_a; - output take_no_action_break_b; - output take_no_action_break_c; - output take_no_action_ocimem_a; - output take_no_action_tracemem_a; - input [ 31: 0] MonDReg; - input [ 31: 0] break_readreg; - input clk; - input dbrk_hit0_latch; - input dbrk_hit1_latch; - input dbrk_hit2_latch; - input dbrk_hit3_latch; - input debugack; - input monitor_error; - input monitor_ready; - input reset_n; - input resetlatch; - input tracemem_on; - input [ 35: 0] tracemem_trcdata; - input tracemem_tw; - input [ 6: 0] trc_im_addr; - input trc_on; - input trc_wrap; - input trigbrktype; - input trigger_state_1; - - wire [ 37: 0] jdo; - wire jrst_n; - wire [ 37: 0] sr; - wire st_ready_test_idle; - wire take_action_break_a; - wire take_action_break_b; - wire take_action_break_c; - wire take_action_ocimem_a; - wire take_action_ocimem_b; - wire take_action_tracectrl; - wire take_action_tracemem_a; - wire take_action_tracemem_b; - wire take_no_action_break_a; - wire take_no_action_break_b; - wire take_no_action_break_c; - wire take_no_action_ocimem_a; - wire take_no_action_tracemem_a; - wire vji_cdr; - wire [ 1: 0] vji_ir_in; - wire [ 1: 0] vji_ir_out; - wire vji_rti; - wire vji_sdr; - wire vji_tck; - wire vji_tdi; - wire vji_tdo; - wire vji_udr; - wire vji_uir; - //Change the sld_virtual_jtag_basic's defparams to - //switch between a regular Nios II or an internally embedded Nios II. - //For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34. - //For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135. - nios_system_nios2_processor_jtag_debug_module_tck the_nios_system_nios2_processor_jtag_debug_module_tck - ( - .MonDReg (MonDReg), - .break_readreg (break_readreg), - .dbrk_hit0_latch (dbrk_hit0_latch), - .dbrk_hit1_latch (dbrk_hit1_latch), - .dbrk_hit2_latch (dbrk_hit2_latch), - .dbrk_hit3_latch (dbrk_hit3_latch), - .debugack (debugack), - .ir_in (vji_ir_in), - .ir_out (vji_ir_out), - .jrst_n (jrst_n), - .jtag_state_rti (vji_rti), - .monitor_error (monitor_error), - .monitor_ready (monitor_ready), - .reset_n (reset_n), - .resetlatch (resetlatch), - .sr (sr), - .st_ready_test_idle (st_ready_test_idle), - .tck (vji_tck), - .tdi (vji_tdi), - .tdo (vji_tdo), - .tracemem_on (tracemem_on), - .tracemem_trcdata (tracemem_trcdata), - .tracemem_tw (tracemem_tw), - .trc_im_addr (trc_im_addr), - .trc_on (trc_on), - .trc_wrap (trc_wrap), - .trigbrktype (trigbrktype), - .trigger_state_1 (trigger_state_1), - .vs_cdr (vji_cdr), - .vs_sdr (vji_sdr), - .vs_uir (vji_uir) - ); - - nios_system_nios2_processor_jtag_debug_module_sysclk the_nios_system_nios2_processor_jtag_debug_module_sysclk - ( - .clk (clk), - .ir_in (vji_ir_in), - .jdo (jdo), - .sr (sr), - .take_action_break_a (take_action_break_a), - .take_action_break_b (take_action_break_b), - .take_action_break_c (take_action_break_c), - .take_action_ocimem_a (take_action_ocimem_a), - .take_action_ocimem_b (take_action_ocimem_b), - .take_action_tracectrl (take_action_tracectrl), - .take_action_tracemem_a (take_action_tracemem_a), - .take_action_tracemem_b (take_action_tracemem_b), - .take_no_action_break_a (take_no_action_break_a), - .take_no_action_break_b (take_no_action_break_b), - .take_no_action_break_c (take_no_action_break_c), - .take_no_action_ocimem_a (take_no_action_ocimem_a), - .take_no_action_tracemem_a (take_no_action_tracemem_a), - .vs_udr (vji_udr), - .vs_uir (vji_uir) - ); - - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - assign vji_tck = 1'b0; - assign vji_tdi = 1'b0; - assign vji_sdr = 1'b0; - assign vji_cdr = 1'b0; - assign vji_rti = 1'b0; - assign vji_uir = 1'b0; - assign vji_udr = 1'b0; - assign vji_ir_in = 2'b0; - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on -//synthesis read_comments_as_HDL on -// sld_virtual_jtag_basic nios_system_nios2_processor_jtag_debug_module_phy -// ( -// .ir_in (vji_ir_in), -// .ir_out (vji_ir_out), -// .jtag_state_rti (vji_rti), -// .tck (vji_tck), -// .tdi (vji_tdi), -// .tdo (vji_tdo), -// .virtual_state_cdr (vji_cdr), -// .virtual_state_sdr (vji_sdr), -// .virtual_state_udr (vji_udr), -// .virtual_state_uir (vji_uir) -// ); -// -// defparam nios_system_nios2_processor_jtag_debug_module_phy.sld_auto_instance_index = "YES", -// nios_system_nios2_processor_jtag_debug_module_phy.sld_instance_index = 0, -// nios_system_nios2_processor_jtag_debug_module_phy.sld_ir_width = 2, -// nios_system_nios2_processor_jtag_debug_module_phy.sld_mfg_id = 70, -// nios_system_nios2_processor_jtag_debug_module_phy.sld_sim_action = "", -// nios_system_nios2_processor_jtag_debug_module_phy.sld_sim_n_scan = 0, -// nios_system_nios2_processor_jtag_debug_module_phy.sld_sim_total_length = 0, -// nios_system_nios2_processor_jtag_debug_module_phy.sld_type_id = 34, -// nios_system_nios2_processor_jtag_debug_module_phy.sld_version = 3; -// -//synthesis read_comments_as_HDL off - -endmodule - diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v b/db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v deleted file mode 100644 index 0046686..0000000 --- a/db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v +++ /dev/null @@ -1,37 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_oci_test_bench ( - // inputs: - dct_buffer, - dct_count, - test_ending, - test_has_ended - ) -; - - input [ 29: 0] dct_buffer; - input [ 3: 0] dct_count; - input test_ending; - input test_has_ended; - - -endmodule - diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor_ociram_default_contents.mif b/db/ip/nios_system/submodules/nios_system_nios2_processor_ociram_default_contents.mif deleted file mode 100644 index 44481aa..0000000 --- a/db/ip/nios_system/submodules/nios_system_nios2_processor_ociram_default_contents.mif +++ /dev/null @@ -1,267 +0,0 @@ --- Contents are randomly generated during RTL generation. -WIDTH=32; -DEPTH=256; - -ADDRESS_RADIX=HEX; -DATA_RADIX=HEX; - -CONTENT BEGIN - -00 : 88997af9; -01 : abaae595; -02 : 32fd14d1; -03 : b66193c4; -04 : c6a6aa09; -05 : 0b43de5b; -06 : d1d93028; -07 : bcd08e2a; -08 : 1c8bae85; -09 : b11dad63; -0a : 864ddf62; -0b : 68301486; -0c : 51a3d8d0; -0d : 7af7d39e; -0e : 4761b503; -0f : 2a976e14; -10 : 98141041; -11 : 4c1f6471; -12 : 41dc0a35; -13 : 7d484ae3; -14 : 2a1329f3; -15 : 44ecf499; -16 : dccdd125; -17 : 240142e9; -18 : 3b7e4b05; -19 : bb92e762; -1a : 4594a3c5; -1b : ea0d940f; -1c : 66525d7c; -1d : 0f552242; -1e : 452bd52d; -1f : d1f4ed11; -20 : 5d590422; -21 : c8016b5f; -22 : 9ab94f07; -23 : 16bac9b4; -24 : fe569ae3; -25 : c6e1e6e7; -26 : 2ff19932; -27 : feb058ad; -28 : 1dcce651; -29 : e18b9bfb; -2a : e2f4fc64; -2b : 05d34847; -2c : 077a8143; -2d : 2ce4207f; -2e : 3f3e5113; -2f : c24d2803; -30 : e289b503; -31 : d16bcd4e; -32 : 57a841cf; -33 : 1194f754; -34 : 5c925a31; -35 : 40fd6946; -36 : e397e5d7; -37 : eada7553; -38 : eba8ec01; -39 : f5b39d0b; -3a : 88af39a3; -3b : 5b7f243e; -3c : 4f2bb4ba; -3d : 9451a234; -3e : 10fd984d; -3f : ad4ef4f7; -40 : 7fe97f8b; -41 : 08ea614d; -42 : 9f2c5cf4; -43 : 3f90b7a2; -44 : 8c2bc774; -45 : 45dd63a5; -46 : 3204329c; -47 : 9909be0d; -48 : be65c97b; -49 : 78f3d4a4; -4a : 3ee8b71c; -4b : 9e9a0de4; -4c : 56db426b; -4d : e6869d81; -4e : 20ab0652; -4f : 05d247ed; -50 : 1edccf12; -51 : 1e483b5a; -52 : 8e48ef1e; -53 : f19aefbf; -54 : 98335d23; -55 : 954ac923; -56 : 4679ced6; -57 : ae18d9b8; -58 : be57db48; -59 : 2af933e3; -5a : 3f04e244; -5b : 5d11c958; -5c : 65bda8cb; -5d : c53fe664; -5e : 797ceac8; -5f : aaa406e5; -60 : f785e24e; -61 : 95510077; -62 : 5b6f55a3; -63 : 2a3c749a; -64 : a92e6ae6; -65 : b2117fb0; -66 : 262a254e; -67 : b8c4da74; -68 : f69070ee; -69 : 9e7f80b8; -6a : 834528b4; -6b : 4aaf6d98; -6c : 96023372; -6d : d11663ed; -6e : 33a3c007; -6f : 0e7f06ee; -70 : 34385787; -71 : 2edfd7b0; -72 : 00d60e4b; -73 : 49535c30; -74 : e83f5c14; -75 : 5e0c4c59; -76 : 1d7b944a; -77 : 6ae69731; -78 : bf8414e4; -79 : 7451c212; -7a : 74ede6d2; -7b : 080eafa5; -7c : f21052d8; -7d : cc0819fb; -7e : 8993e5b6; -7f : e20f2df6; -80 : 0f267a65; -81 : 7a8e8407; -82 : e7be656d; -83 : 01ba4ca3; -84 : 7f998e44; -85 : 29d83420; -86 : 149f9a73; -87 : 643ae51e; -88 : 125714d3; -89 : 6e49dc21; -8a : 0b227946; -8b : 360a837d; -8c : b2187074; -8d : 17b0bdbd; -8e : 938fc73d; -8f : e73f501e; -90 : 70b5b87e; -91 : 2a2aed8a; -92 : f96cc881; -93 : 021b49e1; -94 : 8691600d; -95 : b45e1d12; -96 : 64d9644e; -97 : 486cbaf9; -98 : 386acf20; -99 : 0d1384d4; -9a : 62455f77; -9b : 866fde20; -9c : 006fecec; -9d : 94e84514; -9e : 7babc333; -9f : afaa8445; -a0 : b1175e3a; -a1 : e08de629; -a2 : 7f12a52d; -a3 : 0e322909; -a4 : 18784dc6; -a5 : b23bcc20; -a6 : 266c9e34; -a7 : c857eaf3; -a8 : 2ae3b164; -a9 : 038acf2a; -aa : c1abc60d; -ab : 8af787bd; -ac : 043723a9; -ad : c37c952d; -ae : 693a361f; -af : da4b8e99; -b0 : fb8fdb10; -b1 : 4d6365f2; -b2 : 712358e9; -b3 : 85dae0fa; -b4 : 7e82a418; -b5 : d3493768; -b6 : 739c65ec; -b7 : 73b66b19; -b8 : 22142816; -b9 : ff498322; -ba : 3266495e; -bb : e26e8214; -bc : c8c47131; -bd : 660793d8; -be : 689f8d69; -bf : faae340b; -c0 : 37518ba7; -c1 : f2865fe5; -c2 : 1bb44f3d; -c3 : 3bce44c5; -c4 : aff2d188; -c5 : 985442da; -c6 : 85bb58bd; -c7 : 0c53135d; -c8 : 495f80bc; -c9 : 853c95dc; -ca : dde937f1; -cb : 418f9452; -cc : 7669641c; -cd : 0e752434; -ce : b0fe17a7; -cf : d1be9b88; -d0 : cfbfeb76; -d1 : 80b48a11; -d2 : 9327c69e; -d3 : beca5a88; -d4 : e71d428f; -d5 : b318d275; -d6 : 56fea35e; -d7 : 140cd6bd; -d8 : b8c937ce; -d9 : 540eea36; -da : ee58fc7f; -db : 5615c389; -dc : 46692ad0; -dd : 5c713e51; -de : 6ba95f60; -df : 0e166732; -e0 : ac0e49f5; -e1 : c9a5ea76; -e2 : 05b04d86; -e3 : b29ac712; -e4 : 4e344493; -e5 : d45ede48; -e6 : 3da7e426; -e7 : 4d6a8937; -e8 : 99b59bd4; -e9 : 1f8a5751; -ea : 8b07e64e; -eb : b4dcd496; -ec : 42f84fe6; -ed : f1d5952f; -ee : a2e5a42d; -ef : 15b1af16; -f0 : 168012bc; -f1 : 2e276612; -f2 : 89913eaa; -f3 : c607a1a2; -f4 : fd8b544d; -f5 : aec31a53; -f6 : 25f958ad; -f7 : 365903ec; -f8 : 14761865; -f9 : 568cc23b; -fa : b0386305; -fb : fb9ebd8a; -fc : a25911d4; -fd : 806e3fbb; -fe : 9df35264; -ff : d62b3814; - -END; diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor_rf_ram_a.mif b/db/ip/nios_system/submodules/nios_system_nios2_processor_rf_ram_a.mif deleted file mode 100644 index 7969f10..0000000 --- a/db/ip/nios_system/submodules/nios_system_nios2_processor_rf_ram_a.mif +++ /dev/null @@ -1,42 +0,0 @@ -WIDTH=32; -DEPTH=32; - -ADDRESS_RADIX=HEX; -DATA_RADIX=HEX; - -CONTENT BEGIN - -00 : deadbeef; -01 : deadbeef; -02 : deadbeef; -03 : deadbeef; -04 : deadbeef; -05 : deadbeef; -06 : deadbeef; -07 : deadbeef; -08 : deadbeef; -09 : deadbeef; -0a : deadbeef; -0b : deadbeef; -0c : deadbeef; -0d : deadbeef; -0e : deadbeef; -0f : deadbeef; -10 : deadbeef; -11 : deadbeef; -12 : deadbeef; -13 : deadbeef; -14 : deadbeef; -15 : deadbeef; -16 : deadbeef; -17 : deadbeef; -18 : deadbeef; -19 : deadbeef; -1a : deadbeef; -1b : deadbeef; -1c : deadbeef; -1d : deadbeef; -1e : deadbeef; -1f : deadbeef; - -END; diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor_rf_ram_b.mif b/db/ip/nios_system/submodules/nios_system_nios2_processor_rf_ram_b.mif deleted file mode 100644 index 7969f10..0000000 --- a/db/ip/nios_system/submodules/nios_system_nios2_processor_rf_ram_b.mif +++ /dev/null @@ -1,42 +0,0 @@ -WIDTH=32; -DEPTH=32; - -ADDRESS_RADIX=HEX; -DATA_RADIX=HEX; - -CONTENT BEGIN - -00 : deadbeef; -01 : deadbeef; -02 : deadbeef; -03 : deadbeef; -04 : deadbeef; -05 : deadbeef; -06 : deadbeef; -07 : deadbeef; -08 : deadbeef; -09 : deadbeef; -0a : deadbeef; -0b : deadbeef; -0c : deadbeef; -0d : deadbeef; -0e : deadbeef; -0f : deadbeef; -10 : deadbeef; -11 : deadbeef; -12 : deadbeef; -13 : deadbeef; -14 : deadbeef; -15 : deadbeef; -16 : deadbeef; -17 : deadbeef; -18 : deadbeef; -19 : deadbeef; -1a : deadbeef; -1b : deadbeef; -1c : deadbeef; -1d : deadbeef; -1e : deadbeef; -1f : deadbeef; - -END; diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v b/db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v deleted file mode 100644 index 9ce093e..0000000 --- a/db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v +++ /dev/null @@ -1,667 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_test_bench ( - // inputs: - D_iw, - D_iw_op, - D_iw_opx, - D_valid, - E_valid, - F_pcb, - F_valid, - R_ctrl_ld, - R_ctrl_ld_non_io, - R_dst_regnum, - R_wr_dst_reg, - W_valid, - W_vinst, - W_wr_data, - av_ld_data_aligned_unfiltered, - clk, - d_address, - d_byteenable, - d_read, - d_write_nxt, - i_address, - i_read, - i_readdata, - i_waitrequest, - reset_n, - - // outputs: - av_ld_data_aligned_filtered, - d_write, - test_has_ended - ) -; - - output [ 31: 0] av_ld_data_aligned_filtered; - output d_write; - output test_has_ended; - input [ 31: 0] D_iw; - input [ 5: 0] D_iw_op; - input [ 5: 0] D_iw_opx; - input D_valid; - input E_valid; - input [ 18: 0] F_pcb; - input F_valid; - input R_ctrl_ld; - input R_ctrl_ld_non_io; - input [ 4: 0] R_dst_regnum; - input R_wr_dst_reg; - input W_valid; - input [ 55: 0] W_vinst; - input [ 31: 0] W_wr_data; - input [ 31: 0] av_ld_data_aligned_unfiltered; - input clk; - input [ 18: 0] d_address; - input [ 3: 0] d_byteenable; - input d_read; - input d_write_nxt; - input [ 18: 0] i_address; - input i_read; - input [ 31: 0] i_readdata; - input i_waitrequest; - input reset_n; - - wire D_op_add; - wire D_op_addi; - wire D_op_and; - wire D_op_andhi; - wire D_op_andi; - wire D_op_beq; - wire D_op_bge; - wire D_op_bgeu; - wire D_op_blt; - wire D_op_bltu; - wire D_op_bne; - wire D_op_br; - wire D_op_break; - wire D_op_bret; - wire D_op_call; - wire D_op_callr; - wire D_op_cmpeq; - wire D_op_cmpeqi; - wire D_op_cmpge; - wire D_op_cmpgei; - wire D_op_cmpgeu; - wire D_op_cmpgeui; - wire D_op_cmplt; - wire D_op_cmplti; - wire D_op_cmpltu; - wire D_op_cmpltui; - wire D_op_cmpne; - wire D_op_cmpnei; - wire D_op_crst; - wire D_op_custom; - wire D_op_div; - wire D_op_divu; - wire D_op_eret; - wire D_op_flushd; - wire D_op_flushda; - wire D_op_flushi; - wire D_op_flushp; - wire D_op_hbreak; - wire D_op_initd; - wire D_op_initda; - wire D_op_initi; - wire D_op_intr; - wire D_op_jmp; - wire D_op_jmpi; - wire D_op_ldb; - wire D_op_ldbio; - wire D_op_ldbu; - wire D_op_ldbuio; - wire D_op_ldh; - wire D_op_ldhio; - wire D_op_ldhu; - wire D_op_ldhuio; - wire D_op_ldl; - wire D_op_ldw; - wire D_op_ldwio; - wire D_op_mul; - wire D_op_muli; - wire D_op_mulxss; - wire D_op_mulxsu; - wire D_op_mulxuu; - wire D_op_nextpc; - wire D_op_nor; - wire D_op_opx; - wire D_op_or; - wire D_op_orhi; - wire D_op_ori; - wire D_op_rdctl; - wire D_op_rdprs; - wire D_op_ret; - wire D_op_rol; - wire D_op_roli; - wire D_op_ror; - wire D_op_rsv02; - wire D_op_rsv09; - wire D_op_rsv10; - wire D_op_rsv17; - wire D_op_rsv18; - wire D_op_rsv25; - wire D_op_rsv26; - wire D_op_rsv33; - wire D_op_rsv34; - wire D_op_rsv41; - wire D_op_rsv42; - wire D_op_rsv49; - wire D_op_rsv57; - wire D_op_rsv61; - wire D_op_rsv62; - wire D_op_rsv63; - wire D_op_rsvx00; - wire D_op_rsvx10; - wire D_op_rsvx15; - wire D_op_rsvx17; - wire D_op_rsvx21; - wire D_op_rsvx25; - wire D_op_rsvx33; - wire D_op_rsvx34; - wire D_op_rsvx35; - wire D_op_rsvx42; - wire D_op_rsvx43; - wire D_op_rsvx44; - wire D_op_rsvx47; - wire D_op_rsvx50; - wire D_op_rsvx51; - wire D_op_rsvx55; - wire D_op_rsvx56; - wire D_op_rsvx60; - wire D_op_rsvx63; - wire D_op_sll; - wire D_op_slli; - wire D_op_sra; - wire D_op_srai; - wire D_op_srl; - wire D_op_srli; - wire D_op_stb; - wire D_op_stbio; - wire D_op_stc; - wire D_op_sth; - wire D_op_sthio; - wire D_op_stw; - wire D_op_stwio; - wire D_op_sub; - wire D_op_sync; - wire D_op_trap; - wire D_op_wrctl; - wire D_op_wrprs; - wire D_op_xor; - wire D_op_xorhi; - wire D_op_xori; - wire [ 31: 0] av_ld_data_aligned_filtered; - wire av_ld_data_aligned_unfiltered_0_is_x; - wire av_ld_data_aligned_unfiltered_10_is_x; - wire av_ld_data_aligned_unfiltered_11_is_x; - wire av_ld_data_aligned_unfiltered_12_is_x; - wire av_ld_data_aligned_unfiltered_13_is_x; - wire av_ld_data_aligned_unfiltered_14_is_x; - wire av_ld_data_aligned_unfiltered_15_is_x; - wire av_ld_data_aligned_unfiltered_16_is_x; - wire av_ld_data_aligned_unfiltered_17_is_x; - wire av_ld_data_aligned_unfiltered_18_is_x; - wire av_ld_data_aligned_unfiltered_19_is_x; - wire av_ld_data_aligned_unfiltered_1_is_x; - wire av_ld_data_aligned_unfiltered_20_is_x; - wire av_ld_data_aligned_unfiltered_21_is_x; - wire av_ld_data_aligned_unfiltered_22_is_x; - wire av_ld_data_aligned_unfiltered_23_is_x; - wire av_ld_data_aligned_unfiltered_24_is_x; - wire av_ld_data_aligned_unfiltered_25_is_x; - wire av_ld_data_aligned_unfiltered_26_is_x; - wire av_ld_data_aligned_unfiltered_27_is_x; - wire av_ld_data_aligned_unfiltered_28_is_x; - wire av_ld_data_aligned_unfiltered_29_is_x; - wire av_ld_data_aligned_unfiltered_2_is_x; - wire av_ld_data_aligned_unfiltered_30_is_x; - wire av_ld_data_aligned_unfiltered_31_is_x; - wire av_ld_data_aligned_unfiltered_3_is_x; - wire av_ld_data_aligned_unfiltered_4_is_x; - wire av_ld_data_aligned_unfiltered_5_is_x; - wire av_ld_data_aligned_unfiltered_6_is_x; - wire av_ld_data_aligned_unfiltered_7_is_x; - wire av_ld_data_aligned_unfiltered_8_is_x; - wire av_ld_data_aligned_unfiltered_9_is_x; - reg d_write; - wire test_has_ended; - assign D_op_call = D_iw_op == 0; - assign D_op_jmpi = D_iw_op == 1; - assign D_op_ldbu = D_iw_op == 3; - assign D_op_addi = D_iw_op == 4; - assign D_op_stb = D_iw_op == 5; - assign D_op_br = D_iw_op == 6; - assign D_op_ldb = D_iw_op == 7; - assign D_op_cmpgei = D_iw_op == 8; - assign D_op_ldhu = D_iw_op == 11; - assign D_op_andi = D_iw_op == 12; - assign D_op_sth = D_iw_op == 13; - assign D_op_bge = D_iw_op == 14; - assign D_op_ldh = D_iw_op == 15; - assign D_op_cmplti = D_iw_op == 16; - assign D_op_initda = D_iw_op == 19; - assign D_op_ori = D_iw_op == 20; - assign D_op_stw = D_iw_op == 21; - assign D_op_blt = D_iw_op == 22; - assign D_op_ldw = D_iw_op == 23; - assign D_op_cmpnei = D_iw_op == 24; - assign D_op_flushda = D_iw_op == 27; - assign D_op_xori = D_iw_op == 28; - assign D_op_stc = D_iw_op == 29; - assign D_op_bne = D_iw_op == 30; - assign D_op_ldl = D_iw_op == 31; - assign D_op_cmpeqi = D_iw_op == 32; - assign D_op_ldbuio = D_iw_op == 35; - assign D_op_muli = D_iw_op == 36; - assign D_op_stbio = D_iw_op == 37; - assign D_op_beq = D_iw_op == 38; - assign D_op_ldbio = D_iw_op == 39; - assign D_op_cmpgeui = D_iw_op == 40; - assign D_op_ldhuio = D_iw_op == 43; - assign D_op_andhi = D_iw_op == 44; - assign D_op_sthio = D_iw_op == 45; - assign D_op_bgeu = D_iw_op == 46; - assign D_op_ldhio = D_iw_op == 47; - assign D_op_cmpltui = D_iw_op == 48; - assign D_op_initd = D_iw_op == 51; - assign D_op_orhi = D_iw_op == 52; - assign D_op_stwio = D_iw_op == 53; - assign D_op_bltu = D_iw_op == 54; - assign D_op_ldwio = D_iw_op == 55; - assign D_op_rdprs = D_iw_op == 56; - assign D_op_flushd = D_iw_op == 59; - assign D_op_xorhi = D_iw_op == 60; - assign D_op_rsv02 = D_iw_op == 2; - assign D_op_rsv09 = D_iw_op == 9; - assign D_op_rsv10 = D_iw_op == 10; - assign D_op_rsv17 = D_iw_op == 17; - assign D_op_rsv18 = D_iw_op == 18; - assign D_op_rsv25 = D_iw_op == 25; - assign D_op_rsv26 = D_iw_op == 26; - assign D_op_rsv33 = D_iw_op == 33; - assign D_op_rsv34 = D_iw_op == 34; - assign D_op_rsv41 = D_iw_op == 41; - assign D_op_rsv42 = D_iw_op == 42; - assign D_op_rsv49 = D_iw_op == 49; - assign D_op_rsv57 = D_iw_op == 57; - assign D_op_rsv61 = D_iw_op == 61; - assign D_op_rsv62 = D_iw_op == 62; - assign D_op_rsv63 = D_iw_op == 63; - assign D_op_eret = D_op_opx & (D_iw_opx == 1); - assign D_op_roli = D_op_opx & (D_iw_opx == 2); - assign D_op_rol = D_op_opx & (D_iw_opx == 3); - assign D_op_flushp = D_op_opx & (D_iw_opx == 4); - assign D_op_ret = D_op_opx & (D_iw_opx == 5); - assign D_op_nor = D_op_opx & (D_iw_opx == 6); - assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7); - assign D_op_cmpge = D_op_opx & (D_iw_opx == 8); - assign D_op_bret = D_op_opx & (D_iw_opx == 9); - assign D_op_ror = D_op_opx & (D_iw_opx == 11); - assign D_op_flushi = D_op_opx & (D_iw_opx == 12); - assign D_op_jmp = D_op_opx & (D_iw_opx == 13); - assign D_op_and = D_op_opx & (D_iw_opx == 14); - assign D_op_cmplt = D_op_opx & (D_iw_opx == 16); - assign D_op_slli = D_op_opx & (D_iw_opx == 18); - assign D_op_sll = D_op_opx & (D_iw_opx == 19); - assign D_op_wrprs = D_op_opx & (D_iw_opx == 20); - assign D_op_or = D_op_opx & (D_iw_opx == 22); - assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23); - assign D_op_cmpne = D_op_opx & (D_iw_opx == 24); - assign D_op_srli = D_op_opx & (D_iw_opx == 26); - assign D_op_srl = D_op_opx & (D_iw_opx == 27); - assign D_op_nextpc = D_op_opx & (D_iw_opx == 28); - assign D_op_callr = D_op_opx & (D_iw_opx == 29); - assign D_op_xor = D_op_opx & (D_iw_opx == 30); - assign D_op_mulxss = D_op_opx & (D_iw_opx == 31); - assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32); - assign D_op_divu = D_op_opx & (D_iw_opx == 36); - assign D_op_div = D_op_opx & (D_iw_opx == 37); - assign D_op_rdctl = D_op_opx & (D_iw_opx == 38); - assign D_op_mul = D_op_opx & (D_iw_opx == 39); - assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40); - assign D_op_initi = D_op_opx & (D_iw_opx == 41); - assign D_op_trap = D_op_opx & (D_iw_opx == 45); - assign D_op_wrctl = D_op_opx & (D_iw_opx == 46); - assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48); - assign D_op_add = D_op_opx & (D_iw_opx == 49); - assign D_op_break = D_op_opx & (D_iw_opx == 52); - assign D_op_hbreak = D_op_opx & (D_iw_opx == 53); - assign D_op_sync = D_op_opx & (D_iw_opx == 54); - assign D_op_sub = D_op_opx & (D_iw_opx == 57); - assign D_op_srai = D_op_opx & (D_iw_opx == 58); - assign D_op_sra = D_op_opx & (D_iw_opx == 59); - assign D_op_intr = D_op_opx & (D_iw_opx == 61); - assign D_op_crst = D_op_opx & (D_iw_opx == 62); - assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0); - assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10); - assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15); - assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17); - assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21); - assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25); - assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33); - assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34); - assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35); - assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42); - assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43); - assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44); - assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47); - assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50); - assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51); - assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55); - assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56); - assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60); - assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63); - assign D_op_opx = D_iw_op == 58; - assign D_op_custom = D_iw_op == 50; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - d_write <= 0; - else - d_write <= d_write_nxt; - end - - - assign test_has_ended = 1'b0; - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - //Clearing 'X' data bits - assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx; - - assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0]; - assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx; - assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1]; - assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx; - assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2]; - assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx; - assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3]; - assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx; - assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4]; - assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx; - assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5]; - assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx; - assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6]; - assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx; - assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7]; - assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx; - assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8]; - assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx; - assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9]; - assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx; - assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10]; - assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx; - assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11]; - assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx; - assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12]; - assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx; - assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13]; - assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx; - assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14]; - assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx; - assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15]; - assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx; - assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16]; - assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx; - assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17]; - assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx; - assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18]; - assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx; - assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19]; - assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx; - assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20]; - assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx; - assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21]; - assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx; - assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22]; - assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx; - assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23]; - assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx; - assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24]; - assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx; - assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25]; - assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx; - assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26]; - assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx; - assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27]; - assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx; - assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28]; - assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx; - assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29]; - assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx; - assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30]; - assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx; - assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31]; - always @(posedge clk) - begin - if (reset_n) - if (^(F_valid) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/F_valid is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk) - begin - if (reset_n) - if (^(D_valid) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/D_valid is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk) - begin - if (reset_n) - if (^(E_valid) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/E_valid is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk) - begin - if (reset_n) - if (^(W_valid) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/W_valid is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (W_valid) - if (^(R_wr_dst_reg) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/R_wr_dst_reg is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (W_valid & R_wr_dst_reg) - if (^(W_wr_data) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/W_wr_data is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (W_valid & R_wr_dst_reg) - if (^(R_dst_regnum) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/R_dst_regnum is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk) - begin - if (reset_n) - if (^(d_write) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_write is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (d_write) - if (^(d_byteenable) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_byteenable is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (d_write | d_read) - if (^(d_address) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_address is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk) - begin - if (reset_n) - if (^(d_read) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_read is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk) - begin - if (reset_n) - if (^(i_read) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/i_read is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (i_read) - if (^(i_address) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/i_address is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (i_read & ~i_waitrequest) - if (^(i_readdata) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/i_readdata is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (W_valid & R_ctrl_ld) - if (^(av_ld_data_aligned_unfiltered) === 1'bx) - begin - $write("%0d ns: WARNING: nios_system_nios2_processor_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time); - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (W_valid & R_wr_dst_reg) - if (^(W_wr_data) === 1'bx) - begin - $write("%0d ns: WARNING: nios_system_nios2_processor_test_bench/W_wr_data is 'x'\n", $time); - end - end - - - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on -//synthesis read_comments_as_HDL on -// -// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered; -// -//synthesis read_comments_as_HDL off - -endmodule - diff --git a/db/ip/nios_system/submodules/nios_system_onchip_memory.hex b/db/ip/nios_system/submodules/nios_system_onchip_memory.hex deleted file mode 100644 index e265501..0000000 --- a/db/ip/nios_system/submodules/nios_system_onchip_memory.hex +++ /dev/null @@ -1,51201 +0,0 @@ -:0400000000000000FC -:0400010000000000FB -:0400020000000000FA -:0400030000000000F9 -:0400040000000000F8 -:0400050000000000F7 -:0400060000000000F6 -:0400070000000000F5 -:0400080000000000F4 -:0400090000000000F3 -:04000A0000000000F2 -:04000B0000000000F1 -:04000C0000000000F0 -:04000D0000000000EF -:04000E0000000000EE -:04000F0000000000ED -:0400100000000000EC -:0400110000000000EB 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a/db/ip/nios_system/submodules/nios_system_onchip_memory.v b/db/ip/nios_system/submodules/nios_system_onchip_memory.v deleted file mode 100644 index c12e1cd..0000000 --- a/db/ip/nios_system/submodules/nios_system_onchip_memory.v +++ /dev/null @@ -1,85 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_onchip_memory ( - // inputs: - address, - byteenable, - chipselect, - clk, - clken, - reset, - reset_req, - write, - writedata, - - // outputs: - readdata - ) -; - - parameter INIT_FILE = "nios_system_onchip_memory.hex"; - - - output [ 31: 0] readdata; - input [ 15: 0] address; - input [ 3: 0] byteenable; - input chipselect; - input clk; - input clken; - input reset; - input reset_req; - input write; - input [ 31: 0] writedata; - - wire clocken0; - wire [ 31: 0] readdata; - wire wren; - assign wren = chipselect & write; - assign clocken0 = clken & ~reset_req; - altsyncram the_altsyncram - ( - .address_a (address), - .byteena_a (byteenable), - .clock0 (clk), - .clocken0 (clocken0), - .data_a (writedata), - .q_a (readdata), - .wren_a (wren) - ); - - defparam the_altsyncram.byte_size = 8, - the_altsyncram.init_file = INIT_FILE, - the_altsyncram.lpm_type = "altsyncram", - the_altsyncram.maximum_depth = 51200, - the_altsyncram.numwords_a = 51200, - the_altsyncram.operation_mode = "SINGLE_PORT", - the_altsyncram.outdata_reg_a = "UNREGISTERED", - the_altsyncram.ram_block_type = "AUTO", - the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", - the_altsyncram.width_a = 32, - the_altsyncram.width_byteena_a = 4, - the_altsyncram.widthad_a = 16; - - //s1, which is an e_avalon_slave - //s2, which is an e_avalon_slave - -endmodule - diff --git a/db/ip/nios_system/submodules/nios_system_pio_0.v b/db/ip/nios_system/submodules/nios_system_pio_0.v deleted file mode 100644 index 9cd2e61..0000000 --- a/db/ip/nios_system/submodules/nios_system_pio_0.v +++ /dev/null @@ -1,58 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_pio_0 ( - // inputs: - address, - clk, - in_port, - reset_n, - - // outputs: - readdata - ) -; - - output [ 31: 0] readdata; - input [ 1: 0] address; - input clk; - input [ 17: 0] in_port; - input reset_n; - - wire clk_en; - wire [ 17: 0] data_in; - wire [ 17: 0] read_mux_out; - reg [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {18 {(address == 0)}} & data_in; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - readdata <= 0; - else if (clk_en) - readdata <= {32'b0 | read_mux_out}; - end - - - assign data_in = in_port; - -endmodule - diff --git a/db/ip/nios_system/submodules/nios_system_push_switches.v b/db/ip/nios_system/submodules/nios_system_push_switches.v deleted file mode 100644 index 5b3cb8d..0000000 --- a/db/ip/nios_system/submodules/nios_system_push_switches.v +++ /dev/null @@ -1,58 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_push_switches ( - // inputs: - address, - clk, - in_port, - reset_n, - - // outputs: - readdata - ) -; - - output [ 31: 0] readdata; - input [ 1: 0] address; - input clk; - input [ 2: 0] in_port; - input reset_n; - - wire clk_en; - wire [ 2: 0] data_in; - wire [ 2: 0] read_mux_out; - reg [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {3 {(address == 0)}} & data_in; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - readdata <= 0; - else if (clk_en) - readdata <= {32'b0 | read_mux_out}; - end - - - assign data_in = in_port; - -endmodule - diff --git a/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux.sv b/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux.sv deleted file mode 100644 index 44c4d45..0000000 --- a/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux.sv +++ /dev/null @@ -1,116 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------- -// Merlin Demultiplexer -// -// Asserts valid on the appropriate output -// given a one-hot channel signal. -// ------------------------------------- - -`timescale 1 ns / 1 ns - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_rsp_xbar_demux -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// NUM_OUTPUTS: 2 -// VALID_WIDTH: 1 -// ------------------------------------------ - -//------------------------------------------ -// Message Supression Used -// QIS Warnings -// 15610 - Warning: Design contains x input pin(s) that do not drive logic -//------------------------------------------ - -module nios_system_rsp_xbar_demux -( - // ------------------- - // Sink - // ------------------- - input [1-1 : 0] sink_valid, - input [96-1 : 0] sink_data, // ST_DATA_W=96 - input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Sources - // ------------------- - output reg src0_valid, - output reg [96-1 : 0] src0_data, // ST_DATA_W=96 - output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 - output reg src0_startofpacket, - output reg src0_endofpacket, - input src0_ready, - - output reg src1_valid, - output reg [96-1 : 0] src1_data, // ST_DATA_W=96 - output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18 - output reg src1_startofpacket, - output reg src1_endofpacket, - input src1_ready, - - - // ------------------- - // Clock & Reset - // ------------------- - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk - input clk, - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset - input reset - -); - - localparam NUM_OUTPUTS = 2; - wire [NUM_OUTPUTS - 1 : 0] ready_vector; - - // ------------------- - // Demux - // ------------------- - always @* begin - src0_data = sink_data; - src0_startofpacket = sink_startofpacket; - src0_endofpacket = sink_endofpacket; - src0_channel = sink_channel >> NUM_OUTPUTS; - - src0_valid = sink_channel[0] && sink_valid; - - src1_data = sink_data; - src1_startofpacket = sink_startofpacket; - src1_endofpacket = sink_endofpacket; - src1_channel = sink_channel >> NUM_OUTPUTS; - - src1_valid = sink_channel[1] && sink_valid; - - end - - // ------------------- - // Backpressure - // ------------------- - assign ready_vector[0] = src0_ready; - assign ready_vector[1] = src1_ready; - - assign sink_ready = |(sink_channel & {{16{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); - -endmodule - - diff --git a/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv b/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv deleted file mode 100644 index 52411df..0000000 --- a/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv +++ /dev/null @@ -1,101 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------- -// Merlin Demultiplexer -// -// Asserts valid on the appropriate output -// given a one-hot channel signal. -// ------------------------------------- - -`timescale 1 ns / 1 ns - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_rsp_xbar_demux_002 -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// NUM_OUTPUTS: 1 -// VALID_WIDTH: 1 -// ------------------------------------------ - -//------------------------------------------ -// Message Supression Used -// QIS Warnings -// 15610 - Warning: Design contains x input pin(s) that do not drive logic -//------------------------------------------ - -module nios_system_rsp_xbar_demux_002 -( - // ------------------- - // Sink - // ------------------- - input [1-1 : 0] sink_valid, - input [96-1 : 0] sink_data, // ST_DATA_W=96 - input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Sources - // ------------------- - output reg src0_valid, - output reg [96-1 : 0] src0_data, // ST_DATA_W=96 - output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 - output reg src0_startofpacket, - output reg src0_endofpacket, - input src0_ready, - - - // ------------------- - // Clock & Reset - // ------------------- - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk - input clk, - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset - input reset - -); - - localparam NUM_OUTPUTS = 1; - wire [NUM_OUTPUTS - 1 : 0] ready_vector; - - // ------------------- - // Demux - // ------------------- - always @* begin - src0_data = sink_data; - src0_startofpacket = sink_startofpacket; - src0_endofpacket = sink_endofpacket; - src0_channel = sink_channel >> NUM_OUTPUTS; - - src0_valid = sink_channel[0] && sink_valid; - - end - - // ------------------- - // Backpressure - // ------------------- - assign ready_vector[0] = src0_ready; - - assign sink_ready = |(sink_channel & {{17{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); - -endmodule - - diff --git a/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_003.sv b/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_003.sv deleted file mode 100644 index 755ac9e..0000000 --- a/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_003.sv +++ /dev/null @@ -1,101 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------- -// Merlin Demultiplexer -// -// Asserts valid on the appropriate output -// given a one-hot channel signal. -// ------------------------------------- - -`timescale 1 ns / 1 ns - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_rsp_xbar_demux_003 -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// NUM_OUTPUTS: 1 -// VALID_WIDTH: 1 -// ------------------------------------------ - -//------------------------------------------ -// Message Supression Used -// QIS Warnings -// 15610 - Warning: Design contains x input pin(s) that do not drive logic -//------------------------------------------ - -module nios_system_rsp_xbar_demux_003 -( - // ------------------- - // Sink - // ------------------- - input [1-1 : 0] sink_valid, - input [96-1 : 0] sink_data, // ST_DATA_W=96 - input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Sources - // ------------------- - output reg src0_valid, - output reg [96-1 : 0] src0_data, // ST_DATA_W=96 - output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 - output reg src0_startofpacket, - output reg src0_endofpacket, - input src0_ready, - - - // ------------------- - // Clock & Reset - // ------------------- - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk - input clk, - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset - input reset - -); - - localparam NUM_OUTPUTS = 1; - wire [NUM_OUTPUTS - 1 : 0] ready_vector; - - // ------------------- - // Demux - // ------------------- - always @* begin - src0_data = sink_data; - src0_startofpacket = sink_startofpacket; - src0_endofpacket = sink_endofpacket; - src0_channel = sink_channel >> NUM_OUTPUTS; - - src0_valid = sink_channel[0] && sink_valid; - - end - - // ------------------- - // Backpressure - // ------------------- - assign ready_vector[0] = src0_ready; - - assign sink_ready = |(sink_channel & {{17{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); - -endmodule - - diff --git a/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv b/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv deleted file mode 100644 index 6f30bfb..0000000 --- a/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv +++ /dev/null @@ -1,331 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------ -// Merlin Multiplexer -// ------------------------------------------ - -`timescale 1 ns / 1 ns - - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_rsp_xbar_mux -// NUM_INPUTS: 2 -// ARBITRATION_SHARES: 1 1 -// ARBITRATION_SCHEME "no-arb" -// PIPELINE_ARB: 0 -// PKT_TRANS_LOCK: 59 (arbitration locking enabled) -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// ------------------------------------------ - -module nios_system_rsp_xbar_mux -( - // ---------------------- - // Sinks - // ---------------------- - input sink0_valid, - input [96-1 : 0] sink0_data, - input [18-1: 0] sink0_channel, - input sink0_startofpacket, - input sink0_endofpacket, - output sink0_ready, - - input sink1_valid, - input [96-1 : 0] sink1_data, - input [18-1: 0] sink1_channel, - input sink1_startofpacket, - input sink1_endofpacket, - output sink1_ready, - - - // ---------------------- - // Source - // ---------------------- - output src_valid, - output [96-1 : 0] src_data, - output [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready, - - // ---------------------- - // Clock & Reset - // ---------------------- - input clk, - input reset -); - localparam PAYLOAD_W = 96 + 18 + 2; - localparam NUM_INPUTS = 2; - localparam SHARE_COUNTER_W = 1; - localparam PIPELINE_ARB = 0; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam PKT_TRANS_LOCK = 59; - - // ------------------------------------------ - // Signals - // ------------------------------------------ - wire [NUM_INPUTS - 1 : 0] request; - wire [NUM_INPUTS - 1 : 0] valid; - wire [NUM_INPUTS - 1 : 0] grant; - wire [NUM_INPUTS - 1 : 0] next_grant; - reg [NUM_INPUTS - 1 : 0] saved_grant; - reg [PAYLOAD_W - 1 : 0] src_payload; - wire last_cycle; - reg packet_in_progress; - reg update_grant; - - wire [PAYLOAD_W - 1 : 0] sink0_payload; - wire [PAYLOAD_W - 1 : 0] sink1_payload; - - assign valid[0] = sink0_valid; - assign valid[1] = sink1_valid; - - - // ------------------------------------------ - // ------------------------------------------ - // Grant Logic & Updates - // ------------------------------------------ - // ------------------------------------------ - reg [NUM_INPUTS - 1 : 0] lock; - always @* begin - lock[0] = sink0_data[59]; - lock[1] = sink1_data[59]; - end - - assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); - - // ------------------------------------------ - // We're working on a packet at any time valid is high, except - // when this is the endofpacket. - // ------------------------------------------ - always @(posedge clk or posedge reset) begin - if (reset) begin - packet_in_progress <= 1'b0; - end - else begin - if (src_valid) - packet_in_progress <= 1'b1; - if (last_cycle) - packet_in_progress <= 1'b0; - end - end - - - // ------------------------------------------ - // Shares - // - // Special case: all-equal shares _should_ be optimized into assigning a - // constant to next_grant_share. - // Special case: all-1's shares _should_ result in the share counter - // being optimized away. - // ------------------------------------------ - // Input | arb shares | counter load value - // 0 | 1 | 0 - // 1 | 1 | 0 - wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; - - // ------------------------------------------ - // Choose the share value corresponding to the grant. - // ------------------------------------------ - reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; - always @* begin - next_grant_share = - share_0 & { SHARE_COUNTER_W {next_grant[0]} } | - share_1 & { SHARE_COUNTER_W {next_grant[1]} }; - end - - // ------------------------------------------ - // Flag to indicate first packet of an arb sequence. - // ------------------------------------------ - wire grant_changed = ~packet_in_progress && !(saved_grant & valid); - reg first_packet_r; - wire first_packet = grant_changed | first_packet_r; - always @(posedge clk or posedge reset) begin - if (reset) begin - first_packet_r <= 1'b0; - end - else begin - if (update_grant) - first_packet_r <= 1'b1; - else if (last_cycle) - first_packet_r <= 1'b0; - else if (grant_changed) - first_packet_r <= 1'b1; - end - end - - // ------------------------------------------ - // Compute the next share-count value. - // ------------------------------------------ - reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; - reg [SHARE_COUNTER_W - 1 : 0] share_count; - reg share_count_zero_flag; - - always @* begin - if (first_packet) begin - p1_share_count = next_grant_share; - end - else begin - // Update the counter, but don't decrement below 0. - p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; - end - end - - // ------------------------------------------ - // Update the share counter and share-counter=zero flag. - // ------------------------------------------ - always @(posedge clk or posedge reset) begin - if (reset) begin - share_count <= '0; - share_count_zero_flag <= 1'b1; - end - else begin - if (last_cycle) begin - share_count <= p1_share_count; - share_count_zero_flag <= (p1_share_count == '0); - end - end - end - - // ------------------------------------------ - // For each input, maintain a final_packet signal which goes active for the - // last packet of a full-share packet sequence. Example: if I have 4 - // shares and I'm continuously requesting, final_packet is active in the - // 4th packet. - // ------------------------------------------ - wire final_packet_0 = 1'b1; - - wire final_packet_1 = 1'b1; - - - // ------------------------------------------ - // Concatenate all final_packet signals (wire or reg) into a handy vector. - // ------------------------------------------ - wire [NUM_INPUTS - 1 : 0] final_packet = { - final_packet_1, - final_packet_0 - }; - - // ------------------------------------------ - // ------------------------------------------ - wire p1_done = |(final_packet & grant); - - // ------------------------------------------ - // Flag for the first cycle of packets within an - // arb sequence - // ------------------------------------------ - reg first_cycle; - always @(posedge clk, posedge reset) begin - if (reset) - first_cycle <= 0; - else - first_cycle <= last_cycle && ~p1_done; - end - - - always @* begin - update_grant = 0; - - // ------------------------------------------ - // No arbitration pipeline, update grant whenever - // the current arb winner has consumed all shares, - // or all requests are low - // ------------------------------------------ - update_grant = (last_cycle && p1_done) || (first_cycle && !valid); - update_grant = last_cycle; - end - - wire save_grant; - assign save_grant = 1; - assign grant = next_grant; - - always @(posedge clk, posedge reset) begin - if (reset) - saved_grant <= '0; - else if (save_grant) - saved_grant <= next_grant; - end - - // ------------------------------------------ - // ------------------------------------------ - // Arbitrator - // ------------------------------------------ - // ------------------------------------------ - - // ------------------------------------------ - // Create a request vector that stays high during - // the packet for unpipelined arbitration. - // - // The pipelined arbitration scheme does not require - // request to be held high during the packet. - // ------------------------------------------ - assign request = valid; - - - altera_merlin_arbitrator - #( - .NUM_REQUESTERS(NUM_INPUTS), - .SCHEME ("no-arb"), - .PIPELINE (0) - ) arb ( - .clk (clk), - .reset (reset), - .request (request), - .grant (next_grant), - .save_top_priority (src_valid), - .increment_top_priority (update_grant) - ); - - // ------------------------------------------ - // ------------------------------------------ - // Mux - // - // Implemented as a sum of products. - // ------------------------------------------ - // ------------------------------------------ - - assign sink0_ready = src_ready && grant[0]; - assign sink1_ready = src_ready && grant[1]; - - assign src_valid = |(grant & valid); - - always @* begin - src_payload = - sink0_payload & {PAYLOAD_W {grant[0]} } | - sink1_payload & {PAYLOAD_W {grant[1]} }; - end - - // ------------------------------------------ - // Mux Payload Mapping - // ------------------------------------------ - - assign sink0_payload = {sink0_channel,sink0_data, - sink0_startofpacket,sink0_endofpacket}; - assign sink1_payload = {sink1_channel,sink1_data, - sink1_startofpacket,sink1_endofpacket}; - - assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; - -endmodule - - - diff --git a/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv b/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv deleted file mode 100644 index ce9f7a1..0000000 --- a/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv +++ /dev/null @@ -1,651 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------ -// Merlin Multiplexer -// ------------------------------------------ - -`timescale 1 ns / 1 ns - - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_rsp_xbar_mux_001 -// NUM_INPUTS: 18 -// ARBITRATION_SHARES: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -// ARBITRATION_SCHEME "no-arb" -// PIPELINE_ARB: 0 -// PKT_TRANS_LOCK: 59 (arbitration locking enabled) -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// ------------------------------------------ - -module nios_system_rsp_xbar_mux_001 -( - // ---------------------- - // Sinks - // ---------------------- - input sink0_valid, - input [96-1 : 0] sink0_data, - input [18-1: 0] sink0_channel, - input sink0_startofpacket, - input sink0_endofpacket, - output sink0_ready, - - input sink1_valid, - input [96-1 : 0] sink1_data, - input [18-1: 0] sink1_channel, - input sink1_startofpacket, - input sink1_endofpacket, - output sink1_ready, - - input sink2_valid, - input [96-1 : 0] sink2_data, - input [18-1: 0] sink2_channel, - input sink2_startofpacket, - input sink2_endofpacket, - output sink2_ready, - - input sink3_valid, - input [96-1 : 0] sink3_data, - input [18-1: 0] sink3_channel, - input sink3_startofpacket, - input sink3_endofpacket, - output sink3_ready, - - input sink4_valid, - input [96-1 : 0] sink4_data, - input [18-1: 0] sink4_channel, - input sink4_startofpacket, - input sink4_endofpacket, - output sink4_ready, - - input sink5_valid, - input [96-1 : 0] sink5_data, - input [18-1: 0] sink5_channel, - input sink5_startofpacket, - input sink5_endofpacket, - output sink5_ready, - - input sink6_valid, - input [96-1 : 0] sink6_data, - input [18-1: 0] sink6_channel, - input sink6_startofpacket, - input sink6_endofpacket, - output sink6_ready, - - input sink7_valid, - input [96-1 : 0] sink7_data, - input [18-1: 0] sink7_channel, - input sink7_startofpacket, - input sink7_endofpacket, - output sink7_ready, - - input sink8_valid, - input [96-1 : 0] sink8_data, - input [18-1: 0] sink8_channel, - input sink8_startofpacket, - input sink8_endofpacket, - output sink8_ready, - - input sink9_valid, - input [96-1 : 0] sink9_data, - input [18-1: 0] sink9_channel, - input sink9_startofpacket, - input sink9_endofpacket, - output sink9_ready, - - input sink10_valid, - input [96-1 : 0] sink10_data, - input [18-1: 0] sink10_channel, - input sink10_startofpacket, - input sink10_endofpacket, - output sink10_ready, - - input sink11_valid, - input [96-1 : 0] sink11_data, - input [18-1: 0] sink11_channel, - input sink11_startofpacket, - input sink11_endofpacket, - output sink11_ready, - - input sink12_valid, - input [96-1 : 0] sink12_data, - input [18-1: 0] sink12_channel, - input sink12_startofpacket, - input sink12_endofpacket, - output sink12_ready, - - input sink13_valid, - input [96-1 : 0] sink13_data, - input [18-1: 0] sink13_channel, - input sink13_startofpacket, - input sink13_endofpacket, - output sink13_ready, - - input sink14_valid, - input [96-1 : 0] sink14_data, - input [18-1: 0] sink14_channel, - input sink14_startofpacket, - input sink14_endofpacket, - output sink14_ready, - - input sink15_valid, - input [96-1 : 0] sink15_data, - input [18-1: 0] sink15_channel, - input sink15_startofpacket, - input sink15_endofpacket, - output sink15_ready, - - input sink16_valid, - input [96-1 : 0] sink16_data, - input [18-1: 0] sink16_channel, - input sink16_startofpacket, - input sink16_endofpacket, - output sink16_ready, - - input sink17_valid, - input [96-1 : 0] sink17_data, - input [18-1: 0] sink17_channel, - input sink17_startofpacket, - input sink17_endofpacket, - output sink17_ready, - - - // ---------------------- - // Source - // ---------------------- - output src_valid, - output [96-1 : 0] src_data, - output [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready, - - // ---------------------- - // Clock & Reset - // ---------------------- - input clk, - input reset -); - localparam PAYLOAD_W = 96 + 18 + 2; - localparam NUM_INPUTS = 18; - localparam SHARE_COUNTER_W = 1; - localparam PIPELINE_ARB = 0; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam PKT_TRANS_LOCK = 59; - - // ------------------------------------------ - // Signals - // ------------------------------------------ - wire [NUM_INPUTS - 1 : 0] request; - wire [NUM_INPUTS - 1 : 0] valid; - wire [NUM_INPUTS - 1 : 0] grant; - wire [NUM_INPUTS - 1 : 0] next_grant; - reg [NUM_INPUTS - 1 : 0] saved_grant; - reg [PAYLOAD_W - 1 : 0] src_payload; - wire last_cycle; - reg packet_in_progress; - reg update_grant; - - wire [PAYLOAD_W - 1 : 0] sink0_payload; - wire [PAYLOAD_W - 1 : 0] sink1_payload; - wire [PAYLOAD_W - 1 : 0] sink2_payload; - wire [PAYLOAD_W - 1 : 0] sink3_payload; - wire [PAYLOAD_W - 1 : 0] sink4_payload; - wire [PAYLOAD_W - 1 : 0] sink5_payload; - wire [PAYLOAD_W - 1 : 0] sink6_payload; - wire [PAYLOAD_W - 1 : 0] sink7_payload; - wire [PAYLOAD_W - 1 : 0] sink8_payload; - wire [PAYLOAD_W - 1 : 0] sink9_payload; - wire [PAYLOAD_W - 1 : 0] sink10_payload; - wire [PAYLOAD_W - 1 : 0] sink11_payload; - wire [PAYLOAD_W - 1 : 0] sink12_payload; - wire [PAYLOAD_W - 1 : 0] sink13_payload; - wire [PAYLOAD_W - 1 : 0] sink14_payload; - wire [PAYLOAD_W - 1 : 0] sink15_payload; - wire [PAYLOAD_W - 1 : 0] sink16_payload; - wire [PAYLOAD_W - 1 : 0] sink17_payload; - - assign valid[0] = sink0_valid; - assign valid[1] = sink1_valid; - assign valid[2] = sink2_valid; - assign valid[3] = sink3_valid; - assign valid[4] = sink4_valid; - assign valid[5] = sink5_valid; - assign valid[6] = sink6_valid; - assign valid[7] = sink7_valid; - assign valid[8] = sink8_valid; - assign valid[9] = sink9_valid; - assign valid[10] = sink10_valid; - assign valid[11] = sink11_valid; - assign valid[12] = sink12_valid; - assign valid[13] = sink13_valid; - assign valid[14] = sink14_valid; - assign valid[15] = sink15_valid; - assign valid[16] = sink16_valid; - assign valid[17] = sink17_valid; - - - // ------------------------------------------ - // ------------------------------------------ - // Grant Logic & Updates - // ------------------------------------------ - // ------------------------------------------ - reg [NUM_INPUTS - 1 : 0] lock; - always @* begin - lock[0] = sink0_data[59]; - lock[1] = sink1_data[59]; - lock[2] = sink2_data[59]; - lock[3] = sink3_data[59]; - lock[4] = sink4_data[59]; - lock[5] = sink5_data[59]; - lock[6] = sink6_data[59]; - lock[7] = sink7_data[59]; - lock[8] = sink8_data[59]; - lock[9] = sink9_data[59]; - lock[10] = sink10_data[59]; - lock[11] = sink11_data[59]; - lock[12] = sink12_data[59]; - lock[13] = sink13_data[59]; - lock[14] = sink14_data[59]; - lock[15] = sink15_data[59]; - lock[16] = sink16_data[59]; - lock[17] = sink17_data[59]; - end - - assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); - - // ------------------------------------------ - // We're working on a packet at any time valid is high, except - // when this is the endofpacket. - // ------------------------------------------ - always @(posedge clk or posedge reset) begin - if (reset) begin - packet_in_progress <= 1'b0; - end - else begin - if (src_valid) - packet_in_progress <= 1'b1; - if (last_cycle) - packet_in_progress <= 1'b0; - end - end - - - // ------------------------------------------ - // Shares - // - // Special case: all-equal shares _should_ be optimized into assigning a - // constant to next_grant_share. - // Special case: all-1's shares _should_ result in the share counter - // being optimized away. - // ------------------------------------------ - // Input | arb shares | counter load value - // 0 | 1 | 0 - // 1 | 1 | 0 - // 2 | 1 | 0 - // 3 | 1 | 0 - // 4 | 1 | 0 - // 5 | 1 | 0 - // 6 | 1 | 0 - // 7 | 1 | 0 - // 8 | 1 | 0 - // 9 | 1 | 0 - // 10 | 1 | 0 - // 11 | 1 | 0 - // 12 | 1 | 0 - // 13 | 1 | 0 - // 14 | 1 | 0 - // 15 | 1 | 0 - // 16 | 1 | 0 - // 17 | 1 | 0 - wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_6 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_7 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_8 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_9 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_10 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_11 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_12 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_13 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_14 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_15 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_16 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_17 = 1'd0; - - // ------------------------------------------ - // Choose the share value corresponding to the grant. - // ------------------------------------------ - reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; - always @* begin - next_grant_share = - share_0 & { SHARE_COUNTER_W {next_grant[0]} } | - share_1 & { SHARE_COUNTER_W {next_grant[1]} } | - share_2 & { SHARE_COUNTER_W {next_grant[2]} } | - share_3 & { SHARE_COUNTER_W {next_grant[3]} } | - share_4 & { SHARE_COUNTER_W {next_grant[4]} } | - share_5 & { SHARE_COUNTER_W {next_grant[5]} } | - share_6 & { SHARE_COUNTER_W {next_grant[6]} } | - share_7 & { SHARE_COUNTER_W {next_grant[7]} } | - share_8 & { SHARE_COUNTER_W {next_grant[8]} } | - share_9 & { SHARE_COUNTER_W {next_grant[9]} } | - share_10 & { SHARE_COUNTER_W {next_grant[10]} } | - share_11 & { SHARE_COUNTER_W {next_grant[11]} } | - share_12 & { SHARE_COUNTER_W {next_grant[12]} } | - share_13 & { SHARE_COUNTER_W {next_grant[13]} } | - share_14 & { SHARE_COUNTER_W {next_grant[14]} } | - share_15 & { SHARE_COUNTER_W {next_grant[15]} } | - share_16 & { SHARE_COUNTER_W {next_grant[16]} } | - share_17 & { SHARE_COUNTER_W {next_grant[17]} }; - end - - // ------------------------------------------ - // Flag to indicate first packet of an arb sequence. - // ------------------------------------------ - wire grant_changed = ~packet_in_progress && !(saved_grant & valid); - reg first_packet_r; - wire first_packet = grant_changed | first_packet_r; - always @(posedge clk or posedge reset) begin - if (reset) begin - first_packet_r <= 1'b0; - end - else begin - if (update_grant) - first_packet_r <= 1'b1; - else if (last_cycle) - first_packet_r <= 1'b0; - else if (grant_changed) - first_packet_r <= 1'b1; - end - end - - // ------------------------------------------ - // Compute the next share-count value. - // ------------------------------------------ - reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; - reg [SHARE_COUNTER_W - 1 : 0] share_count; - reg share_count_zero_flag; - - always @* begin - if (first_packet) begin - p1_share_count = next_grant_share; - end - else begin - // Update the counter, but don't decrement below 0. - p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; - end - end - - // ------------------------------------------ - // Update the share counter and share-counter=zero flag. - // ------------------------------------------ - always @(posedge clk or posedge reset) begin - if (reset) begin - share_count <= '0; - share_count_zero_flag <= 1'b1; - end - else begin - if (last_cycle) begin - share_count <= p1_share_count; - share_count_zero_flag <= (p1_share_count == '0); - end - end - end - - // ------------------------------------------ - // For each input, maintain a final_packet signal which goes active for the - // last packet of a full-share packet sequence. Example: if I have 4 - // shares and I'm continuously requesting, final_packet is active in the - // 4th packet. - // ------------------------------------------ - wire final_packet_0 = 1'b1; - - wire final_packet_1 = 1'b1; - - wire final_packet_2 = 1'b1; - - wire final_packet_3 = 1'b1; - - wire final_packet_4 = 1'b1; - - wire final_packet_5 = 1'b1; - - wire final_packet_6 = 1'b1; - - wire final_packet_7 = 1'b1; - - wire final_packet_8 = 1'b1; - - wire final_packet_9 = 1'b1; - - wire final_packet_10 = 1'b1; - - wire final_packet_11 = 1'b1; - - wire final_packet_12 = 1'b1; - - wire final_packet_13 = 1'b1; - - wire final_packet_14 = 1'b1; - - wire final_packet_15 = 1'b1; - - wire final_packet_16 = 1'b1; - - wire final_packet_17 = 1'b1; - - - // ------------------------------------------ - // Concatenate all final_packet signals (wire or reg) into a handy vector. - // ------------------------------------------ - wire [NUM_INPUTS - 1 : 0] final_packet = { - final_packet_17, - final_packet_16, - final_packet_15, - final_packet_14, - final_packet_13, - final_packet_12, - final_packet_11, - final_packet_10, - final_packet_9, - final_packet_8, - final_packet_7, - final_packet_6, - final_packet_5, - final_packet_4, - final_packet_3, - final_packet_2, - final_packet_1, - final_packet_0 - }; - - // ------------------------------------------ - // ------------------------------------------ - wire p1_done = |(final_packet & grant); - - // ------------------------------------------ - // Flag for the first cycle of packets within an - // arb sequence - // ------------------------------------------ - reg first_cycle; - always @(posedge clk, posedge reset) begin - if (reset) - first_cycle <= 0; - else - first_cycle <= last_cycle && ~p1_done; - end - - - always @* begin - update_grant = 0; - - // ------------------------------------------ - // No arbitration pipeline, update grant whenever - // the current arb winner has consumed all shares, - // or all requests are low - // ------------------------------------------ - update_grant = (last_cycle && p1_done) || (first_cycle && !valid); - update_grant = last_cycle; - end - - wire save_grant; - assign save_grant = 1; - assign grant = next_grant; - - always @(posedge clk, posedge reset) begin - if (reset) - saved_grant <= '0; - else if (save_grant) - saved_grant <= next_grant; - end - - // ------------------------------------------ - // ------------------------------------------ - // Arbitrator - // ------------------------------------------ - // ------------------------------------------ - - // ------------------------------------------ - // Create a request vector that stays high during - // the packet for unpipelined arbitration. - // - // The pipelined arbitration scheme does not require - // request to be held high during the packet. - // ------------------------------------------ - assign request = valid; - - - altera_merlin_arbitrator - #( - .NUM_REQUESTERS(NUM_INPUTS), - .SCHEME ("no-arb"), - .PIPELINE (0) - ) arb ( - .clk (clk), - .reset (reset), - .request (request), - .grant (next_grant), - .save_top_priority (src_valid), - .increment_top_priority (update_grant) - ); - - // ------------------------------------------ - // ------------------------------------------ - // Mux - // - // Implemented as a sum of products. - // ------------------------------------------ - // ------------------------------------------ - - assign sink0_ready = src_ready && grant[0]; - assign sink1_ready = src_ready && grant[1]; - assign sink2_ready = src_ready && grant[2]; - assign sink3_ready = src_ready && grant[3]; - assign sink4_ready = src_ready && grant[4]; - assign sink5_ready = src_ready && grant[5]; - assign sink6_ready = src_ready && grant[6]; - assign sink7_ready = src_ready && grant[7]; - assign sink8_ready = src_ready && grant[8]; - assign sink9_ready = src_ready && grant[9]; - assign sink10_ready = src_ready && grant[10]; - assign sink11_ready = src_ready && grant[11]; - assign sink12_ready = src_ready && grant[12]; - assign sink13_ready = src_ready && grant[13]; - assign sink14_ready = src_ready && grant[14]; - assign sink15_ready = src_ready && grant[15]; - assign sink16_ready = src_ready && grant[16]; - assign sink17_ready = src_ready && grant[17]; - - assign src_valid = |(grant & valid); - - always @* begin - src_payload = - sink0_payload & {PAYLOAD_W {grant[0]} } | - sink1_payload & {PAYLOAD_W {grant[1]} } | - sink2_payload & {PAYLOAD_W {grant[2]} } | - sink3_payload & {PAYLOAD_W {grant[3]} } | - sink4_payload & {PAYLOAD_W {grant[4]} } | - sink5_payload & {PAYLOAD_W {grant[5]} } | - sink6_payload & {PAYLOAD_W {grant[6]} } | - sink7_payload & {PAYLOAD_W {grant[7]} } | - sink8_payload & {PAYLOAD_W {grant[8]} } | - sink9_payload & {PAYLOAD_W {grant[9]} } | - sink10_payload & {PAYLOAD_W {grant[10]} } | - sink11_payload & {PAYLOAD_W {grant[11]} } | - sink12_payload & {PAYLOAD_W {grant[12]} } | - sink13_payload & {PAYLOAD_W {grant[13]} } | - sink14_payload & {PAYLOAD_W {grant[14]} } | - sink15_payload & {PAYLOAD_W {grant[15]} } | - sink16_payload & {PAYLOAD_W {grant[16]} } | - sink17_payload & {PAYLOAD_W {grant[17]} }; - end - - // ------------------------------------------ - // Mux Payload Mapping - // ------------------------------------------ - - assign sink0_payload = {sink0_channel,sink0_data, - sink0_startofpacket,sink0_endofpacket}; - assign sink1_payload = {sink1_channel,sink1_data, - sink1_startofpacket,sink1_endofpacket}; - assign sink2_payload = {sink2_channel,sink2_data, - sink2_startofpacket,sink2_endofpacket}; - assign sink3_payload = {sink3_channel,sink3_data, - sink3_startofpacket,sink3_endofpacket}; - assign sink4_payload = {sink4_channel,sink4_data, - sink4_startofpacket,sink4_endofpacket}; - assign sink5_payload = {sink5_channel,sink5_data, - sink5_startofpacket,sink5_endofpacket}; - assign sink6_payload = {sink6_channel,sink6_data, - sink6_startofpacket,sink6_endofpacket}; - assign sink7_payload = {sink7_channel,sink7_data, - sink7_startofpacket,sink7_endofpacket}; - assign sink8_payload = {sink8_channel,sink8_data, - sink8_startofpacket,sink8_endofpacket}; - assign sink9_payload = {sink9_channel,sink9_data, - sink9_startofpacket,sink9_endofpacket}; - assign sink10_payload = {sink10_channel,sink10_data, - sink10_startofpacket,sink10_endofpacket}; - assign sink11_payload = {sink11_channel,sink11_data, - sink11_startofpacket,sink11_endofpacket}; - assign sink12_payload = {sink12_channel,sink12_data, - sink12_startofpacket,sink12_endofpacket}; - assign sink13_payload = {sink13_channel,sink13_data, - sink13_startofpacket,sink13_endofpacket}; - assign sink14_payload = {sink14_channel,sink14_data, - sink14_startofpacket,sink14_endofpacket}; - assign sink15_payload = {sink15_channel,sink15_data, - sink15_startofpacket,sink15_endofpacket}; - assign sink16_payload = {sink16_channel,sink16_data, - sink16_startofpacket,sink16_endofpacket}; - assign sink17_payload = {sink17_channel,sink17_data, - sink17_startofpacket,sink17_endofpacket}; - - assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; - -endmodule - - - diff --git a/db/ip/nios_system/submodules/nios_system_switches.v b/db/ip/nios_system/submodules/nios_system_switches.v deleted file mode 100644 index 1fd0e98..0000000 --- a/db/ip/nios_system/submodules/nios_system_switches.v +++ /dev/null @@ -1,58 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_switches ( - // inputs: - address, - clk, - in_port, - reset_n, - - // outputs: - readdata - ) -; - - output [ 31: 0] readdata; - input [ 1: 0] address; - input clk; - input [ 17: 0] in_port; - input reset_n; - - wire clk_en; - wire [ 17: 0] data_in; - wire [ 17: 0] read_mux_out; - reg [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {18 {(address == 0)}} & data_in; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - readdata <= 0; - else if (clk_en) - readdata <= {32'b0 | read_mux_out}; - end - - - assign data_in = in_port; - -endmodule - diff --git "a/db/lights.\0500\051.cnf.cdb" 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"b/db/lights.\05096\051.cnf.cdb" deleted file mode 100644 index 779cd80..0000000 --- "a/db/lights.\05096\051.cnf.cdb" +++ /dev/null Binary files differ diff --git "a/db/lights.\05096\051.cnf.hdb" "b/db/lights.\05096\051.cnf.hdb" deleted file mode 100644 index 83f5dac..0000000 --- "a/db/lights.\05096\051.cnf.hdb" +++ /dev/null Binary files differ diff --git "a/db/lights.\05097\051.cnf.cdb" "b/db/lights.\05097\051.cnf.cdb" deleted file mode 100644 index b257d29..0000000 --- "a/db/lights.\05097\051.cnf.cdb" +++ /dev/null Binary files differ diff --git "a/db/lights.\05097\051.cnf.hdb" "b/db/lights.\05097\051.cnf.hdb" deleted file mode 100644 index 7e0a046..0000000 --- "a/db/lights.\05097\051.cnf.hdb" +++ /dev/null Binary files differ diff --git "a/db/lights.\05098\051.cnf.cdb" "b/db/lights.\05098\051.cnf.cdb" deleted file mode 100644 index a1b964c..0000000 --- "a/db/lights.\05098\051.cnf.cdb" +++ /dev/null Binary files differ diff --git "a/db/lights.\05098\051.cnf.hdb" "b/db/lights.\05098\051.cnf.hdb" deleted file mode 100644 index 7c889a9..0000000 --- "a/db/lights.\05098\051.cnf.hdb" +++ /dev/null Binary files differ diff --git "a/db/lights.\05099\051.cnf.cdb" "b/db/lights.\05099\051.cnf.cdb" deleted file mode 100644 index 4c7f2a0..0000000 --- "a/db/lights.\05099\051.cnf.cdb" +++ /dev/null Binary files differ diff --git "a/db/lights.\05099\051.cnf.hdb" "b/db/lights.\05099\051.cnf.hdb" deleted file mode 100644 index f9840e0..0000000 --- "a/db/lights.\05099\051.cnf.hdb" +++ /dev/null Binary files differ diff --git a/db/lights.asm.qmsg b/db/lights.asm.qmsg deleted file mode 100644 index d4c2583..0000000 --- a/db/lights.asm.qmsg +++ /dev/null @@ -1,6 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1482368914623 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1482368914623 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 22 10:08:34 2016 " "Processing started: Thu Dec 22 10:08:34 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1482368914623 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1482368914623 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off lights -c lights " "Command: quartus_asm --read_settings_files=off --write_settings_files=off lights -c lights" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1482368914623 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1482368919572 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1482368919706 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "481 " "Peak virtual memory: 481 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1482368921649 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 22 10:08:41 2016 " "Processing ended: Thu Dec 22 10:08:41 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1482368921649 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1482368921649 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1482368921649 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1482368921649 ""} diff --git a/db/lights.asm.rdb b/db/lights.asm.rdb deleted file mode 100644 index 9e7d533..0000000 --- a/db/lights.asm.rdb +++ /dev/null Binary files differ diff --git a/db/lights.asm_labs.ddb b/db/lights.asm_labs.ddb deleted file mode 100644 index 822b00c..0000000 --- a/db/lights.asm_labs.ddb +++ /dev/null Binary files differ diff --git a/db/lights.autoh_e40e1.map.reg_db.cdb b/db/lights.autoh_e40e1.map.reg_db.cdb deleted file mode 100644 index a1d8689..0000000 --- a/db/lights.autoh_e40e1.map.reg_db.cdb +++ /dev/null Binary files differ diff --git a/db/lights.cbx.xml b/db/lights.cbx.xml deleted file mode 100644 index e529c3c..0000000 --- a/db/lights.cbx.xml +++ /dev/null @@ -1,11 +0,0 @@ - - - - - - - - - - - diff --git a/db/lights.cmp.bpm b/db/lights.cmp.bpm deleted file mode 100644 index e89ad04..0000000 --- a/db/lights.cmp.bpm +++ /dev/null Binary files differ diff --git a/db/lights.cmp.cdb b/db/lights.cmp.cdb deleted file mode 100644 index 3f5da5e..0000000 --- a/db/lights.cmp.cdb +++ /dev/null Binary files differ diff --git a/db/lights.cmp.hdb b/db/lights.cmp.hdb deleted file mode 100644 index 5aad9c6..0000000 --- a/db/lights.cmp.hdb +++ /dev/null Binary files differ diff --git a/db/lights.cmp.idb b/db/lights.cmp.idb deleted file mode 100644 index 9fc3827..0000000 --- a/db/lights.cmp.idb +++ /dev/null Binary files differ diff --git a/db/lights.cmp.kpt b/db/lights.cmp.kpt deleted file mode 100644 index 647b550..0000000 --- a/db/lights.cmp.kpt +++ /dev/null Binary files differ diff --git a/db/lights.cmp.logdb b/db/lights.cmp.logdb deleted file mode 100644 index 1de615f..0000000 --- a/db/lights.cmp.logdb +++ /dev/null @@ -1,164 +0,0 @@ -v1 -IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, -IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, -IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, -IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, -IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, -IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, -IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, -IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, -IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, -IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, -IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, -IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, -IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, -IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, -IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, -IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, -IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, -IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, -IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, -IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, -IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, -IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,, -IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, -IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, -IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, -IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, -IO_RULES_MATRIX,Total Pass,118;0;118;0;0;122;118;0;122;122;0;49;0;0;31;0;49;31;0;0;0;49;0;0;0;0;0;122;0;0, -IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, -IO_RULES_MATRIX,Total Inapplicable,4;122;4;122;122;0;4;122;0;0;122;73;122;122;91;122;73;91;122;122;122;73;122;122;122;122;122;0;122;122, -IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, -IO_RULES_MATRIX,LEDG[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDG[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDG[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDG[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDG[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDG[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDG[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDG[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[12],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[13],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[14],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[15],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[16],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[17],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 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-IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 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-IO_RULES_MATRIX,HEX5[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX5[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX5[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX5[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 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-IO_RULES_MATRIX,HEX6[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX6[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX6[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX6[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX6[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX7[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX7[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX7[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX7[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX7[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX7[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX7[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LCD_RS,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LCD_RW,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LCD_data[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LCD_data[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LCD_data[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LCD_data[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LCD_data[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LCD_data[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 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-IO_RULES_MATRIX,LCD_EN,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LCD_ON,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LCD_BLON,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,KEY[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,KEY[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[12],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[13],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[14],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[15],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[16],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[17],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,altera_reserved_tms,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,altera_reserved_tck,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,altera_reserved_tdi,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,altera_reserved_tdo,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_SUMMARY,Total I/O Rules,30, -IO_RULES_SUMMARY,Number of I/O Rules Passed,12, -IO_RULES_SUMMARY,Number of I/O Rules Failed,0, -IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, -IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18, diff --git a/db/lights.cmp.rdb b/db/lights.cmp.rdb deleted file mode 100644 index 4c83dc6..0000000 --- a/db/lights.cmp.rdb +++ /dev/null Binary files differ diff --git a/db/lights.cmp_merge.kpt b/db/lights.cmp_merge.kpt deleted file mode 100644 index 07f5db6..0000000 --- a/db/lights.cmp_merge.kpt +++ /dev/null Binary files differ diff --git a/db/lights.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/db/lights.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd deleted file mode 100644 index 246e7b7..0000000 --- a/db/lights.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd +++ /dev/null Binary files differ diff --git a/db/lights.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd b/db/lights.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd deleted file mode 100644 index a0ed3e0..0000000 --- a/db/lights.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd +++ /dev/null Binary files differ diff --git a/db/lights.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd b/db/lights.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd deleted file mode 100644 index 9930150..0000000 --- a/db/lights.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd +++ /dev/null Binary files differ diff --git a/db/lights.db_info b/db/lights.db_info deleted file mode 100644 index 485a3e4..0000000 --- a/db/lights.db_info +++ /dev/null @@ -1,3 +0,0 @@ -Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition -Version_Index = 302049280 -Creation_Time = Thu Dec 22 10:31:00 2016 diff --git a/db/lights.fit.qmsg b/db/lights.fit.qmsg deleted file mode 100644 index df5236c..0000000 --- a/db/lights.fit.qmsg +++ /dev/null @@ -1,53 +0,0 @@ -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1482368874734 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "lights EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"lights\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1482368874772 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1482368874834 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1482368874834 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1482368874834 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1482368875056 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1482368875056 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1482368875657 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1482368875657 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1482368875657 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1482368875657 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1482368875657 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1482368875657 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1482368875657 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1482368875657 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1482368875657 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1482368875657 ""} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 11994 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1482368875657 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 11996 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1482368875657 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 11998 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1482368875657 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 12000 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1482368875657 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 12002 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1482368875657 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1482368875657 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1482368875673 ""} -{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1482368875704 ""} -{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\] " "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Fitter" 0 -1 1482368879713 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "lights.sdc " "Synopsys Design Constraints File file not found: 'lights.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1482368879797 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1482368879828 "|lights|CLOCK_50"} -{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1482368879929 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1482368879929 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1482368879929 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Fitter" 0 -1 1482368879929 ""} -{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1482368879929 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879929 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879929 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " " 100.000 altera_reserved_tck" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879929 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1482368879929 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p)) " "Automatically promoted node CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1482368880414 ""} } { { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 5 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 11962 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1482368880414 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP " "Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1482368880414 ""} } { { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 4019 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1482368880414 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "nios_system:NiosII\|altera_reset_controller:rst_controller\|r_sync_rst " "Automatically promoted node nios_system:NiosII\|altera_reset_controller:rst_controller\|r_sync_rst " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1482368880414 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "nios_system:NiosII\|altera_reset_controller:rst_controller\|WideOr0~0 " "Destination node nios_system:NiosII\|altera_reset_controller:rst_controller\|WideOr0~0" { } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 177 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|altera_reset_controller:rst_controller|WideOr0~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 4470 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1482368880414 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|W_rf_wren " "Destination node nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|W_rf_wren" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3700 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wren } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 3289 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1482368880414 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\|din_s1~0 " "Destination node nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\|din_s1~0" { } { { "altera_std_synchronizer.v" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altera_std_synchronizer.v" 45 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|din_s1~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 5950 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1482368880414 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1482368880414 ""} } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 172 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 905 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1482368880414 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "nios_system:NiosII\|altera_reset_controller:rst_controller\|merged_reset~0 " "Automatically promoted node nios_system:NiosII\|altera_reset_controller:rst_controller\|merged_reset~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1482368880414 ""} } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 68 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|altera_reset_controller:rst_controller|merged_reset~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 5706 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1482368880414 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1482368882447 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1482368882492 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1482368882493 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1482368882547 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1482368882613 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1482368882635 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1482368882636 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1482368882651 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1482368882819 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "8 EC " "Packed 8 registers into blocks of type EC" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1482368882837 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1482368882837 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN" "" "Ignored I/O standard assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_ADCDAT " "Ignored I/O standard assignment to node \"AUD_ADCDAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_ADCLRCK " "Ignored I/O standard assignment to node \"AUD_ADCLRCK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_BCLK " "Ignored I/O standard assignment to node \"AUD_BCLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_DACDAT " "Ignored I/O standard assignment to node \"AUD_DACDAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_DACLRCK " "Ignored I/O standard assignment to node \"AUD_DACLRCK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_XCK " "Ignored I/O standard assignment to node \"AUD_XCK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK2_50 " "Ignored I/O standard assignment to node \"CLOCK2_50\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK3_50 " "Ignored I/O standard assignment to node \"CLOCK3_50\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[0\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[10\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[11\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[12\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[1\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[2\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[3\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[4\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[5\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[6\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[7\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[8\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[9\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_BA\[0\] " "Ignored I/O standard assignment to node \"DRAM_BA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_BA\[1\] " "Ignored I/O standard assignment to node \"DRAM_BA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CAS_N " "Ignored I/O standard assignment to node \"DRAM_CAS_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CKE " "Ignored I/O standard assignment to node \"DRAM_CKE\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CLK " "Ignored I/O standard assignment to node \"DRAM_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CS_N " "Ignored I/O standard assignment to node \"DRAM_CS_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQM\[0\] " "Ignored I/O standard assignment to node \"DRAM_DQM\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQM\[1\] " "Ignored I/O standard assignment to node \"DRAM_DQM\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQM\[2\] " "Ignored I/O standard assignment to node \"DRAM_DQM\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQM\[3\] " "Ignored I/O standard assignment to node \"DRAM_DQM\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[0\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[10\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[11\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[12\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[13\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[14\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[15\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[16\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[17\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[17\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[18\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[18\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[19\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[19\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[1\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[20\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[20\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[21\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[21\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[22\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[22\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[23\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[23\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[24\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[24\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[25\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[25\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[26\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[26\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[27\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[27\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[28\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[28\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[29\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[29\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[2\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[30\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[30\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[31\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[31\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[3\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[4\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[5\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[6\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[7\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[8\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[9\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_RAS_N " "Ignored I/O standard assignment to node \"DRAM_RAS_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_WE_N " "Ignored I/O standard assignment to node \"DRAM_WE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EEP_I2C_SCLK " "Ignored I/O standard assignment to node \"EEP_I2C_SCLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EEP_I2C_SDAT " "Ignored I/O standard assignment to node \"EEP_I2C_SDAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_GTX_CLK " "Ignored I/O standard assignment to node \"ENET0_GTX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_INT_N " "Ignored I/O standard assignment to node \"ENET0_INT_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_LINK100 " "Ignored I/O standard assignment to node \"ENET0_LINK100\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_MDC " "Ignored I/O standard assignment to node \"ENET0_MDC\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_MDIO " "Ignored I/O standard assignment to node \"ENET0_MDIO\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RST_N " "Ignored I/O standard assignment to node \"ENET0_RST_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_CLK " "Ignored I/O standard assignment to node \"ENET0_RX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_COL " "Ignored I/O standard assignment to node \"ENET0_RX_COL\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_CRS " "Ignored I/O standard assignment to node \"ENET0_RX_CRS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Ignored I/O standard assignment to node \"ENET0_RX_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Ignored I/O standard assignment to node \"ENET0_RX_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Ignored I/O standard assignment to node \"ENET0_RX_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Ignored I/O standard assignment to node \"ENET0_RX_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DV " "Ignored I/O standard assignment to node \"ENET0_RX_DV\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_ER " "Ignored I/O standard assignment to node \"ENET0_RX_ER\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_CLK " "Ignored I/O standard assignment to node \"ENET0_TX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Ignored I/O standard assignment to node \"ENET0_TX_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Ignored I/O standard assignment to node \"ENET0_TX_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Ignored I/O standard assignment to node \"ENET0_TX_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Ignored I/O standard assignment to node \"ENET0_TX_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_EN " "Ignored I/O standard assignment to node \"ENET0_TX_EN\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_ER " "Ignored I/O standard assignment to node \"ENET0_TX_ER\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_GTX_CLK " "Ignored I/O standard assignment to node \"ENET1_GTX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_INT_N " "Ignored I/O standard assignment to node \"ENET1_INT_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_LINK100 " "Ignored I/O standard assignment to node \"ENET1_LINK100\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_MDC " "Ignored I/O standard assignment to node \"ENET1_MDC\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_MDIO " "Ignored I/O standard assignment to node \"ENET1_MDIO\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RST_N " "Ignored I/O standard assignment to node \"ENET1_RST_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_CLK " "Ignored I/O standard assignment to node \"ENET1_RX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_COL " "Ignored I/O standard assignment to node \"ENET1_RX_COL\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_CRS " "Ignored I/O standard assignment to node \"ENET1_RX_CRS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Ignored I/O standard assignment to node \"ENET1_RX_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Ignored I/O standard assignment to node \"ENET1_RX_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Ignored I/O standard assignment to node \"ENET1_RX_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Ignored I/O standard assignment to node \"ENET1_RX_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DV " "Ignored I/O standard assignment to node \"ENET1_RX_DV\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_ER " "Ignored I/O standard assignment to node \"ENET1_RX_ER\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_CLK " "Ignored I/O standard assignment to node \"ENET1_TX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Ignored I/O standard assignment to node \"ENET1_TX_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Ignored I/O standard assignment to node \"ENET1_TX_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Ignored I/O standard assignment to node \"ENET1_TX_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Ignored I/O standard assignment to node \"ENET1_TX_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_EN " "Ignored I/O standard assignment to node \"ENET1_TX_EN\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_ER " "Ignored I/O standard assignment to node \"ENET1_TX_ER\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENETCLK_25 " "Ignored I/O standard assignment to node \"ENETCLK_25\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[0\] " "Ignored I/O standard assignment to node \"EX_IO\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[1\] " "Ignored I/O standard assignment to node \"EX_IO\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[2\] " "Ignored I/O standard assignment to node \"EX_IO\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[3\] " "Ignored I/O standard assignment to node \"EX_IO\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[4\] " "Ignored I/O standard assignment to node \"EX_IO\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[5\] " "Ignored I/O standard assignment to node \"EX_IO\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[6\] " "Ignored I/O standard assignment to node \"EX_IO\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[0\] " "Ignored I/O standard assignment to node \"FL_ADDR\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[10\] " "Ignored I/O standard assignment to node \"FL_ADDR\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[11\] " "Ignored I/O standard assignment to node \"FL_ADDR\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[12\] " "Ignored I/O standard assignment to node \"FL_ADDR\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[13\] " "Ignored I/O standard assignment to node \"FL_ADDR\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[14\] " "Ignored I/O standard assignment to node \"FL_ADDR\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[15\] " "Ignored I/O standard assignment to node \"FL_ADDR\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[16\] " "Ignored I/O standard assignment to node \"FL_ADDR\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[17\] " "Ignored I/O standard assignment to node \"FL_ADDR\[17\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[18\] " "Ignored I/O standard assignment to node \"FL_ADDR\[18\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[19\] " "Ignored I/O standard assignment to node \"FL_ADDR\[19\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[1\] " "Ignored I/O standard assignment to node \"FL_ADDR\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[20\] " "Ignored I/O standard assignment to node \"FL_ADDR\[20\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[21\] " "Ignored I/O standard assignment to node \"FL_ADDR\[21\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[22\] " "Ignored I/O standard assignment to node \"FL_ADDR\[22\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[2\] " "Ignored I/O standard assignment to node \"FL_ADDR\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[3\] " "Ignored I/O standard assignment to node \"FL_ADDR\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[4\] " "Ignored I/O standard assignment to node \"FL_ADDR\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[5\] " "Ignored I/O standard assignment to node \"FL_ADDR\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[6\] " "Ignored I/O standard assignment to node \"FL_ADDR\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[7\] " "Ignored I/O standard assignment to node \"FL_ADDR\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[8\] " "Ignored I/O standard assignment to node \"FL_ADDR\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[9\] " "Ignored I/O standard assignment to node \"FL_ADDR\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_CE_N " "Ignored I/O standard assignment to node \"FL_CE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[0\] " "Ignored I/O standard assignment to node \"FL_DQ\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[1\] " "Ignored I/O standard assignment to node \"FL_DQ\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[2\] " "Ignored I/O standard assignment to node \"FL_DQ\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[3\] " "Ignored I/O standard assignment to node \"FL_DQ\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[4\] " "Ignored I/O standard assignment to node \"FL_DQ\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[5\] " "Ignored I/O standard assignment to node \"FL_DQ\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[6\] " "Ignored I/O standard assignment to node \"FL_DQ\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[7\] " "Ignored I/O standard assignment to node \"FL_DQ\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_OE_N " "Ignored I/O standard assignment to node \"FL_OE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_RST_N " "Ignored I/O standard assignment to node \"FL_RST_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_RY " "Ignored I/O standard assignment to node \"FL_RY\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_WE_N " "Ignored I/O standard assignment to node \"FL_WE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_WP_N " "Ignored I/O standard assignment to node \"FL_WP_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[0\] " "Ignored I/O standard assignment to node \"GPIO\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[10\] " "Ignored I/O standard assignment to node \"GPIO\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[11\] " "Ignored I/O standard assignment to node \"GPIO\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[12\] " "Ignored I/O standard assignment to node \"GPIO\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[13\] " "Ignored I/O standard assignment to node \"GPIO\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[14\] " "Ignored I/O standard assignment to node \"GPIO\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[15\] " "Ignored I/O standard assignment to node \"GPIO\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[16\] " "Ignored I/O standard assignment to node \"GPIO\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[17\] " "Ignored I/O standard assignment to node \"GPIO\[17\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[18\] " "Ignored I/O standard assignment to node \"GPIO\[18\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[19\] " "Ignored I/O standard assignment to node \"GPIO\[19\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[1\] " "Ignored I/O standard assignment to node \"GPIO\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[20\] " "Ignored I/O standard assignment to node \"GPIO\[20\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[21\] " "Ignored I/O standard assignment to node \"GPIO\[21\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[22\] " "Ignored I/O standard assignment to node \"GPIO\[22\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[23\] " "Ignored I/O standard assignment to node \"GPIO\[23\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[24\] " "Ignored I/O standard assignment to node \"GPIO\[24\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[25\] " "Ignored I/O standard assignment to node \"GPIO\[25\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[26\] " "Ignored I/O standard assignment to node \"GPIO\[26\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[27\] " "Ignored I/O standard assignment to node \"GPIO\[27\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[28\] " "Ignored I/O standard assignment to node \"GPIO\[28\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[29\] " "Ignored I/O standard assignment to node \"GPIO\[29\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[2\] " "Ignored I/O standard assignment to node \"GPIO\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[30\] " "Ignored I/O standard assignment to node \"GPIO\[30\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[31\] " "Ignored I/O standard assignment to node \"GPIO\[31\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[32\] " "Ignored I/O standard assignment to node \"GPIO\[32\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[33\] " "Ignored I/O standard assignment to node \"GPIO\[33\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[34\] " "Ignored I/O standard assignment to node \"GPIO\[34\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[35\] " "Ignored I/O standard assignment to node \"GPIO\[35\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[3\] " "Ignored I/O standard assignment to node \"GPIO\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[4\] " "Ignored I/O standard assignment to node \"GPIO\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[5\] " "Ignored I/O standard assignment to node \"GPIO\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[6\] " "Ignored I/O standard assignment to node \"GPIO\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[7\] " "Ignored I/O standard assignment to node \"GPIO\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[8\] " "Ignored I/O standard assignment to node \"GPIO\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[9\] " "Ignored I/O standard assignment to node \"GPIO\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN0 " "Ignored I/O standard assignment to node \"HSMC_CLKIN0\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN_N1 " "Ignored I/O standard assignment to node \"HSMC_CLKIN_N1\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN_N2 " "Ignored I/O standard assignment to node \"HSMC_CLKIN_N2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN_P1 " "Ignored I/O standard assignment to node \"HSMC_CLKIN_P1\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN_P2 " "Ignored I/O standard assignment to node \"HSMC_CLKIN_P2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT0 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT0\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT_N1 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT_N1\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT_N2 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT_N2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT_P1 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT_P1\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT_P2 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT_P2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_D\[0\] " "Ignored I/O standard assignment to node \"HSMC_D\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_D\[1\] " "Ignored I/O standard assignment to node \"HSMC_D\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_D\[2\] " "Ignored I/O standard assignment to node \"HSMC_D\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_D\[3\] " "Ignored I/O standard assignment to node \"HSMC_D\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "I2C_SCLK " "Ignored I/O standard assignment to node \"I2C_SCLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "I2C_SDAT " "Ignored I/O standard assignment to node \"I2C_SDAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "IRDA_RXD " "Ignored I/O standard assignment to node \"IRDA_RXD\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LEDG\[8\] " "Ignored I/O standard assignment to node \"LEDG\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_ADDR\[0\] " "Ignored I/O standard assignment to node \"OTG_ADDR\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_ADDR\[1\] " "Ignored I/O standard assignment to node \"OTG_ADDR\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_CS_N " "Ignored I/O standard assignment to node \"OTG_CS_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DACK_N\[0\] " "Ignored I/O standard assignment to node \"OTG_DACK_N\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DACK_N\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DACK_N\[1\] " "Ignored I/O standard assignment to node \"OTG_DACK_N\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DACK_N\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[0\] " "Ignored I/O standard assignment to node \"OTG_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[10\] " "Ignored I/O standard assignment to node \"OTG_DATA\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[11\] " "Ignored I/O standard assignment to node \"OTG_DATA\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[12\] " "Ignored I/O standard assignment to node \"OTG_DATA\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[13\] " "Ignored I/O standard assignment to node \"OTG_DATA\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[14\] " "Ignored I/O standard assignment to node \"OTG_DATA\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[15\] " "Ignored I/O standard assignment to node \"OTG_DATA\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[1\] " "Ignored I/O standard assignment to node \"OTG_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[2\] " "Ignored I/O standard assignment to node \"OTG_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[3\] " "Ignored I/O standard assignment to node \"OTG_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[4\] " "Ignored I/O standard assignment to node \"OTG_DATA\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[5\] " "Ignored I/O standard assignment to node \"OTG_DATA\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[6\] " "Ignored I/O standard assignment to node \"OTG_DATA\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[7\] " "Ignored I/O standard assignment to node \"OTG_DATA\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[8\] " "Ignored I/O standard assignment to node \"OTG_DATA\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[9\] " "Ignored I/O standard assignment to node \"OTG_DATA\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DREQ\[0\] " "Ignored I/O standard assignment to node \"OTG_DREQ\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DREQ\[1\] " "Ignored I/O standard assignment to node \"OTG_DREQ\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_FSPEED " "Ignored I/O standard assignment to node \"OTG_FSPEED\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_FSPEED" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_INT\[0\] " "Ignored I/O standard assignment to node \"OTG_INT\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_INT\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_INT\[1\] " "Ignored I/O standard assignment to node \"OTG_INT\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_INT\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_LSPEED " "Ignored I/O standard assignment to node \"OTG_LSPEED\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_LSPEED" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_RD_N " "Ignored I/O standard assignment to node \"OTG_RD_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_RST_N " "Ignored I/O standard assignment to node \"OTG_RST_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_WR_N " "Ignored I/O standard assignment to node \"OTG_WR_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_CLK " "Ignored I/O standard assignment to node \"PS2_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_CLK2 " "Ignored I/O standard assignment to node \"PS2_CLK2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_DAT " "Ignored I/O standard assignment to node \"PS2_DAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_DAT2 " "Ignored I/O standard assignment to node \"PS2_DAT2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_CLK " "Ignored I/O standard assignment to node \"SD_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_CMD " "Ignored I/O standard assignment to node \"SD_CMD\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT\[0\] " "Ignored I/O standard assignment to node \"SD_DAT\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT\[1\] " "Ignored I/O standard assignment to node \"SD_DAT\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT\[2\] " "Ignored I/O standard assignment to node \"SD_DAT\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT\[3\] " "Ignored I/O standard assignment to node \"SD_DAT\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_WP_N " "Ignored I/O standard assignment to node \"SD_WP_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SMA_CLKIN " "Ignored I/O standard assignment to node \"SMA_CLKIN\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SMA_CLKOUT " "Ignored I/O standard assignment to node \"SMA_CLKOUT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[0\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[10\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[11\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[12\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[13\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[14\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[15\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[16\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[17\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[17\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[18\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[18\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[19\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[19\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[1\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[2\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[3\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[4\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[5\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[6\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[7\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[8\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[9\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_CE_N " "Ignored I/O standard assignment to node \"SRAM_CE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[0\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[10\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[11\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[12\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[13\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[14\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[15\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[1\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[2\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[3\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[4\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[5\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[6\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[7\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[8\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[9\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_LB_N " "Ignored I/O standard assignment to node \"SRAM_LB_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_OE_N " "Ignored I/O standard assignment to node \"SRAM_OE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_UB_N " "Ignored I/O standard assignment to node \"SRAM_UB_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_WE_N " "Ignored I/O standard assignment to node \"SRAM_WE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_CLK27 " "Ignored I/O standard assignment to node \"TD_CLK27\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[0\] " "Ignored I/O standard assignment to node \"TD_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[1\] " "Ignored I/O standard assignment to node \"TD_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[2\] " "Ignored I/O standard assignment to node \"TD_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[3\] " "Ignored I/O standard assignment to node \"TD_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[4\] " "Ignored I/O standard assignment to node \"TD_DATA\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[5\] " "Ignored I/O standard assignment to node \"TD_DATA\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[6\] " "Ignored I/O standard assignment to node \"TD_DATA\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[7\] " "Ignored I/O standard assignment to node \"TD_DATA\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_HS " "Ignored I/O standard assignment to node \"TD_HS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_RESET_N " "Ignored I/O standard assignment to node \"TD_RESET_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_VS " "Ignored I/O standard assignment to node \"TD_VS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_CTS " "Ignored I/O standard assignment to node \"UART_CTS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_RTS " "Ignored I/O standard assignment to node \"UART_RTS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_RXD " "Ignored I/O standard assignment to node \"UART_RXD\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_TXD " "Ignored I/O standard assignment to node \"UART_TXD\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_BLANK_N " "Ignored I/O standard assignment to node \"VGA_BLANK_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[0\] " "Ignored I/O standard assignment to node \"VGA_B\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[1\] " "Ignored I/O standard assignment to node \"VGA_B\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[2\] " "Ignored I/O standard assignment to node \"VGA_B\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[3\] " "Ignored I/O standard assignment to node \"VGA_B\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[4\] " "Ignored I/O standard assignment to node \"VGA_B\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[5\] " "Ignored I/O standard assignment to node \"VGA_B\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[6\] " "Ignored I/O standard assignment to node \"VGA_B\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[7\] " "Ignored I/O standard assignment to node \"VGA_B\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_CLK " "Ignored I/O standard assignment to node \"VGA_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[0\] " "Ignored I/O standard assignment to node \"VGA_G\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[1\] " "Ignored I/O standard assignment to node \"VGA_G\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[2\] " "Ignored I/O standard assignment to node \"VGA_G\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[3\] " "Ignored I/O standard assignment to node \"VGA_G\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[4\] " "Ignored I/O standard assignment to node \"VGA_G\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[5\] " "Ignored I/O standard assignment to node \"VGA_G\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[6\] " "Ignored I/O standard assignment to node \"VGA_G\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[7\] " "Ignored I/O standard assignment to node \"VGA_G\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_HS " "Ignored I/O standard assignment to node \"VGA_HS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[0\] " "Ignored I/O standard assignment to node \"VGA_R\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[1\] " "Ignored I/O standard assignment to node \"VGA_R\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[2\] " "Ignored I/O standard assignment to node \"VGA_R\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[3\] " "Ignored I/O standard assignment to node \"VGA_R\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[4\] " "Ignored I/O standard assignment to node \"VGA_R\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[5\] " "Ignored I/O standard assignment to node \"VGA_R\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[6\] " "Ignored I/O standard assignment to node \"VGA_R\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[7\] " "Ignored I/O standard assignment to node \"VGA_R\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_SYNC_N " "Ignored I/O standard assignment to node \"VGA_SYNC_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_VS " "Ignored I/O standard assignment to node \"VGA_VS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} } { } 0 15709 "Ignored I/O standard assignments to the following nodes" 0 0 "Fitter" 0 -1 1482368883390 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DACK_N\[0\] " "Node \"OTG_DACK_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DACK_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DACK_N\[1\] " "Node \"OTG_DACK_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DACK_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[1\] " "Node \"OTG_DREQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_FSPEED " "Node \"OTG_FSPEED\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_FSPEED" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT\[0\] " "Node \"OTG_INT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_INT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT\[1\] " "Node \"OTG_INT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_INT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_LSPEED " "Node \"OTG_LSPEED\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_LSPEED" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1482368883435 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:08 " "Fitter preparation operations ending: elapsed time is 00:00:08" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1482368883485 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1482368892897 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Fitter placement preparation operations ending: elapsed time is 00:00:02" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1482368894400 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1482368894431 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1482368896380 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1482368896380 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1482368897502 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 " "Router estimated average interconnect usage is 2% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "18 X46_Y24 X57_Y36 " "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X46_Y24 to location X57_Y36" { } { { "loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 1 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X46_Y24 to location X57_Y36"} { { 11 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X46_Y24 to location X57_Y36"} 46 24 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1482368903174 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1482368903174 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Fitter routing operations ending: elapsed time is 00:00:04" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1482368904176 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1482368904176 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1482368904176 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1482368904176 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.84 " "Total time spent on timing analysis during the Fitter is 0.84 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1482368904345 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1482368904430 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1482368905498 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1482368905576 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1482368906647 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1482368907900 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1482368909597 ""} -{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "9 Cyclone IV E " "9 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[0\] 3.3-V LVTTL L3 " "Pin LCD_data\[0\] uses I/O standard 3.3-V LVTTL at L3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[0\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 352 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1482368909634 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[1\] 3.3-V LVTTL L1 " "Pin LCD_data\[1\] uses I/O standard 3.3-V LVTTL at L1" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[1\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 353 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1482368909634 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[2\] 3.3-V LVTTL L2 " "Pin LCD_data\[2\] uses I/O standard 3.3-V LVTTL at L2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[2\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 354 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1482368909634 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[3\] 3.3-V LVTTL K7 " "Pin LCD_data\[3\] uses I/O standard 3.3-V LVTTL at K7" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[3\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 355 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1482368909634 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[4\] 3.3-V LVTTL K1 " "Pin LCD_data\[4\] uses I/O standard 3.3-V LVTTL at K1" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[4\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 356 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1482368909634 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[5\] 3.3-V LVTTL K2 " "Pin LCD_data\[5\] uses I/O standard 3.3-V LVTTL at K2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[5\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 357 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1482368909634 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[6\] 3.3-V LVTTL M3 " "Pin LCD_data\[6\] uses I/O standard 3.3-V LVTTL at M3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[6\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 358 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1482368909634 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[7\] 3.3-V LVTTL M5 " "Pin LCD_data\[7\] uses I/O standard 3.3-V LVTTL at M5" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[7\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 359 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1482368909634 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL Y2 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at Y2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { CLOCK_50 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 5 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 360 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1482368909634 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1482368909634 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.fit.smsg " "Generated suppressed messages file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1482368910689 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 827 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 827 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1017 " "Peak virtual memory: 1017 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1482368913407 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 22 10:08:33 2016 " "Processing ended: Thu Dec 22 10:08:33 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1482368913407 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:39 " "Elapsed time: 00:00:39" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1482368913407 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:38 " "Total CPU time (on all processors): 00:00:38" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1482368913407 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1482368913407 ""} diff --git a/db/lights.hier_info b/db/lights.hier_info deleted file mode 100644 index 2695faa..0000000 --- a/db/lights.hier_info +++ /dev/null @@ -1,68868 +0,0 @@ -|lights -CLOCK_50 => nios_system:NiosII.clk_clk -KEY[0] => nios_system:NiosII.reset_reset_n -KEY[1] => nios_system:NiosII.push_switches_export[0] -KEY[2] => nios_system:NiosII.push_switches_export[1] -KEY[3] => nios_system:NiosII.push_switches_export[2] -SW[0] => nios_system:NiosII.switches_export[0] -SW[1] => nios_system:NiosII.switches_export[1] -SW[2] => nios_system:NiosII.switches_export[2] -SW[3] => nios_system:NiosII.switches_export[3] -SW[4] => nios_system:NiosII.switches_export[4] -SW[5] => nios_system:NiosII.switches_export[5] -SW[6] => nios_system:NiosII.switches_export[6] -SW[7] => nios_system:NiosII.switches_export[7] -SW[8] => nios_system:NiosII.switches_export[8] -SW[9] => nios_system:NiosII.switches_export[9] -SW[10] => nios_system:NiosII.switches_export[10] -SW[11] => nios_system:NiosII.switches_export[11] -SW[12] => nios_system:NiosII.switches_export[12] -SW[13] => nios_system:NiosII.switches_export[13] -SW[14] => nios_system:NiosII.switches_export[14] -SW[15] => nios_system:NiosII.switches_export[15] -SW[16] => nios_system:NiosII.switches_export[16] -SW[17] => nios_system:NiosII.switches_export[17] -LEDG[0] <= nios_system:NiosII.leds_export[0] -LEDG[1] <= nios_system:NiosII.leds_export[1] -LEDG[2] <= nios_system:NiosII.leds_export[2] -LEDG[3] <= nios_system:NiosII.leds_export[3] -LEDG[4] <= nios_system:NiosII.leds_export[4] -LEDG[5] <= nios_system:NiosII.leds_export[5] -LEDG[6] <= nios_system:NiosII.leds_export[6] -LEDG[7] <= nios_system:NiosII.leds_export[7] -LEDR[0] <= nios_system:NiosII.ledrs_export[0] -LEDR[1] <= nios_system:NiosII.ledrs_export[1] -LEDR[2] <= nios_system:NiosII.ledrs_export[2] -LEDR[3] <= nios_system:NiosII.ledrs_export[3] -LEDR[4] <= nios_system:NiosII.ledrs_export[4] -LEDR[5] <= nios_system:NiosII.ledrs_export[5] -LEDR[6] <= nios_system:NiosII.ledrs_export[6] -LEDR[7] <= nios_system:NiosII.ledrs_export[7] -LEDR[8] <= nios_system:NiosII.ledrs_export[8] -LEDR[9] <= nios_system:NiosII.ledrs_export[9] -LEDR[10] <= nios_system:NiosII.ledrs_export[10] -LEDR[11] <= nios_system:NiosII.ledrs_export[11] -LEDR[12] <= nios_system:NiosII.ledrs_export[12] -LEDR[13] <= nios_system:NiosII.ledrs_export[13] -LEDR[14] <= nios_system:NiosII.ledrs_export[14] -LEDR[15] <= nios_system:NiosII.ledrs_export[15] -LEDR[16] <= nios_system:NiosII.ledrs_export[16] -LEDR[17] <= nios_system:NiosII.ledrs_export[17] -HEX0[0] <= nios_system:NiosII.hex0_export[0] -HEX0[1] <= nios_system:NiosII.hex0_export[1] -HEX0[2] <= nios_system:NiosII.hex0_export[2] -HEX0[3] <= nios_system:NiosII.hex0_export[3] -HEX0[4] <= nios_system:NiosII.hex0_export[4] -HEX0[5] <= nios_system:NiosII.hex0_export[5] -HEX0[6] <= nios_system:NiosII.hex0_export[6] -HEX1[0] <= nios_system:NiosII.hex1_export[0] -HEX1[1] <= nios_system:NiosII.hex1_export[1] -HEX1[2] <= nios_system:NiosII.hex1_export[2] -HEX1[3] <= nios_system:NiosII.hex1_export[3] -HEX1[4] <= nios_system:NiosII.hex1_export[4] -HEX1[5] <= nios_system:NiosII.hex1_export[5] -HEX1[6] <= nios_system:NiosII.hex1_export[6] -HEX2[0] <= nios_system:NiosII.hex2_export[0] -HEX2[1] <= nios_system:NiosII.hex2_export[1] -HEX2[2] <= nios_system:NiosII.hex2_export[2] -HEX2[3] <= nios_system:NiosII.hex2_export[3] -HEX2[4] <= nios_system:NiosII.hex2_export[4] -HEX2[5] <= nios_system:NiosII.hex2_export[5] -HEX2[6] <= nios_system:NiosII.hex2_export[6] -HEX3[0] <= nios_system:NiosII.hex3_export[0] -HEX3[1] <= nios_system:NiosII.hex3_export[1] -HEX3[2] <= nios_system:NiosII.hex3_export[2] -HEX3[3] <= nios_system:NiosII.hex3_export[3] -HEX3[4] <= nios_system:NiosII.hex3_export[4] -HEX3[5] <= nios_system:NiosII.hex3_export[5] -HEX3[6] <= nios_system:NiosII.hex3_export[6] -HEX4[0] <= nios_system:NiosII.hex4_export[0] -HEX4[1] <= nios_system:NiosII.hex4_export[1] -HEX4[2] <= nios_system:NiosII.hex4_export[2] -HEX4[3] <= nios_system:NiosII.hex4_export[3] -HEX4[4] <= nios_system:NiosII.hex4_export[4] -HEX4[5] <= nios_system:NiosII.hex4_export[5] -HEX4[6] <= nios_system:NiosII.hex4_export[6] -HEX5[0] <= nios_system:NiosII.hex5_export[0] -HEX5[1] <= nios_system:NiosII.hex5_export[1] -HEX5[2] <= nios_system:NiosII.hex5_export[2] -HEX5[3] <= nios_system:NiosII.hex5_export[3] -HEX5[4] <= nios_system:NiosII.hex5_export[4] -HEX5[5] <= nios_system:NiosII.hex5_export[5] -HEX5[6] <= nios_system:NiosII.hex5_export[6] -HEX6[0] <= nios_system:NiosII.hex6_export[0] -HEX6[1] <= nios_system:NiosII.hex6_export[1] -HEX6[2] <= nios_system:NiosII.hex6_export[2] -HEX6[3] <= nios_system:NiosII.hex6_export[3] -HEX6[4] <= nios_system:NiosII.hex6_export[4] -HEX6[5] <= nios_system:NiosII.hex6_export[5] -HEX6[6] <= nios_system:NiosII.hex6_export[6] -HEX7[0] <= nios_system:NiosII.hex7_export[0] -HEX7[1] <= nios_system:NiosII.hex7_export[1] -HEX7[2] <= nios_system:NiosII.hex7_export[2] -HEX7[3] <= nios_system:NiosII.hex7_export[3] -HEX7[4] <= nios_system:NiosII.hex7_export[4] -HEX7[5] <= nios_system:NiosII.hex7_export[5] -HEX7[6] <= nios_system:NiosII.hex7_export[6] -LCD_RS <= nios_system:NiosII.lcd_16207_0_RS -LCD_RW <= nios_system:NiosII.lcd_16207_0_RW -LCD_data[0] <= nios_system:NiosII.lcd_16207_0_data[0] -LCD_data[1] <= nios_system:NiosII.lcd_16207_0_data[1] -LCD_data[2] <= nios_system:NiosII.lcd_16207_0_data[2] -LCD_data[3] <= nios_system:NiosII.lcd_16207_0_data[3] -LCD_data[4] <= nios_system:NiosII.lcd_16207_0_data[4] -LCD_data[5] <= nios_system:NiosII.lcd_16207_0_data[5] -LCD_data[6] <= nios_system:NiosII.lcd_16207_0_data[6] -LCD_data[7] <= nios_system:NiosII.lcd_16207_0_data[7] -LCD_EN <= nios_system:NiosII.lcd_16207_0_E -LCD_ON <= nios_system:NiosII.lcd_on_export -LCD_BLON <= nios_system:NiosII.lcd_blon_export - - -|lights|nios_system:NiosII -clk_clk => clk_clk.IN122 -leds_export[0] <= nios_system_LEDs:leds.out_port -leds_export[1] <= nios_system_LEDs:leds.out_port -leds_export[2] <= nios_system_LEDs:leds.out_port -leds_export[3] <= nios_system_LEDs:leds.out_port -leds_export[4] <= nios_system_LEDs:leds.out_port -leds_export[5] <= nios_system_LEDs:leds.out_port -leds_export[6] <= nios_system_LEDs:leds.out_port -leds_export[7] <= nios_system_LEDs:leds.out_port -reset_reset_n => _.IN1 -ledrs_export[0] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[1] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[2] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[3] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[4] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[5] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[6] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[7] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[8] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[9] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[10] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[11] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[12] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[13] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[14] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[15] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[16] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[17] <= nios_system_LEDRs:ledrs.out_port -switches_export[0] => switches_export[0].IN1 -switches_export[1] => switches_export[1].IN1 -switches_export[2] => switches_export[2].IN1 -switches_export[3] => switches_export[3].IN1 -switches_export[4] => switches_export[4].IN1 -switches_export[5] => switches_export[5].IN1 -switches_export[6] => switches_export[6].IN1 -switches_export[7] => switches_export[7].IN1 -switches_export[8] => switches_export[8].IN1 -switches_export[9] => switches_export[9].IN1 -switches_export[10] => switches_export[10].IN1 -switches_export[11] => switches_export[11].IN1 -switches_export[12] => switches_export[12].IN1 -switches_export[13] => switches_export[13].IN1 -switches_export[14] => switches_export[14].IN1 -switches_export[15] => switches_export[15].IN1 -switches_export[16] => switches_export[16].IN1 -switches_export[17] => switches_export[17].IN1 -push_switches_export[0] => push_switches_export[0].IN1 -push_switches_export[1] => push_switches_export[1].IN1 -push_switches_export[2] => push_switches_export[2].IN1 -hex0_export[0] <= nios_system_hex0:hex0.out_port -hex0_export[1] <= nios_system_hex0:hex0.out_port -hex0_export[2] <= nios_system_hex0:hex0.out_port -hex0_export[3] <= nios_system_hex0:hex0.out_port -hex0_export[4] <= nios_system_hex0:hex0.out_port -hex0_export[5] <= nios_system_hex0:hex0.out_port -hex0_export[6] <= nios_system_hex0:hex0.out_port -hex1_export[0] <= nios_system_hex0:hex1.out_port -hex1_export[1] <= nios_system_hex0:hex1.out_port -hex1_export[2] <= nios_system_hex0:hex1.out_port -hex1_export[3] <= nios_system_hex0:hex1.out_port -hex1_export[4] <= nios_system_hex0:hex1.out_port -hex1_export[5] <= nios_system_hex0:hex1.out_port -hex1_export[6] <= nios_system_hex0:hex1.out_port -hex2_export[0] <= nios_system_hex0:hex2.out_port -hex2_export[1] <= nios_system_hex0:hex2.out_port -hex2_export[2] <= nios_system_hex0:hex2.out_port -hex2_export[3] <= nios_system_hex0:hex2.out_port -hex2_export[4] <= nios_system_hex0:hex2.out_port -hex2_export[5] <= nios_system_hex0:hex2.out_port -hex2_export[6] <= nios_system_hex0:hex2.out_port -hex3_export[0] <= nios_system_hex0:hex3.out_port -hex3_export[1] <= nios_system_hex0:hex3.out_port -hex3_export[2] <= nios_system_hex0:hex3.out_port -hex3_export[3] <= nios_system_hex0:hex3.out_port -hex3_export[4] <= nios_system_hex0:hex3.out_port -hex3_export[5] <= nios_system_hex0:hex3.out_port -hex3_export[6] <= nios_system_hex0:hex3.out_port -hex4_export[0] <= nios_system_hex0:hex4.out_port -hex4_export[1] <= nios_system_hex0:hex4.out_port -hex4_export[2] <= nios_system_hex0:hex4.out_port -hex4_export[3] <= nios_system_hex0:hex4.out_port -hex4_export[4] <= nios_system_hex0:hex4.out_port -hex4_export[5] <= nios_system_hex0:hex4.out_port -hex4_export[6] <= nios_system_hex0:hex4.out_port -hex5_export[0] <= nios_system_hex0:hex5.out_port -hex5_export[1] <= nios_system_hex0:hex5.out_port -hex5_export[2] <= nios_system_hex0:hex5.out_port -hex5_export[3] <= nios_system_hex0:hex5.out_port -hex5_export[4] <= nios_system_hex0:hex5.out_port -hex5_export[5] <= nios_system_hex0:hex5.out_port -hex5_export[6] <= nios_system_hex0:hex5.out_port -hex6_export[0] <= nios_system_hex0:hex6.out_port -hex6_export[1] <= nios_system_hex0:hex6.out_port -hex6_export[2] <= nios_system_hex0:hex6.out_port -hex6_export[3] <= nios_system_hex0:hex6.out_port -hex6_export[4] <= nios_system_hex0:hex6.out_port -hex6_export[5] <= nios_system_hex0:hex6.out_port -hex6_export[6] <= nios_system_hex0:hex6.out_port -hex7_export[0] <= nios_system_hex0:hex7.out_port -hex7_export[1] <= nios_system_hex0:hex7.out_port -hex7_export[2] <= nios_system_hex0:hex7.out_port -hex7_export[3] <= nios_system_hex0:hex7.out_port -hex7_export[4] <= nios_system_hex0:hex7.out_port -hex7_export[5] <= nios_system_hex0:hex7.out_port -hex7_export[6] <= nios_system_hex0:hex7.out_port -lcd_16207_0_RS <= nios_system_lcd_16207_0:lcd_16207_0.LCD_RS -lcd_16207_0_RW <= nios_system_lcd_16207_0:lcd_16207_0.LCD_RW -lcd_16207_0_data[0] <> nios_system_lcd_16207_0:lcd_16207_0.LCD_data -lcd_16207_0_data[1] <> nios_system_lcd_16207_0:lcd_16207_0.LCD_data -lcd_16207_0_data[2] <> nios_system_lcd_16207_0:lcd_16207_0.LCD_data -lcd_16207_0_data[3] <> nios_system_lcd_16207_0:lcd_16207_0.LCD_data -lcd_16207_0_data[4] <> nios_system_lcd_16207_0:lcd_16207_0.LCD_data -lcd_16207_0_data[5] <> nios_system_lcd_16207_0:lcd_16207_0.LCD_data -lcd_16207_0_data[6] <> nios_system_lcd_16207_0:lcd_16207_0.LCD_data -lcd_16207_0_data[7] <> nios_system_lcd_16207_0:lcd_16207_0.LCD_data -lcd_16207_0_E <= nios_system_lcd_16207_0:lcd_16207_0.LCD_E -lcd_on_export <= nios_system_lcd_on:lcd_on.out_port -lcd_blon_export <= nios_system_lcd_on:lcd_blon.out_port - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor -clk => clk.IN4 -d_irq[0] => ~NO_FANOUT~ -d_irq[1] => ~NO_FANOUT~ -d_irq[2] => ~NO_FANOUT~ -d_irq[3] => ~NO_FANOUT~ -d_irq[4] => ~NO_FANOUT~ -d_irq[5] => W_ipending_reg_nxt.IN1 -d_irq[6] => ~NO_FANOUT~ -d_irq[7] => ~NO_FANOUT~ -d_irq[8] => ~NO_FANOUT~ -d_irq[9] => ~NO_FANOUT~ -d_irq[10] => ~NO_FANOUT~ -d_irq[11] => ~NO_FANOUT~ -d_irq[12] => ~NO_FANOUT~ -d_irq[13] => ~NO_FANOUT~ -d_irq[14] => ~NO_FANOUT~ -d_irq[15] => ~NO_FANOUT~ -d_irq[16] => ~NO_FANOUT~ -d_irq[17] => ~NO_FANOUT~ -d_irq[18] => ~NO_FANOUT~ -d_irq[19] => ~NO_FANOUT~ -d_irq[20] => ~NO_FANOUT~ -d_irq[21] => ~NO_FANOUT~ -d_irq[22] => ~NO_FANOUT~ -d_irq[23] => ~NO_FANOUT~ -d_irq[24] => ~NO_FANOUT~ -d_irq[25] => ~NO_FANOUT~ -d_irq[26] => ~NO_FANOUT~ -d_irq[27] => ~NO_FANOUT~ -d_irq[28] => ~NO_FANOUT~ -d_irq[29] => ~NO_FANOUT~ -d_irq[30] => ~NO_FANOUT~ -d_irq[31] => ~NO_FANOUT~ -d_readdata[0] => av_ld_byte0_data_nxt.DATAA -d_readdata[1] => av_ld_byte0_data_nxt.DATAA -d_readdata[2] => av_ld_byte0_data_nxt.DATAA -d_readdata[3] => av_ld_byte0_data_nxt.DATAA -d_readdata[4] => av_ld_byte0_data_nxt.DATAA -d_readdata[5] => av_ld_byte0_data_nxt.DATAA -d_readdata[6] => av_ld_byte0_data_nxt.DATAA -d_readdata[7] => av_ld_byte0_data_nxt.DATAA -d_readdata[8] => av_ld_byte1_data_nxt.DATAA -d_readdata[9] => av_ld_byte1_data_nxt.DATAA -d_readdata[10] => av_ld_byte1_data_nxt.DATAA -d_readdata[11] => av_ld_byte1_data_nxt.DATAA -d_readdata[12] => av_ld_byte1_data_nxt.DATAA -d_readdata[13] => av_ld_byte1_data_nxt.DATAA -d_readdata[14] => av_ld_byte1_data_nxt.DATAA -d_readdata[15] => av_ld_byte1_data_nxt.DATAA -d_readdata[16] => av_ld_byte2_data_nxt.DATAA -d_readdata[17] => av_ld_byte2_data_nxt.DATAA -d_readdata[18] => av_ld_byte2_data_nxt.DATAA -d_readdata[19] => av_ld_byte2_data_nxt.DATAA -d_readdata[20] => av_ld_byte2_data_nxt.DATAA -d_readdata[21] => av_ld_byte2_data_nxt.DATAA -d_readdata[22] => av_ld_byte2_data_nxt.DATAA -d_readdata[23] => av_ld_byte2_data_nxt.DATAA -d_readdata[24] => av_ld_byte3_data_nxt.DATAA -d_readdata[25] => av_ld_byte3_data_nxt.DATAA -d_readdata[26] => av_ld_byte3_data_nxt.DATAA -d_readdata[27] => av_ld_byte3_data_nxt.DATAA -d_readdata[28] => av_ld_byte3_data_nxt.DATAA -d_readdata[29] => av_ld_byte3_data_nxt.DATAA -d_readdata[30] => av_ld_byte3_data_nxt.DATAA -d_readdata[31] => av_ld_byte3_data_nxt.DATAA -d_waitrequest => d_waitrequest.IN1 -i_readdata[0] => i_readdata[0].IN1 -i_readdata[1] => i_readdata[1].IN1 -i_readdata[2] => i_readdata[2].IN1 -i_readdata[3] => i_readdata[3].IN1 -i_readdata[4] => i_readdata[4].IN1 -i_readdata[5] => i_readdata[5].IN1 -i_readdata[6] => i_readdata[6].IN1 -i_readdata[7] => i_readdata[7].IN1 -i_readdata[8] => i_readdata[8].IN1 -i_readdata[9] => i_readdata[9].IN1 -i_readdata[10] => i_readdata[10].IN1 -i_readdata[11] => i_readdata[11].IN1 -i_readdata[12] => i_readdata[12].IN1 -i_readdata[13] => i_readdata[13].IN1 -i_readdata[14] => i_readdata[14].IN1 -i_readdata[15] => i_readdata[15].IN1 -i_readdata[16] => i_readdata[16].IN1 -i_readdata[17] => i_readdata[17].IN1 -i_readdata[18] => i_readdata[18].IN1 -i_readdata[19] => i_readdata[19].IN1 -i_readdata[20] => i_readdata[20].IN1 -i_readdata[21] => i_readdata[21].IN1 -i_readdata[22] => i_readdata[22].IN1 -i_readdata[23] => i_readdata[23].IN1 -i_readdata[24] => i_readdata[24].IN1 -i_readdata[25] => i_readdata[25].IN1 -i_readdata[26] => i_readdata[26].IN1 -i_readdata[27] => i_readdata[27].IN1 -i_readdata[28] => i_readdata[28].IN1 -i_readdata[29] => i_readdata[29].IN1 -i_readdata[30] => i_readdata[30].IN1 -i_readdata[31] => i_readdata[31].IN1 -i_waitrequest => i_waitrequest.IN1 -jtag_debug_module_address[0] => jtag_debug_module_address[0].IN1 -jtag_debug_module_address[1] => jtag_debug_module_address[1].IN1 -jtag_debug_module_address[2] => jtag_debug_module_address[2].IN1 -jtag_debug_module_address[3] => jtag_debug_module_address[3].IN1 -jtag_debug_module_address[4] => jtag_debug_module_address[4].IN1 -jtag_debug_module_address[5] => jtag_debug_module_address[5].IN1 -jtag_debug_module_address[6] => jtag_debug_module_address[6].IN1 -jtag_debug_module_address[7] => jtag_debug_module_address[7].IN1 -jtag_debug_module_address[8] => jtag_debug_module_address[8].IN1 -jtag_debug_module_byteenable[0] => jtag_debug_module_byteenable[0].IN1 -jtag_debug_module_byteenable[1] => jtag_debug_module_byteenable[1].IN1 -jtag_debug_module_byteenable[2] => jtag_debug_module_byteenable[2].IN1 -jtag_debug_module_byteenable[3] => jtag_debug_module_byteenable[3].IN1 -jtag_debug_module_debugaccess => jtag_debug_module_debugaccess.IN1 -jtag_debug_module_read => jtag_debug_module_read.IN1 -jtag_debug_module_write => jtag_debug_module_write.IN1 -jtag_debug_module_writedata[0] => jtag_debug_module_writedata[0].IN1 -jtag_debug_module_writedata[1] => jtag_debug_module_writedata[1].IN1 -jtag_debug_module_writedata[2] => jtag_debug_module_writedata[2].IN1 -jtag_debug_module_writedata[3] => jtag_debug_module_writedata[3].IN1 -jtag_debug_module_writedata[4] => jtag_debug_module_writedata[4].IN1 -jtag_debug_module_writedata[5] => jtag_debug_module_writedata[5].IN1 -jtag_debug_module_writedata[6] => jtag_debug_module_writedata[6].IN1 -jtag_debug_module_writedata[7] => jtag_debug_module_writedata[7].IN1 -jtag_debug_module_writedata[8] => jtag_debug_module_writedata[8].IN1 -jtag_debug_module_writedata[9] => jtag_debug_module_writedata[9].IN1 -jtag_debug_module_writedata[10] => jtag_debug_module_writedata[10].IN1 -jtag_debug_module_writedata[11] => jtag_debug_module_writedata[11].IN1 -jtag_debug_module_writedata[12] => jtag_debug_module_writedata[12].IN1 -jtag_debug_module_writedata[13] => jtag_debug_module_writedata[13].IN1 -jtag_debug_module_writedata[14] => jtag_debug_module_writedata[14].IN1 -jtag_debug_module_writedata[15] => jtag_debug_module_writedata[15].IN1 -jtag_debug_module_writedata[16] => jtag_debug_module_writedata[16].IN1 -jtag_debug_module_writedata[17] => jtag_debug_module_writedata[17].IN1 -jtag_debug_module_writedata[18] => jtag_debug_module_writedata[18].IN1 -jtag_debug_module_writedata[19] => jtag_debug_module_writedata[19].IN1 -jtag_debug_module_writedata[20] => jtag_debug_module_writedata[20].IN1 -jtag_debug_module_writedata[21] => jtag_debug_module_writedata[21].IN1 -jtag_debug_module_writedata[22] => jtag_debug_module_writedata[22].IN1 -jtag_debug_module_writedata[23] => jtag_debug_module_writedata[23].IN1 -jtag_debug_module_writedata[24] => jtag_debug_module_writedata[24].IN1 -jtag_debug_module_writedata[25] => jtag_debug_module_writedata[25].IN1 -jtag_debug_module_writedata[26] => jtag_debug_module_writedata[26].IN1 -jtag_debug_module_writedata[27] => jtag_debug_module_writedata[27].IN1 -jtag_debug_module_writedata[28] => jtag_debug_module_writedata[28].IN1 -jtag_debug_module_writedata[29] => jtag_debug_module_writedata[29].IN1 -jtag_debug_module_writedata[30] => jtag_debug_module_writedata[30].IN1 -jtag_debug_module_writedata[31] => jtag_debug_module_writedata[31].IN1 -reset_n => reset_n.IN2 -d_address[0] <= d_address[0].DB_MAX_OUTPUT_PORT_TYPE -d_address[1] <= d_address[1].DB_MAX_OUTPUT_PORT_TYPE -d_address[2] <= d_address[2].DB_MAX_OUTPUT_PORT_TYPE -d_address[3] <= d_address[3].DB_MAX_OUTPUT_PORT_TYPE -d_address[4] <= d_address[4].DB_MAX_OUTPUT_PORT_TYPE -d_address[5] <= d_address[5].DB_MAX_OUTPUT_PORT_TYPE -d_address[6] <= d_address[6].DB_MAX_OUTPUT_PORT_TYPE -d_address[7] <= d_address[7].DB_MAX_OUTPUT_PORT_TYPE -d_address[8] <= d_address[8].DB_MAX_OUTPUT_PORT_TYPE -d_address[9] <= d_address[9].DB_MAX_OUTPUT_PORT_TYPE -d_address[10] <= d_address[10].DB_MAX_OUTPUT_PORT_TYPE -d_address[11] <= d_address[11].DB_MAX_OUTPUT_PORT_TYPE -d_address[12] <= d_address[12].DB_MAX_OUTPUT_PORT_TYPE -d_address[13] <= d_address[13].DB_MAX_OUTPUT_PORT_TYPE -d_address[14] <= d_address[14].DB_MAX_OUTPUT_PORT_TYPE -d_address[15] <= d_address[15].DB_MAX_OUTPUT_PORT_TYPE -d_address[16] <= d_address[16].DB_MAX_OUTPUT_PORT_TYPE -d_address[17] <= d_address[17].DB_MAX_OUTPUT_PORT_TYPE -d_address[18] <= d_address[18].DB_MAX_OUTPUT_PORT_TYPE -d_byteenable[0] <= d_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -d_byteenable[1] <= d_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE -d_byteenable[2] <= d_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE -d_byteenable[3] <= d_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE -d_read <= d_read.DB_MAX_OUTPUT_PORT_TYPE -d_write <= d_write.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[0] <= d_writedata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[1] <= d_writedata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[2] <= d_writedata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[3] <= d_writedata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[4] <= d_writedata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[5] <= d_writedata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[6] <= d_writedata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[7] <= d_writedata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[8] <= d_writedata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[9] <= d_writedata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[10] <= d_writedata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[11] <= d_writedata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[12] <= d_writedata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[13] <= d_writedata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[14] <= d_writedata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[15] <= d_writedata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[16] <= d_writedata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[17] <= d_writedata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[18] <= d_writedata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[19] <= d_writedata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[20] <= d_writedata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[21] <= d_writedata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[22] <= d_writedata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[23] <= d_writedata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[24] <= d_writedata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[25] <= d_writedata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[26] <= d_writedata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[27] <= d_writedata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[28] <= d_writedata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[29] <= d_writedata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[30] <= d_writedata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[31] <= d_writedata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -i_address[0] <= i_address[0].DB_MAX_OUTPUT_PORT_TYPE -i_address[1] <= i_address[1].DB_MAX_OUTPUT_PORT_TYPE -i_address[2] <= i_address[2].DB_MAX_OUTPUT_PORT_TYPE -i_address[3] <= i_address[3].DB_MAX_OUTPUT_PORT_TYPE -i_address[4] <= i_address[4].DB_MAX_OUTPUT_PORT_TYPE -i_address[5] <= i_address[5].DB_MAX_OUTPUT_PORT_TYPE -i_address[6] <= i_address[6].DB_MAX_OUTPUT_PORT_TYPE -i_address[7] <= i_address[7].DB_MAX_OUTPUT_PORT_TYPE -i_address[8] <= i_address[8].DB_MAX_OUTPUT_PORT_TYPE -i_address[9] <= i_address[9].DB_MAX_OUTPUT_PORT_TYPE -i_address[10] <= i_address[10].DB_MAX_OUTPUT_PORT_TYPE -i_address[11] <= i_address[11].DB_MAX_OUTPUT_PORT_TYPE -i_address[12] <= i_address[12].DB_MAX_OUTPUT_PORT_TYPE -i_address[13] <= i_address[13].DB_MAX_OUTPUT_PORT_TYPE -i_address[14] <= i_address[14].DB_MAX_OUTPUT_PORT_TYPE -i_address[15] <= i_address[15].DB_MAX_OUTPUT_PORT_TYPE -i_address[16] <= i_address[16].DB_MAX_OUTPUT_PORT_TYPE -i_address[17] <= i_address[17].DB_MAX_OUTPUT_PORT_TYPE -i_address[18] <= i_address[18].DB_MAX_OUTPUT_PORT_TYPE -i_read <= i_read.DB_MAX_OUTPUT_PORT_TYPE -jtag_debug_module_debugaccess_to_roms <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.jtag_debug_module_debugaccess_to_roms -jtag_debug_module_readdata[0] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[1] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[2] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[3] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[4] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[5] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[6] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[7] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[8] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[9] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[10] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[11] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[12] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[13] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[14] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[15] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[16] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[17] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[18] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[19] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[20] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[21] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[22] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[23] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[24] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[25] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[26] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[27] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[28] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[29] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[30] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[31] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_resetrequest <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.resetrequest -jtag_debug_module_waitrequest <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.waitrequest -no_ci_readra <= - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench -D_iw[0] => ~NO_FANOUT~ -D_iw[1] => ~NO_FANOUT~ -D_iw[2] => ~NO_FANOUT~ -D_iw[3] => ~NO_FANOUT~ -D_iw[4] => ~NO_FANOUT~ -D_iw[5] => ~NO_FANOUT~ -D_iw[6] => ~NO_FANOUT~ -D_iw[7] => ~NO_FANOUT~ -D_iw[8] => ~NO_FANOUT~ -D_iw[9] => ~NO_FANOUT~ -D_iw[10] => ~NO_FANOUT~ -D_iw[11] => ~NO_FANOUT~ -D_iw[12] => ~NO_FANOUT~ -D_iw[13] => ~NO_FANOUT~ -D_iw[14] => ~NO_FANOUT~ -D_iw[15] => ~NO_FANOUT~ -D_iw[16] => ~NO_FANOUT~ -D_iw[17] => ~NO_FANOUT~ -D_iw[18] => ~NO_FANOUT~ -D_iw[19] => ~NO_FANOUT~ -D_iw[20] => ~NO_FANOUT~ -D_iw[21] => ~NO_FANOUT~ -D_iw[22] => ~NO_FANOUT~ -D_iw[23] => ~NO_FANOUT~ -D_iw[24] => ~NO_FANOUT~ -D_iw[25] => ~NO_FANOUT~ -D_iw[26] => ~NO_FANOUT~ -D_iw[27] => ~NO_FANOUT~ -D_iw[28] => ~NO_FANOUT~ -D_iw[29] => ~NO_FANOUT~ -D_iw[30] => ~NO_FANOUT~ -D_iw[31] => ~NO_FANOUT~ -D_iw_op[0] => ~NO_FANOUT~ -D_iw_op[1] => ~NO_FANOUT~ -D_iw_op[2] => ~NO_FANOUT~ -D_iw_op[3] => ~NO_FANOUT~ -D_iw_op[4] => ~NO_FANOUT~ -D_iw_op[5] => ~NO_FANOUT~ -D_iw_opx[0] => ~NO_FANOUT~ -D_iw_opx[1] => ~NO_FANOUT~ -D_iw_opx[2] => ~NO_FANOUT~ -D_iw_opx[3] => ~NO_FANOUT~ -D_iw_opx[4] => ~NO_FANOUT~ -D_iw_opx[5] => ~NO_FANOUT~ -D_valid => ~NO_FANOUT~ -E_valid => ~NO_FANOUT~ -F_pcb[0] => ~NO_FANOUT~ -F_pcb[1] => ~NO_FANOUT~ -F_pcb[2] => ~NO_FANOUT~ -F_pcb[3] => ~NO_FANOUT~ -F_pcb[4] => ~NO_FANOUT~ -F_pcb[5] => ~NO_FANOUT~ -F_pcb[6] => ~NO_FANOUT~ -F_pcb[7] => ~NO_FANOUT~ -F_pcb[8] => ~NO_FANOUT~ -F_pcb[9] => ~NO_FANOUT~ -F_pcb[10] => ~NO_FANOUT~ -F_pcb[11] => ~NO_FANOUT~ -F_pcb[12] => ~NO_FANOUT~ -F_pcb[13] => ~NO_FANOUT~ -F_pcb[14] => ~NO_FANOUT~ -F_pcb[15] => ~NO_FANOUT~ -F_pcb[16] => ~NO_FANOUT~ -F_pcb[17] => ~NO_FANOUT~ -F_pcb[18] => ~NO_FANOUT~ -F_valid => ~NO_FANOUT~ -R_ctrl_ld => ~NO_FANOUT~ -R_ctrl_ld_non_io => ~NO_FANOUT~ -R_dst_regnum[0] => ~NO_FANOUT~ -R_dst_regnum[1] => ~NO_FANOUT~ -R_dst_regnum[2] => ~NO_FANOUT~ -R_dst_regnum[3] => ~NO_FANOUT~ -R_dst_regnum[4] => ~NO_FANOUT~ -R_wr_dst_reg => ~NO_FANOUT~ -W_valid => ~NO_FANOUT~ -W_vinst[0] => ~NO_FANOUT~ -W_vinst[1] => ~NO_FANOUT~ -W_vinst[2] => ~NO_FANOUT~ -W_vinst[3] => ~NO_FANOUT~ -W_vinst[4] => ~NO_FANOUT~ -W_vinst[5] => ~NO_FANOUT~ -W_vinst[6] => ~NO_FANOUT~ -W_vinst[7] => ~NO_FANOUT~ -W_vinst[8] => ~NO_FANOUT~ -W_vinst[9] => ~NO_FANOUT~ -W_vinst[10] => ~NO_FANOUT~ -W_vinst[11] => ~NO_FANOUT~ -W_vinst[12] => ~NO_FANOUT~ -W_vinst[13] => ~NO_FANOUT~ -W_vinst[14] => ~NO_FANOUT~ -W_vinst[15] => ~NO_FANOUT~ -W_vinst[16] => ~NO_FANOUT~ -W_vinst[17] => ~NO_FANOUT~ -W_vinst[18] => ~NO_FANOUT~ -W_vinst[19] => ~NO_FANOUT~ -W_vinst[20] => ~NO_FANOUT~ -W_vinst[21] => ~NO_FANOUT~ -W_vinst[22] => ~NO_FANOUT~ -W_vinst[23] => ~NO_FANOUT~ -W_vinst[24] => ~NO_FANOUT~ -W_vinst[25] => ~NO_FANOUT~ -W_vinst[26] => ~NO_FANOUT~ -W_vinst[27] => ~NO_FANOUT~ -W_vinst[28] => ~NO_FANOUT~ -W_vinst[29] => ~NO_FANOUT~ -W_vinst[30] => ~NO_FANOUT~ -W_vinst[31] => ~NO_FANOUT~ -W_vinst[32] => ~NO_FANOUT~ -W_vinst[33] => ~NO_FANOUT~ -W_vinst[34] => ~NO_FANOUT~ -W_vinst[35] => ~NO_FANOUT~ -W_vinst[36] => ~NO_FANOUT~ -W_vinst[37] => ~NO_FANOUT~ -W_vinst[38] => ~NO_FANOUT~ -W_vinst[39] => ~NO_FANOUT~ -W_vinst[40] => ~NO_FANOUT~ -W_vinst[41] => ~NO_FANOUT~ -W_vinst[42] => ~NO_FANOUT~ -W_vinst[43] => ~NO_FANOUT~ -W_vinst[44] => ~NO_FANOUT~ -W_vinst[45] => ~NO_FANOUT~ -W_vinst[46] => ~NO_FANOUT~ -W_vinst[47] => ~NO_FANOUT~ -W_vinst[48] => ~NO_FANOUT~ -W_vinst[49] => ~NO_FANOUT~ -W_vinst[50] => ~NO_FANOUT~ -W_vinst[51] => ~NO_FANOUT~ -W_vinst[52] => ~NO_FANOUT~ -W_vinst[53] => ~NO_FANOUT~ -W_vinst[54] => ~NO_FANOUT~ -W_vinst[55] => ~NO_FANOUT~ -W_wr_data[0] => ~NO_FANOUT~ -W_wr_data[1] => ~NO_FANOUT~ -W_wr_data[2] => ~NO_FANOUT~ -W_wr_data[3] => ~NO_FANOUT~ -W_wr_data[4] => ~NO_FANOUT~ -W_wr_data[5] => ~NO_FANOUT~ -W_wr_data[6] => ~NO_FANOUT~ -W_wr_data[7] => ~NO_FANOUT~ -W_wr_data[8] => ~NO_FANOUT~ -W_wr_data[9] => ~NO_FANOUT~ -W_wr_data[10] => ~NO_FANOUT~ -W_wr_data[11] => ~NO_FANOUT~ -W_wr_data[12] => ~NO_FANOUT~ -W_wr_data[13] => ~NO_FANOUT~ -W_wr_data[14] => ~NO_FANOUT~ -W_wr_data[15] => ~NO_FANOUT~ -W_wr_data[16] => ~NO_FANOUT~ -W_wr_data[17] => ~NO_FANOUT~ -W_wr_data[18] => ~NO_FANOUT~ -W_wr_data[19] => ~NO_FANOUT~ -W_wr_data[20] => ~NO_FANOUT~ -W_wr_data[21] => ~NO_FANOUT~ -W_wr_data[22] => ~NO_FANOUT~ -W_wr_data[23] => ~NO_FANOUT~ -W_wr_data[24] => ~NO_FANOUT~ -W_wr_data[25] => ~NO_FANOUT~ -W_wr_data[26] => ~NO_FANOUT~ -W_wr_data[27] => ~NO_FANOUT~ -W_wr_data[28] => ~NO_FANOUT~ -W_wr_data[29] => ~NO_FANOUT~ -W_wr_data[30] => ~NO_FANOUT~ -W_wr_data[31] => ~NO_FANOUT~ -av_ld_data_aligned_unfiltered[0] => av_ld_data_aligned_filtered[0].DATAIN -av_ld_data_aligned_unfiltered[1] => av_ld_data_aligned_filtered[1].DATAIN -av_ld_data_aligned_unfiltered[2] => av_ld_data_aligned_filtered[2].DATAIN -av_ld_data_aligned_unfiltered[3] => av_ld_data_aligned_filtered[3].DATAIN -av_ld_data_aligned_unfiltered[4] => av_ld_data_aligned_filtered[4].DATAIN -av_ld_data_aligned_unfiltered[5] => av_ld_data_aligned_filtered[5].DATAIN -av_ld_data_aligned_unfiltered[6] => av_ld_data_aligned_filtered[6].DATAIN -av_ld_data_aligned_unfiltered[7] => av_ld_data_aligned_filtered[7].DATAIN -av_ld_data_aligned_unfiltered[8] => av_ld_data_aligned_filtered[8].DATAIN -av_ld_data_aligned_unfiltered[9] => av_ld_data_aligned_filtered[9].DATAIN -av_ld_data_aligned_unfiltered[10] => av_ld_data_aligned_filtered[10].DATAIN -av_ld_data_aligned_unfiltered[11] => av_ld_data_aligned_filtered[11].DATAIN -av_ld_data_aligned_unfiltered[12] => av_ld_data_aligned_filtered[12].DATAIN -av_ld_data_aligned_unfiltered[13] => av_ld_data_aligned_filtered[13].DATAIN -av_ld_data_aligned_unfiltered[14] => av_ld_data_aligned_filtered[14].DATAIN -av_ld_data_aligned_unfiltered[15] => av_ld_data_aligned_filtered[15].DATAIN -av_ld_data_aligned_unfiltered[16] => av_ld_data_aligned_filtered[16].DATAIN -av_ld_data_aligned_unfiltered[17] => av_ld_data_aligned_filtered[17].DATAIN -av_ld_data_aligned_unfiltered[18] => av_ld_data_aligned_filtered[18].DATAIN -av_ld_data_aligned_unfiltered[19] => av_ld_data_aligned_filtered[19].DATAIN -av_ld_data_aligned_unfiltered[20] => av_ld_data_aligned_filtered[20].DATAIN -av_ld_data_aligned_unfiltered[21] => av_ld_data_aligned_filtered[21].DATAIN -av_ld_data_aligned_unfiltered[22] => av_ld_data_aligned_filtered[22].DATAIN -av_ld_data_aligned_unfiltered[23] => av_ld_data_aligned_filtered[23].DATAIN -av_ld_data_aligned_unfiltered[24] => av_ld_data_aligned_filtered[24].DATAIN -av_ld_data_aligned_unfiltered[25] => av_ld_data_aligned_filtered[25].DATAIN -av_ld_data_aligned_unfiltered[26] => av_ld_data_aligned_filtered[26].DATAIN -av_ld_data_aligned_unfiltered[27] => av_ld_data_aligned_filtered[27].DATAIN -av_ld_data_aligned_unfiltered[28] => av_ld_data_aligned_filtered[28].DATAIN -av_ld_data_aligned_unfiltered[29] => av_ld_data_aligned_filtered[29].DATAIN -av_ld_data_aligned_unfiltered[30] => av_ld_data_aligned_filtered[30].DATAIN -av_ld_data_aligned_unfiltered[31] => av_ld_data_aligned_filtered[31].DATAIN -clk => d_write~reg0.CLK -d_address[0] => ~NO_FANOUT~ -d_address[1] => ~NO_FANOUT~ -d_address[2] => ~NO_FANOUT~ -d_address[3] => ~NO_FANOUT~ -d_address[4] => ~NO_FANOUT~ -d_address[5] => ~NO_FANOUT~ -d_address[6] => ~NO_FANOUT~ -d_address[7] => ~NO_FANOUT~ -d_address[8] => ~NO_FANOUT~ -d_address[9] => ~NO_FANOUT~ -d_address[10] => ~NO_FANOUT~ -d_address[11] => ~NO_FANOUT~ -d_address[12] => ~NO_FANOUT~ -d_address[13] => ~NO_FANOUT~ -d_address[14] => ~NO_FANOUT~ -d_address[15] => ~NO_FANOUT~ -d_address[16] => ~NO_FANOUT~ -d_address[17] => ~NO_FANOUT~ -d_address[18] => ~NO_FANOUT~ -d_byteenable[0] => ~NO_FANOUT~ -d_byteenable[1] => ~NO_FANOUT~ -d_byteenable[2] => ~NO_FANOUT~ -d_byteenable[3] => ~NO_FANOUT~ -d_read => ~NO_FANOUT~ -d_write_nxt => d_write~reg0.DATAIN -i_address[0] => ~NO_FANOUT~ -i_address[1] => ~NO_FANOUT~ -i_address[2] => ~NO_FANOUT~ -i_address[3] => ~NO_FANOUT~ -i_address[4] => ~NO_FANOUT~ -i_address[5] => ~NO_FANOUT~ -i_address[6] => ~NO_FANOUT~ -i_address[7] => ~NO_FANOUT~ -i_address[8] => ~NO_FANOUT~ -i_address[9] => ~NO_FANOUT~ -i_address[10] => ~NO_FANOUT~ -i_address[11] => ~NO_FANOUT~ -i_address[12] => ~NO_FANOUT~ -i_address[13] => ~NO_FANOUT~ -i_address[14] => ~NO_FANOUT~ -i_address[15] => ~NO_FANOUT~ -i_address[16] => ~NO_FANOUT~ -i_address[17] => ~NO_FANOUT~ -i_address[18] => ~NO_FANOUT~ -i_read => ~NO_FANOUT~ -i_readdata[0] => ~NO_FANOUT~ -i_readdata[1] => ~NO_FANOUT~ -i_readdata[2] => ~NO_FANOUT~ -i_readdata[3] => ~NO_FANOUT~ -i_readdata[4] => ~NO_FANOUT~ -i_readdata[5] => ~NO_FANOUT~ -i_readdata[6] => ~NO_FANOUT~ -i_readdata[7] => ~NO_FANOUT~ -i_readdata[8] => ~NO_FANOUT~ -i_readdata[9] => ~NO_FANOUT~ -i_readdata[10] => ~NO_FANOUT~ -i_readdata[11] => ~NO_FANOUT~ -i_readdata[12] => ~NO_FANOUT~ -i_readdata[13] => ~NO_FANOUT~ -i_readdata[14] => ~NO_FANOUT~ -i_readdata[15] => ~NO_FANOUT~ -i_readdata[16] => ~NO_FANOUT~ -i_readdata[17] => ~NO_FANOUT~ -i_readdata[18] => ~NO_FANOUT~ -i_readdata[19] => ~NO_FANOUT~ -i_readdata[20] => ~NO_FANOUT~ -i_readdata[21] => ~NO_FANOUT~ -i_readdata[22] => ~NO_FANOUT~ -i_readdata[23] => ~NO_FANOUT~ -i_readdata[24] => ~NO_FANOUT~ -i_readdata[25] => ~NO_FANOUT~ -i_readdata[26] => ~NO_FANOUT~ -i_readdata[27] => ~NO_FANOUT~ -i_readdata[28] => ~NO_FANOUT~ -i_readdata[29] => ~NO_FANOUT~ -i_readdata[30] => ~NO_FANOUT~ -i_readdata[31] => ~NO_FANOUT~ -i_waitrequest => ~NO_FANOUT~ -reset_n => d_write~reg0.ACLR -av_ld_data_aligned_filtered[0] <= av_ld_data_aligned_unfiltered[0].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[1] <= av_ld_data_aligned_unfiltered[1].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[2] <= av_ld_data_aligned_unfiltered[2].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[3] <= av_ld_data_aligned_unfiltered[3].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[4] <= av_ld_data_aligned_unfiltered[4].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[5] <= av_ld_data_aligned_unfiltered[5].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[6] <= av_ld_data_aligned_unfiltered[6].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[7] <= av_ld_data_aligned_unfiltered[7].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[8] <= av_ld_data_aligned_unfiltered[8].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[9] <= av_ld_data_aligned_unfiltered[9].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[10] <= av_ld_data_aligned_unfiltered[10].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[11] <= av_ld_data_aligned_unfiltered[11].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[12] <= av_ld_data_aligned_unfiltered[12].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[13] <= av_ld_data_aligned_unfiltered[13].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[14] <= av_ld_data_aligned_unfiltered[14].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[15] <= av_ld_data_aligned_unfiltered[15].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[16] <= av_ld_data_aligned_unfiltered[16].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[17] <= av_ld_data_aligned_unfiltered[17].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[18] <= av_ld_data_aligned_unfiltered[18].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[19] <= av_ld_data_aligned_unfiltered[19].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[20] <= av_ld_data_aligned_unfiltered[20].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[21] <= av_ld_data_aligned_unfiltered[21].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[22] <= av_ld_data_aligned_unfiltered[22].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[23] <= av_ld_data_aligned_unfiltered[23].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[24] <= av_ld_data_aligned_unfiltered[24].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[25] <= av_ld_data_aligned_unfiltered[25].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[26] <= av_ld_data_aligned_unfiltered[26].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[27] <= av_ld_data_aligned_unfiltered[27].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[28] <= av_ld_data_aligned_unfiltered[28].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[29] <= av_ld_data_aligned_unfiltered[29].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[30] <= av_ld_data_aligned_unfiltered[30].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[31] <= av_ld_data_aligned_unfiltered[31].DB_MAX_OUTPUT_PORT_TYPE -d_write <= d_write~reg0.DB_MAX_OUTPUT_PORT_TYPE -test_has_ended <= - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a -clock => clock.IN1 -data[0] => data[0].IN1 -data[1] => data[1].IN1 -data[2] => data[2].IN1 -data[3] => data[3].IN1 -data[4] => data[4].IN1 -data[5] => data[5].IN1 -data[6] => data[6].IN1 -data[7] => data[7].IN1 -data[8] => data[8].IN1 -data[9] => data[9].IN1 -data[10] => data[10].IN1 -data[11] => data[11].IN1 -data[12] => data[12].IN1 -data[13] => data[13].IN1 -data[14] => data[14].IN1 -data[15] => data[15].IN1 -data[16] => data[16].IN1 -data[17] => data[17].IN1 -data[18] => data[18].IN1 -data[19] => data[19].IN1 -data[20] => data[20].IN1 -data[21] => data[21].IN1 -data[22] => data[22].IN1 -data[23] => data[23].IN1 -data[24] => data[24].IN1 -data[25] => data[25].IN1 -data[26] => data[26].IN1 -data[27] => data[27].IN1 -data[28] => data[28].IN1 -data[29] => data[29].IN1 -data[30] => data[30].IN1 -data[31] => data[31].IN1 -rdaddress[0] => rdaddress[0].IN1 -rdaddress[1] => rdaddress[1].IN1 -rdaddress[2] => rdaddress[2].IN1 -rdaddress[3] => rdaddress[3].IN1 -rdaddress[4] => rdaddress[4].IN1 -wraddress[0] => wraddress[0].IN1 -wraddress[1] => wraddress[1].IN1 -wraddress[2] => wraddress[2].IN1 -wraddress[3] => wraddress[3].IN1 -wraddress[4] => wraddress[4].IN1 -wren => wren.IN1 -q[0] <= altsyncram:the_altsyncram.q_b -q[1] <= altsyncram:the_altsyncram.q_b -q[2] <= altsyncram:the_altsyncram.q_b -q[3] <= altsyncram:the_altsyncram.q_b -q[4] <= altsyncram:the_altsyncram.q_b -q[5] <= altsyncram:the_altsyncram.q_b -q[6] <= altsyncram:the_altsyncram.q_b -q[7] <= altsyncram:the_altsyncram.q_b -q[8] <= altsyncram:the_altsyncram.q_b -q[9] <= altsyncram:the_altsyncram.q_b -q[10] <= altsyncram:the_altsyncram.q_b -q[11] <= altsyncram:the_altsyncram.q_b -q[12] <= altsyncram:the_altsyncram.q_b -q[13] <= altsyncram:the_altsyncram.q_b -q[14] <= altsyncram:the_altsyncram.q_b -q[15] <= altsyncram:the_altsyncram.q_b -q[16] <= altsyncram:the_altsyncram.q_b -q[17] <= altsyncram:the_altsyncram.q_b -q[18] <= altsyncram:the_altsyncram.q_b -q[19] <= altsyncram:the_altsyncram.q_b -q[20] <= altsyncram:the_altsyncram.q_b -q[21] <= altsyncram:the_altsyncram.q_b -q[22] <= altsyncram:the_altsyncram.q_b -q[23] <= altsyncram:the_altsyncram.q_b -q[24] <= altsyncram:the_altsyncram.q_b -q[25] <= altsyncram:the_altsyncram.q_b -q[26] <= altsyncram:the_altsyncram.q_b -q[27] <= altsyncram:the_altsyncram.q_b -q[28] <= altsyncram:the_altsyncram.q_b -q[29] <= altsyncram:the_altsyncram.q_b -q[30] <= altsyncram:the_altsyncram.q_b -q[31] <= altsyncram:the_altsyncram.q_b - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram -wren_a => altsyncram_0rh1:auto_generated.wren_a -rden_a => ~NO_FANOUT~ -wren_b => ~NO_FANOUT~ -rden_b => ~NO_FANOUT~ -data_a[0] => altsyncram_0rh1:auto_generated.data_a[0] -data_a[1] => altsyncram_0rh1:auto_generated.data_a[1] -data_a[2] => altsyncram_0rh1:auto_generated.data_a[2] -data_a[3] => altsyncram_0rh1:auto_generated.data_a[3] -data_a[4] => altsyncram_0rh1:auto_generated.data_a[4] -data_a[5] => altsyncram_0rh1:auto_generated.data_a[5] -data_a[6] => altsyncram_0rh1:auto_generated.data_a[6] -data_a[7] => altsyncram_0rh1:auto_generated.data_a[7] -data_a[8] => altsyncram_0rh1:auto_generated.data_a[8] -data_a[9] => altsyncram_0rh1:auto_generated.data_a[9] -data_a[10] => altsyncram_0rh1:auto_generated.data_a[10] -data_a[11] => altsyncram_0rh1:auto_generated.data_a[11] -data_a[12] => altsyncram_0rh1:auto_generated.data_a[12] -data_a[13] => altsyncram_0rh1:auto_generated.data_a[13] -data_a[14] => altsyncram_0rh1:auto_generated.data_a[14] -data_a[15] => altsyncram_0rh1:auto_generated.data_a[15] -data_a[16] => altsyncram_0rh1:auto_generated.data_a[16] -data_a[17] => altsyncram_0rh1:auto_generated.data_a[17] -data_a[18] => altsyncram_0rh1:auto_generated.data_a[18] -data_a[19] => altsyncram_0rh1:auto_generated.data_a[19] -data_a[20] => altsyncram_0rh1:auto_generated.data_a[20] -data_a[21] => altsyncram_0rh1:auto_generated.data_a[21] -data_a[22] => altsyncram_0rh1:auto_generated.data_a[22] -data_a[23] => altsyncram_0rh1:auto_generated.data_a[23] -data_a[24] => altsyncram_0rh1:auto_generated.data_a[24] -data_a[25] => altsyncram_0rh1:auto_generated.data_a[25] -data_a[26] => altsyncram_0rh1:auto_generated.data_a[26] -data_a[27] => altsyncram_0rh1:auto_generated.data_a[27] -data_a[28] => altsyncram_0rh1:auto_generated.data_a[28] -data_a[29] => altsyncram_0rh1:auto_generated.data_a[29] -data_a[30] => altsyncram_0rh1:auto_generated.data_a[30] -data_a[31] => altsyncram_0rh1:auto_generated.data_a[31] -data_b[0] => ~NO_FANOUT~ -data_b[1] => ~NO_FANOUT~ -data_b[2] => ~NO_FANOUT~ -data_b[3] => ~NO_FANOUT~ -data_b[4] => ~NO_FANOUT~ -data_b[5] => ~NO_FANOUT~ -data_b[6] => ~NO_FANOUT~ -data_b[7] => ~NO_FANOUT~ -data_b[8] => ~NO_FANOUT~ -data_b[9] => ~NO_FANOUT~ -data_b[10] => ~NO_FANOUT~ -data_b[11] => ~NO_FANOUT~ -data_b[12] => ~NO_FANOUT~ -data_b[13] => ~NO_FANOUT~ -data_b[14] => ~NO_FANOUT~ -data_b[15] => ~NO_FANOUT~ -data_b[16] => ~NO_FANOUT~ -data_b[17] => ~NO_FANOUT~ -data_b[18] => ~NO_FANOUT~ -data_b[19] => ~NO_FANOUT~ -data_b[20] => ~NO_FANOUT~ -data_b[21] => ~NO_FANOUT~ -data_b[22] => ~NO_FANOUT~ -data_b[23] => ~NO_FANOUT~ -data_b[24] => ~NO_FANOUT~ -data_b[25] => ~NO_FANOUT~ -data_b[26] => ~NO_FANOUT~ -data_b[27] => ~NO_FANOUT~ -data_b[28] => ~NO_FANOUT~ -data_b[29] => ~NO_FANOUT~ -data_b[30] => ~NO_FANOUT~ -data_b[31] => ~NO_FANOUT~ -address_a[0] => altsyncram_0rh1:auto_generated.address_a[0] -address_a[1] => altsyncram_0rh1:auto_generated.address_a[1] -address_a[2] => altsyncram_0rh1:auto_generated.address_a[2] -address_a[3] => altsyncram_0rh1:auto_generated.address_a[3] -address_a[4] => altsyncram_0rh1:auto_generated.address_a[4] -address_b[0] => altsyncram_0rh1:auto_generated.address_b[0] -address_b[1] => altsyncram_0rh1:auto_generated.address_b[1] -address_b[2] => altsyncram_0rh1:auto_generated.address_b[2] -address_b[3] => altsyncram_0rh1:auto_generated.address_b[3] -address_b[4] => altsyncram_0rh1:auto_generated.address_b[4] -addressstall_a => ~NO_FANOUT~ -addressstall_b => ~NO_FANOUT~ -clock0 => altsyncram_0rh1:auto_generated.clock0 -clock1 => ~NO_FANOUT~ -clocken0 => ~NO_FANOUT~ -clocken1 => ~NO_FANOUT~ -clocken2 => ~NO_FANOUT~ -clocken3 => ~NO_FANOUT~ -aclr0 => ~NO_FANOUT~ -aclr1 => ~NO_FANOUT~ -byteena_a[0] => ~NO_FANOUT~ -byteena_b[0] => ~NO_FANOUT~ -q_a[0] <= -q_a[1] <= -q_a[2] <= -q_a[3] <= -q_a[4] <= -q_a[5] <= -q_a[6] <= -q_a[7] <= -q_a[8] <= -q_a[9] <= -q_a[10] <= -q_a[11] <= -q_a[12] <= -q_a[13] <= -q_a[14] <= -q_a[15] <= -q_a[16] <= -q_a[17] <= -q_a[18] <= -q_a[19] <= -q_a[20] <= -q_a[21] <= -q_a[22] <= -q_a[23] <= -q_a[24] <= -q_a[25] <= -q_a[26] <= -q_a[27] <= -q_a[28] <= -q_a[29] <= -q_a[30] <= -q_a[31] <= -q_b[0] <= altsyncram_0rh1:auto_generated.q_b[0] -q_b[1] <= altsyncram_0rh1:auto_generated.q_b[1] -q_b[2] <= altsyncram_0rh1:auto_generated.q_b[2] -q_b[3] <= altsyncram_0rh1:auto_generated.q_b[3] -q_b[4] <= altsyncram_0rh1:auto_generated.q_b[4] -q_b[5] <= altsyncram_0rh1:auto_generated.q_b[5] -q_b[6] <= altsyncram_0rh1:auto_generated.q_b[6] -q_b[7] <= altsyncram_0rh1:auto_generated.q_b[7] -q_b[8] <= altsyncram_0rh1:auto_generated.q_b[8] -q_b[9] <= altsyncram_0rh1:auto_generated.q_b[9] -q_b[10] <= altsyncram_0rh1:auto_generated.q_b[10] -q_b[11] <= altsyncram_0rh1:auto_generated.q_b[11] -q_b[12] <= altsyncram_0rh1:auto_generated.q_b[12] -q_b[13] <= altsyncram_0rh1:auto_generated.q_b[13] -q_b[14] <= altsyncram_0rh1:auto_generated.q_b[14] -q_b[15] <= altsyncram_0rh1:auto_generated.q_b[15] -q_b[16] <= altsyncram_0rh1:auto_generated.q_b[16] -q_b[17] <= altsyncram_0rh1:auto_generated.q_b[17] -q_b[18] <= altsyncram_0rh1:auto_generated.q_b[18] -q_b[19] <= altsyncram_0rh1:auto_generated.q_b[19] -q_b[20] <= altsyncram_0rh1:auto_generated.q_b[20] -q_b[21] <= altsyncram_0rh1:auto_generated.q_b[21] -q_b[22] <= altsyncram_0rh1:auto_generated.q_b[22] -q_b[23] <= altsyncram_0rh1:auto_generated.q_b[23] -q_b[24] <= altsyncram_0rh1:auto_generated.q_b[24] -q_b[25] <= altsyncram_0rh1:auto_generated.q_b[25] -q_b[26] <= altsyncram_0rh1:auto_generated.q_b[26] -q_b[27] <= altsyncram_0rh1:auto_generated.q_b[27] -q_b[28] <= altsyncram_0rh1:auto_generated.q_b[28] -q_b[29] <= altsyncram_0rh1:auto_generated.q_b[29] -q_b[30] <= altsyncram_0rh1:auto_generated.q_b[30] -q_b[31] <= altsyncram_0rh1:auto_generated.q_b[31] -eccstatus[0] <= -eccstatus[1] <= -eccstatus[2] <= - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated -address_a[0] => ram_block1a0.PORTAADDR -address_a[0] => ram_block1a1.PORTAADDR -address_a[0] => ram_block1a2.PORTAADDR -address_a[0] => ram_block1a3.PORTAADDR -address_a[0] => ram_block1a4.PORTAADDR -address_a[0] => ram_block1a5.PORTAADDR -address_a[0] => ram_block1a6.PORTAADDR -address_a[0] => ram_block1a7.PORTAADDR -address_a[0] => ram_block1a8.PORTAADDR -address_a[0] => ram_block1a9.PORTAADDR -address_a[0] => ram_block1a10.PORTAADDR -address_a[0] => ram_block1a11.PORTAADDR -address_a[0] => ram_block1a12.PORTAADDR -address_a[0] => ram_block1a13.PORTAADDR -address_a[0] => ram_block1a14.PORTAADDR -address_a[0] => ram_block1a15.PORTAADDR -address_a[0] => ram_block1a16.PORTAADDR -address_a[0] => ram_block1a17.PORTAADDR -address_a[0] => ram_block1a18.PORTAADDR -address_a[0] => ram_block1a19.PORTAADDR -address_a[0] => ram_block1a20.PORTAADDR -address_a[0] => ram_block1a21.PORTAADDR -address_a[0] => ram_block1a22.PORTAADDR -address_a[0] => ram_block1a23.PORTAADDR -address_a[0] => ram_block1a24.PORTAADDR -address_a[0] => ram_block1a25.PORTAADDR -address_a[0] => ram_block1a26.PORTAADDR -address_a[0] => ram_block1a27.PORTAADDR -address_a[0] => ram_block1a28.PORTAADDR -address_a[0] => ram_block1a29.PORTAADDR -address_a[0] => ram_block1a30.PORTAADDR -address_a[0] => ram_block1a31.PORTAADDR -address_a[1] => ram_block1a0.PORTAADDR1 -address_a[1] => ram_block1a1.PORTAADDR1 -address_a[1] => ram_block1a2.PORTAADDR1 -address_a[1] => ram_block1a3.PORTAADDR1 -address_a[1] => ram_block1a4.PORTAADDR1 -address_a[1] => ram_block1a5.PORTAADDR1 -address_a[1] => ram_block1a6.PORTAADDR1 -address_a[1] => ram_block1a7.PORTAADDR1 -address_a[1] => ram_block1a8.PORTAADDR1 -address_a[1] => ram_block1a9.PORTAADDR1 -address_a[1] => ram_block1a10.PORTAADDR1 -address_a[1] => ram_block1a11.PORTAADDR1 -address_a[1] => ram_block1a12.PORTAADDR1 -address_a[1] => ram_block1a13.PORTAADDR1 -address_a[1] => ram_block1a14.PORTAADDR1 -address_a[1] => ram_block1a15.PORTAADDR1 -address_a[1] => ram_block1a16.PORTAADDR1 -address_a[1] => ram_block1a17.PORTAADDR1 -address_a[1] => ram_block1a18.PORTAADDR1 -address_a[1] => ram_block1a19.PORTAADDR1 -address_a[1] => ram_block1a20.PORTAADDR1 -address_a[1] => ram_block1a21.PORTAADDR1 -address_a[1] => ram_block1a22.PORTAADDR1 -address_a[1] => ram_block1a23.PORTAADDR1 -address_a[1] => ram_block1a24.PORTAADDR1 -address_a[1] => ram_block1a25.PORTAADDR1 -address_a[1] => ram_block1a26.PORTAADDR1 -address_a[1] => ram_block1a27.PORTAADDR1 -address_a[1] => ram_block1a28.PORTAADDR1 -address_a[1] => ram_block1a29.PORTAADDR1 -address_a[1] => ram_block1a30.PORTAADDR1 -address_a[1] => ram_block1a31.PORTAADDR1 -address_a[2] => ram_block1a0.PORTAADDR2 -address_a[2] => ram_block1a1.PORTAADDR2 -address_a[2] => ram_block1a2.PORTAADDR2 -address_a[2] => ram_block1a3.PORTAADDR2 -address_a[2] => ram_block1a4.PORTAADDR2 -address_a[2] => ram_block1a5.PORTAADDR2 -address_a[2] => ram_block1a6.PORTAADDR2 -address_a[2] => ram_block1a7.PORTAADDR2 -address_a[2] => ram_block1a8.PORTAADDR2 -address_a[2] => ram_block1a9.PORTAADDR2 -address_a[2] => ram_block1a10.PORTAADDR2 -address_a[2] => ram_block1a11.PORTAADDR2 -address_a[2] => ram_block1a12.PORTAADDR2 -address_a[2] => ram_block1a13.PORTAADDR2 -address_a[2] => ram_block1a14.PORTAADDR2 -address_a[2] => ram_block1a15.PORTAADDR2 -address_a[2] => ram_block1a16.PORTAADDR2 -address_a[2] => ram_block1a17.PORTAADDR2 -address_a[2] => ram_block1a18.PORTAADDR2 -address_a[2] => ram_block1a19.PORTAADDR2 -address_a[2] => ram_block1a20.PORTAADDR2 -address_a[2] => ram_block1a21.PORTAADDR2 -address_a[2] => ram_block1a22.PORTAADDR2 -address_a[2] => ram_block1a23.PORTAADDR2 -address_a[2] => ram_block1a24.PORTAADDR2 -address_a[2] => ram_block1a25.PORTAADDR2 -address_a[2] => ram_block1a26.PORTAADDR2 -address_a[2] => ram_block1a27.PORTAADDR2 -address_a[2] => ram_block1a28.PORTAADDR2 -address_a[2] => ram_block1a29.PORTAADDR2 -address_a[2] => ram_block1a30.PORTAADDR2 -address_a[2] => ram_block1a31.PORTAADDR2 -address_a[3] => ram_block1a0.PORTAADDR3 -address_a[3] => ram_block1a1.PORTAADDR3 -address_a[3] => ram_block1a2.PORTAADDR3 -address_a[3] => ram_block1a3.PORTAADDR3 -address_a[3] => ram_block1a4.PORTAADDR3 -address_a[3] => ram_block1a5.PORTAADDR3 -address_a[3] => ram_block1a6.PORTAADDR3 -address_a[3] => ram_block1a7.PORTAADDR3 -address_a[3] => ram_block1a8.PORTAADDR3 -address_a[3] => ram_block1a9.PORTAADDR3 -address_a[3] => ram_block1a10.PORTAADDR3 -address_a[3] => ram_block1a11.PORTAADDR3 -address_a[3] => ram_block1a12.PORTAADDR3 -address_a[3] => ram_block1a13.PORTAADDR3 -address_a[3] => ram_block1a14.PORTAADDR3 -address_a[3] => ram_block1a15.PORTAADDR3 -address_a[3] => ram_block1a16.PORTAADDR3 -address_a[3] => ram_block1a17.PORTAADDR3 -address_a[3] => ram_block1a18.PORTAADDR3 -address_a[3] => ram_block1a19.PORTAADDR3 -address_a[3] => ram_block1a20.PORTAADDR3 -address_a[3] => ram_block1a21.PORTAADDR3 -address_a[3] => ram_block1a22.PORTAADDR3 -address_a[3] => ram_block1a23.PORTAADDR3 -address_a[3] => ram_block1a24.PORTAADDR3 -address_a[3] => ram_block1a25.PORTAADDR3 -address_a[3] => ram_block1a26.PORTAADDR3 -address_a[3] => ram_block1a27.PORTAADDR3 -address_a[3] => ram_block1a28.PORTAADDR3 -address_a[3] => ram_block1a29.PORTAADDR3 -address_a[3] => ram_block1a30.PORTAADDR3 -address_a[3] => ram_block1a31.PORTAADDR3 -address_a[4] => ram_block1a0.PORTAADDR4 -address_a[4] => ram_block1a1.PORTAADDR4 -address_a[4] => ram_block1a2.PORTAADDR4 -address_a[4] => ram_block1a3.PORTAADDR4 -address_a[4] => ram_block1a4.PORTAADDR4 -address_a[4] => ram_block1a5.PORTAADDR4 -address_a[4] => ram_block1a6.PORTAADDR4 -address_a[4] => ram_block1a7.PORTAADDR4 -address_a[4] => ram_block1a8.PORTAADDR4 -address_a[4] => ram_block1a9.PORTAADDR4 -address_a[4] => ram_block1a10.PORTAADDR4 -address_a[4] => ram_block1a11.PORTAADDR4 -address_a[4] => ram_block1a12.PORTAADDR4 -address_a[4] => ram_block1a13.PORTAADDR4 -address_a[4] => ram_block1a14.PORTAADDR4 -address_a[4] => ram_block1a15.PORTAADDR4 -address_a[4] => ram_block1a16.PORTAADDR4 -address_a[4] => ram_block1a17.PORTAADDR4 -address_a[4] => ram_block1a18.PORTAADDR4 -address_a[4] => ram_block1a19.PORTAADDR4 -address_a[4] => ram_block1a20.PORTAADDR4 -address_a[4] => ram_block1a21.PORTAADDR4 -address_a[4] => ram_block1a22.PORTAADDR4 -address_a[4] => ram_block1a23.PORTAADDR4 -address_a[4] => ram_block1a24.PORTAADDR4 -address_a[4] => ram_block1a25.PORTAADDR4 -address_a[4] => ram_block1a26.PORTAADDR4 -address_a[4] => ram_block1a27.PORTAADDR4 -address_a[4] => ram_block1a28.PORTAADDR4 -address_a[4] => ram_block1a29.PORTAADDR4 -address_a[4] => ram_block1a30.PORTAADDR4 -address_a[4] => ram_block1a31.PORTAADDR4 -address_b[0] => ram_block1a0.PORTBADDR -address_b[0] => ram_block1a1.PORTBADDR -address_b[0] => ram_block1a2.PORTBADDR -address_b[0] => ram_block1a3.PORTBADDR -address_b[0] => ram_block1a4.PORTBADDR -address_b[0] => ram_block1a5.PORTBADDR -address_b[0] => ram_block1a6.PORTBADDR -address_b[0] => ram_block1a7.PORTBADDR -address_b[0] => ram_block1a8.PORTBADDR -address_b[0] => ram_block1a9.PORTBADDR -address_b[0] => ram_block1a10.PORTBADDR -address_b[0] => ram_block1a11.PORTBADDR -address_b[0] => ram_block1a12.PORTBADDR -address_b[0] => ram_block1a13.PORTBADDR -address_b[0] => ram_block1a14.PORTBADDR -address_b[0] => ram_block1a15.PORTBADDR -address_b[0] => ram_block1a16.PORTBADDR -address_b[0] => ram_block1a17.PORTBADDR -address_b[0] => ram_block1a18.PORTBADDR -address_b[0] => ram_block1a19.PORTBADDR -address_b[0] => ram_block1a20.PORTBADDR -address_b[0] => ram_block1a21.PORTBADDR -address_b[0] => ram_block1a22.PORTBADDR -address_b[0] => ram_block1a23.PORTBADDR -address_b[0] => ram_block1a24.PORTBADDR -address_b[0] => ram_block1a25.PORTBADDR -address_b[0] => ram_block1a26.PORTBADDR -address_b[0] => ram_block1a27.PORTBADDR -address_b[0] => ram_block1a28.PORTBADDR -address_b[0] => ram_block1a29.PORTBADDR -address_b[0] => ram_block1a30.PORTBADDR -address_b[0] => ram_block1a31.PORTBADDR -address_b[1] => ram_block1a0.PORTBADDR1 -address_b[1] => ram_block1a1.PORTBADDR1 -address_b[1] => ram_block1a2.PORTBADDR1 -address_b[1] => ram_block1a3.PORTBADDR1 -address_b[1] => ram_block1a4.PORTBADDR1 -address_b[1] => ram_block1a5.PORTBADDR1 -address_b[1] => ram_block1a6.PORTBADDR1 -address_b[1] => ram_block1a7.PORTBADDR1 -address_b[1] => ram_block1a8.PORTBADDR1 -address_b[1] => ram_block1a9.PORTBADDR1 -address_b[1] => ram_block1a10.PORTBADDR1 -address_b[1] => ram_block1a11.PORTBADDR1 -address_b[1] => ram_block1a12.PORTBADDR1 -address_b[1] => ram_block1a13.PORTBADDR1 -address_b[1] => ram_block1a14.PORTBADDR1 -address_b[1] => ram_block1a15.PORTBADDR1 -address_b[1] => ram_block1a16.PORTBADDR1 -address_b[1] => ram_block1a17.PORTBADDR1 -address_b[1] => ram_block1a18.PORTBADDR1 -address_b[1] => ram_block1a19.PORTBADDR1 -address_b[1] => ram_block1a20.PORTBADDR1 -address_b[1] => ram_block1a21.PORTBADDR1 -address_b[1] => ram_block1a22.PORTBADDR1 -address_b[1] => ram_block1a23.PORTBADDR1 -address_b[1] => ram_block1a24.PORTBADDR1 -address_b[1] => ram_block1a25.PORTBADDR1 -address_b[1] => ram_block1a26.PORTBADDR1 -address_b[1] => ram_block1a27.PORTBADDR1 -address_b[1] => ram_block1a28.PORTBADDR1 -address_b[1] => ram_block1a29.PORTBADDR1 -address_b[1] => ram_block1a30.PORTBADDR1 -address_b[1] => ram_block1a31.PORTBADDR1 -address_b[2] => ram_block1a0.PORTBADDR2 -address_b[2] => ram_block1a1.PORTBADDR2 -address_b[2] => ram_block1a2.PORTBADDR2 -address_b[2] => ram_block1a3.PORTBADDR2 -address_b[2] => ram_block1a4.PORTBADDR2 -address_b[2] => ram_block1a5.PORTBADDR2 -address_b[2] => ram_block1a6.PORTBADDR2 -address_b[2] => ram_block1a7.PORTBADDR2 -address_b[2] => ram_block1a8.PORTBADDR2 -address_b[2] => ram_block1a9.PORTBADDR2 -address_b[2] => ram_block1a10.PORTBADDR2 -address_b[2] => ram_block1a11.PORTBADDR2 -address_b[2] => ram_block1a12.PORTBADDR2 -address_b[2] => ram_block1a13.PORTBADDR2 -address_b[2] => ram_block1a14.PORTBADDR2 -address_b[2] => ram_block1a15.PORTBADDR2 -address_b[2] => ram_block1a16.PORTBADDR2 -address_b[2] => ram_block1a17.PORTBADDR2 -address_b[2] => ram_block1a18.PORTBADDR2 -address_b[2] => ram_block1a19.PORTBADDR2 -address_b[2] => ram_block1a20.PORTBADDR2 -address_b[2] => ram_block1a21.PORTBADDR2 -address_b[2] => ram_block1a22.PORTBADDR2 -address_b[2] => ram_block1a23.PORTBADDR2 -address_b[2] => ram_block1a24.PORTBADDR2 -address_b[2] => ram_block1a25.PORTBADDR2 -address_b[2] => ram_block1a26.PORTBADDR2 -address_b[2] => ram_block1a27.PORTBADDR2 -address_b[2] => ram_block1a28.PORTBADDR2 -address_b[2] => ram_block1a29.PORTBADDR2 -address_b[2] => ram_block1a30.PORTBADDR2 -address_b[2] => ram_block1a31.PORTBADDR2 -address_b[3] => ram_block1a0.PORTBADDR3 -address_b[3] => ram_block1a1.PORTBADDR3 -address_b[3] => ram_block1a2.PORTBADDR3 -address_b[3] => ram_block1a3.PORTBADDR3 -address_b[3] => ram_block1a4.PORTBADDR3 -address_b[3] => ram_block1a5.PORTBADDR3 -address_b[3] => ram_block1a6.PORTBADDR3 -address_b[3] => ram_block1a7.PORTBADDR3 -address_b[3] => ram_block1a8.PORTBADDR3 -address_b[3] => ram_block1a9.PORTBADDR3 -address_b[3] => ram_block1a10.PORTBADDR3 -address_b[3] => ram_block1a11.PORTBADDR3 -address_b[3] => ram_block1a12.PORTBADDR3 -address_b[3] => ram_block1a13.PORTBADDR3 -address_b[3] => ram_block1a14.PORTBADDR3 -address_b[3] => ram_block1a15.PORTBADDR3 -address_b[3] => ram_block1a16.PORTBADDR3 -address_b[3] => ram_block1a17.PORTBADDR3 -address_b[3] => ram_block1a18.PORTBADDR3 -address_b[3] => ram_block1a19.PORTBADDR3 -address_b[3] => ram_block1a20.PORTBADDR3 -address_b[3] => ram_block1a21.PORTBADDR3 -address_b[3] => ram_block1a22.PORTBADDR3 -address_b[3] => ram_block1a23.PORTBADDR3 -address_b[3] => ram_block1a24.PORTBADDR3 -address_b[3] => ram_block1a25.PORTBADDR3 -address_b[3] => ram_block1a26.PORTBADDR3 -address_b[3] => ram_block1a27.PORTBADDR3 -address_b[3] => ram_block1a28.PORTBADDR3 -address_b[3] => ram_block1a29.PORTBADDR3 -address_b[3] => ram_block1a30.PORTBADDR3 -address_b[3] => ram_block1a31.PORTBADDR3 -address_b[4] => ram_block1a0.PORTBADDR4 -address_b[4] => ram_block1a1.PORTBADDR4 -address_b[4] => ram_block1a2.PORTBADDR4 -address_b[4] => ram_block1a3.PORTBADDR4 -address_b[4] => ram_block1a4.PORTBADDR4 -address_b[4] => ram_block1a5.PORTBADDR4 -address_b[4] => ram_block1a6.PORTBADDR4 -address_b[4] => ram_block1a7.PORTBADDR4 -address_b[4] => ram_block1a8.PORTBADDR4 -address_b[4] => ram_block1a9.PORTBADDR4 -address_b[4] => ram_block1a10.PORTBADDR4 -address_b[4] => ram_block1a11.PORTBADDR4 -address_b[4] => ram_block1a12.PORTBADDR4 -address_b[4] => ram_block1a13.PORTBADDR4 -address_b[4] => ram_block1a14.PORTBADDR4 -address_b[4] => ram_block1a15.PORTBADDR4 -address_b[4] => ram_block1a16.PORTBADDR4 -address_b[4] => ram_block1a17.PORTBADDR4 -address_b[4] => ram_block1a18.PORTBADDR4 -address_b[4] => ram_block1a19.PORTBADDR4 -address_b[4] => ram_block1a20.PORTBADDR4 -address_b[4] => ram_block1a21.PORTBADDR4 -address_b[4] => ram_block1a22.PORTBADDR4 -address_b[4] => ram_block1a23.PORTBADDR4 -address_b[4] => ram_block1a24.PORTBADDR4 -address_b[4] => ram_block1a25.PORTBADDR4 -address_b[4] => ram_block1a26.PORTBADDR4 -address_b[4] => ram_block1a27.PORTBADDR4 -address_b[4] => ram_block1a28.PORTBADDR4 -address_b[4] => ram_block1a29.PORTBADDR4 -address_b[4] => ram_block1a30.PORTBADDR4 -address_b[4] => ram_block1a31.PORTBADDR4 -clock0 => ram_block1a0.CLK0 -clock0 => ram_block1a1.CLK0 -clock0 => ram_block1a2.CLK0 -clock0 => ram_block1a3.CLK0 -clock0 => ram_block1a4.CLK0 -clock0 => ram_block1a5.CLK0 -clock0 => ram_block1a6.CLK0 -clock0 => ram_block1a7.CLK0 -clock0 => ram_block1a8.CLK0 -clock0 => ram_block1a9.CLK0 -clock0 => ram_block1a10.CLK0 -clock0 => ram_block1a11.CLK0 -clock0 => ram_block1a12.CLK0 -clock0 => ram_block1a13.CLK0 -clock0 => ram_block1a14.CLK0 -clock0 => ram_block1a15.CLK0 -clock0 => ram_block1a16.CLK0 -clock0 => ram_block1a17.CLK0 -clock0 => ram_block1a18.CLK0 -clock0 => ram_block1a19.CLK0 -clock0 => ram_block1a20.CLK0 -clock0 => ram_block1a21.CLK0 -clock0 => ram_block1a22.CLK0 -clock0 => ram_block1a23.CLK0 -clock0 => ram_block1a24.CLK0 -clock0 => ram_block1a25.CLK0 -clock0 => ram_block1a26.CLK0 -clock0 => ram_block1a27.CLK0 -clock0 => ram_block1a28.CLK0 -clock0 => ram_block1a29.CLK0 -clock0 => ram_block1a30.CLK0 -clock0 => ram_block1a31.CLK0 -data_a[0] => ram_block1a0.PORTADATAIN -data_a[1] => ram_block1a1.PORTADATAIN -data_a[2] => ram_block1a2.PORTADATAIN -data_a[3] => ram_block1a3.PORTADATAIN -data_a[4] => ram_block1a4.PORTADATAIN -data_a[5] => ram_block1a5.PORTADATAIN -data_a[6] => ram_block1a6.PORTADATAIN -data_a[7] => ram_block1a7.PORTADATAIN -data_a[8] => ram_block1a8.PORTADATAIN -data_a[9] => ram_block1a9.PORTADATAIN -data_a[10] => ram_block1a10.PORTADATAIN -data_a[11] => ram_block1a11.PORTADATAIN -data_a[12] => ram_block1a12.PORTADATAIN -data_a[13] => ram_block1a13.PORTADATAIN -data_a[14] => ram_block1a14.PORTADATAIN -data_a[15] => ram_block1a15.PORTADATAIN -data_a[16] => ram_block1a16.PORTADATAIN -data_a[17] => ram_block1a17.PORTADATAIN -data_a[18] => ram_block1a18.PORTADATAIN -data_a[19] => ram_block1a19.PORTADATAIN -data_a[20] => ram_block1a20.PORTADATAIN -data_a[21] => ram_block1a21.PORTADATAIN -data_a[22] => ram_block1a22.PORTADATAIN -data_a[23] => ram_block1a23.PORTADATAIN -data_a[24] => ram_block1a24.PORTADATAIN -data_a[25] => ram_block1a25.PORTADATAIN -data_a[26] => ram_block1a26.PORTADATAIN -data_a[27] => ram_block1a27.PORTADATAIN -data_a[28] => ram_block1a28.PORTADATAIN -data_a[29] => ram_block1a29.PORTADATAIN -data_a[30] => ram_block1a30.PORTADATAIN -data_a[31] => ram_block1a31.PORTADATAIN -q_b[0] <= ram_block1a0.PORTBDATAOUT -q_b[1] <= ram_block1a1.PORTBDATAOUT -q_b[2] <= ram_block1a2.PORTBDATAOUT -q_b[3] <= ram_block1a3.PORTBDATAOUT -q_b[4] <= ram_block1a4.PORTBDATAOUT -q_b[5] <= ram_block1a5.PORTBDATAOUT -q_b[6] <= ram_block1a6.PORTBDATAOUT -q_b[7] <= ram_block1a7.PORTBDATAOUT -q_b[8] <= ram_block1a8.PORTBDATAOUT -q_b[9] <= ram_block1a9.PORTBDATAOUT -q_b[10] <= ram_block1a10.PORTBDATAOUT -q_b[11] <= ram_block1a11.PORTBDATAOUT -q_b[12] <= ram_block1a12.PORTBDATAOUT -q_b[13] <= ram_block1a13.PORTBDATAOUT -q_b[14] <= ram_block1a14.PORTBDATAOUT -q_b[15] <= ram_block1a15.PORTBDATAOUT -q_b[16] <= ram_block1a16.PORTBDATAOUT -q_b[17] <= ram_block1a17.PORTBDATAOUT -q_b[18] <= ram_block1a18.PORTBDATAOUT -q_b[19] <= ram_block1a19.PORTBDATAOUT -q_b[20] <= ram_block1a20.PORTBDATAOUT -q_b[21] <= ram_block1a21.PORTBDATAOUT -q_b[22] <= ram_block1a22.PORTBDATAOUT -q_b[23] <= ram_block1a23.PORTBDATAOUT -q_b[24] <= ram_block1a24.PORTBDATAOUT -q_b[25] <= ram_block1a25.PORTBDATAOUT -q_b[26] <= ram_block1a26.PORTBDATAOUT -q_b[27] <= ram_block1a27.PORTBDATAOUT -q_b[28] <= ram_block1a28.PORTBDATAOUT -q_b[29] <= ram_block1a29.PORTBDATAOUT -q_b[30] <= ram_block1a30.PORTBDATAOUT -q_b[31] <= ram_block1a31.PORTBDATAOUT -wren_a => ram_block1a0.PORTAWE -wren_a => ram_block1a1.PORTAWE -wren_a => ram_block1a2.PORTAWE -wren_a => ram_block1a3.PORTAWE -wren_a => ram_block1a4.PORTAWE -wren_a => ram_block1a5.PORTAWE -wren_a => ram_block1a6.PORTAWE -wren_a => ram_block1a7.PORTAWE -wren_a => ram_block1a8.PORTAWE -wren_a => ram_block1a9.PORTAWE -wren_a => ram_block1a10.PORTAWE -wren_a => ram_block1a11.PORTAWE -wren_a => ram_block1a12.PORTAWE -wren_a => ram_block1a13.PORTAWE -wren_a => ram_block1a14.PORTAWE -wren_a => ram_block1a15.PORTAWE -wren_a => ram_block1a16.PORTAWE -wren_a => ram_block1a17.PORTAWE -wren_a => ram_block1a18.PORTAWE -wren_a => ram_block1a19.PORTAWE -wren_a => ram_block1a20.PORTAWE -wren_a => ram_block1a21.PORTAWE -wren_a => ram_block1a22.PORTAWE -wren_a => ram_block1a23.PORTAWE -wren_a => ram_block1a24.PORTAWE -wren_a => ram_block1a25.PORTAWE -wren_a => ram_block1a26.PORTAWE -wren_a => ram_block1a27.PORTAWE -wren_a => ram_block1a28.PORTAWE -wren_a => ram_block1a29.PORTAWE -wren_a => ram_block1a30.PORTAWE -wren_a => ram_block1a31.PORTAWE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b -clock => clock.IN1 -data[0] => data[0].IN1 -data[1] => data[1].IN1 -data[2] => data[2].IN1 -data[3] => data[3].IN1 -data[4] => data[4].IN1 -data[5] => data[5].IN1 -data[6] => data[6].IN1 -data[7] => data[7].IN1 -data[8] => data[8].IN1 -data[9] => data[9].IN1 -data[10] => data[10].IN1 -data[11] => data[11].IN1 -data[12] => data[12].IN1 -data[13] => data[13].IN1 -data[14] => data[14].IN1 -data[15] => data[15].IN1 -data[16] => data[16].IN1 -data[17] => data[17].IN1 -data[18] => data[18].IN1 -data[19] => data[19].IN1 -data[20] => data[20].IN1 -data[21] => data[21].IN1 -data[22] => data[22].IN1 -data[23] => data[23].IN1 -data[24] => data[24].IN1 -data[25] => data[25].IN1 -data[26] => data[26].IN1 -data[27] => data[27].IN1 -data[28] => data[28].IN1 -data[29] => data[29].IN1 -data[30] => data[30].IN1 -data[31] => data[31].IN1 -rdaddress[0] => rdaddress[0].IN1 -rdaddress[1] => rdaddress[1].IN1 -rdaddress[2] => rdaddress[2].IN1 -rdaddress[3] => rdaddress[3].IN1 -rdaddress[4] => rdaddress[4].IN1 -wraddress[0] => wraddress[0].IN1 -wraddress[1] => wraddress[1].IN1 -wraddress[2] => wraddress[2].IN1 -wraddress[3] => wraddress[3].IN1 -wraddress[4] => wraddress[4].IN1 -wren => wren.IN1 -q[0] <= altsyncram:the_altsyncram.q_b -q[1] <= altsyncram:the_altsyncram.q_b -q[2] <= altsyncram:the_altsyncram.q_b -q[3] <= altsyncram:the_altsyncram.q_b -q[4] <= altsyncram:the_altsyncram.q_b -q[5] <= altsyncram:the_altsyncram.q_b -q[6] <= altsyncram:the_altsyncram.q_b -q[7] <= altsyncram:the_altsyncram.q_b -q[8] <= altsyncram:the_altsyncram.q_b -q[9] <= altsyncram:the_altsyncram.q_b -q[10] <= altsyncram:the_altsyncram.q_b -q[11] <= altsyncram:the_altsyncram.q_b -q[12] <= altsyncram:the_altsyncram.q_b -q[13] <= altsyncram:the_altsyncram.q_b -q[14] <= altsyncram:the_altsyncram.q_b -q[15] <= altsyncram:the_altsyncram.q_b -q[16] <= altsyncram:the_altsyncram.q_b -q[17] <= altsyncram:the_altsyncram.q_b -q[18] <= altsyncram:the_altsyncram.q_b -q[19] <= altsyncram:the_altsyncram.q_b -q[20] <= altsyncram:the_altsyncram.q_b -q[21] <= altsyncram:the_altsyncram.q_b -q[22] <= altsyncram:the_altsyncram.q_b -q[23] <= altsyncram:the_altsyncram.q_b -q[24] <= altsyncram:the_altsyncram.q_b -q[25] <= altsyncram:the_altsyncram.q_b -q[26] <= altsyncram:the_altsyncram.q_b -q[27] <= altsyncram:the_altsyncram.q_b -q[28] <= altsyncram:the_altsyncram.q_b -q[29] <= altsyncram:the_altsyncram.q_b -q[30] <= altsyncram:the_altsyncram.q_b -q[31] <= altsyncram:the_altsyncram.q_b - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram -wren_a => altsyncram_1rh1:auto_generated.wren_a -rden_a => ~NO_FANOUT~ -wren_b => ~NO_FANOUT~ -rden_b => ~NO_FANOUT~ -data_a[0] => altsyncram_1rh1:auto_generated.data_a[0] -data_a[1] => altsyncram_1rh1:auto_generated.data_a[1] -data_a[2] => altsyncram_1rh1:auto_generated.data_a[2] -data_a[3] => altsyncram_1rh1:auto_generated.data_a[3] -data_a[4] => altsyncram_1rh1:auto_generated.data_a[4] -data_a[5] => altsyncram_1rh1:auto_generated.data_a[5] -data_a[6] => altsyncram_1rh1:auto_generated.data_a[6] -data_a[7] => altsyncram_1rh1:auto_generated.data_a[7] -data_a[8] => altsyncram_1rh1:auto_generated.data_a[8] -data_a[9] => altsyncram_1rh1:auto_generated.data_a[9] -data_a[10] => altsyncram_1rh1:auto_generated.data_a[10] -data_a[11] => altsyncram_1rh1:auto_generated.data_a[11] -data_a[12] => altsyncram_1rh1:auto_generated.data_a[12] -data_a[13] => altsyncram_1rh1:auto_generated.data_a[13] -data_a[14] => altsyncram_1rh1:auto_generated.data_a[14] -data_a[15] => altsyncram_1rh1:auto_generated.data_a[15] -data_a[16] => altsyncram_1rh1:auto_generated.data_a[16] -data_a[17] => altsyncram_1rh1:auto_generated.data_a[17] -data_a[18] => altsyncram_1rh1:auto_generated.data_a[18] -data_a[19] => altsyncram_1rh1:auto_generated.data_a[19] -data_a[20] => altsyncram_1rh1:auto_generated.data_a[20] -data_a[21] => altsyncram_1rh1:auto_generated.data_a[21] -data_a[22] => altsyncram_1rh1:auto_generated.data_a[22] -data_a[23] => altsyncram_1rh1:auto_generated.data_a[23] -data_a[24] => altsyncram_1rh1:auto_generated.data_a[24] -data_a[25] => altsyncram_1rh1:auto_generated.data_a[25] -data_a[26] => altsyncram_1rh1:auto_generated.data_a[26] -data_a[27] => altsyncram_1rh1:auto_generated.data_a[27] -data_a[28] => altsyncram_1rh1:auto_generated.data_a[28] -data_a[29] => altsyncram_1rh1:auto_generated.data_a[29] -data_a[30] => altsyncram_1rh1:auto_generated.data_a[30] -data_a[31] => altsyncram_1rh1:auto_generated.data_a[31] -data_b[0] => ~NO_FANOUT~ -data_b[1] => ~NO_FANOUT~ -data_b[2] => ~NO_FANOUT~ -data_b[3] => ~NO_FANOUT~ -data_b[4] => ~NO_FANOUT~ -data_b[5] => ~NO_FANOUT~ -data_b[6] => ~NO_FANOUT~ -data_b[7] => ~NO_FANOUT~ -data_b[8] => ~NO_FANOUT~ -data_b[9] => ~NO_FANOUT~ -data_b[10] => ~NO_FANOUT~ -data_b[11] => ~NO_FANOUT~ -data_b[12] => ~NO_FANOUT~ -data_b[13] => ~NO_FANOUT~ -data_b[14] => ~NO_FANOUT~ -data_b[15] => ~NO_FANOUT~ -data_b[16] => ~NO_FANOUT~ -data_b[17] => ~NO_FANOUT~ -data_b[18] => ~NO_FANOUT~ -data_b[19] => ~NO_FANOUT~ -data_b[20] => ~NO_FANOUT~ -data_b[21] => ~NO_FANOUT~ -data_b[22] => ~NO_FANOUT~ -data_b[23] => ~NO_FANOUT~ -data_b[24] => ~NO_FANOUT~ -data_b[25] => ~NO_FANOUT~ -data_b[26] => ~NO_FANOUT~ -data_b[27] => ~NO_FANOUT~ -data_b[28] => ~NO_FANOUT~ -data_b[29] => ~NO_FANOUT~ -data_b[30] => ~NO_FANOUT~ -data_b[31] => ~NO_FANOUT~ -address_a[0] => altsyncram_1rh1:auto_generated.address_a[0] -address_a[1] => altsyncram_1rh1:auto_generated.address_a[1] -address_a[2] => altsyncram_1rh1:auto_generated.address_a[2] -address_a[3] => altsyncram_1rh1:auto_generated.address_a[3] -address_a[4] => altsyncram_1rh1:auto_generated.address_a[4] -address_b[0] => altsyncram_1rh1:auto_generated.address_b[0] -address_b[1] => altsyncram_1rh1:auto_generated.address_b[1] -address_b[2] => altsyncram_1rh1:auto_generated.address_b[2] -address_b[3] => altsyncram_1rh1:auto_generated.address_b[3] -address_b[4] => altsyncram_1rh1:auto_generated.address_b[4] -addressstall_a => ~NO_FANOUT~ -addressstall_b => ~NO_FANOUT~ -clock0 => altsyncram_1rh1:auto_generated.clock0 -clock1 => ~NO_FANOUT~ -clocken0 => ~NO_FANOUT~ -clocken1 => ~NO_FANOUT~ -clocken2 => ~NO_FANOUT~ -clocken3 => ~NO_FANOUT~ -aclr0 => ~NO_FANOUT~ -aclr1 => ~NO_FANOUT~ -byteena_a[0] => ~NO_FANOUT~ -byteena_b[0] => ~NO_FANOUT~ -q_a[0] <= -q_a[1] <= -q_a[2] <= -q_a[3] <= -q_a[4] <= -q_a[5] <= -q_a[6] <= -q_a[7] <= -q_a[8] <= -q_a[9] <= -q_a[10] <= -q_a[11] <= -q_a[12] <= -q_a[13] <= -q_a[14] <= -q_a[15] <= -q_a[16] <= -q_a[17] <= -q_a[18] <= -q_a[19] <= -q_a[20] <= -q_a[21] <= -q_a[22] <= -q_a[23] <= -q_a[24] <= -q_a[25] <= -q_a[26] <= -q_a[27] <= -q_a[28] <= -q_a[29] <= -q_a[30] <= -q_a[31] <= -q_b[0] <= altsyncram_1rh1:auto_generated.q_b[0] -q_b[1] <= altsyncram_1rh1:auto_generated.q_b[1] -q_b[2] <= altsyncram_1rh1:auto_generated.q_b[2] -q_b[3] <= altsyncram_1rh1:auto_generated.q_b[3] -q_b[4] <= altsyncram_1rh1:auto_generated.q_b[4] -q_b[5] <= altsyncram_1rh1:auto_generated.q_b[5] -q_b[6] <= altsyncram_1rh1:auto_generated.q_b[6] -q_b[7] <= altsyncram_1rh1:auto_generated.q_b[7] -q_b[8] <= altsyncram_1rh1:auto_generated.q_b[8] -q_b[9] <= altsyncram_1rh1:auto_generated.q_b[9] -q_b[10] <= altsyncram_1rh1:auto_generated.q_b[10] -q_b[11] <= altsyncram_1rh1:auto_generated.q_b[11] -q_b[12] <= altsyncram_1rh1:auto_generated.q_b[12] -q_b[13] <= altsyncram_1rh1:auto_generated.q_b[13] -q_b[14] <= altsyncram_1rh1:auto_generated.q_b[14] -q_b[15] <= altsyncram_1rh1:auto_generated.q_b[15] -q_b[16] <= altsyncram_1rh1:auto_generated.q_b[16] -q_b[17] <= altsyncram_1rh1:auto_generated.q_b[17] -q_b[18] <= altsyncram_1rh1:auto_generated.q_b[18] -q_b[19] <= altsyncram_1rh1:auto_generated.q_b[19] -q_b[20] <= altsyncram_1rh1:auto_generated.q_b[20] -q_b[21] <= altsyncram_1rh1:auto_generated.q_b[21] -q_b[22] <= altsyncram_1rh1:auto_generated.q_b[22] -q_b[23] <= altsyncram_1rh1:auto_generated.q_b[23] -q_b[24] <= altsyncram_1rh1:auto_generated.q_b[24] -q_b[25] <= altsyncram_1rh1:auto_generated.q_b[25] -q_b[26] <= altsyncram_1rh1:auto_generated.q_b[26] -q_b[27] <= altsyncram_1rh1:auto_generated.q_b[27] -q_b[28] <= altsyncram_1rh1:auto_generated.q_b[28] -q_b[29] <= altsyncram_1rh1:auto_generated.q_b[29] -q_b[30] <= altsyncram_1rh1:auto_generated.q_b[30] -q_b[31] <= altsyncram_1rh1:auto_generated.q_b[31] -eccstatus[0] <= -eccstatus[1] <= -eccstatus[2] <= - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated -address_a[0] => ram_block1a0.PORTAADDR -address_a[0] => ram_block1a1.PORTAADDR -address_a[0] => ram_block1a2.PORTAADDR -address_a[0] => ram_block1a3.PORTAADDR -address_a[0] => ram_block1a4.PORTAADDR -address_a[0] => ram_block1a5.PORTAADDR -address_a[0] => ram_block1a6.PORTAADDR -address_a[0] => ram_block1a7.PORTAADDR -address_a[0] => ram_block1a8.PORTAADDR -address_a[0] => ram_block1a9.PORTAADDR -address_a[0] => ram_block1a10.PORTAADDR -address_a[0] => ram_block1a11.PORTAADDR -address_a[0] => ram_block1a12.PORTAADDR -address_a[0] => ram_block1a13.PORTAADDR -address_a[0] => ram_block1a14.PORTAADDR -address_a[0] => ram_block1a15.PORTAADDR -address_a[0] => ram_block1a16.PORTAADDR -address_a[0] => ram_block1a17.PORTAADDR -address_a[0] => ram_block1a18.PORTAADDR -address_a[0] => ram_block1a19.PORTAADDR -address_a[0] => ram_block1a20.PORTAADDR -address_a[0] => ram_block1a21.PORTAADDR -address_a[0] => ram_block1a22.PORTAADDR -address_a[0] => ram_block1a23.PORTAADDR -address_a[0] => ram_block1a24.PORTAADDR -address_a[0] => ram_block1a25.PORTAADDR -address_a[0] => ram_block1a26.PORTAADDR -address_a[0] => ram_block1a27.PORTAADDR -address_a[0] => ram_block1a28.PORTAADDR -address_a[0] => ram_block1a29.PORTAADDR -address_a[0] => ram_block1a30.PORTAADDR -address_a[0] => ram_block1a31.PORTAADDR -address_a[1] => ram_block1a0.PORTAADDR1 -address_a[1] => ram_block1a1.PORTAADDR1 -address_a[1] => ram_block1a2.PORTAADDR1 -address_a[1] => ram_block1a3.PORTAADDR1 -address_a[1] => ram_block1a4.PORTAADDR1 -address_a[1] => ram_block1a5.PORTAADDR1 -address_a[1] => ram_block1a6.PORTAADDR1 -address_a[1] => ram_block1a7.PORTAADDR1 -address_a[1] => ram_block1a8.PORTAADDR1 -address_a[1] => ram_block1a9.PORTAADDR1 -address_a[1] => ram_block1a10.PORTAADDR1 -address_a[1] => ram_block1a11.PORTAADDR1 -address_a[1] => ram_block1a12.PORTAADDR1 -address_a[1] => ram_block1a13.PORTAADDR1 -address_a[1] => ram_block1a14.PORTAADDR1 -address_a[1] => ram_block1a15.PORTAADDR1 -address_a[1] => ram_block1a16.PORTAADDR1 -address_a[1] => ram_block1a17.PORTAADDR1 -address_a[1] => ram_block1a18.PORTAADDR1 -address_a[1] => ram_block1a19.PORTAADDR1 -address_a[1] => ram_block1a20.PORTAADDR1 -address_a[1] => ram_block1a21.PORTAADDR1 -address_a[1] => ram_block1a22.PORTAADDR1 -address_a[1] => ram_block1a23.PORTAADDR1 -address_a[1] => ram_block1a24.PORTAADDR1 -address_a[1] => ram_block1a25.PORTAADDR1 -address_a[1] => ram_block1a26.PORTAADDR1 -address_a[1] => ram_block1a27.PORTAADDR1 -address_a[1] => ram_block1a28.PORTAADDR1 -address_a[1] => ram_block1a29.PORTAADDR1 -address_a[1] => ram_block1a30.PORTAADDR1 -address_a[1] => ram_block1a31.PORTAADDR1 -address_a[2] => ram_block1a0.PORTAADDR2 -address_a[2] => ram_block1a1.PORTAADDR2 -address_a[2] => ram_block1a2.PORTAADDR2 -address_a[2] => ram_block1a3.PORTAADDR2 -address_a[2] => ram_block1a4.PORTAADDR2 -address_a[2] => ram_block1a5.PORTAADDR2 -address_a[2] => ram_block1a6.PORTAADDR2 -address_a[2] => ram_block1a7.PORTAADDR2 -address_a[2] => ram_block1a8.PORTAADDR2 -address_a[2] => ram_block1a9.PORTAADDR2 -address_a[2] => ram_block1a10.PORTAADDR2 -address_a[2] => ram_block1a11.PORTAADDR2 -address_a[2] => ram_block1a12.PORTAADDR2 -address_a[2] => ram_block1a13.PORTAADDR2 -address_a[2] => ram_block1a14.PORTAADDR2 -address_a[2] => ram_block1a15.PORTAADDR2 -address_a[2] => ram_block1a16.PORTAADDR2 -address_a[2] => ram_block1a17.PORTAADDR2 -address_a[2] => ram_block1a18.PORTAADDR2 -address_a[2] => ram_block1a19.PORTAADDR2 -address_a[2] => ram_block1a20.PORTAADDR2 -address_a[2] => ram_block1a21.PORTAADDR2 -address_a[2] => ram_block1a22.PORTAADDR2 -address_a[2] => ram_block1a23.PORTAADDR2 -address_a[2] => ram_block1a24.PORTAADDR2 -address_a[2] => ram_block1a25.PORTAADDR2 -address_a[2] => ram_block1a26.PORTAADDR2 -address_a[2] => ram_block1a27.PORTAADDR2 -address_a[2] => ram_block1a28.PORTAADDR2 -address_a[2] => ram_block1a29.PORTAADDR2 -address_a[2] => ram_block1a30.PORTAADDR2 -address_a[2] => ram_block1a31.PORTAADDR2 -address_a[3] => ram_block1a0.PORTAADDR3 -address_a[3] => ram_block1a1.PORTAADDR3 -address_a[3] => ram_block1a2.PORTAADDR3 -address_a[3] => ram_block1a3.PORTAADDR3 -address_a[3] => ram_block1a4.PORTAADDR3 -address_a[3] => ram_block1a5.PORTAADDR3 -address_a[3] => ram_block1a6.PORTAADDR3 -address_a[3] => ram_block1a7.PORTAADDR3 -address_a[3] => ram_block1a8.PORTAADDR3 -address_a[3] => ram_block1a9.PORTAADDR3 -address_a[3] => ram_block1a10.PORTAADDR3 -address_a[3] => ram_block1a11.PORTAADDR3 -address_a[3] => ram_block1a12.PORTAADDR3 -address_a[3] => ram_block1a13.PORTAADDR3 -address_a[3] => ram_block1a14.PORTAADDR3 -address_a[3] => ram_block1a15.PORTAADDR3 -address_a[3] => ram_block1a16.PORTAADDR3 -address_a[3] => ram_block1a17.PORTAADDR3 -address_a[3] => ram_block1a18.PORTAADDR3 -address_a[3] => ram_block1a19.PORTAADDR3 -address_a[3] => ram_block1a20.PORTAADDR3 -address_a[3] => ram_block1a21.PORTAADDR3 -address_a[3] => ram_block1a22.PORTAADDR3 -address_a[3] => ram_block1a23.PORTAADDR3 -address_a[3] => ram_block1a24.PORTAADDR3 -address_a[3] => ram_block1a25.PORTAADDR3 -address_a[3] => ram_block1a26.PORTAADDR3 -address_a[3] => ram_block1a27.PORTAADDR3 -address_a[3] => ram_block1a28.PORTAADDR3 -address_a[3] => ram_block1a29.PORTAADDR3 -address_a[3] => ram_block1a30.PORTAADDR3 -address_a[3] => ram_block1a31.PORTAADDR3 -address_a[4] => ram_block1a0.PORTAADDR4 -address_a[4] => ram_block1a1.PORTAADDR4 -address_a[4] => ram_block1a2.PORTAADDR4 -address_a[4] => ram_block1a3.PORTAADDR4 -address_a[4] => ram_block1a4.PORTAADDR4 -address_a[4] => ram_block1a5.PORTAADDR4 -address_a[4] => ram_block1a6.PORTAADDR4 -address_a[4] => ram_block1a7.PORTAADDR4 -address_a[4] => ram_block1a8.PORTAADDR4 -address_a[4] => ram_block1a9.PORTAADDR4 -address_a[4] => ram_block1a10.PORTAADDR4 -address_a[4] => ram_block1a11.PORTAADDR4 -address_a[4] => ram_block1a12.PORTAADDR4 -address_a[4] => ram_block1a13.PORTAADDR4 -address_a[4] => ram_block1a14.PORTAADDR4 -address_a[4] => ram_block1a15.PORTAADDR4 -address_a[4] => ram_block1a16.PORTAADDR4 -address_a[4] => ram_block1a17.PORTAADDR4 -address_a[4] => ram_block1a18.PORTAADDR4 -address_a[4] => ram_block1a19.PORTAADDR4 -address_a[4] => ram_block1a20.PORTAADDR4 -address_a[4] => ram_block1a21.PORTAADDR4 -address_a[4] => ram_block1a22.PORTAADDR4 -address_a[4] => ram_block1a23.PORTAADDR4 -address_a[4] => ram_block1a24.PORTAADDR4 -address_a[4] => ram_block1a25.PORTAADDR4 -address_a[4] => ram_block1a26.PORTAADDR4 -address_a[4] => ram_block1a27.PORTAADDR4 -address_a[4] => ram_block1a28.PORTAADDR4 -address_a[4] => ram_block1a29.PORTAADDR4 -address_a[4] => ram_block1a30.PORTAADDR4 -address_a[4] => ram_block1a31.PORTAADDR4 -address_b[0] => ram_block1a0.PORTBADDR -address_b[0] => ram_block1a1.PORTBADDR -address_b[0] => ram_block1a2.PORTBADDR -address_b[0] => ram_block1a3.PORTBADDR -address_b[0] => ram_block1a4.PORTBADDR -address_b[0] => ram_block1a5.PORTBADDR -address_b[0] => ram_block1a6.PORTBADDR -address_b[0] => ram_block1a7.PORTBADDR -address_b[0] => ram_block1a8.PORTBADDR -address_b[0] => ram_block1a9.PORTBADDR -address_b[0] => ram_block1a10.PORTBADDR -address_b[0] => ram_block1a11.PORTBADDR -address_b[0] => ram_block1a12.PORTBADDR -address_b[0] => ram_block1a13.PORTBADDR -address_b[0] => ram_block1a14.PORTBADDR -address_b[0] => ram_block1a15.PORTBADDR -address_b[0] => ram_block1a16.PORTBADDR -address_b[0] => ram_block1a17.PORTBADDR -address_b[0] => ram_block1a18.PORTBADDR -address_b[0] => ram_block1a19.PORTBADDR -address_b[0] => ram_block1a20.PORTBADDR -address_b[0] => ram_block1a21.PORTBADDR -address_b[0] => ram_block1a22.PORTBADDR -address_b[0] => ram_block1a23.PORTBADDR -address_b[0] => ram_block1a24.PORTBADDR -address_b[0] => ram_block1a25.PORTBADDR -address_b[0] => ram_block1a26.PORTBADDR -address_b[0] => ram_block1a27.PORTBADDR -address_b[0] => ram_block1a28.PORTBADDR -address_b[0] => ram_block1a29.PORTBADDR -address_b[0] => ram_block1a30.PORTBADDR -address_b[0] => ram_block1a31.PORTBADDR -address_b[1] => ram_block1a0.PORTBADDR1 -address_b[1] => ram_block1a1.PORTBADDR1 -address_b[1] => ram_block1a2.PORTBADDR1 -address_b[1] => ram_block1a3.PORTBADDR1 -address_b[1] => ram_block1a4.PORTBADDR1 -address_b[1] => ram_block1a5.PORTBADDR1 -address_b[1] => ram_block1a6.PORTBADDR1 -address_b[1] => ram_block1a7.PORTBADDR1 -address_b[1] => ram_block1a8.PORTBADDR1 -address_b[1] => ram_block1a9.PORTBADDR1 -address_b[1] => ram_block1a10.PORTBADDR1 -address_b[1] => ram_block1a11.PORTBADDR1 -address_b[1] => ram_block1a12.PORTBADDR1 -address_b[1] => ram_block1a13.PORTBADDR1 -address_b[1] => ram_block1a14.PORTBADDR1 -address_b[1] => ram_block1a15.PORTBADDR1 -address_b[1] => ram_block1a16.PORTBADDR1 -address_b[1] => ram_block1a17.PORTBADDR1 -address_b[1] => ram_block1a18.PORTBADDR1 -address_b[1] => ram_block1a19.PORTBADDR1 -address_b[1] => ram_block1a20.PORTBADDR1 -address_b[1] => ram_block1a21.PORTBADDR1 -address_b[1] => ram_block1a22.PORTBADDR1 -address_b[1] => ram_block1a23.PORTBADDR1 -address_b[1] => ram_block1a24.PORTBADDR1 -address_b[1] => ram_block1a25.PORTBADDR1 -address_b[1] => ram_block1a26.PORTBADDR1 -address_b[1] => ram_block1a27.PORTBADDR1 -address_b[1] => ram_block1a28.PORTBADDR1 -address_b[1] => ram_block1a29.PORTBADDR1 -address_b[1] => ram_block1a30.PORTBADDR1 -address_b[1] => ram_block1a31.PORTBADDR1 -address_b[2] => ram_block1a0.PORTBADDR2 -address_b[2] => ram_block1a1.PORTBADDR2 -address_b[2] => ram_block1a2.PORTBADDR2 -address_b[2] => ram_block1a3.PORTBADDR2 -address_b[2] => ram_block1a4.PORTBADDR2 -address_b[2] => ram_block1a5.PORTBADDR2 -address_b[2] => ram_block1a6.PORTBADDR2 -address_b[2] => ram_block1a7.PORTBADDR2 -address_b[2] => ram_block1a8.PORTBADDR2 -address_b[2] => ram_block1a9.PORTBADDR2 -address_b[2] => ram_block1a10.PORTBADDR2 -address_b[2] => ram_block1a11.PORTBADDR2 -address_b[2] => ram_block1a12.PORTBADDR2 -address_b[2] => ram_block1a13.PORTBADDR2 -address_b[2] => ram_block1a14.PORTBADDR2 -address_b[2] => ram_block1a15.PORTBADDR2 -address_b[2] => ram_block1a16.PORTBADDR2 -address_b[2] => ram_block1a17.PORTBADDR2 -address_b[2] => ram_block1a18.PORTBADDR2 -address_b[2] => ram_block1a19.PORTBADDR2 -address_b[2] => ram_block1a20.PORTBADDR2 -address_b[2] => ram_block1a21.PORTBADDR2 -address_b[2] => ram_block1a22.PORTBADDR2 -address_b[2] => ram_block1a23.PORTBADDR2 -address_b[2] => ram_block1a24.PORTBADDR2 -address_b[2] => ram_block1a25.PORTBADDR2 -address_b[2] => ram_block1a26.PORTBADDR2 -address_b[2] => ram_block1a27.PORTBADDR2 -address_b[2] => ram_block1a28.PORTBADDR2 -address_b[2] => ram_block1a29.PORTBADDR2 -address_b[2] => ram_block1a30.PORTBADDR2 -address_b[2] => ram_block1a31.PORTBADDR2 -address_b[3] => ram_block1a0.PORTBADDR3 -address_b[3] => ram_block1a1.PORTBADDR3 -address_b[3] => ram_block1a2.PORTBADDR3 -address_b[3] => ram_block1a3.PORTBADDR3 -address_b[3] => ram_block1a4.PORTBADDR3 -address_b[3] => ram_block1a5.PORTBADDR3 -address_b[3] => ram_block1a6.PORTBADDR3 -address_b[3] => ram_block1a7.PORTBADDR3 -address_b[3] => ram_block1a8.PORTBADDR3 -address_b[3] => ram_block1a9.PORTBADDR3 -address_b[3] => ram_block1a10.PORTBADDR3 -address_b[3] => ram_block1a11.PORTBADDR3 -address_b[3] => ram_block1a12.PORTBADDR3 -address_b[3] => ram_block1a13.PORTBADDR3 -address_b[3] => ram_block1a14.PORTBADDR3 -address_b[3] => ram_block1a15.PORTBADDR3 -address_b[3] => ram_block1a16.PORTBADDR3 -address_b[3] => ram_block1a17.PORTBADDR3 -address_b[3] => ram_block1a18.PORTBADDR3 -address_b[3] => ram_block1a19.PORTBADDR3 -address_b[3] => ram_block1a20.PORTBADDR3 -address_b[3] => ram_block1a21.PORTBADDR3 -address_b[3] => ram_block1a22.PORTBADDR3 -address_b[3] => ram_block1a23.PORTBADDR3 -address_b[3] => ram_block1a24.PORTBADDR3 -address_b[3] => ram_block1a25.PORTBADDR3 -address_b[3] => ram_block1a26.PORTBADDR3 -address_b[3] => ram_block1a27.PORTBADDR3 -address_b[3] => ram_block1a28.PORTBADDR3 -address_b[3] => ram_block1a29.PORTBADDR3 -address_b[3] => ram_block1a30.PORTBADDR3 -address_b[3] => ram_block1a31.PORTBADDR3 -address_b[4] => ram_block1a0.PORTBADDR4 -address_b[4] => ram_block1a1.PORTBADDR4 -address_b[4] => ram_block1a2.PORTBADDR4 -address_b[4] => ram_block1a3.PORTBADDR4 -address_b[4] => ram_block1a4.PORTBADDR4 -address_b[4] => ram_block1a5.PORTBADDR4 -address_b[4] => ram_block1a6.PORTBADDR4 -address_b[4] => ram_block1a7.PORTBADDR4 -address_b[4] => ram_block1a8.PORTBADDR4 -address_b[4] => ram_block1a9.PORTBADDR4 -address_b[4] => ram_block1a10.PORTBADDR4 -address_b[4] => ram_block1a11.PORTBADDR4 -address_b[4] => ram_block1a12.PORTBADDR4 -address_b[4] => ram_block1a13.PORTBADDR4 -address_b[4] => ram_block1a14.PORTBADDR4 -address_b[4] => ram_block1a15.PORTBADDR4 -address_b[4] => ram_block1a16.PORTBADDR4 -address_b[4] => ram_block1a17.PORTBADDR4 -address_b[4] => ram_block1a18.PORTBADDR4 -address_b[4] => ram_block1a19.PORTBADDR4 -address_b[4] => ram_block1a20.PORTBADDR4 -address_b[4] => ram_block1a21.PORTBADDR4 -address_b[4] => ram_block1a22.PORTBADDR4 -address_b[4] => ram_block1a23.PORTBADDR4 -address_b[4] => ram_block1a24.PORTBADDR4 -address_b[4] => ram_block1a25.PORTBADDR4 -address_b[4] => ram_block1a26.PORTBADDR4 -address_b[4] => ram_block1a27.PORTBADDR4 -address_b[4] => ram_block1a28.PORTBADDR4 -address_b[4] => ram_block1a29.PORTBADDR4 -address_b[4] => ram_block1a30.PORTBADDR4 -address_b[4] => ram_block1a31.PORTBADDR4 -clock0 => ram_block1a0.CLK0 -clock0 => ram_block1a1.CLK0 -clock0 => ram_block1a2.CLK0 -clock0 => ram_block1a3.CLK0 -clock0 => ram_block1a4.CLK0 -clock0 => ram_block1a5.CLK0 -clock0 => ram_block1a6.CLK0 -clock0 => ram_block1a7.CLK0 -clock0 => ram_block1a8.CLK0 -clock0 => ram_block1a9.CLK0 -clock0 => ram_block1a10.CLK0 -clock0 => ram_block1a11.CLK0 -clock0 => ram_block1a12.CLK0 -clock0 => ram_block1a13.CLK0 -clock0 => ram_block1a14.CLK0 -clock0 => ram_block1a15.CLK0 -clock0 => ram_block1a16.CLK0 -clock0 => ram_block1a17.CLK0 -clock0 => ram_block1a18.CLK0 -clock0 => ram_block1a19.CLK0 -clock0 => ram_block1a20.CLK0 -clock0 => ram_block1a21.CLK0 -clock0 => ram_block1a22.CLK0 -clock0 => ram_block1a23.CLK0 -clock0 => ram_block1a24.CLK0 -clock0 => ram_block1a25.CLK0 -clock0 => ram_block1a26.CLK0 -clock0 => ram_block1a27.CLK0 -clock0 => ram_block1a28.CLK0 -clock0 => ram_block1a29.CLK0 -clock0 => ram_block1a30.CLK0 -clock0 => ram_block1a31.CLK0 -data_a[0] => ram_block1a0.PORTADATAIN -data_a[1] => ram_block1a1.PORTADATAIN -data_a[2] => ram_block1a2.PORTADATAIN -data_a[3] => ram_block1a3.PORTADATAIN -data_a[4] => ram_block1a4.PORTADATAIN -data_a[5] => ram_block1a5.PORTADATAIN -data_a[6] => ram_block1a6.PORTADATAIN -data_a[7] => ram_block1a7.PORTADATAIN -data_a[8] => ram_block1a8.PORTADATAIN -data_a[9] => ram_block1a9.PORTADATAIN -data_a[10] => ram_block1a10.PORTADATAIN -data_a[11] => ram_block1a11.PORTADATAIN -data_a[12] => ram_block1a12.PORTADATAIN -data_a[13] => ram_block1a13.PORTADATAIN -data_a[14] => ram_block1a14.PORTADATAIN -data_a[15] => ram_block1a15.PORTADATAIN -data_a[16] => ram_block1a16.PORTADATAIN -data_a[17] => ram_block1a17.PORTADATAIN -data_a[18] => ram_block1a18.PORTADATAIN -data_a[19] => ram_block1a19.PORTADATAIN -data_a[20] => ram_block1a20.PORTADATAIN -data_a[21] => ram_block1a21.PORTADATAIN -data_a[22] => ram_block1a22.PORTADATAIN -data_a[23] => ram_block1a23.PORTADATAIN -data_a[24] => ram_block1a24.PORTADATAIN -data_a[25] => ram_block1a25.PORTADATAIN -data_a[26] => ram_block1a26.PORTADATAIN -data_a[27] => ram_block1a27.PORTADATAIN -data_a[28] => ram_block1a28.PORTADATAIN -data_a[29] => ram_block1a29.PORTADATAIN -data_a[30] => ram_block1a30.PORTADATAIN -data_a[31] => ram_block1a31.PORTADATAIN -q_b[0] <= ram_block1a0.PORTBDATAOUT -q_b[1] <= ram_block1a1.PORTBDATAOUT -q_b[2] <= ram_block1a2.PORTBDATAOUT -q_b[3] <= ram_block1a3.PORTBDATAOUT -q_b[4] <= ram_block1a4.PORTBDATAOUT -q_b[5] <= ram_block1a5.PORTBDATAOUT -q_b[6] <= ram_block1a6.PORTBDATAOUT -q_b[7] <= ram_block1a7.PORTBDATAOUT -q_b[8] <= ram_block1a8.PORTBDATAOUT -q_b[9] <= ram_block1a9.PORTBDATAOUT -q_b[10] <= ram_block1a10.PORTBDATAOUT -q_b[11] <= ram_block1a11.PORTBDATAOUT -q_b[12] <= ram_block1a12.PORTBDATAOUT -q_b[13] <= ram_block1a13.PORTBDATAOUT -q_b[14] <= ram_block1a14.PORTBDATAOUT -q_b[15] <= ram_block1a15.PORTBDATAOUT -q_b[16] <= ram_block1a16.PORTBDATAOUT -q_b[17] <= ram_block1a17.PORTBDATAOUT -q_b[18] <= ram_block1a18.PORTBDATAOUT -q_b[19] <= ram_block1a19.PORTBDATAOUT -q_b[20] <= ram_block1a20.PORTBDATAOUT -q_b[21] <= ram_block1a21.PORTBDATAOUT -q_b[22] <= ram_block1a22.PORTBDATAOUT -q_b[23] <= ram_block1a23.PORTBDATAOUT -q_b[24] <= ram_block1a24.PORTBDATAOUT -q_b[25] <= ram_block1a25.PORTBDATAOUT -q_b[26] <= ram_block1a26.PORTBDATAOUT -q_b[27] <= ram_block1a27.PORTBDATAOUT -q_b[28] <= ram_block1a28.PORTBDATAOUT -q_b[29] <= ram_block1a29.PORTBDATAOUT -q_b[30] <= ram_block1a30.PORTBDATAOUT -q_b[31] <= ram_block1a31.PORTBDATAOUT -wren_a => ram_block1a0.PORTAWE -wren_a => ram_block1a1.PORTAWE -wren_a => ram_block1a2.PORTAWE -wren_a => ram_block1a3.PORTAWE -wren_a => ram_block1a4.PORTAWE -wren_a => ram_block1a5.PORTAWE -wren_a => ram_block1a6.PORTAWE -wren_a => ram_block1a7.PORTAWE -wren_a => ram_block1a8.PORTAWE -wren_a => ram_block1a9.PORTAWE -wren_a => ram_block1a10.PORTAWE -wren_a => ram_block1a11.PORTAWE -wren_a => ram_block1a12.PORTAWE -wren_a => ram_block1a13.PORTAWE -wren_a => ram_block1a14.PORTAWE -wren_a => ram_block1a15.PORTAWE -wren_a => ram_block1a16.PORTAWE -wren_a => ram_block1a17.PORTAWE -wren_a => ram_block1a18.PORTAWE -wren_a => ram_block1a19.PORTAWE -wren_a => ram_block1a20.PORTAWE -wren_a => ram_block1a21.PORTAWE -wren_a => ram_block1a22.PORTAWE -wren_a => ram_block1a23.PORTAWE -wren_a => ram_block1a24.PORTAWE -wren_a => ram_block1a25.PORTAWE -wren_a => ram_block1a26.PORTAWE -wren_a => ram_block1a27.PORTAWE -wren_a => ram_block1a28.PORTAWE -wren_a => ram_block1a29.PORTAWE -wren_a => ram_block1a30.PORTAWE -wren_a => ram_block1a31.PORTAWE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci -D_valid => D_valid.IN1 -E_st_data[0] => E_st_data[0].IN1 -E_st_data[1] => E_st_data[1].IN1 -E_st_data[2] => E_st_data[2].IN1 -E_st_data[3] => E_st_data[3].IN1 -E_st_data[4] => E_st_data[4].IN1 -E_st_data[5] => E_st_data[5].IN1 -E_st_data[6] => E_st_data[6].IN1 -E_st_data[7] => E_st_data[7].IN1 -E_st_data[8] => E_st_data[8].IN1 -E_st_data[9] => E_st_data[9].IN1 -E_st_data[10] => E_st_data[10].IN1 -E_st_data[11] => E_st_data[11].IN1 -E_st_data[12] => E_st_data[12].IN1 -E_st_data[13] => E_st_data[13].IN1 -E_st_data[14] => E_st_data[14].IN1 -E_st_data[15] => E_st_data[15].IN1 -E_st_data[16] => E_st_data[16].IN1 -E_st_data[17] => E_st_data[17].IN1 -E_st_data[18] => E_st_data[18].IN1 -E_st_data[19] => E_st_data[19].IN1 -E_st_data[20] => E_st_data[20].IN1 -E_st_data[21] => E_st_data[21].IN1 -E_st_data[22] => E_st_data[22].IN1 -E_st_data[23] => E_st_data[23].IN1 -E_st_data[24] => E_st_data[24].IN1 -E_st_data[25] => E_st_data[25].IN1 -E_st_data[26] => E_st_data[26].IN1 -E_st_data[27] => E_st_data[27].IN1 -E_st_data[28] => E_st_data[28].IN1 -E_st_data[29] => E_st_data[29].IN1 -E_st_data[30] => E_st_data[30].IN1 -E_st_data[31] => E_st_data[31].IN1 -E_valid => E_valid.IN1 -F_pc[0] => F_pc[0].IN1 -F_pc[1] => F_pc[1].IN1 -F_pc[2] => F_pc[2].IN1 -F_pc[3] => F_pc[3].IN1 -F_pc[4] => F_pc[4].IN1 -F_pc[5] => F_pc[5].IN1 -F_pc[6] => F_pc[6].IN1 -F_pc[7] => F_pc[7].IN1 -F_pc[8] => F_pc[8].IN1 -F_pc[9] => F_pc[9].IN1 -F_pc[10] => F_pc[10].IN1 -F_pc[11] => F_pc[11].IN1 -F_pc[12] => F_pc[12].IN1 -F_pc[13] => F_pc[13].IN1 -F_pc[14] => F_pc[14].IN1 -F_pc[15] => F_pc[15].IN1 -F_pc[16] => F_pc[16].IN1 -address_nxt[0] => address[0].DATAIN -address_nxt[1] => address[1].DATAIN -address_nxt[2] => address[2].DATAIN -address_nxt[3] => address[3].DATAIN -address_nxt[4] => address[4].DATAIN -address_nxt[5] => address[5].DATAIN -address_nxt[6] => address[6].DATAIN -address_nxt[7] => address[7].DATAIN -address_nxt[8] => address[8].DATAIN -av_ld_data_aligned_filtered[0] => av_ld_data_aligned_filtered[0].IN1 -av_ld_data_aligned_filtered[1] => av_ld_data_aligned_filtered[1].IN1 -av_ld_data_aligned_filtered[2] => av_ld_data_aligned_filtered[2].IN1 -av_ld_data_aligned_filtered[3] => av_ld_data_aligned_filtered[3].IN1 -av_ld_data_aligned_filtered[4] => av_ld_data_aligned_filtered[4].IN1 -av_ld_data_aligned_filtered[5] => av_ld_data_aligned_filtered[5].IN1 -av_ld_data_aligned_filtered[6] => av_ld_data_aligned_filtered[6].IN1 -av_ld_data_aligned_filtered[7] => av_ld_data_aligned_filtered[7].IN1 -av_ld_data_aligned_filtered[8] => av_ld_data_aligned_filtered[8].IN1 -av_ld_data_aligned_filtered[9] => av_ld_data_aligned_filtered[9].IN1 -av_ld_data_aligned_filtered[10] => av_ld_data_aligned_filtered[10].IN1 -av_ld_data_aligned_filtered[11] => av_ld_data_aligned_filtered[11].IN1 -av_ld_data_aligned_filtered[12] => av_ld_data_aligned_filtered[12].IN1 -av_ld_data_aligned_filtered[13] => av_ld_data_aligned_filtered[13].IN1 -av_ld_data_aligned_filtered[14] => av_ld_data_aligned_filtered[14].IN1 -av_ld_data_aligned_filtered[15] => av_ld_data_aligned_filtered[15].IN1 -av_ld_data_aligned_filtered[16] => av_ld_data_aligned_filtered[16].IN1 -av_ld_data_aligned_filtered[17] => av_ld_data_aligned_filtered[17].IN1 -av_ld_data_aligned_filtered[18] => av_ld_data_aligned_filtered[18].IN1 -av_ld_data_aligned_filtered[19] => av_ld_data_aligned_filtered[19].IN1 -av_ld_data_aligned_filtered[20] => av_ld_data_aligned_filtered[20].IN1 -av_ld_data_aligned_filtered[21] => av_ld_data_aligned_filtered[21].IN1 -av_ld_data_aligned_filtered[22] => av_ld_data_aligned_filtered[22].IN1 -av_ld_data_aligned_filtered[23] => av_ld_data_aligned_filtered[23].IN1 -av_ld_data_aligned_filtered[24] => av_ld_data_aligned_filtered[24].IN1 -av_ld_data_aligned_filtered[25] => av_ld_data_aligned_filtered[25].IN1 -av_ld_data_aligned_filtered[26] => av_ld_data_aligned_filtered[26].IN1 -av_ld_data_aligned_filtered[27] => av_ld_data_aligned_filtered[27].IN1 -av_ld_data_aligned_filtered[28] => av_ld_data_aligned_filtered[28].IN1 -av_ld_data_aligned_filtered[29] => av_ld_data_aligned_filtered[29].IN1 -av_ld_data_aligned_filtered[30] => av_ld_data_aligned_filtered[30].IN1 -av_ld_data_aligned_filtered[31] => av_ld_data_aligned_filtered[31].IN1 -byteenable_nxt[0] => byteenable[0].DATAIN -byteenable_nxt[1] => byteenable[1].DATAIN -byteenable_nxt[2] => byteenable[2].DATAIN -byteenable_nxt[3] => byteenable[3].DATAIN -clk => clk.IN12 -d_address[0] => d_address[0].IN1 -d_address[1] => d_address[1].IN1 -d_address[2] => d_address[2].IN1 -d_address[3] => d_address[3].IN1 -d_address[4] => d_address[4].IN1 -d_address[5] => d_address[5].IN1 -d_address[6] => d_address[6].IN1 -d_address[7] => d_address[7].IN1 -d_address[8] => d_address[8].IN1 -d_address[9] => d_address[9].IN1 -d_address[10] => d_address[10].IN1 -d_address[11] => d_address[11].IN1 -d_address[12] => d_address[12].IN1 -d_address[13] => d_address[13].IN1 -d_address[14] => d_address[14].IN1 -d_address[15] => d_address[15].IN1 -d_address[16] => d_address[16].IN1 -d_address[17] => d_address[17].IN1 -d_address[18] => d_address[18].IN1 -d_read => d_read.IN1 -d_waitrequest => d_waitrequest.IN1 -d_write => d_write.IN1 -debugaccess_nxt => debugaccess.DATAIN -hbreak_enabled => hbreak_enabled.IN1 -read_nxt => read.DATAA -reset => reset.IN1 -reset_n => reset_n.IN7 -test_ending => test_ending.IN1 -test_has_ended => test_has_ended.IN1 -write_nxt => write.DATAA -writedata_nxt[0] => writedata[0].DATAIN -writedata_nxt[1] => writedata[1].DATAIN -writedata_nxt[2] => writedata[2].DATAIN -writedata_nxt[3] => writedata[3].DATAIN -writedata_nxt[4] => writedata[4].DATAIN -writedata_nxt[5] => writedata[5].DATAIN -writedata_nxt[6] => writedata[6].DATAIN -writedata_nxt[7] => writedata[7].DATAIN -writedata_nxt[8] => writedata[8].DATAIN -writedata_nxt[9] => writedata[9].DATAIN -writedata_nxt[10] => writedata[10].DATAIN -writedata_nxt[11] => writedata[11].DATAIN -writedata_nxt[12] => writedata[12].DATAIN -writedata_nxt[13] => writedata[13].DATAIN -writedata_nxt[14] => writedata[14].DATAIN -writedata_nxt[15] => writedata[15].DATAIN -writedata_nxt[16] => writedata[16].DATAIN -writedata_nxt[17] => writedata[17].DATAIN -writedata_nxt[18] => writedata[18].DATAIN -writedata_nxt[19] => writedata[19].DATAIN -writedata_nxt[20] => writedata[20].DATAIN -writedata_nxt[21] => writedata[21].DATAIN -writedata_nxt[22] => writedata[22].DATAIN -writedata_nxt[23] => writedata[23].DATAIN -writedata_nxt[24] => writedata[24].DATAIN -writedata_nxt[25] => writedata[25].DATAIN -writedata_nxt[26] => writedata[26].DATAIN -writedata_nxt[27] => writedata[27].DATAIN -writedata_nxt[28] => writedata[28].DATAIN -writedata_nxt[29] => writedata[29].DATAIN -writedata_nxt[30] => writedata[30].DATAIN -writedata_nxt[31] => writedata[31].DATAIN -jtag_debug_module_debugaccess_to_roms <= debugack.DB_MAX_OUTPUT_PORT_TYPE -oci_hbreak_req <= nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug.oci_hbreak_req -oci_ienable[0] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[1] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[2] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[3] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[4] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[5] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[6] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[7] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[8] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[9] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[10] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[11] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[12] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[13] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[14] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[15] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[16] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[17] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[18] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[19] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[20] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[21] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[22] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[23] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[24] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[25] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[26] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[27] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[28] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[29] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[30] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[31] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_single_step_mode <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_single_step_mode -readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[10] <= readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[11] <= readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[12] <= readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[13] <= readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[14] <= readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[15] <= readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[16] <= readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[17] <= readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[18] <= readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[19] <= readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[20] <= readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[21] <= readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[22] <= readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[23] <= readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[24] <= readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[25] <= readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[26] <= readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[27] <= readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[28] <= readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[29] <= readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[30] <= readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[31] <= readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -resetrequest <= nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug.resetrequest -waitrequest <= nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem.waitrequest - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug -clk => clk.IN1 -dbrk_break => oci_hbreak_req.IN1 -debugreq => always0.IN0 -debugreq => oci_hbreak_req.IN1 -hbreak_enabled => always0.IN1 -hbreak_enabled => debugack.DATAIN -jdo[0] => ~NO_FANOUT~ -jdo[1] => ~NO_FANOUT~ -jdo[2] => ~NO_FANOUT~ -jdo[3] => ~NO_FANOUT~ -jdo[4] => ~NO_FANOUT~ -jdo[5] => ~NO_FANOUT~ -jdo[6] => ~NO_FANOUT~ -jdo[7] => ~NO_FANOUT~ -jdo[8] => ~NO_FANOUT~ -jdo[9] => ~NO_FANOUT~ -jdo[10] => ~NO_FANOUT~ -jdo[11] => ~NO_FANOUT~ -jdo[12] => ~NO_FANOUT~ -jdo[13] => ~NO_FANOUT~ -jdo[14] => ~NO_FANOUT~ -jdo[15] => ~NO_FANOUT~ -jdo[16] => ~NO_FANOUT~ -jdo[17] => ~NO_FANOUT~ -jdo[18] => break_on_reset.OUTPUTSELECT -jdo[19] => break_on_reset.OUTPUTSELECT -jdo[20] => jtag_break.OUTPUTSELECT -jdo[21] => jtag_break.OUTPUTSELECT -jdo[22] => resetrequest~reg0.DATAIN -jdo[23] => always1.IN0 -jdo[24] => resetlatch.OUTPUTSELECT -jdo[25] => always1.IN0 -jdo[26] => ~NO_FANOUT~ -jdo[27] => ~NO_FANOUT~ -jdo[28] => ~NO_FANOUT~ -jdo[29] => ~NO_FANOUT~ -jdo[30] => ~NO_FANOUT~ -jdo[31] => ~NO_FANOUT~ -jdo[32] => ~NO_FANOUT~ -jdo[33] => ~NO_FANOUT~ -jdo[34] => ~NO_FANOUT~ -jdo[35] => ~NO_FANOUT~ -jdo[36] => ~NO_FANOUT~ -jdo[37] => ~NO_FANOUT~ -jrst_n => unxcomplemented_resetxx0.IN1 -ocireg_ers => always1.IN0 -ocireg_mrs => always1.IN0 -reset => reset.IN1 -st_ready_test_idle => monitor_go.OUTPUTSELECT -take_action_ocimem_a => jtag_break.OUTPUTSELECT -take_action_ocimem_a => resetlatch.OUTPUTSELECT -take_action_ocimem_a => always1.IN1 -take_action_ocimem_a => always1.IN1 -take_action_ocimem_a => break_on_reset.ENA -take_action_ocimem_a => resetrequest~reg0.ENA -take_action_ocireg => always1.IN1 -take_action_ocireg => always1.IN1 -xbrk_break => oci_hbreak_req.IN1 -debugack <= hbreak_enabled.DB_MAX_OUTPUT_PORT_TYPE -monitor_error <= monitor_error~reg0.DB_MAX_OUTPUT_PORT_TYPE -monitor_go <= monitor_go~reg0.DB_MAX_OUTPUT_PORT_TYPE -monitor_ready <= monitor_ready~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_hbreak_req <= oci_hbreak_req.DB_MAX_OUTPUT_PORT_TYPE -resetlatch <= resetlatch~reg0.DB_MAX_OUTPUT_PORT_TYPE -resetrequest <= resetrequest~reg0.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer -clk => dreg[0].CLK -clk => din_s1.CLK -reset_n => dreg[0].ACLR -reset_n => din_s1.ACLR -din => din_s1.DATAIN -dout <= dout.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem -address[0] => ociram_addr.DATAA -address[1] => ociram_addr.DATAA -address[2] => ociram_addr.DATAA -address[3] => ociram_addr.DATAA -address[4] => ociram_addr.DATAA -address[5] => ociram_addr.DATAA -address[6] => ociram_addr.DATAA -address[7] => ociram_addr.DATAA -address[8] => waitrequest.IN1 -address[8] => avalon_ram_wr.IN0 -byteenable[0] => ociram_byteenable.DATAA -byteenable[1] => ociram_byteenable.DATAA -byteenable[2] => ociram_byteenable.DATAA -byteenable[3] => ociram_byteenable.DATAA -clk => clk.IN1 -debugaccess => avalon_ram_wr.IN1 -jdo[0] => ~NO_FANOUT~ -jdo[1] => ~NO_FANOUT~ -jdo[2] => ~NO_FANOUT~ -jdo[3] => MonDReg.DATAB -jdo[4] => MonDReg.DATAB -jdo[5] => MonDReg.DATAB -jdo[6] => MonDReg.DATAB -jdo[7] => MonDReg.DATAB -jdo[8] => MonDReg.DATAB -jdo[9] => MonDReg.DATAB -jdo[10] => MonDReg.DATAB -jdo[11] => MonDReg.DATAB -jdo[12] => MonDReg.DATAB -jdo[13] => MonDReg.DATAB -jdo[14] => MonDReg.DATAB -jdo[15] => MonDReg.DATAB -jdo[16] => MonDReg.DATAB -jdo[17] => MonDReg.DATAB -jdo[17] => MonAReg.DATAB -jdo[17] => jtag_ram_rd.DATAB -jdo[17] => jtag_ram_access.DATAB -jdo[18] => MonDReg.DATAB -jdo[19] => MonDReg.DATAB -jdo[20] => MonDReg.DATAB -jdo[21] => MonDReg.DATAB -jdo[22] => MonDReg.DATAB -jdo[23] => MonDReg.DATAB -jdo[24] => MonDReg.DATAB -jdo[25] => MonDReg.DATAB -jdo[26] => MonDReg.DATAB -jdo[26] => MonAReg.DATAB -jdo[27] => MonDReg.DATAB -jdo[27] => MonAReg.DATAB -jdo[28] => MonDReg.DATAB -jdo[28] => MonAReg.DATAB -jdo[29] => MonDReg.DATAB -jdo[29] => MonAReg.DATAB -jdo[30] => MonDReg.DATAB -jdo[30] => MonAReg.DATAB -jdo[31] => MonDReg.DATAB -jdo[31] => MonAReg.DATAB -jdo[32] => MonDReg.DATAB -jdo[32] => MonAReg.DATAB -jdo[33] => MonDReg.DATAB -jdo[33] => MonAReg.DATAB -jdo[34] => MonDReg.DATAB -jdo[35] => ~NO_FANOUT~ -jdo[36] => ~NO_FANOUT~ -jdo[37] => ~NO_FANOUT~ -jrst_n => avalon_ociram_readdata_ready.ACLR -jrst_n => waitrequest~reg0.PRESET -jrst_n => MonDReg[0]~reg0.ACLR -jrst_n => MonDReg[1]~reg0.ACLR -jrst_n => MonDReg[2]~reg0.ACLR -jrst_n => MonDReg[3]~reg0.ACLR -jrst_n => MonDReg[4]~reg0.ACLR -jrst_n => MonDReg[5]~reg0.ACLR -jrst_n => MonDReg[6]~reg0.ACLR -jrst_n => MonDReg[7]~reg0.ACLR -jrst_n => MonDReg[8]~reg0.ACLR -jrst_n => MonDReg[9]~reg0.ACLR -jrst_n => MonDReg[10]~reg0.ACLR -jrst_n => MonDReg[11]~reg0.ACLR -jrst_n => MonDReg[12]~reg0.ACLR -jrst_n => MonDReg[13]~reg0.ACLR -jrst_n => MonDReg[14]~reg0.ACLR -jrst_n => MonDReg[15]~reg0.ACLR -jrst_n => MonDReg[16]~reg0.ACLR -jrst_n => MonDReg[17]~reg0.ACLR -jrst_n => MonDReg[18]~reg0.ACLR -jrst_n => MonDReg[19]~reg0.ACLR -jrst_n => MonDReg[20]~reg0.ACLR -jrst_n => MonDReg[21]~reg0.ACLR -jrst_n => MonDReg[22]~reg0.ACLR -jrst_n => MonDReg[23]~reg0.ACLR -jrst_n => MonDReg[24]~reg0.ACLR -jrst_n => MonDReg[25]~reg0.ACLR -jrst_n => MonDReg[26]~reg0.ACLR -jrst_n => MonDReg[27]~reg0.ACLR -jrst_n => MonDReg[28]~reg0.ACLR -jrst_n => MonDReg[29]~reg0.ACLR -jrst_n => MonDReg[30]~reg0.ACLR -jrst_n => MonDReg[31]~reg0.ACLR -jrst_n => MonAReg[2].ACLR -jrst_n => MonAReg[3].ACLR -jrst_n => MonAReg[4].ACLR -jrst_n => MonAReg[5].ACLR -jrst_n => MonAReg[6].ACLR -jrst_n => MonAReg[7].ACLR -jrst_n => MonAReg[8].ACLR -jrst_n => MonAReg[9].ACLR -jrst_n => MonAReg[10].ACLR -jrst_n => jtag_ram_access.ACLR -jrst_n => jtag_ram_rd_d1.ACLR -jrst_n => jtag_ram_rd.ACLR -jrst_n => jtag_ram_wr.ACLR -jrst_n => jtag_rd_d1.ACLR -jrst_n => jtag_rd.ACLR -read => avalon_ociram_readdata_ready.OUTPUTSELECT -read => waitrequest.OUTPUTSELECT -take_action_ocimem_a => MonAReg.OUTPUTSELECT -take_action_ocimem_a => MonAReg.OUTPUTSELECT -take_action_ocimem_a => MonAReg.OUTPUTSELECT -take_action_ocimem_a => MonAReg.OUTPUTSELECT -take_action_ocimem_a => MonAReg.OUTPUTSELECT -take_action_ocimem_a => MonAReg.OUTPUTSELECT -take_action_ocimem_a => MonAReg.OUTPUTSELECT -take_action_ocimem_a => MonAReg.OUTPUTSELECT -take_action_ocimem_a => MonAReg.OUTPUTSELECT -take_action_ocimem_a => jtag_rd.OUTPUTSELECT -take_action_ocimem_a => jtag_ram_rd.OUTPUTSELECT -take_action_ocimem_a => jtag_ram_access.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => jtag_ram_wr.OUTPUTSELECT -take_action_ocimem_b => MonAReg.OUTPUTSELECT -take_action_ocimem_b => MonAReg.OUTPUTSELECT -take_action_ocimem_b => MonAReg.OUTPUTSELECT -take_action_ocimem_b => MonAReg.OUTPUTSELECT -take_action_ocimem_b => MonAReg.OUTPUTSELECT -take_action_ocimem_b => MonAReg.OUTPUTSELECT -take_action_ocimem_b => MonAReg.OUTPUTSELECT -take_action_ocimem_b => MonAReg.OUTPUTSELECT -take_action_ocimem_b => MonAReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => jtag_ram_wr.OUTPUTSELECT -take_action_ocimem_b => jtag_rd.OUTPUTSELECT -take_action_ocimem_b => jtag_ram_rd.OUTPUTSELECT -take_no_action_ocimem_a => MonAReg.OUTPUTSELECT -take_no_action_ocimem_a => MonAReg.OUTPUTSELECT -take_no_action_ocimem_a => MonAReg.OUTPUTSELECT -take_no_action_ocimem_a => MonAReg.OUTPUTSELECT -take_no_action_ocimem_a => MonAReg.OUTPUTSELECT -take_no_action_ocimem_a => MonAReg.OUTPUTSELECT -take_no_action_ocimem_a => MonAReg.OUTPUTSELECT -take_no_action_ocimem_a => MonAReg.OUTPUTSELECT -take_no_action_ocimem_a => MonAReg.OUTPUTSELECT -take_no_action_ocimem_a => jtag_rd.OUTPUTSELECT -take_no_action_ocimem_a => jtag_ram_rd.OUTPUTSELECT -take_no_action_ocimem_a => jtag_ram_access.OUTPUTSELECT -take_no_action_ocimem_a => jtag_ram_wr.ENA -take_no_action_ocimem_a => MonDReg[31]~reg0.ENA -take_no_action_ocimem_a => MonDReg[30]~reg0.ENA -take_no_action_ocimem_a => MonDReg[29]~reg0.ENA -take_no_action_ocimem_a => MonDReg[28]~reg0.ENA -take_no_action_ocimem_a => MonDReg[27]~reg0.ENA -take_no_action_ocimem_a => MonDReg[26]~reg0.ENA -take_no_action_ocimem_a => MonDReg[25]~reg0.ENA -take_no_action_ocimem_a => MonDReg[24]~reg0.ENA -take_no_action_ocimem_a => MonDReg[23]~reg0.ENA -take_no_action_ocimem_a => MonDReg[22]~reg0.ENA -take_no_action_ocimem_a => MonDReg[21]~reg0.ENA -take_no_action_ocimem_a => MonDReg[20]~reg0.ENA -take_no_action_ocimem_a => MonDReg[19]~reg0.ENA -take_no_action_ocimem_a => MonDReg[18]~reg0.ENA -take_no_action_ocimem_a => MonDReg[17]~reg0.ENA -take_no_action_ocimem_a => MonDReg[16]~reg0.ENA -take_no_action_ocimem_a => MonDReg[15]~reg0.ENA -take_no_action_ocimem_a => MonDReg[14]~reg0.ENA -take_no_action_ocimem_a => MonDReg[13]~reg0.ENA -take_no_action_ocimem_a => MonDReg[12]~reg0.ENA -take_no_action_ocimem_a => MonDReg[11]~reg0.ENA -take_no_action_ocimem_a => MonDReg[10]~reg0.ENA -take_no_action_ocimem_a => MonDReg[9]~reg0.ENA -take_no_action_ocimem_a => MonDReg[8]~reg0.ENA -take_no_action_ocimem_a => MonDReg[7]~reg0.ENA -take_no_action_ocimem_a => MonDReg[6]~reg0.ENA -take_no_action_ocimem_a => MonDReg[5]~reg0.ENA -take_no_action_ocimem_a => MonDReg[4]~reg0.ENA -take_no_action_ocimem_a => MonDReg[3]~reg0.ENA -take_no_action_ocimem_a => MonDReg[2]~reg0.ENA -take_no_action_ocimem_a => MonDReg[1]~reg0.ENA -take_no_action_ocimem_a => MonDReg[0]~reg0.ENA -write => waitrequest.OUTPUTSELECT -write => avalon_ociram_readdata_ready.OUTPUTSELECT -write => avalon_ram_wr.IN1 -writedata[0] => ociram_wr_data.DATAA -writedata[1] => ociram_wr_data.DATAA -writedata[2] => ociram_wr_data.DATAA -writedata[3] => ociram_wr_data.DATAA -writedata[4] => ociram_wr_data.DATAA -writedata[5] => ociram_wr_data.DATAA -writedata[6] => ociram_wr_data.DATAA -writedata[7] => ociram_wr_data.DATAA -writedata[8] => ociram_wr_data.DATAA -writedata[9] => ociram_wr_data.DATAA -writedata[10] => ociram_wr_data.DATAA -writedata[11] => ociram_wr_data.DATAA -writedata[12] => ociram_wr_data.DATAA -writedata[13] => ociram_wr_data.DATAA -writedata[14] => ociram_wr_data.DATAA -writedata[15] => ociram_wr_data.DATAA -writedata[16] => ociram_wr_data.DATAA -writedata[17] => ociram_wr_data.DATAA -writedata[18] => ociram_wr_data.DATAA -writedata[19] => ociram_wr_data.DATAA -writedata[20] => ociram_wr_data.DATAA -writedata[21] => ociram_wr_data.DATAA -writedata[22] => ociram_wr_data.DATAA -writedata[23] => ociram_wr_data.DATAA -writedata[24] => ociram_wr_data.DATAA -writedata[25] => ociram_wr_data.DATAA -writedata[26] => ociram_wr_data.DATAA -writedata[27] => ociram_wr_data.DATAA -writedata[28] => ociram_wr_data.DATAA -writedata[29] => ociram_wr_data.DATAA -writedata[30] => ociram_wr_data.DATAA -writedata[31] => ociram_wr_data.DATAA -MonDReg[0] <= MonDReg[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[1] <= MonDReg[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[2] <= MonDReg[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[3] <= MonDReg[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[4] <= MonDReg[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[5] <= MonDReg[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[6] <= MonDReg[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[7] <= MonDReg[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[8] <= MonDReg[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[9] <= MonDReg[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[10] <= MonDReg[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[11] <= MonDReg[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[12] <= MonDReg[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[13] <= MonDReg[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[14] <= MonDReg[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[15] <= MonDReg[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[16] <= MonDReg[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[17] <= MonDReg[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[18] <= MonDReg[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[19] <= MonDReg[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[20] <= MonDReg[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[21] <= MonDReg[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[22] <= MonDReg[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[23] <= MonDReg[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[24] <= MonDReg[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[25] <= MonDReg[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[26] <= MonDReg[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[27] <= MonDReg[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[28] <= MonDReg[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[29] <= MonDReg[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[30] <= MonDReg[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[31] <= MonDReg[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -ociram_readdata[0] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[1] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[2] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[3] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[4] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[5] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[6] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[7] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[8] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[9] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[10] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[11] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[12] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[13] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[14] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[15] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[16] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[17] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[18] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[19] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[20] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[21] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[22] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[23] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[24] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[25] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[26] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[27] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[28] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[29] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[30] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[31] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -waitrequest <= waitrequest~reg0.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram -address[0] => address[0].IN1 -address[1] => address[1].IN1 -address[2] => address[2].IN1 -address[3] => address[3].IN1 -address[4] => address[4].IN1 -address[5] => address[5].IN1 -address[6] => address[6].IN1 -address[7] => address[7].IN1 -byteenable[0] => byteenable[0].IN1 -byteenable[1] => byteenable[1].IN1 -byteenable[2] => byteenable[2].IN1 -byteenable[3] => byteenable[3].IN1 -clock => clock.IN1 -data[0] => data[0].IN1 -data[1] => data[1].IN1 -data[2] => data[2].IN1 -data[3] => data[3].IN1 -data[4] => data[4].IN1 -data[5] => data[5].IN1 -data[6] => data[6].IN1 -data[7] => data[7].IN1 -data[8] => data[8].IN1 -data[9] => data[9].IN1 -data[10] => data[10].IN1 -data[11] => data[11].IN1 -data[12] => data[12].IN1 -data[13] => data[13].IN1 -data[14] => data[14].IN1 -data[15] => data[15].IN1 -data[16] => data[16].IN1 -data[17] => data[17].IN1 -data[18] => data[18].IN1 -data[19] => data[19].IN1 -data[20] => data[20].IN1 -data[21] => data[21].IN1 -data[22] => data[22].IN1 -data[23] => data[23].IN1 -data[24] => data[24].IN1 -data[25] => data[25].IN1 -data[26] => data[26].IN1 -data[27] => data[27].IN1 -data[28] => data[28].IN1 -data[29] => data[29].IN1 -data[30] => data[30].IN1 -data[31] => data[31].IN1 -wren => wren.IN1 -q[0] <= altsyncram:the_altsyncram.q_a -q[1] <= altsyncram:the_altsyncram.q_a -q[2] <= altsyncram:the_altsyncram.q_a -q[3] <= altsyncram:the_altsyncram.q_a -q[4] <= altsyncram:the_altsyncram.q_a -q[5] <= altsyncram:the_altsyncram.q_a -q[6] <= altsyncram:the_altsyncram.q_a -q[7] <= altsyncram:the_altsyncram.q_a -q[8] <= altsyncram:the_altsyncram.q_a -q[9] <= altsyncram:the_altsyncram.q_a -q[10] <= altsyncram:the_altsyncram.q_a -q[11] <= altsyncram:the_altsyncram.q_a -q[12] <= altsyncram:the_altsyncram.q_a -q[13] <= altsyncram:the_altsyncram.q_a -q[14] <= altsyncram:the_altsyncram.q_a -q[15] <= altsyncram:the_altsyncram.q_a -q[16] <= altsyncram:the_altsyncram.q_a -q[17] <= altsyncram:the_altsyncram.q_a -q[18] <= altsyncram:the_altsyncram.q_a -q[19] <= altsyncram:the_altsyncram.q_a -q[20] <= altsyncram:the_altsyncram.q_a -q[21] <= altsyncram:the_altsyncram.q_a -q[22] <= altsyncram:the_altsyncram.q_a -q[23] <= altsyncram:the_altsyncram.q_a -q[24] <= altsyncram:the_altsyncram.q_a -q[25] <= altsyncram:the_altsyncram.q_a -q[26] <= altsyncram:the_altsyncram.q_a -q[27] <= altsyncram:the_altsyncram.q_a -q[28] <= altsyncram:the_altsyncram.q_a -q[29] <= altsyncram:the_altsyncram.q_a -q[30] <= altsyncram:the_altsyncram.q_a -q[31] <= altsyncram:the_altsyncram.q_a - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram -wren_a => altsyncram_4891:auto_generated.wren_a -rden_a => ~NO_FANOUT~ -wren_b => ~NO_FANOUT~ -rden_b => ~NO_FANOUT~ -data_a[0] => altsyncram_4891:auto_generated.data_a[0] -data_a[1] => altsyncram_4891:auto_generated.data_a[1] -data_a[2] => altsyncram_4891:auto_generated.data_a[2] -data_a[3] => altsyncram_4891:auto_generated.data_a[3] -data_a[4] => altsyncram_4891:auto_generated.data_a[4] -data_a[5] => altsyncram_4891:auto_generated.data_a[5] -data_a[6] => altsyncram_4891:auto_generated.data_a[6] -data_a[7] => altsyncram_4891:auto_generated.data_a[7] -data_a[8] => altsyncram_4891:auto_generated.data_a[8] -data_a[9] => altsyncram_4891:auto_generated.data_a[9] -data_a[10] => altsyncram_4891:auto_generated.data_a[10] -data_a[11] => altsyncram_4891:auto_generated.data_a[11] -data_a[12] => altsyncram_4891:auto_generated.data_a[12] -data_a[13] => altsyncram_4891:auto_generated.data_a[13] -data_a[14] => altsyncram_4891:auto_generated.data_a[14] -data_a[15] => altsyncram_4891:auto_generated.data_a[15] -data_a[16] => altsyncram_4891:auto_generated.data_a[16] -data_a[17] => altsyncram_4891:auto_generated.data_a[17] -data_a[18] => altsyncram_4891:auto_generated.data_a[18] -data_a[19] => altsyncram_4891:auto_generated.data_a[19] -data_a[20] => altsyncram_4891:auto_generated.data_a[20] -data_a[21] => altsyncram_4891:auto_generated.data_a[21] -data_a[22] => altsyncram_4891:auto_generated.data_a[22] -data_a[23] => altsyncram_4891:auto_generated.data_a[23] -data_a[24] => altsyncram_4891:auto_generated.data_a[24] -data_a[25] => altsyncram_4891:auto_generated.data_a[25] -data_a[26] => altsyncram_4891:auto_generated.data_a[26] -data_a[27] => altsyncram_4891:auto_generated.data_a[27] -data_a[28] => altsyncram_4891:auto_generated.data_a[28] -data_a[29] => altsyncram_4891:auto_generated.data_a[29] -data_a[30] => altsyncram_4891:auto_generated.data_a[30] -data_a[31] => altsyncram_4891:auto_generated.data_a[31] -data_b[0] => ~NO_FANOUT~ -address_a[0] => altsyncram_4891:auto_generated.address_a[0] -address_a[1] => altsyncram_4891:auto_generated.address_a[1] -address_a[2] => altsyncram_4891:auto_generated.address_a[2] -address_a[3] => altsyncram_4891:auto_generated.address_a[3] -address_a[4] => altsyncram_4891:auto_generated.address_a[4] -address_a[5] => altsyncram_4891:auto_generated.address_a[5] -address_a[6] => altsyncram_4891:auto_generated.address_a[6] -address_a[7] => altsyncram_4891:auto_generated.address_a[7] -address_b[0] => ~NO_FANOUT~ -addressstall_a => ~NO_FANOUT~ -addressstall_b => ~NO_FANOUT~ -clock0 => altsyncram_4891:auto_generated.clock0 -clock1 => ~NO_FANOUT~ -clocken0 => ~NO_FANOUT~ -clocken1 => ~NO_FANOUT~ -clocken2 => ~NO_FANOUT~ -clocken3 => ~NO_FANOUT~ -aclr0 => ~NO_FANOUT~ -aclr1 => ~NO_FANOUT~ -byteena_a[0] => altsyncram_4891:auto_generated.byteena_a[0] -byteena_a[1] => altsyncram_4891:auto_generated.byteena_a[1] -byteena_a[2] => altsyncram_4891:auto_generated.byteena_a[2] -byteena_a[3] => altsyncram_4891:auto_generated.byteena_a[3] -byteena_b[0] => ~NO_FANOUT~ -q_a[0] <= altsyncram_4891:auto_generated.q_a[0] -q_a[1] <= altsyncram_4891:auto_generated.q_a[1] -q_a[2] <= altsyncram_4891:auto_generated.q_a[2] -q_a[3] <= altsyncram_4891:auto_generated.q_a[3] -q_a[4] <= altsyncram_4891:auto_generated.q_a[4] -q_a[5] <= altsyncram_4891:auto_generated.q_a[5] -q_a[6] <= altsyncram_4891:auto_generated.q_a[6] -q_a[7] <= altsyncram_4891:auto_generated.q_a[7] -q_a[8] <= altsyncram_4891:auto_generated.q_a[8] -q_a[9] <= altsyncram_4891:auto_generated.q_a[9] -q_a[10] <= altsyncram_4891:auto_generated.q_a[10] -q_a[11] <= altsyncram_4891:auto_generated.q_a[11] -q_a[12] <= altsyncram_4891:auto_generated.q_a[12] -q_a[13] <= altsyncram_4891:auto_generated.q_a[13] -q_a[14] <= altsyncram_4891:auto_generated.q_a[14] -q_a[15] <= altsyncram_4891:auto_generated.q_a[15] -q_a[16] <= altsyncram_4891:auto_generated.q_a[16] -q_a[17] <= altsyncram_4891:auto_generated.q_a[17] -q_a[18] <= altsyncram_4891:auto_generated.q_a[18] -q_a[19] <= altsyncram_4891:auto_generated.q_a[19] -q_a[20] <= altsyncram_4891:auto_generated.q_a[20] -q_a[21] <= altsyncram_4891:auto_generated.q_a[21] -q_a[22] <= altsyncram_4891:auto_generated.q_a[22] -q_a[23] <= altsyncram_4891:auto_generated.q_a[23] -q_a[24] <= altsyncram_4891:auto_generated.q_a[24] -q_a[25] <= altsyncram_4891:auto_generated.q_a[25] -q_a[26] <= altsyncram_4891:auto_generated.q_a[26] -q_a[27] <= altsyncram_4891:auto_generated.q_a[27] -q_a[28] <= altsyncram_4891:auto_generated.q_a[28] -q_a[29] <= altsyncram_4891:auto_generated.q_a[29] -q_a[30] <= altsyncram_4891:auto_generated.q_a[30] -q_a[31] <= altsyncram_4891:auto_generated.q_a[31] -q_b[0] <= -eccstatus[0] <= -eccstatus[1] <= -eccstatus[2] <= - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated -address_a[0] => ram_block1a0.PORTAADDR -address_a[0] => ram_block1a1.PORTAADDR -address_a[0] => ram_block1a2.PORTAADDR -address_a[0] => ram_block1a3.PORTAADDR -address_a[0] => ram_block1a4.PORTAADDR -address_a[0] => ram_block1a5.PORTAADDR -address_a[0] => ram_block1a6.PORTAADDR -address_a[0] => ram_block1a7.PORTAADDR -address_a[0] => ram_block1a8.PORTAADDR -address_a[0] => ram_block1a9.PORTAADDR -address_a[0] => ram_block1a10.PORTAADDR -address_a[0] => ram_block1a11.PORTAADDR -address_a[0] => ram_block1a12.PORTAADDR -address_a[0] => ram_block1a13.PORTAADDR -address_a[0] => ram_block1a14.PORTAADDR -address_a[0] => ram_block1a15.PORTAADDR -address_a[0] => ram_block1a16.PORTAADDR -address_a[0] => ram_block1a17.PORTAADDR -address_a[0] => ram_block1a18.PORTAADDR -address_a[0] => ram_block1a19.PORTAADDR -address_a[0] => ram_block1a20.PORTAADDR -address_a[0] => ram_block1a21.PORTAADDR -address_a[0] => ram_block1a22.PORTAADDR -address_a[0] => ram_block1a23.PORTAADDR -address_a[0] => ram_block1a24.PORTAADDR -address_a[0] => ram_block1a25.PORTAADDR -address_a[0] => ram_block1a26.PORTAADDR -address_a[0] => ram_block1a27.PORTAADDR -address_a[0] => ram_block1a28.PORTAADDR -address_a[0] => ram_block1a29.PORTAADDR -address_a[0] => ram_block1a30.PORTAADDR -address_a[0] => ram_block1a31.PORTAADDR -address_a[1] => ram_block1a0.PORTAADDR1 -address_a[1] => ram_block1a1.PORTAADDR1 -address_a[1] => ram_block1a2.PORTAADDR1 -address_a[1] => ram_block1a3.PORTAADDR1 -address_a[1] => ram_block1a4.PORTAADDR1 -address_a[1] => ram_block1a5.PORTAADDR1 -address_a[1] => ram_block1a6.PORTAADDR1 -address_a[1] => ram_block1a7.PORTAADDR1 -address_a[1] => ram_block1a8.PORTAADDR1 -address_a[1] => ram_block1a9.PORTAADDR1 -address_a[1] => ram_block1a10.PORTAADDR1 -address_a[1] => ram_block1a11.PORTAADDR1 -address_a[1] => ram_block1a12.PORTAADDR1 -address_a[1] => ram_block1a13.PORTAADDR1 -address_a[1] => ram_block1a14.PORTAADDR1 -address_a[1] => ram_block1a15.PORTAADDR1 -address_a[1] => ram_block1a16.PORTAADDR1 -address_a[1] => ram_block1a17.PORTAADDR1 -address_a[1] => ram_block1a18.PORTAADDR1 -address_a[1] => ram_block1a19.PORTAADDR1 -address_a[1] => ram_block1a20.PORTAADDR1 -address_a[1] => ram_block1a21.PORTAADDR1 -address_a[1] => ram_block1a22.PORTAADDR1 -address_a[1] => ram_block1a23.PORTAADDR1 -address_a[1] => ram_block1a24.PORTAADDR1 -address_a[1] => ram_block1a25.PORTAADDR1 -address_a[1] => ram_block1a26.PORTAADDR1 -address_a[1] => ram_block1a27.PORTAADDR1 -address_a[1] => ram_block1a28.PORTAADDR1 -address_a[1] => ram_block1a29.PORTAADDR1 -address_a[1] => ram_block1a30.PORTAADDR1 -address_a[1] => ram_block1a31.PORTAADDR1 -address_a[2] => ram_block1a0.PORTAADDR2 -address_a[2] => ram_block1a1.PORTAADDR2 -address_a[2] => ram_block1a2.PORTAADDR2 -address_a[2] => ram_block1a3.PORTAADDR2 -address_a[2] => ram_block1a4.PORTAADDR2 -address_a[2] => ram_block1a5.PORTAADDR2 -address_a[2] => ram_block1a6.PORTAADDR2 -address_a[2] => ram_block1a7.PORTAADDR2 -address_a[2] => ram_block1a8.PORTAADDR2 -address_a[2] => ram_block1a9.PORTAADDR2 -address_a[2] => ram_block1a10.PORTAADDR2 -address_a[2] => ram_block1a11.PORTAADDR2 -address_a[2] => ram_block1a12.PORTAADDR2 -address_a[2] => ram_block1a13.PORTAADDR2 -address_a[2] => ram_block1a14.PORTAADDR2 -address_a[2] => ram_block1a15.PORTAADDR2 -address_a[2] => ram_block1a16.PORTAADDR2 -address_a[2] => ram_block1a17.PORTAADDR2 -address_a[2] => ram_block1a18.PORTAADDR2 -address_a[2] => ram_block1a19.PORTAADDR2 -address_a[2] => ram_block1a20.PORTAADDR2 -address_a[2] => ram_block1a21.PORTAADDR2 -address_a[2] => ram_block1a22.PORTAADDR2 -address_a[2] => ram_block1a23.PORTAADDR2 -address_a[2] => ram_block1a24.PORTAADDR2 -address_a[2] => ram_block1a25.PORTAADDR2 -address_a[2] => ram_block1a26.PORTAADDR2 -address_a[2] => ram_block1a27.PORTAADDR2 -address_a[2] => ram_block1a28.PORTAADDR2 -address_a[2] => ram_block1a29.PORTAADDR2 -address_a[2] => ram_block1a30.PORTAADDR2 -address_a[2] => ram_block1a31.PORTAADDR2 -address_a[3] => ram_block1a0.PORTAADDR3 -address_a[3] => ram_block1a1.PORTAADDR3 -address_a[3] => ram_block1a2.PORTAADDR3 -address_a[3] => ram_block1a3.PORTAADDR3 -address_a[3] => ram_block1a4.PORTAADDR3 -address_a[3] => ram_block1a5.PORTAADDR3 -address_a[3] => ram_block1a6.PORTAADDR3 -address_a[3] => ram_block1a7.PORTAADDR3 -address_a[3] => ram_block1a8.PORTAADDR3 -address_a[3] => ram_block1a9.PORTAADDR3 -address_a[3] => ram_block1a10.PORTAADDR3 -address_a[3] => ram_block1a11.PORTAADDR3 -address_a[3] => ram_block1a12.PORTAADDR3 -address_a[3] => ram_block1a13.PORTAADDR3 -address_a[3] => ram_block1a14.PORTAADDR3 -address_a[3] => ram_block1a15.PORTAADDR3 -address_a[3] => ram_block1a16.PORTAADDR3 -address_a[3] => ram_block1a17.PORTAADDR3 -address_a[3] => ram_block1a18.PORTAADDR3 -address_a[3] => ram_block1a19.PORTAADDR3 -address_a[3] => ram_block1a20.PORTAADDR3 -address_a[3] => ram_block1a21.PORTAADDR3 -address_a[3] => ram_block1a22.PORTAADDR3 -address_a[3] => ram_block1a23.PORTAADDR3 -address_a[3] => ram_block1a24.PORTAADDR3 -address_a[3] => ram_block1a25.PORTAADDR3 -address_a[3] => ram_block1a26.PORTAADDR3 -address_a[3] => ram_block1a27.PORTAADDR3 -address_a[3] => ram_block1a28.PORTAADDR3 -address_a[3] => ram_block1a29.PORTAADDR3 -address_a[3] => ram_block1a30.PORTAADDR3 -address_a[3] => ram_block1a31.PORTAADDR3 -address_a[4] => ram_block1a0.PORTAADDR4 -address_a[4] => ram_block1a1.PORTAADDR4 -address_a[4] => ram_block1a2.PORTAADDR4 -address_a[4] => ram_block1a3.PORTAADDR4 -address_a[4] => ram_block1a4.PORTAADDR4 -address_a[4] => ram_block1a5.PORTAADDR4 -address_a[4] => ram_block1a6.PORTAADDR4 -address_a[4] => ram_block1a7.PORTAADDR4 -address_a[4] => ram_block1a8.PORTAADDR4 -address_a[4] => ram_block1a9.PORTAADDR4 -address_a[4] => ram_block1a10.PORTAADDR4 -address_a[4] => ram_block1a11.PORTAADDR4 -address_a[4] => ram_block1a12.PORTAADDR4 -address_a[4] => ram_block1a13.PORTAADDR4 -address_a[4] => ram_block1a14.PORTAADDR4 -address_a[4] => ram_block1a15.PORTAADDR4 -address_a[4] => ram_block1a16.PORTAADDR4 -address_a[4] => ram_block1a17.PORTAADDR4 -address_a[4] => ram_block1a18.PORTAADDR4 -address_a[4] => ram_block1a19.PORTAADDR4 -address_a[4] => ram_block1a20.PORTAADDR4 -address_a[4] => ram_block1a21.PORTAADDR4 -address_a[4] => ram_block1a22.PORTAADDR4 -address_a[4] => ram_block1a23.PORTAADDR4 -address_a[4] => ram_block1a24.PORTAADDR4 -address_a[4] => ram_block1a25.PORTAADDR4 -address_a[4] => ram_block1a26.PORTAADDR4 -address_a[4] => ram_block1a27.PORTAADDR4 -address_a[4] => ram_block1a28.PORTAADDR4 -address_a[4] => ram_block1a29.PORTAADDR4 -address_a[4] => ram_block1a30.PORTAADDR4 -address_a[4] => ram_block1a31.PORTAADDR4 -address_a[5] => ram_block1a0.PORTAADDR5 -address_a[5] => ram_block1a1.PORTAADDR5 -address_a[5] => ram_block1a2.PORTAADDR5 -address_a[5] => ram_block1a3.PORTAADDR5 -address_a[5] => ram_block1a4.PORTAADDR5 -address_a[5] => ram_block1a5.PORTAADDR5 -address_a[5] => ram_block1a6.PORTAADDR5 -address_a[5] => ram_block1a7.PORTAADDR5 -address_a[5] => ram_block1a8.PORTAADDR5 -address_a[5] => ram_block1a9.PORTAADDR5 -address_a[5] => ram_block1a10.PORTAADDR5 -address_a[5] => ram_block1a11.PORTAADDR5 -address_a[5] => ram_block1a12.PORTAADDR5 -address_a[5] => ram_block1a13.PORTAADDR5 -address_a[5] => ram_block1a14.PORTAADDR5 -address_a[5] => ram_block1a15.PORTAADDR5 -address_a[5] => ram_block1a16.PORTAADDR5 -address_a[5] => ram_block1a17.PORTAADDR5 -address_a[5] => ram_block1a18.PORTAADDR5 -address_a[5] => ram_block1a19.PORTAADDR5 -address_a[5] => ram_block1a20.PORTAADDR5 -address_a[5] => ram_block1a21.PORTAADDR5 -address_a[5] => ram_block1a22.PORTAADDR5 -address_a[5] => ram_block1a23.PORTAADDR5 -address_a[5] => ram_block1a24.PORTAADDR5 -address_a[5] => ram_block1a25.PORTAADDR5 -address_a[5] => ram_block1a26.PORTAADDR5 -address_a[5] => ram_block1a27.PORTAADDR5 -address_a[5] => ram_block1a28.PORTAADDR5 -address_a[5] => ram_block1a29.PORTAADDR5 -address_a[5] => ram_block1a30.PORTAADDR5 -address_a[5] => ram_block1a31.PORTAADDR5 -address_a[6] => ram_block1a0.PORTAADDR6 -address_a[6] => ram_block1a1.PORTAADDR6 -address_a[6] => ram_block1a2.PORTAADDR6 -address_a[6] => ram_block1a3.PORTAADDR6 -address_a[6] => ram_block1a4.PORTAADDR6 -address_a[6] => ram_block1a5.PORTAADDR6 -address_a[6] => ram_block1a6.PORTAADDR6 -address_a[6] => ram_block1a7.PORTAADDR6 -address_a[6] => ram_block1a8.PORTAADDR6 -address_a[6] => ram_block1a9.PORTAADDR6 -address_a[6] => ram_block1a10.PORTAADDR6 -address_a[6] => ram_block1a11.PORTAADDR6 -address_a[6] => ram_block1a12.PORTAADDR6 -address_a[6] => ram_block1a13.PORTAADDR6 -address_a[6] => ram_block1a14.PORTAADDR6 -address_a[6] => ram_block1a15.PORTAADDR6 -address_a[6] => ram_block1a16.PORTAADDR6 -address_a[6] => ram_block1a17.PORTAADDR6 -address_a[6] => ram_block1a18.PORTAADDR6 -address_a[6] => ram_block1a19.PORTAADDR6 -address_a[6] => ram_block1a20.PORTAADDR6 -address_a[6] => ram_block1a21.PORTAADDR6 -address_a[6] => ram_block1a22.PORTAADDR6 -address_a[6] => ram_block1a23.PORTAADDR6 -address_a[6] => ram_block1a24.PORTAADDR6 -address_a[6] => ram_block1a25.PORTAADDR6 -address_a[6] => ram_block1a26.PORTAADDR6 -address_a[6] => ram_block1a27.PORTAADDR6 -address_a[6] => ram_block1a28.PORTAADDR6 -address_a[6] => ram_block1a29.PORTAADDR6 -address_a[6] => ram_block1a30.PORTAADDR6 -address_a[6] => ram_block1a31.PORTAADDR6 -address_a[7] => ram_block1a0.PORTAADDR7 -address_a[7] => ram_block1a1.PORTAADDR7 -address_a[7] => ram_block1a2.PORTAADDR7 -address_a[7] => ram_block1a3.PORTAADDR7 -address_a[7] => ram_block1a4.PORTAADDR7 -address_a[7] => ram_block1a5.PORTAADDR7 -address_a[7] => ram_block1a6.PORTAADDR7 -address_a[7] => ram_block1a7.PORTAADDR7 -address_a[7] => ram_block1a8.PORTAADDR7 -address_a[7] => ram_block1a9.PORTAADDR7 -address_a[7] => ram_block1a10.PORTAADDR7 -address_a[7] => ram_block1a11.PORTAADDR7 -address_a[7] => ram_block1a12.PORTAADDR7 -address_a[7] => ram_block1a13.PORTAADDR7 -address_a[7] => ram_block1a14.PORTAADDR7 -address_a[7] => ram_block1a15.PORTAADDR7 -address_a[7] => ram_block1a16.PORTAADDR7 -address_a[7] => ram_block1a17.PORTAADDR7 -address_a[7] => ram_block1a18.PORTAADDR7 -address_a[7] => ram_block1a19.PORTAADDR7 -address_a[7] => ram_block1a20.PORTAADDR7 -address_a[7] => ram_block1a21.PORTAADDR7 -address_a[7] => ram_block1a22.PORTAADDR7 -address_a[7] => ram_block1a23.PORTAADDR7 -address_a[7] => ram_block1a24.PORTAADDR7 -address_a[7] => ram_block1a25.PORTAADDR7 -address_a[7] => ram_block1a26.PORTAADDR7 -address_a[7] => ram_block1a27.PORTAADDR7 -address_a[7] => ram_block1a28.PORTAADDR7 -address_a[7] => ram_block1a29.PORTAADDR7 -address_a[7] => ram_block1a30.PORTAADDR7 -address_a[7] => ram_block1a31.PORTAADDR7 -byteena_a[0] => ram_block1a0.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a1.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a2.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a3.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a4.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a5.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a6.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a7.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a8.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a9.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a10.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a11.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a12.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a13.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a14.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a15.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a16.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a17.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a18.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a19.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a20.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a21.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a22.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a23.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a24.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a25.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a26.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a27.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a28.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a29.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a30.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a31.PORTABYTEENAMASKS -clock0 => ram_block1a0.CLK0 -clock0 => ram_block1a1.CLK0 -clock0 => ram_block1a2.CLK0 -clock0 => ram_block1a3.CLK0 -clock0 => ram_block1a4.CLK0 -clock0 => ram_block1a5.CLK0 -clock0 => ram_block1a6.CLK0 -clock0 => ram_block1a7.CLK0 -clock0 => ram_block1a8.CLK0 -clock0 => ram_block1a9.CLK0 -clock0 => ram_block1a10.CLK0 -clock0 => ram_block1a11.CLK0 -clock0 => ram_block1a12.CLK0 -clock0 => ram_block1a13.CLK0 -clock0 => ram_block1a14.CLK0 -clock0 => ram_block1a15.CLK0 -clock0 => ram_block1a16.CLK0 -clock0 => ram_block1a17.CLK0 -clock0 => ram_block1a18.CLK0 -clock0 => ram_block1a19.CLK0 -clock0 => ram_block1a20.CLK0 -clock0 => ram_block1a21.CLK0 -clock0 => ram_block1a22.CLK0 -clock0 => ram_block1a23.CLK0 -clock0 => ram_block1a24.CLK0 -clock0 => ram_block1a25.CLK0 -clock0 => ram_block1a26.CLK0 -clock0 => ram_block1a27.CLK0 -clock0 => ram_block1a28.CLK0 -clock0 => ram_block1a29.CLK0 -clock0 => ram_block1a30.CLK0 -clock0 => ram_block1a31.CLK0 -data_a[0] => ram_block1a0.PORTADATAIN -data_a[1] => ram_block1a1.PORTADATAIN -data_a[2] => ram_block1a2.PORTADATAIN -data_a[3] => ram_block1a3.PORTADATAIN -data_a[4] => ram_block1a4.PORTADATAIN -data_a[5] => ram_block1a5.PORTADATAIN -data_a[6] => ram_block1a6.PORTADATAIN -data_a[7] => ram_block1a7.PORTADATAIN -data_a[8] => ram_block1a8.PORTADATAIN -data_a[9] => ram_block1a9.PORTADATAIN -data_a[10] => ram_block1a10.PORTADATAIN -data_a[11] => ram_block1a11.PORTADATAIN -data_a[12] => ram_block1a12.PORTADATAIN -data_a[13] => ram_block1a13.PORTADATAIN -data_a[14] => ram_block1a14.PORTADATAIN -data_a[15] => ram_block1a15.PORTADATAIN -data_a[16] => ram_block1a16.PORTADATAIN -data_a[17] => ram_block1a17.PORTADATAIN -data_a[18] => ram_block1a18.PORTADATAIN -data_a[19] => ram_block1a19.PORTADATAIN -data_a[20] => ram_block1a20.PORTADATAIN -data_a[21] => ram_block1a21.PORTADATAIN -data_a[22] => ram_block1a22.PORTADATAIN -data_a[23] => ram_block1a23.PORTADATAIN -data_a[24] => ram_block1a24.PORTADATAIN -data_a[25] => ram_block1a25.PORTADATAIN -data_a[26] => ram_block1a26.PORTADATAIN -data_a[27] => ram_block1a27.PORTADATAIN -data_a[28] => ram_block1a28.PORTADATAIN -data_a[29] => ram_block1a29.PORTADATAIN -data_a[30] => ram_block1a30.PORTADATAIN -data_a[31] => ram_block1a31.PORTADATAIN -q_a[0] <= ram_block1a0.PORTADATAOUT -q_a[1] <= ram_block1a1.PORTADATAOUT -q_a[2] <= ram_block1a2.PORTADATAOUT -q_a[3] <= ram_block1a3.PORTADATAOUT -q_a[4] <= ram_block1a4.PORTADATAOUT -q_a[5] <= ram_block1a5.PORTADATAOUT -q_a[6] <= ram_block1a6.PORTADATAOUT -q_a[7] <= ram_block1a7.PORTADATAOUT -q_a[8] <= ram_block1a8.PORTADATAOUT -q_a[9] <= ram_block1a9.PORTADATAOUT -q_a[10] <= ram_block1a10.PORTADATAOUT -q_a[11] <= ram_block1a11.PORTADATAOUT -q_a[12] <= ram_block1a12.PORTADATAOUT -q_a[13] <= ram_block1a13.PORTADATAOUT -q_a[14] <= ram_block1a14.PORTADATAOUT -q_a[15] <= ram_block1a15.PORTADATAOUT -q_a[16] <= ram_block1a16.PORTADATAOUT -q_a[17] <= ram_block1a17.PORTADATAOUT -q_a[18] <= ram_block1a18.PORTADATAOUT -q_a[19] <= ram_block1a19.PORTADATAOUT -q_a[20] <= ram_block1a20.PORTADATAOUT -q_a[21] <= ram_block1a21.PORTADATAOUT -q_a[22] <= ram_block1a22.PORTADATAOUT -q_a[23] <= ram_block1a23.PORTADATAOUT -q_a[24] <= ram_block1a24.PORTADATAOUT -q_a[25] <= ram_block1a25.PORTADATAOUT -q_a[26] <= ram_block1a26.PORTADATAOUT -q_a[27] <= ram_block1a27.PORTADATAOUT -q_a[28] <= ram_block1a28.PORTADATAOUT -q_a[29] <= ram_block1a29.PORTADATAOUT -q_a[30] <= ram_block1a30.PORTADATAOUT -q_a[31] <= ram_block1a31.PORTADATAOUT -wren_a => ram_block1a0.PORTAWE -wren_a => ram_block1a1.PORTAWE -wren_a => ram_block1a2.PORTAWE -wren_a => ram_block1a3.PORTAWE -wren_a => ram_block1a4.PORTAWE -wren_a => ram_block1a5.PORTAWE -wren_a => ram_block1a6.PORTAWE -wren_a => ram_block1a7.PORTAWE -wren_a => ram_block1a8.PORTAWE -wren_a => ram_block1a9.PORTAWE -wren_a => ram_block1a10.PORTAWE -wren_a => ram_block1a11.PORTAWE -wren_a => ram_block1a12.PORTAWE -wren_a => ram_block1a13.PORTAWE -wren_a => ram_block1a14.PORTAWE -wren_a => ram_block1a15.PORTAWE -wren_a => ram_block1a16.PORTAWE -wren_a => ram_block1a17.PORTAWE -wren_a => ram_block1a18.PORTAWE -wren_a => ram_block1a19.PORTAWE -wren_a => ram_block1a20.PORTAWE -wren_a => ram_block1a21.PORTAWE -wren_a => ram_block1a22.PORTAWE -wren_a => ram_block1a23.PORTAWE -wren_a => ram_block1a24.PORTAWE -wren_a => ram_block1a25.PORTAWE -wren_a => ram_block1a26.PORTAWE -wren_a => ram_block1a27.PORTAWE -wren_a => ram_block1a28.PORTAWE -wren_a => ram_block1a29.PORTAWE -wren_a => ram_block1a30.PORTAWE -wren_a => ram_block1a31.PORTAWE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg -address[0] => Equal0.IN8 -address[0] => Equal1.IN1 -address[1] => Equal0.IN7 -address[1] => Equal1.IN8 -address[2] => Equal0.IN6 -address[2] => Equal1.IN7 -address[3] => Equal0.IN5 -address[3] => Equal1.IN6 -address[4] => Equal0.IN4 -address[4] => Equal1.IN5 -address[5] => Equal0.IN3 -address[5] => Equal1.IN4 -address[6] => Equal0.IN2 -address[6] => Equal1.IN3 -address[7] => Equal0.IN1 -address[7] => Equal1.IN2 -address[8] => Equal0.IN0 -address[8] => Equal1.IN0 -clk => oci_ienable[0]~reg0.CLK -clk => oci_ienable[1]~reg0.CLK -clk => oci_ienable[2]~reg0.CLK -clk => oci_ienable[3]~reg0.CLK -clk => oci_ienable[4]~reg0.CLK -clk => oci_ienable[5]~reg0.CLK -clk => oci_ienable[6]~reg0.CLK -clk => oci_ienable[7]~reg0.CLK -clk => oci_ienable[8]~reg0.CLK -clk => oci_ienable[9]~reg0.CLK -clk => oci_ienable[10]~reg0.CLK -clk => oci_ienable[11]~reg0.CLK -clk => oci_ienable[12]~reg0.CLK -clk => oci_ienable[13]~reg0.CLK -clk => oci_ienable[14]~reg0.CLK -clk => oci_ienable[15]~reg0.CLK -clk => oci_ienable[16]~reg0.CLK -clk => oci_ienable[17]~reg0.CLK -clk => oci_ienable[18]~reg0.CLK -clk => oci_ienable[19]~reg0.CLK -clk => oci_ienable[20]~reg0.CLK -clk => oci_ienable[21]~reg0.CLK -clk => oci_ienable[22]~reg0.CLK -clk => oci_ienable[23]~reg0.CLK -clk => oci_ienable[24]~reg0.CLK -clk => oci_ienable[25]~reg0.CLK -clk => oci_ienable[26]~reg0.CLK -clk => oci_ienable[27]~reg0.CLK -clk => oci_ienable[28]~reg0.CLK -clk => oci_ienable[29]~reg0.CLK -clk => oci_ienable[30]~reg0.CLK -clk => oci_ienable[31]~reg0.CLK -clk => oci_single_step_mode~reg0.CLK -debugaccess => write_strobe.IN0 -monitor_error => oci_reg_readdata.DATAB -monitor_go => oci_reg_readdata.DATAB -monitor_ready => oci_reg_readdata.DATAB -reset_n => oci_ienable[0]~reg0.ACLR -reset_n => oci_ienable[1]~reg0.ACLR -reset_n => oci_ienable[2]~reg0.ACLR -reset_n => oci_ienable[3]~reg0.ACLR -reset_n => oci_ienable[4]~reg0.ACLR -reset_n => oci_ienable[5]~reg0.PRESET -reset_n => oci_ienable[6]~reg0.ACLR -reset_n => oci_ienable[7]~reg0.ACLR -reset_n => oci_ienable[8]~reg0.ACLR -reset_n => oci_ienable[9]~reg0.ACLR -reset_n => oci_ienable[10]~reg0.ACLR -reset_n => oci_ienable[11]~reg0.ACLR -reset_n => oci_ienable[12]~reg0.ACLR -reset_n => oci_ienable[13]~reg0.ACLR -reset_n => oci_ienable[14]~reg0.ACLR -reset_n => oci_ienable[15]~reg0.ACLR -reset_n => oci_ienable[16]~reg0.ACLR -reset_n => oci_ienable[17]~reg0.ACLR -reset_n => oci_ienable[18]~reg0.ACLR -reset_n => oci_ienable[19]~reg0.ACLR -reset_n => oci_ienable[20]~reg0.ACLR -reset_n => oci_ienable[21]~reg0.ACLR -reset_n => oci_ienable[22]~reg0.ACLR -reset_n => oci_ienable[23]~reg0.ACLR -reset_n => oci_ienable[24]~reg0.ACLR -reset_n => oci_ienable[25]~reg0.ACLR -reset_n => oci_ienable[26]~reg0.ACLR -reset_n => oci_ienable[27]~reg0.ACLR -reset_n => oci_ienable[28]~reg0.ACLR -reset_n => oci_ienable[29]~reg0.ACLR -reset_n => oci_ienable[30]~reg0.ACLR -reset_n => oci_ienable[31]~reg0.ACLR -reset_n => oci_single_step_mode~reg0.ACLR -write => write_strobe.IN1 -writedata[0] => ocireg_mrs.DATAIN -writedata[1] => ocireg_ers.DATAIN -writedata[2] => ~NO_FANOUT~ -writedata[3] => oci_single_step_mode~reg0.DATAIN -writedata[4] => ~NO_FANOUT~ -writedata[5] => oci_ienable[5]~reg0.DATAIN -writedata[6] => ~NO_FANOUT~ -writedata[7] => ~NO_FANOUT~ -writedata[8] => ~NO_FANOUT~ -writedata[9] => ~NO_FANOUT~ -writedata[10] => ~NO_FANOUT~ -writedata[11] => ~NO_FANOUT~ -writedata[12] => ~NO_FANOUT~ -writedata[13] => ~NO_FANOUT~ -writedata[14] => ~NO_FANOUT~ -writedata[15] => ~NO_FANOUT~ -writedata[16] => ~NO_FANOUT~ -writedata[17] => ~NO_FANOUT~ -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -oci_ienable[0] <= oci_ienable[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[1] <= oci_ienable[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[2] <= oci_ienable[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[3] <= oci_ienable[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[4] <= oci_ienable[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[5] <= oci_ienable[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[6] <= oci_ienable[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[7] <= oci_ienable[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[8] <= oci_ienable[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[9] <= oci_ienable[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[10] <= oci_ienable[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[11] <= oci_ienable[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[12] <= oci_ienable[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[13] <= oci_ienable[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[14] <= oci_ienable[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[15] <= oci_ienable[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[16] <= oci_ienable[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[17] <= oci_ienable[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[18] <= oci_ienable[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[19] <= oci_ienable[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[20] <= oci_ienable[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[21] <= oci_ienable[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[22] <= oci_ienable[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[23] <= oci_ienable[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[24] <= oci_ienable[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[25] <= oci_ienable[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[26] <= oci_ienable[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[27] <= oci_ienable[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[28] <= oci_ienable[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[29] <= oci_ienable[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[30] <= oci_ienable[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[31] <= oci_ienable[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[0] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[1] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[2] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[3] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[4] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[5] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[6] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[7] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[8] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[9] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[10] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[11] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[12] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[13] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[14] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[15] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[16] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[17] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[18] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[19] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[20] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[21] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[22] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[23] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[24] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[25] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[26] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[27] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[28] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[29] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[30] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[31] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_single_step_mode <= oci_single_step_mode~reg0.DB_MAX_OUTPUT_PORT_TYPE -ocireg_ers <= writedata[1].DB_MAX_OUTPUT_PORT_TYPE -ocireg_mrs <= writedata[0].DB_MAX_OUTPUT_PORT_TYPE -take_action_ocireg <= take_action_ocireg.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break -clk => trigger_state.CLK -clk => break_readreg[0]~reg0.CLK -clk => break_readreg[1]~reg0.CLK -clk => break_readreg[2]~reg0.CLK -clk => break_readreg[3]~reg0.CLK -clk => break_readreg[4]~reg0.CLK -clk => break_readreg[5]~reg0.CLK -clk => break_readreg[6]~reg0.CLK -clk => break_readreg[7]~reg0.CLK -clk => break_readreg[8]~reg0.CLK -clk => break_readreg[9]~reg0.CLK -clk => break_readreg[10]~reg0.CLK -clk => break_readreg[11]~reg0.CLK -clk => break_readreg[12]~reg0.CLK -clk => break_readreg[13]~reg0.CLK -clk => break_readreg[14]~reg0.CLK -clk => break_readreg[15]~reg0.CLK -clk => break_readreg[16]~reg0.CLK -clk => break_readreg[17]~reg0.CLK -clk => break_readreg[18]~reg0.CLK -clk => break_readreg[19]~reg0.CLK -clk => break_readreg[20]~reg0.CLK -clk => break_readreg[21]~reg0.CLK -clk => break_readreg[22]~reg0.CLK -clk => break_readreg[23]~reg0.CLK -clk => break_readreg[24]~reg0.CLK -clk => break_readreg[25]~reg0.CLK -clk => break_readreg[26]~reg0.CLK -clk => break_readreg[27]~reg0.CLK -clk => break_readreg[28]~reg0.CLK -clk => break_readreg[29]~reg0.CLK -clk => break_readreg[30]~reg0.CLK -clk => break_readreg[31]~reg0.CLK -clk => trigbrktype~reg0.CLK -dbrk_break => trigbrktype.OUTPUTSELECT -dbrk_goto0 => always2.IN0 -dbrk_goto1 => always2.IN0 -jdo[0] => break_readreg.DATAB -jdo[0] => break_readreg.DATAB -jdo[0] => break_readreg.DATAB -jdo[1] => break_readreg.DATAB -jdo[1] => break_readreg.DATAB -jdo[1] => break_readreg.DATAB -jdo[2] => break_readreg.DATAB -jdo[2] => break_readreg.DATAB -jdo[2] => break_readreg.DATAB -jdo[3] => break_readreg.DATAB -jdo[3] => break_readreg.DATAB -jdo[3] => break_readreg.DATAB -jdo[4] => break_readreg.DATAB -jdo[4] => break_readreg.DATAB -jdo[4] => break_readreg.DATAB -jdo[5] => break_readreg.DATAB -jdo[5] => break_readreg.DATAB -jdo[5] => break_readreg.DATAB -jdo[6] => break_readreg.DATAB -jdo[6] => break_readreg.DATAB -jdo[6] => break_readreg.DATAB -jdo[7] => break_readreg.DATAB -jdo[7] => break_readreg.DATAB -jdo[7] => break_readreg.DATAB -jdo[8] => break_readreg.DATAB -jdo[8] => break_readreg.DATAB -jdo[8] => break_readreg.DATAB -jdo[9] => break_readreg.DATAB -jdo[9] => break_readreg.DATAB -jdo[9] => break_readreg.DATAB -jdo[10] => break_readreg.DATAB -jdo[10] => break_readreg.DATAB -jdo[10] => break_readreg.DATAB -jdo[11] => break_readreg.DATAB -jdo[11] => break_readreg.DATAB -jdo[11] => break_readreg.DATAB -jdo[12] => break_readreg.DATAB -jdo[12] => break_readreg.DATAB -jdo[12] => break_readreg.DATAB -jdo[13] => break_readreg.DATAB -jdo[13] => break_readreg.DATAB -jdo[13] => break_readreg.DATAB -jdo[14] => break_readreg.DATAB -jdo[14] => break_readreg.DATAB -jdo[14] => break_readreg.DATAB -jdo[15] => break_readreg.DATAB -jdo[15] => break_readreg.DATAB -jdo[15] => break_readreg.DATAB -jdo[16] => break_readreg.DATAB -jdo[16] => break_readreg.DATAB -jdo[16] => break_readreg.DATAB -jdo[17] => break_readreg.DATAB -jdo[17] => break_readreg.DATAB -jdo[17] => break_readreg.DATAB -jdo[18] => break_readreg.DATAB -jdo[18] => break_readreg.DATAB -jdo[18] => break_readreg.DATAB -jdo[19] => break_readreg.DATAB -jdo[19] => break_readreg.DATAB -jdo[19] => break_readreg.DATAB -jdo[20] => break_readreg.DATAB -jdo[20] => break_readreg.DATAB -jdo[20] => break_readreg.DATAB -jdo[21] => break_readreg.DATAB -jdo[21] => break_readreg.DATAB -jdo[21] => break_readreg.DATAB -jdo[22] => break_readreg.DATAB -jdo[22] => break_readreg.DATAB -jdo[22] => break_readreg.DATAB -jdo[23] => break_readreg.DATAB -jdo[23] => break_readreg.DATAB -jdo[23] => break_readreg.DATAB -jdo[24] => break_readreg.DATAB -jdo[24] => break_readreg.DATAB -jdo[24] => break_readreg.DATAB -jdo[25] => break_readreg.DATAB -jdo[25] => break_readreg.DATAB -jdo[25] => break_readreg.DATAB -jdo[26] => break_readreg.DATAB -jdo[26] => break_readreg.DATAB -jdo[26] => break_readreg.DATAB -jdo[27] => break_readreg.DATAB -jdo[27] => break_readreg.DATAB -jdo[27] => break_readreg.DATAB -jdo[28] => break_readreg.DATAB -jdo[28] => break_readreg.DATAB -jdo[28] => break_readreg.DATAB -jdo[29] => break_readreg.DATAB -jdo[29] => break_readreg.DATAB -jdo[29] => break_readreg.DATAB -jdo[30] => break_readreg.DATAB -jdo[30] => break_readreg.DATAB -jdo[30] => break_readreg.DATAB -jdo[31] => break_readreg.DATAB -jdo[31] => break_readreg.DATAB -jdo[31] => break_readreg.DATAB -jdo[32] => ~NO_FANOUT~ -jdo[33] => ~NO_FANOUT~ -jdo[34] => ~NO_FANOUT~ -jdo[35] => ~NO_FANOUT~ -jdo[36] => ~NO_FANOUT~ -jdo[37] => ~NO_FANOUT~ -jrst_n => break_readreg[0]~reg0.ACLR -jrst_n => break_readreg[1]~reg0.ACLR -jrst_n => break_readreg[2]~reg0.ACLR -jrst_n => break_readreg[3]~reg0.ACLR -jrst_n => break_readreg[4]~reg0.ACLR -jrst_n => break_readreg[5]~reg0.ACLR -jrst_n => break_readreg[6]~reg0.ACLR -jrst_n => break_readreg[7]~reg0.ACLR -jrst_n => break_readreg[8]~reg0.ACLR -jrst_n => break_readreg[9]~reg0.ACLR -jrst_n => break_readreg[10]~reg0.ACLR -jrst_n => break_readreg[11]~reg0.ACLR -jrst_n => break_readreg[12]~reg0.ACLR -jrst_n => break_readreg[13]~reg0.ACLR -jrst_n => break_readreg[14]~reg0.ACLR -jrst_n => break_readreg[15]~reg0.ACLR -jrst_n => break_readreg[16]~reg0.ACLR -jrst_n => break_readreg[17]~reg0.ACLR -jrst_n => break_readreg[18]~reg0.ACLR -jrst_n => break_readreg[19]~reg0.ACLR -jrst_n => break_readreg[20]~reg0.ACLR -jrst_n => break_readreg[21]~reg0.ACLR -jrst_n => break_readreg[22]~reg0.ACLR -jrst_n => break_readreg[23]~reg0.ACLR -jrst_n => break_readreg[24]~reg0.ACLR -jrst_n => break_readreg[25]~reg0.ACLR -jrst_n => break_readreg[26]~reg0.ACLR -jrst_n => break_readreg[27]~reg0.ACLR -jrst_n => break_readreg[28]~reg0.ACLR -jrst_n => break_readreg[29]~reg0.ACLR -jrst_n => break_readreg[30]~reg0.ACLR -jrst_n => break_readreg[31]~reg0.ACLR -jrst_n => trigbrktype~reg0.ACLR -reset_n => trigger_state.ACLR -take_action_break_a => take_action_any_break.IN0 -take_action_break_b => take_action_any_break.IN1 -take_action_break_c => take_action_any_break.IN1 -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -xbrk_goto0 => always2.IN1 -xbrk_goto1 => always2.IN1 -break_readreg[0] <= break_readreg[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[1] <= break_readreg[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[2] <= break_readreg[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[3] <= break_readreg[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[4] <= break_readreg[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[5] <= break_readreg[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[6] <= break_readreg[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[7] <= break_readreg[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[8] <= break_readreg[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[9] <= break_readreg[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[10] <= break_readreg[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[11] <= break_readreg[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[12] <= break_readreg[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[13] <= break_readreg[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[14] <= break_readreg[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[15] <= break_readreg[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[16] <= break_readreg[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[17] <= break_readreg[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[18] <= break_readreg[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[19] <= break_readreg[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[20] <= break_readreg[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[21] <= break_readreg[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[22] <= break_readreg[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[23] <= break_readreg[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[24] <= break_readreg[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[25] <= break_readreg[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[26] <= break_readreg[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[27] <= break_readreg[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[28] <= break_readreg[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[29] <= break_readreg[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[30] <= break_readreg[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[31] <= break_readreg[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dbrk_hit0_latch <= -dbrk_hit1_latch <= -dbrk_hit2_latch <= -dbrk_hit3_latch <= -trigbrktype <= trigbrktype~reg0.DB_MAX_OUTPUT_PORT_TYPE -trigger_state_0 <= trigger_state.DB_MAX_OUTPUT_PORT_TYPE -trigger_state_1 <= trigger_state.DB_MAX_OUTPUT_PORT_TYPE -xbrk_ctrl0[0] <= -xbrk_ctrl0[1] <= -xbrk_ctrl0[2] <= -xbrk_ctrl0[3] <= -xbrk_ctrl0[4] <= -xbrk_ctrl0[5] <= -xbrk_ctrl0[6] <= -xbrk_ctrl0[7] <= -xbrk_ctrl1[0] <= -xbrk_ctrl1[1] <= -xbrk_ctrl1[2] <= -xbrk_ctrl1[3] <= -xbrk_ctrl1[4] <= -xbrk_ctrl1[5] <= -xbrk_ctrl1[6] <= -xbrk_ctrl1[7] <= -xbrk_ctrl2[0] <= -xbrk_ctrl2[1] <= -xbrk_ctrl2[2] <= -xbrk_ctrl2[3] <= -xbrk_ctrl2[4] <= -xbrk_ctrl2[5] <= -xbrk_ctrl2[6] <= -xbrk_ctrl2[7] <= -xbrk_ctrl3[0] <= -xbrk_ctrl3[1] <= -xbrk_ctrl3[2] <= -xbrk_ctrl3[3] <= -xbrk_ctrl3[4] <= -xbrk_ctrl3[5] <= -xbrk_ctrl3[6] <= -xbrk_ctrl3[7] <= - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk -D_valid => ~NO_FANOUT~ -E_valid => xbrk_break~reg0.ENA -F_pc[0] => ~NO_FANOUT~ -F_pc[1] => ~NO_FANOUT~ -F_pc[2] => ~NO_FANOUT~ -F_pc[3] => ~NO_FANOUT~ -F_pc[4] => ~NO_FANOUT~ -F_pc[5] => ~NO_FANOUT~ -F_pc[6] => ~NO_FANOUT~ -F_pc[7] => ~NO_FANOUT~ -F_pc[8] => ~NO_FANOUT~ -F_pc[9] => ~NO_FANOUT~ -F_pc[10] => ~NO_FANOUT~ -F_pc[11] => ~NO_FANOUT~ -F_pc[12] => ~NO_FANOUT~ -F_pc[13] => ~NO_FANOUT~ -F_pc[14] => ~NO_FANOUT~ -F_pc[15] => ~NO_FANOUT~ -F_pc[16] => ~NO_FANOUT~ -clk => xbrk_break~reg0.CLK -reset_n => xbrk_break~reg0.ACLR -trigger_state_0 => ~NO_FANOUT~ -trigger_state_1 => ~NO_FANOUT~ -xbrk_ctrl0[0] => ~NO_FANOUT~ -xbrk_ctrl0[1] => ~NO_FANOUT~ -xbrk_ctrl0[2] => ~NO_FANOUT~ -xbrk_ctrl0[3] => ~NO_FANOUT~ -xbrk_ctrl0[4] => ~NO_FANOUT~ -xbrk_ctrl0[5] => ~NO_FANOUT~ -xbrk_ctrl0[6] => ~NO_FANOUT~ -xbrk_ctrl0[7] => ~NO_FANOUT~ -xbrk_ctrl1[0] => ~NO_FANOUT~ -xbrk_ctrl1[1] => ~NO_FANOUT~ -xbrk_ctrl1[2] => ~NO_FANOUT~ -xbrk_ctrl1[3] => ~NO_FANOUT~ -xbrk_ctrl1[4] => ~NO_FANOUT~ -xbrk_ctrl1[5] => ~NO_FANOUT~ -xbrk_ctrl1[6] => ~NO_FANOUT~ -xbrk_ctrl1[7] => ~NO_FANOUT~ -xbrk_ctrl2[0] => ~NO_FANOUT~ -xbrk_ctrl2[1] => ~NO_FANOUT~ -xbrk_ctrl2[2] => ~NO_FANOUT~ -xbrk_ctrl2[3] => ~NO_FANOUT~ -xbrk_ctrl2[4] => ~NO_FANOUT~ -xbrk_ctrl2[5] => ~NO_FANOUT~ -xbrk_ctrl2[6] => ~NO_FANOUT~ -xbrk_ctrl2[7] => ~NO_FANOUT~ -xbrk_ctrl3[0] => ~NO_FANOUT~ -xbrk_ctrl3[1] => ~NO_FANOUT~ -xbrk_ctrl3[2] => ~NO_FANOUT~ -xbrk_ctrl3[3] => ~NO_FANOUT~ -xbrk_ctrl3[4] => ~NO_FANOUT~ -xbrk_ctrl3[5] => ~NO_FANOUT~ -xbrk_ctrl3[6] => ~NO_FANOUT~ -xbrk_ctrl3[7] => ~NO_FANOUT~ -xbrk_break <= xbrk_break~reg0.DB_MAX_OUTPUT_PORT_TYPE -xbrk_goto0 <= -xbrk_goto1 <= -xbrk_traceoff <= -xbrk_traceon <= -xbrk_trigout <= - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk -E_st_data[0] => cpu_d_writedata[0].DATAIN -E_st_data[1] => cpu_d_writedata[1].DATAIN -E_st_data[2] => cpu_d_writedata[2].DATAIN -E_st_data[3] => cpu_d_writedata[3].DATAIN -E_st_data[4] => cpu_d_writedata[4].DATAIN -E_st_data[5] => cpu_d_writedata[5].DATAIN -E_st_data[6] => cpu_d_writedata[6].DATAIN -E_st_data[7] => cpu_d_writedata[7].DATAIN -E_st_data[8] => cpu_d_writedata[8].DATAIN -E_st_data[9] => cpu_d_writedata[9].DATAIN -E_st_data[10] => cpu_d_writedata[10].DATAIN -E_st_data[11] => cpu_d_writedata[11].DATAIN -E_st_data[12] => cpu_d_writedata[12].DATAIN -E_st_data[13] => cpu_d_writedata[13].DATAIN -E_st_data[14] => cpu_d_writedata[14].DATAIN -E_st_data[15] => cpu_d_writedata[15].DATAIN -E_st_data[16] => cpu_d_writedata[16].DATAIN -E_st_data[17] => cpu_d_writedata[17].DATAIN -E_st_data[18] => cpu_d_writedata[18].DATAIN -E_st_data[19] => cpu_d_writedata[19].DATAIN -E_st_data[20] => cpu_d_writedata[20].DATAIN -E_st_data[21] => cpu_d_writedata[21].DATAIN -E_st_data[22] => cpu_d_writedata[22].DATAIN -E_st_data[23] => cpu_d_writedata[23].DATAIN -E_st_data[24] => cpu_d_writedata[24].DATAIN -E_st_data[25] => cpu_d_writedata[25].DATAIN -E_st_data[26] => cpu_d_writedata[26].DATAIN -E_st_data[27] => cpu_d_writedata[27].DATAIN -E_st_data[28] => cpu_d_writedata[28].DATAIN -E_st_data[29] => cpu_d_writedata[29].DATAIN -E_st_data[30] => cpu_d_writedata[30].DATAIN -E_st_data[31] => cpu_d_writedata[31].DATAIN -av_ld_data_aligned_filtered[0] => cpu_d_readdata[0].DATAIN -av_ld_data_aligned_filtered[1] => cpu_d_readdata[1].DATAIN -av_ld_data_aligned_filtered[2] => cpu_d_readdata[2].DATAIN -av_ld_data_aligned_filtered[3] => cpu_d_readdata[3].DATAIN -av_ld_data_aligned_filtered[4] => cpu_d_readdata[4].DATAIN -av_ld_data_aligned_filtered[5] => cpu_d_readdata[5].DATAIN -av_ld_data_aligned_filtered[6] => cpu_d_readdata[6].DATAIN -av_ld_data_aligned_filtered[7] => cpu_d_readdata[7].DATAIN -av_ld_data_aligned_filtered[8] => cpu_d_readdata[8].DATAIN -av_ld_data_aligned_filtered[9] => cpu_d_readdata[9].DATAIN -av_ld_data_aligned_filtered[10] => cpu_d_readdata[10].DATAIN -av_ld_data_aligned_filtered[11] => cpu_d_readdata[11].DATAIN -av_ld_data_aligned_filtered[12] => cpu_d_readdata[12].DATAIN -av_ld_data_aligned_filtered[13] => cpu_d_readdata[13].DATAIN -av_ld_data_aligned_filtered[14] => cpu_d_readdata[14].DATAIN -av_ld_data_aligned_filtered[15] => cpu_d_readdata[15].DATAIN -av_ld_data_aligned_filtered[16] => cpu_d_readdata[16].DATAIN -av_ld_data_aligned_filtered[17] => cpu_d_readdata[17].DATAIN -av_ld_data_aligned_filtered[18] => cpu_d_readdata[18].DATAIN -av_ld_data_aligned_filtered[19] => cpu_d_readdata[19].DATAIN -av_ld_data_aligned_filtered[20] => cpu_d_readdata[20].DATAIN -av_ld_data_aligned_filtered[21] => cpu_d_readdata[21].DATAIN -av_ld_data_aligned_filtered[22] => cpu_d_readdata[22].DATAIN -av_ld_data_aligned_filtered[23] => cpu_d_readdata[23].DATAIN -av_ld_data_aligned_filtered[24] => cpu_d_readdata[24].DATAIN -av_ld_data_aligned_filtered[25] => cpu_d_readdata[25].DATAIN -av_ld_data_aligned_filtered[26] => cpu_d_readdata[26].DATAIN -av_ld_data_aligned_filtered[27] => cpu_d_readdata[27].DATAIN -av_ld_data_aligned_filtered[28] => cpu_d_readdata[28].DATAIN -av_ld_data_aligned_filtered[29] => cpu_d_readdata[29].DATAIN -av_ld_data_aligned_filtered[30] => cpu_d_readdata[30].DATAIN -av_ld_data_aligned_filtered[31] => cpu_d_readdata[31].DATAIN -clk => dbrk_goto1~reg0.CLK -clk => dbrk_goto0~reg0.CLK -clk => dbrk_traceme~reg0.CLK -clk => dbrk_traceon~reg0.CLK -clk => dbrk_traceoff~reg0.CLK -clk => dbrk_break_pulse.CLK -clk => dbrk_trigout~reg0.CLK -clk => dbrk_break~reg0.CLK -d_address[0] => cpu_d_address[0].DATAIN -d_address[1] => cpu_d_address[1].DATAIN -d_address[2] => cpu_d_address[2].DATAIN -d_address[3] => cpu_d_address[3].DATAIN -d_address[4] => cpu_d_address[4].DATAIN -d_address[5] => cpu_d_address[5].DATAIN -d_address[6] => cpu_d_address[6].DATAIN -d_address[7] => cpu_d_address[7].DATAIN -d_address[8] => cpu_d_address[8].DATAIN -d_address[9] => cpu_d_address[9].DATAIN -d_address[10] => cpu_d_address[10].DATAIN -d_address[11] => cpu_d_address[11].DATAIN -d_address[12] => cpu_d_address[12].DATAIN -d_address[13] => cpu_d_address[13].DATAIN -d_address[14] => cpu_d_address[14].DATAIN -d_address[15] => cpu_d_address[15].DATAIN -d_address[16] => cpu_d_address[16].DATAIN -d_address[17] => cpu_d_address[17].DATAIN -d_address[18] => cpu_d_address[18].DATAIN -d_read => cpu_d_read.DATAIN -d_waitrequest => cpu_d_wait.DATAIN -d_write => cpu_d_write.DATAIN -debugack => dbrk_break.DATAB -reset_n => dbrk_goto1~reg0.ACLR -reset_n => dbrk_goto0~reg0.ACLR -reset_n => dbrk_traceme~reg0.ACLR -reset_n => dbrk_traceon~reg0.ACLR -reset_n => dbrk_traceoff~reg0.ACLR -reset_n => dbrk_break_pulse.ACLR -reset_n => dbrk_trigout~reg0.ACLR -reset_n => dbrk_break~reg0.ACLR -cpu_d_address[0] <= d_address[0].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[1] <= d_address[1].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[2] <= d_address[2].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[3] <= d_address[3].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[4] <= d_address[4].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[5] <= d_address[5].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[6] <= d_address[6].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[7] <= d_address[7].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[8] <= d_address[8].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[9] <= d_address[9].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[10] <= d_address[10].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[11] <= d_address[11].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[12] <= d_address[12].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[13] <= d_address[13].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[14] <= d_address[14].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[15] <= d_address[15].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[16] <= d_address[16].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[17] <= d_address[17].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[18] <= d_address[18].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_read <= d_read.DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[0] <= av_ld_data_aligned_filtered[0].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[1] <= av_ld_data_aligned_filtered[1].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[2] <= av_ld_data_aligned_filtered[2].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[3] <= av_ld_data_aligned_filtered[3].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[4] <= av_ld_data_aligned_filtered[4].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[5] <= av_ld_data_aligned_filtered[5].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[6] <= av_ld_data_aligned_filtered[6].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[7] <= av_ld_data_aligned_filtered[7].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[8] <= av_ld_data_aligned_filtered[8].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[9] <= av_ld_data_aligned_filtered[9].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[10] <= av_ld_data_aligned_filtered[10].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[11] <= av_ld_data_aligned_filtered[11].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[12] <= av_ld_data_aligned_filtered[12].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[13] <= av_ld_data_aligned_filtered[13].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[14] <= av_ld_data_aligned_filtered[14].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[15] <= av_ld_data_aligned_filtered[15].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[16] <= av_ld_data_aligned_filtered[16].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[17] <= av_ld_data_aligned_filtered[17].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[18] <= av_ld_data_aligned_filtered[18].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[19] <= av_ld_data_aligned_filtered[19].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[20] <= av_ld_data_aligned_filtered[20].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[21] <= av_ld_data_aligned_filtered[21].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[22] <= av_ld_data_aligned_filtered[22].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[23] <= av_ld_data_aligned_filtered[23].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[24] <= av_ld_data_aligned_filtered[24].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[25] <= av_ld_data_aligned_filtered[25].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[26] <= av_ld_data_aligned_filtered[26].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[27] <= av_ld_data_aligned_filtered[27].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[28] <= av_ld_data_aligned_filtered[28].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[29] <= av_ld_data_aligned_filtered[29].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[30] <= av_ld_data_aligned_filtered[30].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[31] <= av_ld_data_aligned_filtered[31].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_wait <= d_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -cpu_d_write <= d_write.DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[0] <= E_st_data[0].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[1] <= E_st_data[1].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[2] <= E_st_data[2].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[3] <= E_st_data[3].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[4] <= E_st_data[4].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[5] <= E_st_data[5].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[6] <= E_st_data[6].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[7] <= E_st_data[7].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[8] <= E_st_data[8].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[9] <= E_st_data[9].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[10] <= E_st_data[10].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[11] <= E_st_data[11].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[12] <= E_st_data[12].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[13] <= E_st_data[13].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[14] <= E_st_data[14].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[15] <= E_st_data[15].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[16] <= E_st_data[16].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[17] <= E_st_data[17].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[18] <= E_st_data[18].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[19] <= E_st_data[19].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[20] <= E_st_data[20].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[21] <= E_st_data[21].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[22] <= E_st_data[22].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[23] <= E_st_data[23].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[24] <= E_st_data[24].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[25] <= E_st_data[25].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[26] <= E_st_data[26].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[27] <= E_st_data[27].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[28] <= E_st_data[28].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[29] <= E_st_data[29].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[30] <= E_st_data[30].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[31] <= E_st_data[31].DB_MAX_OUTPUT_PORT_TYPE -dbrk_break <= dbrk_break~reg0.DB_MAX_OUTPUT_PORT_TYPE -dbrk_goto0 <= dbrk_goto0~reg0.DB_MAX_OUTPUT_PORT_TYPE -dbrk_goto1 <= dbrk_goto1~reg0.DB_MAX_OUTPUT_PORT_TYPE -dbrk_traceme <= dbrk_traceme~reg0.DB_MAX_OUTPUT_PORT_TYPE -dbrk_traceoff <= dbrk_traceoff~reg0.DB_MAX_OUTPUT_PORT_TYPE -dbrk_traceon <= dbrk_traceon~reg0.DB_MAX_OUTPUT_PORT_TYPE -dbrk_trigout <= dbrk_trigout~reg0.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_itrace:the_nios_system_nios2_processor_nios2_oci_itrace -clk => dct_count[0]~reg0.CLK -clk => dct_count[1]~reg0.CLK -clk => dct_count[2]~reg0.CLK -clk => dct_count[3]~reg0.CLK -clk => dct_buffer[0]~reg0.CLK -clk => dct_buffer[1]~reg0.CLK -clk => dct_buffer[2]~reg0.CLK -clk => dct_buffer[3]~reg0.CLK -clk => dct_buffer[4]~reg0.CLK -clk => dct_buffer[5]~reg0.CLK -clk => dct_buffer[6]~reg0.CLK -clk => dct_buffer[7]~reg0.CLK -clk => dct_buffer[8]~reg0.CLK -clk => dct_buffer[9]~reg0.CLK -clk => dct_buffer[10]~reg0.CLK -clk => dct_buffer[11]~reg0.CLK -clk => dct_buffer[12]~reg0.CLK -clk => dct_buffer[13]~reg0.CLK -clk => dct_buffer[14]~reg0.CLK -clk => dct_buffer[15]~reg0.CLK -clk => dct_buffer[16]~reg0.CLK -clk => dct_buffer[17]~reg0.CLK -clk => dct_buffer[18]~reg0.CLK -clk => dct_buffer[19]~reg0.CLK -clk => dct_buffer[20]~reg0.CLK -clk => dct_buffer[21]~reg0.CLK -clk => dct_buffer[22]~reg0.CLK -clk => dct_buffer[23]~reg0.CLK -clk => dct_buffer[24]~reg0.CLK -clk => dct_buffer[25]~reg0.CLK -clk => dct_buffer[26]~reg0.CLK -clk => dct_buffer[27]~reg0.CLK -clk => dct_buffer[28]~reg0.CLK -clk => dct_buffer[29]~reg0.CLK -clk => itm[0]~reg0.CLK -clk => itm[1]~reg0.CLK -clk => itm[2]~reg0.CLK -clk => itm[3]~reg0.CLK -clk => itm[4]~reg0.CLK -clk => itm[5]~reg0.CLK -clk => itm[6]~reg0.CLK -clk => itm[7]~reg0.CLK -clk => itm[8]~reg0.CLK -clk => itm[9]~reg0.CLK -clk => itm[10]~reg0.CLK -clk => itm[11]~reg0.CLK -clk => itm[12]~reg0.CLK -clk => itm[13]~reg0.CLK -clk => itm[14]~reg0.CLK -clk => itm[15]~reg0.CLK -clk => itm[16]~reg0.CLK -clk => itm[17]~reg0.CLK -clk => itm[18]~reg0.CLK -clk => itm[19]~reg0.CLK -clk => itm[20]~reg0.CLK -clk => itm[21]~reg0.CLK -clk => itm[22]~reg0.CLK -clk => itm[23]~reg0.CLK -clk => itm[24]~reg0.CLK -clk => itm[25]~reg0.CLK -clk => itm[26]~reg0.CLK -clk => itm[27]~reg0.CLK -clk => itm[28]~reg0.CLK -clk => itm[29]~reg0.CLK -clk => itm[30]~reg0.CLK -clk => itm[31]~reg0.CLK -clk => itm[32]~reg0.CLK -clk => itm[33]~reg0.CLK -clk => itm[34]~reg0.CLK -clk => itm[35]~reg0.CLK -dbrk_traceoff => ~NO_FANOUT~ -dbrk_traceon => ~NO_FANOUT~ -jdo[0] => ~NO_FANOUT~ -jdo[1] => ~NO_FANOUT~ -jdo[2] => ~NO_FANOUT~ -jdo[3] => ~NO_FANOUT~ -jdo[4] => ~NO_FANOUT~ -jdo[5] => ~NO_FANOUT~ -jdo[6] => ~NO_FANOUT~ -jdo[7] => ~NO_FANOUT~ -jdo[8] => ~NO_FANOUT~ -jdo[9] => ~NO_FANOUT~ -jdo[10] => ~NO_FANOUT~ -jdo[11] => ~NO_FANOUT~ -jdo[12] => ~NO_FANOUT~ -jdo[13] => ~NO_FANOUT~ -jdo[14] => ~NO_FANOUT~ -jdo[15] => ~NO_FANOUT~ -jrst_n => dct_count[0]~reg0.ACLR -jrst_n => dct_count[1]~reg0.ACLR -jrst_n => dct_count[2]~reg0.ACLR -jrst_n => dct_count[3]~reg0.ACLR -jrst_n => dct_buffer[0]~reg0.ACLR -jrst_n => dct_buffer[1]~reg0.ACLR -jrst_n => dct_buffer[2]~reg0.ACLR -jrst_n => dct_buffer[3]~reg0.ACLR -jrst_n => dct_buffer[4]~reg0.ACLR -jrst_n => dct_buffer[5]~reg0.ACLR -jrst_n => dct_buffer[6]~reg0.ACLR -jrst_n => dct_buffer[7]~reg0.ACLR -jrst_n => dct_buffer[8]~reg0.ACLR -jrst_n => dct_buffer[9]~reg0.ACLR -jrst_n => dct_buffer[10]~reg0.ACLR -jrst_n => dct_buffer[11]~reg0.ACLR -jrst_n => dct_buffer[12]~reg0.ACLR -jrst_n => dct_buffer[13]~reg0.ACLR -jrst_n => dct_buffer[14]~reg0.ACLR -jrst_n => dct_buffer[15]~reg0.ACLR -jrst_n => dct_buffer[16]~reg0.ACLR -jrst_n => dct_buffer[17]~reg0.ACLR -jrst_n => dct_buffer[18]~reg0.ACLR -jrst_n => dct_buffer[19]~reg0.ACLR -jrst_n => dct_buffer[20]~reg0.ACLR -jrst_n => dct_buffer[21]~reg0.ACLR -jrst_n => dct_buffer[22]~reg0.ACLR -jrst_n => dct_buffer[23]~reg0.ACLR -jrst_n => dct_buffer[24]~reg0.ACLR -jrst_n => dct_buffer[25]~reg0.ACLR -jrst_n => dct_buffer[26]~reg0.ACLR -jrst_n => dct_buffer[27]~reg0.ACLR -jrst_n => dct_buffer[28]~reg0.ACLR -jrst_n => dct_buffer[29]~reg0.ACLR -jrst_n => itm[0]~reg0.ACLR -jrst_n => itm[1]~reg0.ACLR -jrst_n => itm[2]~reg0.ACLR -jrst_n => itm[3]~reg0.ACLR -jrst_n => itm[4]~reg0.ACLR -jrst_n => itm[5]~reg0.ACLR -jrst_n => itm[6]~reg0.ACLR -jrst_n => itm[7]~reg0.ACLR -jrst_n => itm[8]~reg0.ACLR -jrst_n => itm[9]~reg0.ACLR -jrst_n => itm[10]~reg0.ACLR -jrst_n => itm[11]~reg0.ACLR -jrst_n => itm[12]~reg0.ACLR -jrst_n => itm[13]~reg0.ACLR -jrst_n => itm[14]~reg0.ACLR -jrst_n => itm[15]~reg0.ACLR -jrst_n => itm[16]~reg0.ACLR -jrst_n => itm[17]~reg0.ACLR -jrst_n => itm[18]~reg0.ACLR -jrst_n => itm[19]~reg0.ACLR -jrst_n => itm[20]~reg0.ACLR -jrst_n => itm[21]~reg0.ACLR -jrst_n => itm[22]~reg0.ACLR -jrst_n => itm[23]~reg0.ACLR -jrst_n => itm[24]~reg0.ACLR -jrst_n => itm[25]~reg0.ACLR -jrst_n => itm[26]~reg0.ACLR -jrst_n => itm[27]~reg0.ACLR -jrst_n => itm[28]~reg0.ACLR -jrst_n => itm[29]~reg0.ACLR -jrst_n => itm[30]~reg0.ACLR -jrst_n => itm[31]~reg0.ACLR -jrst_n => itm[32]~reg0.ACLR -jrst_n => itm[33]~reg0.ACLR -jrst_n => itm[34]~reg0.ACLR -jrst_n => itm[35]~reg0.ACLR -take_action_tracectrl => ~NO_FANOUT~ -trc_enb => ~NO_FANOUT~ -xbrk_traceoff => ~NO_FANOUT~ -xbrk_traceon => ~NO_FANOUT~ -xbrk_wrap_traceoff => ~NO_FANOUT~ -dct_buffer[0] <= dct_buffer[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[1] <= dct_buffer[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[2] <= dct_buffer[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[3] <= dct_buffer[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[4] <= dct_buffer[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[5] <= dct_buffer[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[6] <= dct_buffer[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[7] <= dct_buffer[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[8] <= dct_buffer[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[9] <= dct_buffer[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[10] <= dct_buffer[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[11] <= dct_buffer[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[12] <= dct_buffer[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[13] <= dct_buffer[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[14] <= dct_buffer[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[15] <= dct_buffer[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[16] <= dct_buffer[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[17] <= dct_buffer[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[18] <= dct_buffer[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[19] <= dct_buffer[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[20] <= dct_buffer[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[21] <= dct_buffer[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[22] <= dct_buffer[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[23] <= dct_buffer[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[24] <= dct_buffer[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[25] <= dct_buffer[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[26] <= dct_buffer[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[27] <= dct_buffer[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[28] <= dct_buffer[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[29] <= dct_buffer[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_count[0] <= dct_count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_count[1] <= dct_count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_count[2] <= dct_count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_count[3] <= dct_count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[0] <= itm[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[1] <= itm[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[2] <= itm[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[3] <= itm[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[4] <= itm[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[5] <= itm[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[6] <= itm[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[7] <= itm[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[8] <= itm[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[9] <= itm[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[10] <= itm[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[11] <= itm[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[12] <= itm[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[13] <= itm[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[14] <= itm[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[15] <= itm[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[16] <= itm[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[17] <= itm[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[18] <= itm[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[19] <= itm[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[20] <= itm[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[21] <= itm[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[22] <= itm[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[23] <= itm[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[24] <= itm[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[25] <= itm[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[26] <= itm[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[27] <= itm[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[28] <= itm[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[29] <= itm[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[30] <= itm[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[31] <= itm[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[32] <= itm[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[33] <= itm[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[34] <= itm[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[35] <= itm[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE -trc_ctrl[0] <= -trc_ctrl[1] <= -trc_ctrl[2] <= -trc_ctrl[3] <= -trc_ctrl[4] <= -trc_ctrl[5] <= -trc_ctrl[6] <= -trc_ctrl[7] <= -trc_ctrl[8] <= -trc_ctrl[9] <= -trc_ctrl[10] <= -trc_ctrl[11] <= -trc_ctrl[12] <= -trc_ctrl[13] <= -trc_ctrl[14] <= -trc_ctrl[15] <= -trc_on <= - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace -clk => dtm[0]~reg0.CLK -clk => dtm[1]~reg0.CLK -clk => dtm[2]~reg0.CLK -clk => dtm[3]~reg0.CLK -clk => dtm[4]~reg0.CLK -clk => dtm[5]~reg0.CLK -clk => dtm[6]~reg0.CLK -clk => dtm[7]~reg0.CLK -clk => dtm[8]~reg0.CLK -clk => dtm[9]~reg0.CLK -clk => dtm[10]~reg0.CLK -clk => dtm[11]~reg0.CLK -clk => dtm[12]~reg0.CLK -clk => dtm[13]~reg0.CLK -clk => dtm[14]~reg0.CLK -clk => dtm[15]~reg0.CLK -clk => dtm[16]~reg0.CLK -clk => dtm[17]~reg0.CLK -clk => dtm[18]~reg0.CLK -clk => dtm[19]~reg0.CLK -clk => dtm[20]~reg0.CLK -clk => dtm[21]~reg0.CLK -clk => dtm[22]~reg0.CLK -clk => dtm[23]~reg0.CLK -clk => dtm[24]~reg0.CLK -clk => dtm[25]~reg0.CLK -clk => dtm[26]~reg0.CLK -clk => dtm[27]~reg0.CLK -clk => dtm[28]~reg0.CLK -clk => dtm[29]~reg0.CLK -clk => dtm[30]~reg0.CLK -clk => dtm[31]~reg0.CLK -clk => dtm[32]~reg0.CLK -clk => dtm[33]~reg0.CLK -clk => dtm[34]~reg0.CLK -clk => dtm[35]~reg0.CLK -clk => atm[0]~reg0.CLK -clk => atm[1]~reg0.CLK -clk => atm[2]~reg0.CLK -clk => atm[3]~reg0.CLK -clk => atm[4]~reg0.CLK -clk => atm[5]~reg0.CLK -clk => atm[6]~reg0.CLK -clk => atm[7]~reg0.CLK -clk => atm[8]~reg0.CLK -clk => atm[9]~reg0.CLK -clk => atm[10]~reg0.CLK -clk => atm[11]~reg0.CLK -clk => atm[12]~reg0.CLK -clk => atm[13]~reg0.CLK -clk => atm[14]~reg0.CLK -clk => atm[15]~reg0.CLK -clk => atm[16]~reg0.CLK -clk => atm[17]~reg0.CLK -clk => atm[18]~reg0.CLK -clk => atm[19]~reg0.CLK -clk => atm[20]~reg0.CLK -clk => atm[21]~reg0.CLK -clk => atm[22]~reg0.CLK -clk => atm[23]~reg0.CLK -clk => atm[24]~reg0.CLK -clk => atm[25]~reg0.CLK -clk => atm[26]~reg0.CLK -clk => atm[27]~reg0.CLK -clk => atm[28]~reg0.CLK -clk => atm[29]~reg0.CLK -clk => atm[30]~reg0.CLK -clk => atm[31]~reg0.CLK -clk => atm[32]~reg0.CLK -clk => atm[33]~reg0.CLK -clk => atm[34]~reg0.CLK -clk => atm[35]~reg0.CLK -cpu_d_address[0] => ~NO_FANOUT~ -cpu_d_address[1] => ~NO_FANOUT~ -cpu_d_address[2] => ~NO_FANOUT~ -cpu_d_address[3] => ~NO_FANOUT~ -cpu_d_address[4] => ~NO_FANOUT~ -cpu_d_address[5] => ~NO_FANOUT~ -cpu_d_address[6] => ~NO_FANOUT~ -cpu_d_address[7] => ~NO_FANOUT~ -cpu_d_address[8] => ~NO_FANOUT~ -cpu_d_address[9] => ~NO_FANOUT~ -cpu_d_address[10] => ~NO_FANOUT~ -cpu_d_address[11] => ~NO_FANOUT~ -cpu_d_address[12] => ~NO_FANOUT~ -cpu_d_address[13] => ~NO_FANOUT~ -cpu_d_address[14] => ~NO_FANOUT~ -cpu_d_address[15] => ~NO_FANOUT~ -cpu_d_address[16] => ~NO_FANOUT~ -cpu_d_address[17] => ~NO_FANOUT~ -cpu_d_address[18] => ~NO_FANOUT~ -cpu_d_read => ~NO_FANOUT~ -cpu_d_readdata[0] => ~NO_FANOUT~ -cpu_d_readdata[1] => ~NO_FANOUT~ -cpu_d_readdata[2] => ~NO_FANOUT~ -cpu_d_readdata[3] => ~NO_FANOUT~ -cpu_d_readdata[4] => ~NO_FANOUT~ -cpu_d_readdata[5] => ~NO_FANOUT~ -cpu_d_readdata[6] => ~NO_FANOUT~ -cpu_d_readdata[7] => ~NO_FANOUT~ -cpu_d_readdata[8] => ~NO_FANOUT~ -cpu_d_readdata[9] => ~NO_FANOUT~ -cpu_d_readdata[10] => ~NO_FANOUT~ -cpu_d_readdata[11] => ~NO_FANOUT~ -cpu_d_readdata[12] => ~NO_FANOUT~ -cpu_d_readdata[13] => ~NO_FANOUT~ -cpu_d_readdata[14] => ~NO_FANOUT~ -cpu_d_readdata[15] => ~NO_FANOUT~ -cpu_d_readdata[16] => ~NO_FANOUT~ -cpu_d_readdata[17] => ~NO_FANOUT~ -cpu_d_readdata[18] => ~NO_FANOUT~ -cpu_d_readdata[19] => ~NO_FANOUT~ -cpu_d_readdata[20] => ~NO_FANOUT~ -cpu_d_readdata[21] => ~NO_FANOUT~ -cpu_d_readdata[22] => ~NO_FANOUT~ -cpu_d_readdata[23] => ~NO_FANOUT~ -cpu_d_readdata[24] => ~NO_FANOUT~ -cpu_d_readdata[25] => ~NO_FANOUT~ -cpu_d_readdata[26] => ~NO_FANOUT~ -cpu_d_readdata[27] => ~NO_FANOUT~ -cpu_d_readdata[28] => ~NO_FANOUT~ -cpu_d_readdata[29] => ~NO_FANOUT~ -cpu_d_readdata[30] => ~NO_FANOUT~ -cpu_d_readdata[31] => ~NO_FANOUT~ -cpu_d_wait => ~NO_FANOUT~ -cpu_d_write => ~NO_FANOUT~ -cpu_d_writedata[0] => ~NO_FANOUT~ -cpu_d_writedata[1] => ~NO_FANOUT~ -cpu_d_writedata[2] => ~NO_FANOUT~ -cpu_d_writedata[3] => ~NO_FANOUT~ -cpu_d_writedata[4] => ~NO_FANOUT~ -cpu_d_writedata[5] => ~NO_FANOUT~ -cpu_d_writedata[6] => ~NO_FANOUT~ -cpu_d_writedata[7] => ~NO_FANOUT~ -cpu_d_writedata[8] => ~NO_FANOUT~ -cpu_d_writedata[9] => ~NO_FANOUT~ -cpu_d_writedata[10] => ~NO_FANOUT~ -cpu_d_writedata[11] => ~NO_FANOUT~ -cpu_d_writedata[12] => ~NO_FANOUT~ -cpu_d_writedata[13] => ~NO_FANOUT~ -cpu_d_writedata[14] => ~NO_FANOUT~ -cpu_d_writedata[15] => ~NO_FANOUT~ -cpu_d_writedata[16] => ~NO_FANOUT~ -cpu_d_writedata[17] => ~NO_FANOUT~ -cpu_d_writedata[18] => ~NO_FANOUT~ -cpu_d_writedata[19] => ~NO_FANOUT~ -cpu_d_writedata[20] => ~NO_FANOUT~ -cpu_d_writedata[21] => ~NO_FANOUT~ -cpu_d_writedata[22] => ~NO_FANOUT~ -cpu_d_writedata[23] => ~NO_FANOUT~ -cpu_d_writedata[24] => ~NO_FANOUT~ -cpu_d_writedata[25] => ~NO_FANOUT~ -cpu_d_writedata[26] => ~NO_FANOUT~ -cpu_d_writedata[27] => ~NO_FANOUT~ -cpu_d_writedata[28] => ~NO_FANOUT~ -cpu_d_writedata[29] => ~NO_FANOUT~ -cpu_d_writedata[30] => ~NO_FANOUT~ -cpu_d_writedata[31] => ~NO_FANOUT~ -jrst_n => dtm[0]~reg0.ACLR -jrst_n => dtm[1]~reg0.ACLR -jrst_n => dtm[2]~reg0.ACLR -jrst_n => dtm[3]~reg0.ACLR -jrst_n => dtm[4]~reg0.ACLR -jrst_n => dtm[5]~reg0.ACLR -jrst_n => dtm[6]~reg0.ACLR -jrst_n => dtm[7]~reg0.ACLR -jrst_n => dtm[8]~reg0.ACLR -jrst_n => dtm[9]~reg0.ACLR -jrst_n => dtm[10]~reg0.ACLR -jrst_n => dtm[11]~reg0.ACLR -jrst_n => dtm[12]~reg0.ACLR -jrst_n => dtm[13]~reg0.ACLR -jrst_n => dtm[14]~reg0.ACLR -jrst_n => dtm[15]~reg0.ACLR -jrst_n => dtm[16]~reg0.ACLR -jrst_n => dtm[17]~reg0.ACLR -jrst_n => dtm[18]~reg0.ACLR -jrst_n => dtm[19]~reg0.ACLR -jrst_n => dtm[20]~reg0.ACLR -jrst_n => dtm[21]~reg0.ACLR -jrst_n => dtm[22]~reg0.ACLR -jrst_n => dtm[23]~reg0.ACLR -jrst_n => dtm[24]~reg0.ACLR -jrst_n => dtm[25]~reg0.ACLR -jrst_n => dtm[26]~reg0.ACLR -jrst_n => dtm[27]~reg0.ACLR -jrst_n => dtm[28]~reg0.ACLR -jrst_n => dtm[29]~reg0.ACLR -jrst_n => dtm[30]~reg0.ACLR -jrst_n => dtm[31]~reg0.ACLR -jrst_n => dtm[32]~reg0.ACLR -jrst_n => dtm[33]~reg0.ACLR -jrst_n => dtm[34]~reg0.ACLR -jrst_n => dtm[35]~reg0.ACLR -jrst_n => atm[0]~reg0.ACLR -jrst_n => atm[1]~reg0.ACLR -jrst_n => atm[2]~reg0.ACLR -jrst_n => atm[3]~reg0.ACLR -jrst_n => atm[4]~reg0.ACLR -jrst_n => atm[5]~reg0.ACLR -jrst_n => atm[6]~reg0.ACLR -jrst_n => atm[7]~reg0.ACLR -jrst_n => atm[8]~reg0.ACLR -jrst_n => atm[9]~reg0.ACLR -jrst_n => atm[10]~reg0.ACLR -jrst_n => atm[11]~reg0.ACLR -jrst_n => atm[12]~reg0.ACLR -jrst_n => atm[13]~reg0.ACLR -jrst_n => atm[14]~reg0.ACLR -jrst_n => atm[15]~reg0.ACLR -jrst_n => atm[16]~reg0.ACLR -jrst_n => atm[17]~reg0.ACLR -jrst_n => atm[18]~reg0.ACLR -jrst_n => atm[19]~reg0.ACLR -jrst_n => atm[20]~reg0.ACLR -jrst_n => atm[21]~reg0.ACLR -jrst_n => atm[22]~reg0.ACLR -jrst_n => atm[23]~reg0.ACLR -jrst_n => atm[24]~reg0.ACLR -jrst_n => atm[25]~reg0.ACLR -jrst_n => atm[26]~reg0.ACLR -jrst_n => atm[27]~reg0.ACLR -jrst_n => atm[28]~reg0.ACLR -jrst_n => atm[29]~reg0.ACLR -jrst_n => atm[30]~reg0.ACLR -jrst_n => atm[31]~reg0.ACLR -jrst_n => atm[32]~reg0.ACLR -jrst_n => atm[33]~reg0.ACLR -jrst_n => atm[34]~reg0.ACLR -jrst_n => atm[35]~reg0.ACLR -trc_ctrl[0] => trc_ctrl[0].IN1 -trc_ctrl[1] => trc_ctrl[1].IN1 -trc_ctrl[2] => trc_ctrl[2].IN1 -trc_ctrl[3] => trc_ctrl[3].IN1 -trc_ctrl[4] => trc_ctrl[4].IN1 -trc_ctrl[5] => trc_ctrl[5].IN1 -trc_ctrl[6] => trc_ctrl[6].IN1 -trc_ctrl[7] => trc_ctrl[7].IN1 -trc_ctrl[8] => trc_ctrl[8].IN1 -trc_ctrl[9] => ~NO_FANOUT~ -trc_ctrl[10] => ~NO_FANOUT~ -trc_ctrl[11] => ~NO_FANOUT~ -trc_ctrl[12] => ~NO_FANOUT~ -trc_ctrl[13] => ~NO_FANOUT~ -trc_ctrl[14] => ~NO_FANOUT~ -trc_ctrl[15] => ~NO_FANOUT~ -atm[0] <= atm[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[1] <= atm[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[2] <= atm[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[3] <= atm[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[4] <= atm[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[5] <= atm[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[6] <= atm[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[7] <= atm[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[8] <= atm[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[9] <= atm[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[10] <= atm[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[11] <= atm[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[12] <= atm[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[13] <= atm[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[14] <= atm[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[15] <= atm[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[16] <= atm[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[17] <= atm[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[18] <= atm[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[19] <= atm[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[20] <= atm[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[21] <= atm[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[22] <= atm[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[23] <= atm[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[24] <= atm[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[25] <= atm[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[26] <= atm[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[27] <= atm[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[28] <= atm[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[29] <= atm[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[30] <= atm[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[31] <= atm[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[32] <= atm[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[33] <= atm[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[34] <= atm[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[35] <= atm[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[0] <= dtm[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[1] <= dtm[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[2] <= dtm[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[3] <= dtm[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[4] <= dtm[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[5] <= dtm[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[6] <= dtm[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[7] <= dtm[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[8] <= dtm[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[9] <= dtm[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[10] <= dtm[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[11] <= dtm[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[12] <= dtm[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[13] <= dtm[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[14] <= dtm[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[15] <= dtm[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[16] <= dtm[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[17] <= dtm[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[18] <= dtm[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[19] <= dtm[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[20] <= dtm[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[21] <= dtm[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[22] <= dtm[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[23] <= dtm[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[24] <= dtm[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[25] <= dtm[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[26] <= dtm[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[27] <= dtm[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[28] <= dtm[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[29] <= dtm[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[30] <= dtm[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[31] <= dtm[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[32] <= dtm[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[33] <= dtm[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[34] <= dtm[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[35] <= dtm[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace|nios_system_nios2_processor_nios2_oci_td_mode:nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode -ctrl[0] => ~NO_FANOUT~ -ctrl[1] => ~NO_FANOUT~ -ctrl[2] => ~NO_FANOUT~ -ctrl[3] => ~NO_FANOUT~ -ctrl[4] => ~NO_FANOUT~ -ctrl[5] => Decoder0.IN2 -ctrl[5] => td_mode[3].DATAIN -ctrl[6] => Decoder0.IN1 -ctrl[6] => Decoder1.IN1 -ctrl[6] => td_mode[2].DATAIN -ctrl[7] => Decoder0.IN0 -ctrl[7] => Decoder1.IN0 -ctrl[8] => ~NO_FANOUT~ -td_mode[0] <= Decoder1.DB_MAX_OUTPUT_PORT_TYPE -td_mode[1] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE -td_mode[2] <= ctrl[6].DB_MAX_OUTPUT_PORT_TYPE -td_mode[3] <= ctrl[5].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo -atm[0] => ~NO_FANOUT~ -atm[1] => ~NO_FANOUT~ -atm[2] => ~NO_FANOUT~ -atm[3] => ~NO_FANOUT~ -atm[4] => ~NO_FANOUT~ -atm[5] => ~NO_FANOUT~ -atm[6] => ~NO_FANOUT~ -atm[7] => ~NO_FANOUT~ -atm[8] => ~NO_FANOUT~ -atm[9] => ~NO_FANOUT~ -atm[10] => ~NO_FANOUT~ -atm[11] => ~NO_FANOUT~ -atm[12] => ~NO_FANOUT~ -atm[13] => ~NO_FANOUT~ -atm[14] => ~NO_FANOUT~ -atm[15] => ~NO_FANOUT~ -atm[16] => ~NO_FANOUT~ -atm[17] => ~NO_FANOUT~ -atm[18] => ~NO_FANOUT~ -atm[19] => ~NO_FANOUT~ -atm[20] => ~NO_FANOUT~ -atm[21] => ~NO_FANOUT~ -atm[22] => ~NO_FANOUT~ -atm[23] => ~NO_FANOUT~ -atm[24] => ~NO_FANOUT~ -atm[25] => ~NO_FANOUT~ -atm[26] => ~NO_FANOUT~ -atm[27] => ~NO_FANOUT~ -atm[28] => ~NO_FANOUT~ -atm[29] => ~NO_FANOUT~ -atm[30] => ~NO_FANOUT~ -atm[31] => ~NO_FANOUT~ -atm[32] => WideOr1.IN0 -atm[33] => WideOr1.IN1 -atm[34] => WideOr1.IN2 -atm[35] => WideOr1.IN3 -clk => fifocount[0].CLK -clk => fifocount[1].CLK -clk => fifocount[2].CLK -clk => fifocount[3].CLK -clk => fifocount[4].CLK -dbrk_traceme => trc_this.IN1 -dbrk_traceoff => trc_this.IN0 -dbrk_traceon => trc_this.IN1 -dct_buffer[0] => dct_buffer[0].IN1 -dct_buffer[1] => dct_buffer[1].IN1 -dct_buffer[2] => dct_buffer[2].IN1 -dct_buffer[3] => dct_buffer[3].IN1 -dct_buffer[4] => dct_buffer[4].IN1 -dct_buffer[5] => dct_buffer[5].IN1 -dct_buffer[6] => dct_buffer[6].IN1 -dct_buffer[7] => dct_buffer[7].IN1 -dct_buffer[8] => dct_buffer[8].IN1 -dct_buffer[9] => dct_buffer[9].IN1 -dct_buffer[10] => dct_buffer[10].IN1 -dct_buffer[11] => dct_buffer[11].IN1 -dct_buffer[12] => dct_buffer[12].IN1 -dct_buffer[13] => dct_buffer[13].IN1 -dct_buffer[14] => dct_buffer[14].IN1 -dct_buffer[15] => dct_buffer[15].IN1 -dct_buffer[16] => dct_buffer[16].IN1 -dct_buffer[17] => dct_buffer[17].IN1 -dct_buffer[18] => dct_buffer[18].IN1 -dct_buffer[19] => dct_buffer[19].IN1 -dct_buffer[20] => dct_buffer[20].IN1 -dct_buffer[21] => dct_buffer[21].IN1 -dct_buffer[22] => dct_buffer[22].IN1 -dct_buffer[23] => dct_buffer[23].IN1 -dct_buffer[24] => dct_buffer[24].IN1 -dct_buffer[25] => dct_buffer[25].IN1 -dct_buffer[26] => dct_buffer[26].IN1 -dct_buffer[27] => dct_buffer[27].IN1 -dct_buffer[28] => dct_buffer[28].IN1 -dct_buffer[29] => dct_buffer[29].IN1 -dct_count[0] => dct_count[0].IN1 -dct_count[1] => dct_count[1].IN1 -dct_count[2] => dct_count[2].IN1 -dct_count[3] => dct_count[3].IN1 -dtm[0] => ~NO_FANOUT~ -dtm[1] => ~NO_FANOUT~ -dtm[2] => ~NO_FANOUT~ -dtm[3] => ~NO_FANOUT~ -dtm[4] => ~NO_FANOUT~ -dtm[5] => ~NO_FANOUT~ -dtm[6] => ~NO_FANOUT~ -dtm[7] => ~NO_FANOUT~ -dtm[8] => ~NO_FANOUT~ -dtm[9] => ~NO_FANOUT~ -dtm[10] => ~NO_FANOUT~ -dtm[11] => ~NO_FANOUT~ -dtm[12] => ~NO_FANOUT~ -dtm[13] => ~NO_FANOUT~ -dtm[14] => ~NO_FANOUT~ -dtm[15] => ~NO_FANOUT~ -dtm[16] => ~NO_FANOUT~ -dtm[17] => ~NO_FANOUT~ -dtm[18] => ~NO_FANOUT~ -dtm[19] => ~NO_FANOUT~ -dtm[20] => ~NO_FANOUT~ -dtm[21] => ~NO_FANOUT~ -dtm[22] => ~NO_FANOUT~ -dtm[23] => ~NO_FANOUT~ -dtm[24] => ~NO_FANOUT~ -dtm[25] => ~NO_FANOUT~ -dtm[26] => ~NO_FANOUT~ -dtm[27] => ~NO_FANOUT~ -dtm[28] => ~NO_FANOUT~ -dtm[29] => ~NO_FANOUT~ -dtm[30] => ~NO_FANOUT~ -dtm[31] => ~NO_FANOUT~ -dtm[32] => WideOr2.IN0 -dtm[33] => WideOr2.IN1 -dtm[34] => WideOr2.IN2 -dtm[35] => WideOr2.IN3 -itm[0] => tw[0].DATAIN -itm[1] => tw[1].DATAIN -itm[2] => tw[2].DATAIN -itm[3] => tw[3].DATAIN -itm[4] => tw[4].DATAIN -itm[5] => tw[5].DATAIN -itm[6] => tw[6].DATAIN -itm[7] => tw[7].DATAIN -itm[8] => tw[8].DATAIN -itm[9] => tw[9].DATAIN -itm[10] => tw[10].DATAIN -itm[11] => tw[11].DATAIN -itm[12] => tw[12].DATAIN -itm[13] => tw[13].DATAIN -itm[14] => tw[14].DATAIN -itm[15] => tw[15].DATAIN -itm[16] => tw[16].DATAIN -itm[17] => tw[17].DATAIN -itm[18] => tw[18].DATAIN -itm[19] => tw[19].DATAIN -itm[20] => tw[20].DATAIN -itm[21] => tw[21].DATAIN -itm[22] => tw[22].DATAIN -itm[23] => tw[23].DATAIN -itm[24] => tw[24].DATAIN -itm[25] => tw[25].DATAIN -itm[26] => tw[26].DATAIN -itm[27] => tw[27].DATAIN -itm[28] => tw[28].DATAIN -itm[29] => tw[29].DATAIN -itm[30] => tw[30].DATAIN -itm[31] => tw[31].DATAIN -itm[32] => WideOr0.IN0 -itm[32] => tw[32].DATAIN -itm[33] => WideOr0.IN1 -itm[33] => tw[33].DATAIN -itm[34] => WideOr0.IN2 -itm[34] => tw[34].DATAIN -itm[35] => WideOr0.IN3 -itm[35] => tw[35].DATAIN -jrst_n => fifocount[0].ACLR -jrst_n => fifocount[1].ACLR -jrst_n => fifocount[2].ACLR -jrst_n => fifocount[3].ACLR -jrst_n => fifocount[4].ACLR -reset_n => ~NO_FANOUT~ -test_ending => test_ending.IN1 -test_has_ended => test_has_ended.IN1 -trc_on => trc_this.IN1 -tw[0] <= itm[0].DB_MAX_OUTPUT_PORT_TYPE -tw[1] <= itm[1].DB_MAX_OUTPUT_PORT_TYPE -tw[2] <= itm[2].DB_MAX_OUTPUT_PORT_TYPE -tw[3] <= itm[3].DB_MAX_OUTPUT_PORT_TYPE -tw[4] <= itm[4].DB_MAX_OUTPUT_PORT_TYPE -tw[5] <= itm[5].DB_MAX_OUTPUT_PORT_TYPE -tw[6] <= itm[6].DB_MAX_OUTPUT_PORT_TYPE -tw[7] <= itm[7].DB_MAX_OUTPUT_PORT_TYPE -tw[8] <= itm[8].DB_MAX_OUTPUT_PORT_TYPE -tw[9] <= itm[9].DB_MAX_OUTPUT_PORT_TYPE -tw[10] <= itm[10].DB_MAX_OUTPUT_PORT_TYPE -tw[11] <= itm[11].DB_MAX_OUTPUT_PORT_TYPE -tw[12] <= itm[12].DB_MAX_OUTPUT_PORT_TYPE -tw[13] <= itm[13].DB_MAX_OUTPUT_PORT_TYPE -tw[14] <= itm[14].DB_MAX_OUTPUT_PORT_TYPE -tw[15] <= itm[15].DB_MAX_OUTPUT_PORT_TYPE -tw[16] <= itm[16].DB_MAX_OUTPUT_PORT_TYPE -tw[17] <= itm[17].DB_MAX_OUTPUT_PORT_TYPE -tw[18] <= itm[18].DB_MAX_OUTPUT_PORT_TYPE -tw[19] <= itm[19].DB_MAX_OUTPUT_PORT_TYPE -tw[20] <= itm[20].DB_MAX_OUTPUT_PORT_TYPE -tw[21] <= itm[21].DB_MAX_OUTPUT_PORT_TYPE -tw[22] <= itm[22].DB_MAX_OUTPUT_PORT_TYPE -tw[23] <= itm[23].DB_MAX_OUTPUT_PORT_TYPE -tw[24] <= itm[24].DB_MAX_OUTPUT_PORT_TYPE -tw[25] <= itm[25].DB_MAX_OUTPUT_PORT_TYPE -tw[26] <= itm[26].DB_MAX_OUTPUT_PORT_TYPE -tw[27] <= itm[27].DB_MAX_OUTPUT_PORT_TYPE -tw[28] <= itm[28].DB_MAX_OUTPUT_PORT_TYPE -tw[29] <= itm[29].DB_MAX_OUTPUT_PORT_TYPE -tw[30] <= itm[30].DB_MAX_OUTPUT_PORT_TYPE -tw[31] <= itm[31].DB_MAX_OUTPUT_PORT_TYPE -tw[32] <= itm[32].DB_MAX_OUTPUT_PORT_TYPE -tw[33] <= itm[33].DB_MAX_OUTPUT_PORT_TYPE -tw[34] <= itm[34].DB_MAX_OUTPUT_PORT_TYPE -tw[35] <= itm[35].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_compute_tm_count:nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count -atm_valid => Decoder0.IN1 -dtm_valid => Decoder0.IN2 -itm_valid => Decoder0.IN0 -compute_tm_count[0] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE -compute_tm_count[1] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifowp_inc:nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp -free2 => always0.IN1 -free3 => always0.IN1 -tm_count[0] => LessThan0.IN4 -tm_count[0] => LessThan1.IN4 -tm_count[0] => Equal0.IN1 -tm_count[1] => LessThan0.IN3 -tm_count[1] => LessThan1.IN3 -tm_count[1] => Equal0.IN0 -fifowp_inc[0] <= fifowp_inc.DB_MAX_OUTPUT_PORT_TYPE -fifowp_inc[1] <= fifowp_inc.DB_MAX_OUTPUT_PORT_TYPE -fifowp_inc[2] <= -fifowp_inc[3] <= - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifocount_inc:nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount -empty => fifocount_inc.OUTPUTSELECT -empty => fifocount_inc.OUTPUTSELECT -empty => fifocount_inc.OUTPUTSELECT -empty => fifocount_inc.OUTPUTSELECT -empty => fifocount_inc.OUTPUTSELECT -free2 => always0.IN1 -free3 => always0.IN1 -tm_count[0] => LessThan0.IN4 -tm_count[0] => LessThan1.IN4 -tm_count[0] => fifocount_inc.DATAB -tm_count[0] => Equal0.IN1 -tm_count[1] => LessThan0.IN3 -tm_count[1] => LessThan1.IN3 -tm_count[1] => fifocount_inc.DATAB -tm_count[1] => Equal0.IN0 -fifocount_inc[0] <= fifocount_inc.DB_MAX_OUTPUT_PORT_TYPE -fifocount_inc[1] <= fifocount_inc.DB_MAX_OUTPUT_PORT_TYPE -fifocount_inc[2] <= fifocount_inc.DB_MAX_OUTPUT_PORT_TYPE -fifocount_inc[3] <= fifocount_inc.DB_MAX_OUTPUT_PORT_TYPE -fifocount_inc[4] <= fifocount_inc.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_oci_test_bench:the_nios_system_nios2_processor_oci_test_bench -dct_buffer[0] => ~NO_FANOUT~ -dct_buffer[1] => ~NO_FANOUT~ -dct_buffer[2] => ~NO_FANOUT~ -dct_buffer[3] => ~NO_FANOUT~ -dct_buffer[4] => ~NO_FANOUT~ -dct_buffer[5] => ~NO_FANOUT~ -dct_buffer[6] => ~NO_FANOUT~ -dct_buffer[7] => ~NO_FANOUT~ -dct_buffer[8] => ~NO_FANOUT~ -dct_buffer[9] => ~NO_FANOUT~ -dct_buffer[10] => ~NO_FANOUT~ -dct_buffer[11] => ~NO_FANOUT~ -dct_buffer[12] => ~NO_FANOUT~ -dct_buffer[13] => ~NO_FANOUT~ -dct_buffer[14] => ~NO_FANOUT~ -dct_buffer[15] => ~NO_FANOUT~ -dct_buffer[16] => ~NO_FANOUT~ -dct_buffer[17] => ~NO_FANOUT~ -dct_buffer[18] => ~NO_FANOUT~ -dct_buffer[19] => ~NO_FANOUT~ -dct_buffer[20] => ~NO_FANOUT~ -dct_buffer[21] => ~NO_FANOUT~ -dct_buffer[22] => ~NO_FANOUT~ -dct_buffer[23] => ~NO_FANOUT~ -dct_buffer[24] => ~NO_FANOUT~ -dct_buffer[25] => ~NO_FANOUT~ -dct_buffer[26] => ~NO_FANOUT~ -dct_buffer[27] => ~NO_FANOUT~ -dct_buffer[28] => ~NO_FANOUT~ -dct_buffer[29] => ~NO_FANOUT~ -dct_count[0] => ~NO_FANOUT~ -dct_count[1] => ~NO_FANOUT~ -dct_count[2] => ~NO_FANOUT~ -dct_count[3] => ~NO_FANOUT~ -test_ending => ~NO_FANOUT~ -test_has_ended => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_pib:the_nios_system_nios2_processor_nios2_oci_pib -clk => ~NO_FANOUT~ -clkx2 => ~NO_FANOUT~ -jrst_n => ~NO_FANOUT~ -tw[0] => ~NO_FANOUT~ -tw[1] => ~NO_FANOUT~ -tw[2] => ~NO_FANOUT~ -tw[3] => ~NO_FANOUT~ -tw[4] => ~NO_FANOUT~ -tw[5] => ~NO_FANOUT~ -tw[6] => ~NO_FANOUT~ -tw[7] => ~NO_FANOUT~ -tw[8] => ~NO_FANOUT~ -tw[9] => ~NO_FANOUT~ -tw[10] => ~NO_FANOUT~ -tw[11] => ~NO_FANOUT~ -tw[12] => ~NO_FANOUT~ -tw[13] => ~NO_FANOUT~ -tw[14] => ~NO_FANOUT~ -tw[15] => ~NO_FANOUT~ -tw[16] => ~NO_FANOUT~ -tw[17] => ~NO_FANOUT~ -tw[18] => ~NO_FANOUT~ -tw[19] => ~NO_FANOUT~ -tw[20] => ~NO_FANOUT~ -tw[21] => ~NO_FANOUT~ -tw[22] => ~NO_FANOUT~ -tw[23] => ~NO_FANOUT~ -tw[24] => ~NO_FANOUT~ -tw[25] => ~NO_FANOUT~ -tw[26] => ~NO_FANOUT~ -tw[27] => ~NO_FANOUT~ -tw[28] => ~NO_FANOUT~ -tw[29] => ~NO_FANOUT~ -tw[30] => ~NO_FANOUT~ -tw[31] => ~NO_FANOUT~ -tw[32] => ~NO_FANOUT~ -tw[33] => ~NO_FANOUT~ -tw[34] => ~NO_FANOUT~ -tw[35] => ~NO_FANOUT~ -tr_clk <= -tr_data[0] <= -tr_data[1] <= -tr_data[2] <= -tr_data[3] <= -tr_data[4] <= -tr_data[5] <= -tr_data[6] <= -tr_data[7] <= -tr_data[8] <= -tr_data[9] <= -tr_data[10] <= -tr_data[11] <= -tr_data[12] <= -tr_data[13] <= -tr_data[14] <= -tr_data[15] <= -tr_data[16] <= -tr_data[17] <= - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_im:the_nios_system_nios2_processor_nios2_oci_im -clk => trc_wrap~reg0.CLK -clk => trc_im_addr[0]~reg0.CLK -clk => trc_im_addr[1]~reg0.CLK -clk => trc_im_addr[2]~reg0.CLK -clk => trc_im_addr[3]~reg0.CLK -clk => trc_im_addr[4]~reg0.CLK -clk => trc_im_addr[5]~reg0.CLK -clk => trc_im_addr[6]~reg0.CLK -jdo[0] => ~NO_FANOUT~ -jdo[1] => ~NO_FANOUT~ -jdo[2] => ~NO_FANOUT~ -jdo[3] => ~NO_FANOUT~ -jdo[4] => ~NO_FANOUT~ -jdo[5] => ~NO_FANOUT~ -jdo[6] => ~NO_FANOUT~ -jdo[7] => ~NO_FANOUT~ -jdo[8] => ~NO_FANOUT~ -jdo[9] => ~NO_FANOUT~ -jdo[10] => ~NO_FANOUT~ -jdo[11] => ~NO_FANOUT~ -jdo[12] => ~NO_FANOUT~ -jdo[13] => ~NO_FANOUT~ -jdo[14] => ~NO_FANOUT~ -jdo[15] => ~NO_FANOUT~ -jdo[16] => ~NO_FANOUT~ -jdo[17] => ~NO_FANOUT~ -jdo[18] => ~NO_FANOUT~ -jdo[19] => ~NO_FANOUT~ -jdo[20] => ~NO_FANOUT~ -jdo[21] => ~NO_FANOUT~ -jdo[22] => ~NO_FANOUT~ -jdo[23] => ~NO_FANOUT~ -jdo[24] => ~NO_FANOUT~ -jdo[25] => ~NO_FANOUT~ -jdo[26] => ~NO_FANOUT~ -jdo[27] => ~NO_FANOUT~ -jdo[28] => ~NO_FANOUT~ -jdo[29] => ~NO_FANOUT~ -jdo[30] => ~NO_FANOUT~ -jdo[31] => ~NO_FANOUT~ -jdo[32] => ~NO_FANOUT~ -jdo[33] => ~NO_FANOUT~ -jdo[34] => ~NO_FANOUT~ -jdo[35] => ~NO_FANOUT~ -jdo[36] => ~NO_FANOUT~ -jdo[37] => ~NO_FANOUT~ -jrst_n => trc_wrap~reg0.ACLR -jrst_n => trc_im_addr[0]~reg0.ACLR -jrst_n => trc_im_addr[1]~reg0.ACLR -jrst_n => trc_im_addr[2]~reg0.ACLR -jrst_n => trc_im_addr[3]~reg0.ACLR -jrst_n => trc_im_addr[4]~reg0.ACLR -jrst_n => trc_im_addr[5]~reg0.ACLR -jrst_n => trc_im_addr[6]~reg0.ACLR -reset_n => ~NO_FANOUT~ -take_action_tracectrl => ~NO_FANOUT~ -take_action_tracemem_a => ~NO_FANOUT~ -take_action_tracemem_b => ~NO_FANOUT~ -take_no_action_tracemem_a => ~NO_FANOUT~ -trc_ctrl[0] => tracemem_on.DATAIN -trc_ctrl[0] => trc_enb.DATAIN -trc_ctrl[1] => ~NO_FANOUT~ -trc_ctrl[2] => ~NO_FANOUT~ -trc_ctrl[3] => ~NO_FANOUT~ -trc_ctrl[4] => ~NO_FANOUT~ -trc_ctrl[5] => ~NO_FANOUT~ -trc_ctrl[6] => ~NO_FANOUT~ -trc_ctrl[7] => ~NO_FANOUT~ -trc_ctrl[8] => ~NO_FANOUT~ -trc_ctrl[9] => ~NO_FANOUT~ -trc_ctrl[10] => xbrk_wrap_traceoff.IN1 -trc_ctrl[11] => ~NO_FANOUT~ -trc_ctrl[12] => ~NO_FANOUT~ -trc_ctrl[13] => ~NO_FANOUT~ -trc_ctrl[14] => ~NO_FANOUT~ -trc_ctrl[15] => ~NO_FANOUT~ -tw[0] => ~NO_FANOUT~ -tw[1] => ~NO_FANOUT~ -tw[2] => ~NO_FANOUT~ -tw[3] => ~NO_FANOUT~ -tw[4] => ~NO_FANOUT~ -tw[5] => ~NO_FANOUT~ -tw[6] => ~NO_FANOUT~ -tw[7] => ~NO_FANOUT~ -tw[8] => ~NO_FANOUT~ -tw[9] => ~NO_FANOUT~ -tw[10] => ~NO_FANOUT~ -tw[11] => ~NO_FANOUT~ -tw[12] => ~NO_FANOUT~ -tw[13] => ~NO_FANOUT~ -tw[14] => ~NO_FANOUT~ -tw[15] => ~NO_FANOUT~ -tw[16] => ~NO_FANOUT~ -tw[17] => ~NO_FANOUT~ -tw[18] => ~NO_FANOUT~ -tw[19] => ~NO_FANOUT~ -tw[20] => ~NO_FANOUT~ -tw[21] => ~NO_FANOUT~ -tw[22] => ~NO_FANOUT~ -tw[23] => ~NO_FANOUT~ -tw[24] => ~NO_FANOUT~ -tw[25] => ~NO_FANOUT~ -tw[26] => ~NO_FANOUT~ -tw[27] => ~NO_FANOUT~ -tw[28] => ~NO_FANOUT~ -tw[29] => ~NO_FANOUT~ -tw[30] => ~NO_FANOUT~ -tw[31] => ~NO_FANOUT~ -tw[32] => ~NO_FANOUT~ -tw[33] => ~NO_FANOUT~ -tw[34] => ~NO_FANOUT~ -tw[35] => ~NO_FANOUT~ -tracemem_on <= trc_ctrl[0].DB_MAX_OUTPUT_PORT_TYPE -tracemem_trcdata[0] <= -tracemem_trcdata[1] <= -tracemem_trcdata[2] <= -tracemem_trcdata[3] <= -tracemem_trcdata[4] <= -tracemem_trcdata[5] <= -tracemem_trcdata[6] <= -tracemem_trcdata[7] <= -tracemem_trcdata[8] <= -tracemem_trcdata[9] <= -tracemem_trcdata[10] <= -tracemem_trcdata[11] <= -tracemem_trcdata[12] <= -tracemem_trcdata[13] <= -tracemem_trcdata[14] <= -tracemem_trcdata[15] <= -tracemem_trcdata[16] <= -tracemem_trcdata[17] <= -tracemem_trcdata[18] <= -tracemem_trcdata[19] <= -tracemem_trcdata[20] <= -tracemem_trcdata[21] <= -tracemem_trcdata[22] <= -tracemem_trcdata[23] <= -tracemem_trcdata[24] <= -tracemem_trcdata[25] <= -tracemem_trcdata[26] <= -tracemem_trcdata[27] <= -tracemem_trcdata[28] <= -tracemem_trcdata[29] <= -tracemem_trcdata[30] <= -tracemem_trcdata[31] <= -tracemem_trcdata[32] <= -tracemem_trcdata[33] <= -tracemem_trcdata[34] <= -tracemem_trcdata[35] <= -tracemem_tw <= tracemem_tw.DB_MAX_OUTPUT_PORT_TYPE -trc_enb <= trc_ctrl[0].DB_MAX_OUTPUT_PORT_TYPE -trc_im_addr[0] <= trc_im_addr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -trc_im_addr[1] <= trc_im_addr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -trc_im_addr[2] <= trc_im_addr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -trc_im_addr[3] <= trc_im_addr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -trc_im_addr[4] <= trc_im_addr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -trc_im_addr[5] <= trc_im_addr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -trc_im_addr[6] <= trc_im_addr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -trc_wrap <= trc_wrap~reg0.DB_MAX_OUTPUT_PORT_TYPE -xbrk_wrap_traceoff <= xbrk_wrap_traceoff.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper -MonDReg[0] => MonDReg[0].IN1 -MonDReg[1] => MonDReg[1].IN1 -MonDReg[2] => MonDReg[2].IN1 -MonDReg[3] => MonDReg[3].IN1 -MonDReg[4] => MonDReg[4].IN1 -MonDReg[5] => MonDReg[5].IN1 -MonDReg[6] => MonDReg[6].IN1 -MonDReg[7] => MonDReg[7].IN1 -MonDReg[8] => MonDReg[8].IN1 -MonDReg[9] => MonDReg[9].IN1 -MonDReg[10] => MonDReg[10].IN1 -MonDReg[11] => MonDReg[11].IN1 -MonDReg[12] => MonDReg[12].IN1 -MonDReg[13] => MonDReg[13].IN1 -MonDReg[14] => MonDReg[14].IN1 -MonDReg[15] => MonDReg[15].IN1 -MonDReg[16] => MonDReg[16].IN1 -MonDReg[17] => MonDReg[17].IN1 -MonDReg[18] => MonDReg[18].IN1 -MonDReg[19] => MonDReg[19].IN1 -MonDReg[20] => MonDReg[20].IN1 -MonDReg[21] => MonDReg[21].IN1 -MonDReg[22] => MonDReg[22].IN1 -MonDReg[23] => MonDReg[23].IN1 -MonDReg[24] => MonDReg[24].IN1 -MonDReg[25] => MonDReg[25].IN1 -MonDReg[26] => MonDReg[26].IN1 -MonDReg[27] => MonDReg[27].IN1 -MonDReg[28] => MonDReg[28].IN1 -MonDReg[29] => MonDReg[29].IN1 -MonDReg[30] => MonDReg[30].IN1 -MonDReg[31] => MonDReg[31].IN1 -break_readreg[0] => break_readreg[0].IN1 -break_readreg[1] => break_readreg[1].IN1 -break_readreg[2] => break_readreg[2].IN1 -break_readreg[3] => break_readreg[3].IN1 -break_readreg[4] => break_readreg[4].IN1 -break_readreg[5] => break_readreg[5].IN1 -break_readreg[6] => break_readreg[6].IN1 -break_readreg[7] => break_readreg[7].IN1 -break_readreg[8] => break_readreg[8].IN1 -break_readreg[9] => break_readreg[9].IN1 -break_readreg[10] => break_readreg[10].IN1 -break_readreg[11] => break_readreg[11].IN1 -break_readreg[12] => break_readreg[12].IN1 -break_readreg[13] => break_readreg[13].IN1 -break_readreg[14] => break_readreg[14].IN1 -break_readreg[15] => break_readreg[15].IN1 -break_readreg[16] => break_readreg[16].IN1 -break_readreg[17] => break_readreg[17].IN1 -break_readreg[18] => break_readreg[18].IN1 -break_readreg[19] => break_readreg[19].IN1 -break_readreg[20] => break_readreg[20].IN1 -break_readreg[21] => break_readreg[21].IN1 -break_readreg[22] => break_readreg[22].IN1 -break_readreg[23] => break_readreg[23].IN1 -break_readreg[24] => break_readreg[24].IN1 -break_readreg[25] => break_readreg[25].IN1 -break_readreg[26] => break_readreg[26].IN1 -break_readreg[27] => break_readreg[27].IN1 -break_readreg[28] => break_readreg[28].IN1 -break_readreg[29] => break_readreg[29].IN1 -break_readreg[30] => break_readreg[30].IN1 -break_readreg[31] => break_readreg[31].IN1 -clk => clk.IN1 -dbrk_hit0_latch => dbrk_hit0_latch.IN1 -dbrk_hit1_latch => dbrk_hit1_latch.IN1 -dbrk_hit2_latch => dbrk_hit2_latch.IN1 -dbrk_hit3_latch => dbrk_hit3_latch.IN1 -debugack => debugack.IN1 -monitor_error => monitor_error.IN1 -monitor_ready => monitor_ready.IN1 -reset_n => reset_n.IN1 -resetlatch => resetlatch.IN1 -tracemem_on => tracemem_on.IN1 -tracemem_trcdata[0] => tracemem_trcdata[0].IN1 -tracemem_trcdata[1] => tracemem_trcdata[1].IN1 -tracemem_trcdata[2] => tracemem_trcdata[2].IN1 -tracemem_trcdata[3] => tracemem_trcdata[3].IN1 -tracemem_trcdata[4] => tracemem_trcdata[4].IN1 -tracemem_trcdata[5] => tracemem_trcdata[5].IN1 -tracemem_trcdata[6] => tracemem_trcdata[6].IN1 -tracemem_trcdata[7] => tracemem_trcdata[7].IN1 -tracemem_trcdata[8] => tracemem_trcdata[8].IN1 -tracemem_trcdata[9] => tracemem_trcdata[9].IN1 -tracemem_trcdata[10] => tracemem_trcdata[10].IN1 -tracemem_trcdata[11] => tracemem_trcdata[11].IN1 -tracemem_trcdata[12] => tracemem_trcdata[12].IN1 -tracemem_trcdata[13] => tracemem_trcdata[13].IN1 -tracemem_trcdata[14] => tracemem_trcdata[14].IN1 -tracemem_trcdata[15] => tracemem_trcdata[15].IN1 -tracemem_trcdata[16] => tracemem_trcdata[16].IN1 -tracemem_trcdata[17] => tracemem_trcdata[17].IN1 -tracemem_trcdata[18] => tracemem_trcdata[18].IN1 -tracemem_trcdata[19] => tracemem_trcdata[19].IN1 -tracemem_trcdata[20] => tracemem_trcdata[20].IN1 -tracemem_trcdata[21] => tracemem_trcdata[21].IN1 -tracemem_trcdata[22] => tracemem_trcdata[22].IN1 -tracemem_trcdata[23] => tracemem_trcdata[23].IN1 -tracemem_trcdata[24] => tracemem_trcdata[24].IN1 -tracemem_trcdata[25] => tracemem_trcdata[25].IN1 -tracemem_trcdata[26] => tracemem_trcdata[26].IN1 -tracemem_trcdata[27] => tracemem_trcdata[27].IN1 -tracemem_trcdata[28] => tracemem_trcdata[28].IN1 -tracemem_trcdata[29] => tracemem_trcdata[29].IN1 -tracemem_trcdata[30] => tracemem_trcdata[30].IN1 -tracemem_trcdata[31] => tracemem_trcdata[31].IN1 -tracemem_trcdata[32] => tracemem_trcdata[32].IN1 -tracemem_trcdata[33] => tracemem_trcdata[33].IN1 -tracemem_trcdata[34] => tracemem_trcdata[34].IN1 -tracemem_trcdata[35] => tracemem_trcdata[35].IN1 -tracemem_tw => tracemem_tw.IN1 -trc_im_addr[0] => trc_im_addr[0].IN1 -trc_im_addr[1] => trc_im_addr[1].IN1 -trc_im_addr[2] => trc_im_addr[2].IN1 -trc_im_addr[3] => trc_im_addr[3].IN1 -trc_im_addr[4] => trc_im_addr[4].IN1 -trc_im_addr[5] => trc_im_addr[5].IN1 -trc_im_addr[6] => trc_im_addr[6].IN1 -trc_on => trc_on.IN1 -trc_wrap => trc_wrap.IN1 -trigbrktype => trigbrktype.IN1 -trigger_state_1 => trigger_state_1.IN1 -jdo[0] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[1] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[2] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[3] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[4] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[5] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[6] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[7] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[8] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[9] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[10] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[11] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[12] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[13] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[14] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[15] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[16] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[17] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[18] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[19] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[20] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[21] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[22] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[23] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[24] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[25] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[26] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[27] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[28] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[29] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[30] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[31] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[32] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[33] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[34] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[35] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[36] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[37] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jrst_n <= nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck.jrst_n -st_ready_test_idle <= nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck.st_ready_test_idle -take_action_break_a <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_action_break_a -take_action_break_b <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_action_break_b -take_action_break_c <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_action_break_c -take_action_ocimem_a <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_action_ocimem_a -take_action_ocimem_b <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_action_ocimem_b -take_action_tracectrl <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_action_tracectrl -take_action_tracemem_a <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_action_tracemem_a -take_action_tracemem_b <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_action_tracemem_b -take_no_action_break_a <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_no_action_break_a -take_no_action_break_b <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_no_action_break_b -take_no_action_break_c <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_no_action_break_c -take_no_action_ocimem_a <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_no_action_ocimem_a -take_no_action_tracemem_a <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_no_action_tracemem_a - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck -MonDReg[0] => Mux36.IN0 -MonDReg[1] => Mux35.IN0 -MonDReg[2] => Mux34.IN0 -MonDReg[3] => Mux33.IN0 -MonDReg[4] => Mux32.IN0 -MonDReg[5] => Mux31.IN0 -MonDReg[6] => Mux30.IN0 -MonDReg[7] => Mux29.IN0 -MonDReg[8] => Mux28.IN1 -MonDReg[9] => Mux27.IN1 -MonDReg[10] => Mux26.IN1 -MonDReg[11] => Mux25.IN1 -MonDReg[12] => Mux24.IN1 -MonDReg[13] => Mux23.IN1 -MonDReg[14] => Mux22.IN1 -MonDReg[15] => Mux21.IN1 -MonDReg[16] => Mux20.IN1 -MonDReg[17] => Mux19.IN1 -MonDReg[18] => Mux18.IN1 -MonDReg[19] => Mux17.IN1 -MonDReg[20] => Mux16.IN1 -MonDReg[21] => Mux15.IN1 -MonDReg[22] => Mux14.IN1 -MonDReg[23] => Mux13.IN1 -MonDReg[24] => Mux12.IN1 -MonDReg[25] => Mux11.IN1 -MonDReg[26] => Mux10.IN1 -MonDReg[27] => Mux9.IN1 -MonDReg[28] => Mux8.IN1 -MonDReg[29] => Mux7.IN1 -MonDReg[30] => Mux6.IN1 -MonDReg[31] => Mux5.IN1 -break_readreg[0] => Mux36.IN1 -break_readreg[1] => Mux35.IN1 -break_readreg[2] => Mux34.IN1 -break_readreg[3] => Mux33.IN1 -break_readreg[4] => Mux32.IN1 -break_readreg[5] => Mux31.IN1 -break_readreg[6] => Mux30.IN1 -break_readreg[7] => Mux29.IN1 -break_readreg[8] => Mux28.IN2 -break_readreg[9] => Mux27.IN2 -break_readreg[10] => Mux26.IN2 -break_readreg[11] => Mux25.IN2 -break_readreg[12] => Mux24.IN2 -break_readreg[13] => Mux23.IN2 -break_readreg[14] => Mux22.IN2 -break_readreg[15] => Mux21.IN2 -break_readreg[16] => Mux20.IN2 -break_readreg[17] => Mux19.IN2 -break_readreg[18] => Mux18.IN2 -break_readreg[19] => Mux17.IN2 -break_readreg[20] => Mux16.IN2 -break_readreg[21] => Mux15.IN2 -break_readreg[22] => Mux14.IN2 -break_readreg[23] => Mux13.IN2 -break_readreg[24] => Mux12.IN2 -break_readreg[25] => Mux11.IN2 -break_readreg[26] => Mux10.IN2 -break_readreg[27] => Mux9.IN2 -break_readreg[28] => Mux8.IN2 -break_readreg[29] => Mux7.IN2 -break_readreg[30] => Mux6.IN2 -break_readreg[31] => Mux5.IN2 -dbrk_hit0_latch => Mux4.IN1 -dbrk_hit1_latch => Mux3.IN1 -dbrk_hit2_latch => Mux2.IN1 -dbrk_hit3_latch => Mux1.IN2 -debugack => debugack.IN1 -ir_in[0] => Mux0.IN3 -ir_in[0] => Mux1.IN4 -ir_in[0] => Mux2.IN3 -ir_in[0] => Mux3.IN3 -ir_in[0] => Mux4.IN3 -ir_in[0] => Mux5.IN4 -ir_in[0] => Mux6.IN4 -ir_in[0] => Mux7.IN4 -ir_in[0] => Mux8.IN4 -ir_in[0] => Mux9.IN4 -ir_in[0] => Mux10.IN4 -ir_in[0] => Mux11.IN4 -ir_in[0] => Mux12.IN4 -ir_in[0] => Mux13.IN4 -ir_in[0] => Mux14.IN4 -ir_in[0] => Mux15.IN4 -ir_in[0] => Mux16.IN4 -ir_in[0] => Mux17.IN4 -ir_in[0] => Mux18.IN4 -ir_in[0] => Mux19.IN4 -ir_in[0] => Mux20.IN4 -ir_in[0] => Mux21.IN4 -ir_in[0] => Mux22.IN4 -ir_in[0] => Mux23.IN4 -ir_in[0] => Mux24.IN4 -ir_in[0] => Mux25.IN4 -ir_in[0] => Mux26.IN4 -ir_in[0] => Mux27.IN4 -ir_in[0] => Mux28.IN4 -ir_in[0] => Mux29.IN3 -ir_in[0] => Mux30.IN3 -ir_in[0] => Mux31.IN3 -ir_in[0] => Mux32.IN3 -ir_in[0] => Mux33.IN3 -ir_in[0] => Mux34.IN3 -ir_in[0] => Mux35.IN3 -ir_in[0] => Mux36.IN3 -ir_in[0] => Mux37.IN1 -ir_in[0] => Decoder0.IN1 -ir_in[1] => Mux0.IN2 -ir_in[1] => Mux1.IN3 -ir_in[1] => Mux2.IN2 -ir_in[1] => Mux3.IN2 -ir_in[1] => Mux4.IN2 -ir_in[1] => Mux5.IN3 -ir_in[1] => Mux6.IN3 -ir_in[1] => Mux7.IN3 -ir_in[1] => Mux8.IN3 -ir_in[1] => Mux9.IN3 -ir_in[1] => Mux10.IN3 -ir_in[1] => Mux11.IN3 -ir_in[1] => Mux12.IN3 -ir_in[1] => Mux13.IN3 -ir_in[1] => Mux14.IN3 -ir_in[1] => Mux15.IN3 -ir_in[1] => Mux16.IN3 -ir_in[1] => Mux17.IN3 -ir_in[1] => Mux18.IN3 -ir_in[1] => Mux19.IN3 -ir_in[1] => Mux20.IN3 -ir_in[1] => Mux21.IN3 -ir_in[1] => Mux22.IN3 -ir_in[1] => Mux23.IN3 -ir_in[1] => Mux24.IN3 -ir_in[1] => Mux25.IN3 -ir_in[1] => Mux26.IN3 -ir_in[1] => Mux27.IN3 -ir_in[1] => Mux28.IN3 -ir_in[1] => Mux29.IN2 -ir_in[1] => Mux30.IN2 -ir_in[1] => Mux31.IN2 -ir_in[1] => Mux32.IN2 -ir_in[1] => Mux33.IN2 -ir_in[1] => Mux34.IN2 -ir_in[1] => Mux35.IN2 -ir_in[1] => Mux36.IN2 -ir_in[1] => Mux37.IN0 -ir_in[1] => Decoder0.IN0 -jtag_state_rti => st_ready_test_idle.DATAIN -monitor_error => Mux3.IN4 -monitor_ready => monitor_ready.IN1 -reset_n => ~NO_FANOUT~ -resetlatch => Mux4.IN4 -tck => tck.IN2 -tdi => sr.DATAB -tdi => sr.DATAB -tdi => sr.DATAB -tdi => sr.DATAB -tdi => sr.DATAB -tdi => sr.DATAB -tracemem_on => Mux1.IN5 -tracemem_trcdata[0] => Mux37.IN2 -tracemem_trcdata[1] => Mux36.IN4 -tracemem_trcdata[2] => Mux35.IN4 -tracemem_trcdata[3] => Mux34.IN4 -tracemem_trcdata[4] => Mux33.IN4 -tracemem_trcdata[5] => Mux32.IN4 -tracemem_trcdata[6] => Mux31.IN4 -tracemem_trcdata[7] => Mux30.IN4 -tracemem_trcdata[8] => Mux29.IN4 -tracemem_trcdata[9] => Mux28.IN5 -tracemem_trcdata[10] => Mux27.IN5 -tracemem_trcdata[11] => Mux26.IN5 -tracemem_trcdata[12] => Mux25.IN5 -tracemem_trcdata[13] => Mux24.IN5 -tracemem_trcdata[14] => Mux23.IN5 -tracemem_trcdata[15] => Mux22.IN5 -tracemem_trcdata[16] => Mux21.IN5 -tracemem_trcdata[17] => Mux20.IN5 -tracemem_trcdata[18] => Mux19.IN5 -tracemem_trcdata[19] => Mux18.IN5 -tracemem_trcdata[20] => Mux17.IN5 -tracemem_trcdata[21] => Mux16.IN5 -tracemem_trcdata[22] => Mux15.IN5 -tracemem_trcdata[23] => Mux14.IN5 -tracemem_trcdata[24] => Mux13.IN5 -tracemem_trcdata[25] => Mux12.IN5 -tracemem_trcdata[26] => Mux11.IN5 -tracemem_trcdata[27] => Mux10.IN5 -tracemem_trcdata[28] => Mux9.IN5 -tracemem_trcdata[29] => Mux8.IN5 -tracemem_trcdata[30] => Mux7.IN5 -tracemem_trcdata[31] => Mux6.IN5 -tracemem_trcdata[32] => Mux5.IN5 -tracemem_trcdata[33] => Mux4.IN5 -tracemem_trcdata[34] => Mux3.IN5 -tracemem_trcdata[35] => Mux2.IN4 -tracemem_tw => Mux0.IN4 -trc_im_addr[0] => Mux35.IN5 -trc_im_addr[1] => Mux34.IN5 -trc_im_addr[2] => Mux33.IN5 -trc_im_addr[3] => Mux32.IN5 -trc_im_addr[4] => Mux31.IN5 -trc_im_addr[5] => Mux30.IN5 -trc_im_addr[6] => Mux29.IN5 -trc_on => Mux37.IN3 -trc_wrap => Mux36.IN5 -trigbrktype => Mux37.IN4 -trigger_state_1 => Mux0.IN5 -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_uir => DRsize.OUTPUTSELECT -vs_uir => DRsize.OUTPUTSELECT -vs_uir => DRsize.OUTPUTSELECT -vs_uir => DRsize.OUTPUTSELECT -vs_uir => DRsize.OUTPUTSELECT -vs_uir => DRsize.OUTPUTSELECT -ir_out[0] <= ir_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -ir_out[1] <= ir_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jrst_n <= unxcomplemented_resetxx2.DB_MAX_OUTPUT_PORT_TYPE -sr[0] <= sr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[1] <= sr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[2] <= sr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[3] <= sr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[4] <= sr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[5] <= sr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[6] <= sr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[7] <= sr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[8] <= sr[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[9] <= sr[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[10] <= sr[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[11] <= sr[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[12] <= sr[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[13] <= sr[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[14] <= sr[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[15] <= sr[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[16] <= sr[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[17] <= sr[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[18] <= sr[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[19] <= sr[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[20] <= sr[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[21] <= sr[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[22] <= sr[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[23] <= sr[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[24] <= sr[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[25] <= sr[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[26] <= sr[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[27] <= sr[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[28] <= sr[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[29] <= sr[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[30] <= sr[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[31] <= sr[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[32] <= sr[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[33] <= sr[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[34] <= sr[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[35] <= sr[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[36] <= sr[36]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[37] <= sr[37]~reg0.DB_MAX_OUTPUT_PORT_TYPE -st_ready_test_idle <= jtag_state_rti.DB_MAX_OUTPUT_PORT_TYPE -tdo <= tdo.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 -clk => dreg[0].CLK -clk => din_s1.CLK -reset_n => dreg[0].ACLR -reset_n => din_s1.ACLR -din => din_s1.DATAIN -dout <= dout.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2 -clk => dreg[0].CLK -clk => din_s1.CLK -reset_n => dreg[0].ACLR -reset_n => din_s1.ACLR -din => din_s1.DATAIN -dout <= dout.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk -clk => clk.IN2 -ir_in[0] => ir[0].DATAIN -ir_in[1] => ir[1].DATAIN -sr[0] => jdo[0]~reg0.DATAIN -sr[1] => jdo[1]~reg0.DATAIN -sr[2] => jdo[2]~reg0.DATAIN -sr[3] => jdo[3]~reg0.DATAIN -sr[4] => jdo[4]~reg0.DATAIN -sr[5] => jdo[5]~reg0.DATAIN -sr[6] => jdo[6]~reg0.DATAIN -sr[7] => jdo[7]~reg0.DATAIN -sr[8] => jdo[8]~reg0.DATAIN -sr[9] => jdo[9]~reg0.DATAIN -sr[10] => jdo[10]~reg0.DATAIN -sr[11] => jdo[11]~reg0.DATAIN -sr[12] => jdo[12]~reg0.DATAIN -sr[13] => jdo[13]~reg0.DATAIN -sr[14] => jdo[14]~reg0.DATAIN -sr[15] => jdo[15]~reg0.DATAIN -sr[16] => jdo[16]~reg0.DATAIN -sr[17] => jdo[17]~reg0.DATAIN -sr[18] => jdo[18]~reg0.DATAIN -sr[19] => jdo[19]~reg0.DATAIN -sr[20] => jdo[20]~reg0.DATAIN -sr[21] => jdo[21]~reg0.DATAIN -sr[22] => jdo[22]~reg0.DATAIN -sr[23] => jdo[23]~reg0.DATAIN -sr[24] => jdo[24]~reg0.DATAIN -sr[25] => jdo[25]~reg0.DATAIN -sr[26] => jdo[26]~reg0.DATAIN -sr[27] => jdo[27]~reg0.DATAIN -sr[28] => jdo[28]~reg0.DATAIN -sr[29] => jdo[29]~reg0.DATAIN -sr[30] => jdo[30]~reg0.DATAIN -sr[31] => jdo[31]~reg0.DATAIN -sr[32] => jdo[32]~reg0.DATAIN -sr[33] => jdo[33]~reg0.DATAIN -sr[34] => jdo[34]~reg0.DATAIN -sr[35] => jdo[35]~reg0.DATAIN -sr[36] => jdo[36]~reg0.DATAIN -sr[37] => jdo[37]~reg0.DATAIN -vs_udr => vs_udr.IN1 -vs_uir => vs_uir.IN1 -jdo[0] <= jdo[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[1] <= jdo[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[2] <= jdo[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[3] <= jdo[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[4] <= jdo[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[5] <= jdo[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[6] <= jdo[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[7] <= jdo[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[8] <= jdo[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[9] <= jdo[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[10] <= jdo[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[11] <= jdo[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[12] <= jdo[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[13] <= jdo[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[14] <= jdo[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[15] <= jdo[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[16] <= jdo[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[17] <= jdo[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[18] <= jdo[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[19] <= jdo[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[20] <= jdo[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[21] <= jdo[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[22] <= jdo[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[23] <= jdo[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[24] <= jdo[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[25] <= jdo[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[26] <= jdo[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[27] <= jdo[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[28] <= jdo[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[29] <= jdo[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[30] <= jdo[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[31] <= jdo[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[32] <= jdo[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[33] <= jdo[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[34] <= jdo[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[35] <= jdo[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[36] <= jdo[36]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[37] <= jdo[37]~reg0.DB_MAX_OUTPUT_PORT_TYPE -take_action_break_a <= take_action_break_a.DB_MAX_OUTPUT_PORT_TYPE -take_action_break_b <= take_action_break_b.DB_MAX_OUTPUT_PORT_TYPE -take_action_break_c <= take_action_break_c.DB_MAX_OUTPUT_PORT_TYPE -take_action_ocimem_a <= take_action_ocimem_a.DB_MAX_OUTPUT_PORT_TYPE -take_action_ocimem_b <= take_action_ocimem_b.DB_MAX_OUTPUT_PORT_TYPE -take_action_tracectrl <= take_action_tracectrl.DB_MAX_OUTPUT_PORT_TYPE -take_action_tracemem_a <= take_action_tracemem_a.DB_MAX_OUTPUT_PORT_TYPE -take_action_tracemem_b <= take_action_tracemem_b.DB_MAX_OUTPUT_PORT_TYPE -take_no_action_break_a <= take_no_action_break_a.DB_MAX_OUTPUT_PORT_TYPE -take_no_action_break_b <= take_no_action_break_b.DB_MAX_OUTPUT_PORT_TYPE -take_no_action_break_c <= take_no_action_break_c.DB_MAX_OUTPUT_PORT_TYPE -take_no_action_ocimem_a <= take_no_action_ocimem_a.DB_MAX_OUTPUT_PORT_TYPE -take_no_action_tracemem_a <= take_no_action_tracemem_a.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 -clk => dreg[0].CLK -clk => din_s1.CLK -reset_n => dreg[0].ACLR -reset_n => din_s1.ACLR -din => din_s1.DATAIN -dout <= dout.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4 -clk => dreg[0].CLK -clk => din_s1.CLK -reset_n => dreg[0].ACLR -reset_n => din_s1.ACLR -din => din_s1.DATAIN -dout <= dout.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy -tck <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_tck -tdi <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_tdi -ir_in[0] <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_ir_in -ir_in[1] <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_ir_in -tdo => tdo.IN1 -ir_out[0] => ir_out[0].IN1 -ir_out[1] => ir_out[1].IN1 -virtual_state_cdr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_cdr -virtual_state_sdr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_sdr -virtual_state_e1dr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_e1dr -virtual_state_pdr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_pdr -virtual_state_e2dr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_e2dr -virtual_state_udr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_udr -virtual_state_cir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_cir -virtual_state_uir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_uir -tms <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_tms -jtag_state_tlr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_tlr -jtag_state_rti <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_rti -jtag_state_sdrs <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_sdrs -jtag_state_cdr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_cdr -jtag_state_sdr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_sdr -jtag_state_e1dr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_e1dr -jtag_state_pdr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_pdr -jtag_state_e2dr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_e2dr -jtag_state_udr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_udr -jtag_state_sirs <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_sirs -jtag_state_cir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_cir -jtag_state_sir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_sir -jtag_state_e1ir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_e1ir -jtag_state_pir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_pir -jtag_state_e2ir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_e2ir -jtag_state_uir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_uir - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst -usr_tck <= raw_tck.DB_MAX_OUTPUT_PORT_TYPE -usr_tdi <= tdi.DB_MAX_OUTPUT_PORT_TYPE -usr_ir_in[0] <= ir_in[0].DB_MAX_OUTPUT_PORT_TYPE -usr_ir_in[1] <= ir_in[1].DB_MAX_OUTPUT_PORT_TYPE -usr_tdo => tdo.DATAIN -usr_ir_out[0] => ir_out[0].DATAIN -usr_ir_out[1] => ir_out[1].DATAIN -usr_virtual_state_cdr <= virtual_state_cdr.DB_MAX_OUTPUT_PORT_TYPE -usr_virtual_state_sdr <= virtual_state_sdr.DB_MAX_OUTPUT_PORT_TYPE -usr_virtual_state_e1dr <= virtual_state_e1dr.DB_MAX_OUTPUT_PORT_TYPE -usr_virtual_state_pdr <= virtual_state_pdr.DB_MAX_OUTPUT_PORT_TYPE -usr_virtual_state_e2dr <= virtual_state_e2dr.DB_MAX_OUTPUT_PORT_TYPE -usr_virtual_state_udr <= virtual_state_udr.DB_MAX_OUTPUT_PORT_TYPE -usr_virtual_state_cir <= jtag_state_cdr.DB_MAX_OUTPUT_PORT_TYPE -usr_virtual_state_uir <= virtual_state_uir.DB_MAX_OUTPUT_PORT_TYPE -usr_tms <= raw_tms.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_tlr <= jtag_state_tlr.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_rti <= jtag_state_rti.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_sdrs <= jtag_state_sdrs.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_cdr <= jtag_state_cdr.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_sdr <= jtag_state_sdr.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_e1dr <= jtag_state_e1dr.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_pdr <= jtag_state_pdr.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_e2dr <= jtag_state_e2dr.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_udr <= jtag_state_udr.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_sirs <= jtag_state_sirs.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_cir <= jtag_state_cir.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_sir <= jtag_state_sir.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_e1ir <= jtag_state_e1ir.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_pir <= jtag_state_pir.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_e2ir <= jtag_state_e2ir.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_uir <= jtag_state_uir.DB_MAX_OUTPUT_PORT_TYPE -raw_tck => usr_tck.DATAIN -raw_tms => usr_tms.DATAIN -tdi => usr_tdi.DATAIN -jtag_state_tlr => usr_jtag_state_tlr.DATAIN -jtag_state_rti => usr_jtag_state_rti.DATAIN -jtag_state_sdrs => usr_jtag_state_sdrs.DATAIN -jtag_state_cdr => virtual_state_cdr.IN1 -jtag_state_cdr => usr_virtual_state_cir.DATAIN -jtag_state_cdr => usr_jtag_state_cdr.DATAIN -jtag_state_sdr => virtual_state_sdr.IN1 -jtag_state_sdr => usr_jtag_state_sdr.DATAIN -jtag_state_e1dr => virtual_state_e1dr.IN1 -jtag_state_e1dr => usr_jtag_state_e1dr.DATAIN -jtag_state_pdr => virtual_state_pdr.IN1 -jtag_state_pdr => usr_jtag_state_pdr.DATAIN -jtag_state_e2dr => virtual_state_e2dr.IN1 -jtag_state_e2dr => usr_jtag_state_e2dr.DATAIN -jtag_state_udr => virtual_state_udr.IN1 -jtag_state_udr => virtual_state_uir.IN1 -jtag_state_udr => usr_jtag_state_udr.DATAIN -jtag_state_sirs => usr_jtag_state_sirs.DATAIN -jtag_state_cir => usr_jtag_state_cir.DATAIN -jtag_state_sir => usr_jtag_state_sir.DATAIN -jtag_state_e1ir => usr_jtag_state_e1ir.DATAIN -jtag_state_pir => usr_jtag_state_pir.DATAIN -jtag_state_e2ir => usr_jtag_state_e2ir.DATAIN -jtag_state_uir => usr_jtag_state_uir.DATAIN -usr1 => virtual_ir_scan.IN0 -usr1 => virtual_dr_scan.IN0 -clr => ~NO_FANOUT~ -ena => virtual_dr_scan.IN1 -ena => virtual_ir_scan.IN1 -ir_in[0] => usr_ir_in[0].DATAIN -ir_in[1] => usr_ir_in[1].DATAIN -tdo <= usr_tdo.DB_MAX_OUTPUT_PORT_TYPE -ir_out[0] <= usr_ir_out[0].DB_MAX_OUTPUT_PORT_TYPE -ir_out[1] <= usr_ir_out[1].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory -address[0] => address[0].IN1 -address[1] => address[1].IN1 -address[2] => address[2].IN1 -address[3] => address[3].IN1 -address[4] => address[4].IN1 -address[5] => address[5].IN1 -address[6] => address[6].IN1 -address[7] => address[7].IN1 -address[8] => address[8].IN1 -address[9] => address[9].IN1 -address[10] => address[10].IN1 -address[11] => address[11].IN1 -address[12] => address[12].IN1 -address[13] => address[13].IN1 -address[14] => address[14].IN1 -address[15] => address[15].IN1 -byteenable[0] => byteenable[0].IN1 -byteenable[1] => byteenable[1].IN1 -byteenable[2] => byteenable[2].IN1 -byteenable[3] => byteenable[3].IN1 -chipselect => wren.IN0 -clk => clk.IN1 -clken => clocken0.IN0 -reset => ~NO_FANOUT~ -reset_req => clocken0.IN1 -write => wren.IN1 -writedata[0] => writedata[0].IN1 -writedata[1] => writedata[1].IN1 -writedata[2] => writedata[2].IN1 -writedata[3] => writedata[3].IN1 -writedata[4] => writedata[4].IN1 -writedata[5] => writedata[5].IN1 -writedata[6] => writedata[6].IN1 -writedata[7] => writedata[7].IN1 -writedata[8] => writedata[8].IN1 -writedata[9] => writedata[9].IN1 -writedata[10] => writedata[10].IN1 -writedata[11] => writedata[11].IN1 -writedata[12] => writedata[12].IN1 -writedata[13] => writedata[13].IN1 -writedata[14] => writedata[14].IN1 -writedata[15] => writedata[15].IN1 -writedata[16] => writedata[16].IN1 -writedata[17] => writedata[17].IN1 -writedata[18] => writedata[18].IN1 -writedata[19] => writedata[19].IN1 -writedata[20] => writedata[20].IN1 -writedata[21] => writedata[21].IN1 -writedata[22] => writedata[22].IN1 -writedata[23] => writedata[23].IN1 -writedata[24] => writedata[24].IN1 -writedata[25] => writedata[25].IN1 -writedata[26] => writedata[26].IN1 -writedata[27] => writedata[27].IN1 -writedata[28] => writedata[28].IN1 -writedata[29] => writedata[29].IN1 -writedata[30] => writedata[30].IN1 -writedata[31] => writedata[31].IN1 -readdata[0] <= altsyncram:the_altsyncram.q_a -readdata[1] <= altsyncram:the_altsyncram.q_a -readdata[2] <= altsyncram:the_altsyncram.q_a -readdata[3] <= altsyncram:the_altsyncram.q_a -readdata[4] <= altsyncram:the_altsyncram.q_a -readdata[5] <= altsyncram:the_altsyncram.q_a -readdata[6] <= altsyncram:the_altsyncram.q_a -readdata[7] <= altsyncram:the_altsyncram.q_a -readdata[8] <= altsyncram:the_altsyncram.q_a -readdata[9] <= altsyncram:the_altsyncram.q_a -readdata[10] <= altsyncram:the_altsyncram.q_a -readdata[11] <= altsyncram:the_altsyncram.q_a -readdata[12] <= altsyncram:the_altsyncram.q_a -readdata[13] <= altsyncram:the_altsyncram.q_a -readdata[14] <= altsyncram:the_altsyncram.q_a -readdata[15] <= altsyncram:the_altsyncram.q_a -readdata[16] <= altsyncram:the_altsyncram.q_a -readdata[17] <= altsyncram:the_altsyncram.q_a -readdata[18] <= altsyncram:the_altsyncram.q_a -readdata[19] <= altsyncram:the_altsyncram.q_a -readdata[20] <= altsyncram:the_altsyncram.q_a -readdata[21] <= altsyncram:the_altsyncram.q_a -readdata[22] <= altsyncram:the_altsyncram.q_a -readdata[23] <= altsyncram:the_altsyncram.q_a -readdata[24] <= altsyncram:the_altsyncram.q_a -readdata[25] <= altsyncram:the_altsyncram.q_a -readdata[26] <= altsyncram:the_altsyncram.q_a -readdata[27] <= altsyncram:the_altsyncram.q_a -readdata[28] <= altsyncram:the_altsyncram.q_a -readdata[29] <= altsyncram:the_altsyncram.q_a -readdata[30] <= altsyncram:the_altsyncram.q_a -readdata[31] <= altsyncram:the_altsyncram.q_a - - -|lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram -wren_a => altsyncram_4ed1:auto_generated.wren_a -rden_a => ~NO_FANOUT~ -wren_b => ~NO_FANOUT~ -rden_b => ~NO_FANOUT~ -data_a[0] => altsyncram_4ed1:auto_generated.data_a[0] -data_a[1] => altsyncram_4ed1:auto_generated.data_a[1] -data_a[2] => altsyncram_4ed1:auto_generated.data_a[2] -data_a[3] => altsyncram_4ed1:auto_generated.data_a[3] -data_a[4] => altsyncram_4ed1:auto_generated.data_a[4] -data_a[5] => altsyncram_4ed1:auto_generated.data_a[5] -data_a[6] => altsyncram_4ed1:auto_generated.data_a[6] -data_a[7] => altsyncram_4ed1:auto_generated.data_a[7] -data_a[8] => altsyncram_4ed1:auto_generated.data_a[8] -data_a[9] => altsyncram_4ed1:auto_generated.data_a[9] -data_a[10] => altsyncram_4ed1:auto_generated.data_a[10] -data_a[11] => altsyncram_4ed1:auto_generated.data_a[11] -data_a[12] => altsyncram_4ed1:auto_generated.data_a[12] -data_a[13] => altsyncram_4ed1:auto_generated.data_a[13] -data_a[14] => altsyncram_4ed1:auto_generated.data_a[14] -data_a[15] => altsyncram_4ed1:auto_generated.data_a[15] -data_a[16] => altsyncram_4ed1:auto_generated.data_a[16] -data_a[17] => altsyncram_4ed1:auto_generated.data_a[17] -data_a[18] => altsyncram_4ed1:auto_generated.data_a[18] -data_a[19] => altsyncram_4ed1:auto_generated.data_a[19] -data_a[20] => altsyncram_4ed1:auto_generated.data_a[20] -data_a[21] => altsyncram_4ed1:auto_generated.data_a[21] -data_a[22] => altsyncram_4ed1:auto_generated.data_a[22] -data_a[23] => altsyncram_4ed1:auto_generated.data_a[23] -data_a[24] => altsyncram_4ed1:auto_generated.data_a[24] -data_a[25] => altsyncram_4ed1:auto_generated.data_a[25] -data_a[26] => altsyncram_4ed1:auto_generated.data_a[26] -data_a[27] => altsyncram_4ed1:auto_generated.data_a[27] -data_a[28] => altsyncram_4ed1:auto_generated.data_a[28] -data_a[29] => altsyncram_4ed1:auto_generated.data_a[29] -data_a[30] => altsyncram_4ed1:auto_generated.data_a[30] -data_a[31] => altsyncram_4ed1:auto_generated.data_a[31] -data_b[0] => ~NO_FANOUT~ -address_a[0] => altsyncram_4ed1:auto_generated.address_a[0] -address_a[1] => altsyncram_4ed1:auto_generated.address_a[1] -address_a[2] => altsyncram_4ed1:auto_generated.address_a[2] -address_a[3] => altsyncram_4ed1:auto_generated.address_a[3] -address_a[4] => altsyncram_4ed1:auto_generated.address_a[4] -address_a[5] => altsyncram_4ed1:auto_generated.address_a[5] -address_a[6] => altsyncram_4ed1:auto_generated.address_a[6] -address_a[7] => altsyncram_4ed1:auto_generated.address_a[7] -address_a[8] => altsyncram_4ed1:auto_generated.address_a[8] -address_a[9] => altsyncram_4ed1:auto_generated.address_a[9] -address_a[10] => altsyncram_4ed1:auto_generated.address_a[10] -address_a[11] => altsyncram_4ed1:auto_generated.address_a[11] -address_a[12] => altsyncram_4ed1:auto_generated.address_a[12] -address_a[13] => altsyncram_4ed1:auto_generated.address_a[13] -address_a[14] => altsyncram_4ed1:auto_generated.address_a[14] -address_a[15] => altsyncram_4ed1:auto_generated.address_a[15] -address_b[0] => ~NO_FANOUT~ -addressstall_a => ~NO_FANOUT~ -addressstall_b => ~NO_FANOUT~ -clock0 => altsyncram_4ed1:auto_generated.clock0 -clock1 => ~NO_FANOUT~ -clocken0 => altsyncram_4ed1:auto_generated.clocken0 -clocken1 => ~NO_FANOUT~ -clocken2 => ~NO_FANOUT~ -clocken3 => ~NO_FANOUT~ -aclr0 => ~NO_FANOUT~ -aclr1 => ~NO_FANOUT~ -byteena_a[0] => altsyncram_4ed1:auto_generated.byteena_a[0] -byteena_a[1] => altsyncram_4ed1:auto_generated.byteena_a[1] -byteena_a[2] => altsyncram_4ed1:auto_generated.byteena_a[2] -byteena_a[3] => altsyncram_4ed1:auto_generated.byteena_a[3] -byteena_b[0] => ~NO_FANOUT~ -q_a[0] <= altsyncram_4ed1:auto_generated.q_a[0] -q_a[1] <= altsyncram_4ed1:auto_generated.q_a[1] -q_a[2] <= altsyncram_4ed1:auto_generated.q_a[2] -q_a[3] <= altsyncram_4ed1:auto_generated.q_a[3] -q_a[4] <= altsyncram_4ed1:auto_generated.q_a[4] -q_a[5] <= altsyncram_4ed1:auto_generated.q_a[5] -q_a[6] <= altsyncram_4ed1:auto_generated.q_a[6] -q_a[7] <= altsyncram_4ed1:auto_generated.q_a[7] -q_a[8] <= altsyncram_4ed1:auto_generated.q_a[8] -q_a[9] <= altsyncram_4ed1:auto_generated.q_a[9] -q_a[10] <= altsyncram_4ed1:auto_generated.q_a[10] -q_a[11] <= altsyncram_4ed1:auto_generated.q_a[11] -q_a[12] <= altsyncram_4ed1:auto_generated.q_a[12] -q_a[13] <= altsyncram_4ed1:auto_generated.q_a[13] -q_a[14] <= altsyncram_4ed1:auto_generated.q_a[14] -q_a[15] <= altsyncram_4ed1:auto_generated.q_a[15] -q_a[16] <= altsyncram_4ed1:auto_generated.q_a[16] -q_a[17] <= altsyncram_4ed1:auto_generated.q_a[17] -q_a[18] <= altsyncram_4ed1:auto_generated.q_a[18] -q_a[19] <= altsyncram_4ed1:auto_generated.q_a[19] -q_a[20] <= altsyncram_4ed1:auto_generated.q_a[20] -q_a[21] <= altsyncram_4ed1:auto_generated.q_a[21] -q_a[22] <= altsyncram_4ed1:auto_generated.q_a[22] -q_a[23] <= altsyncram_4ed1:auto_generated.q_a[23] -q_a[24] <= altsyncram_4ed1:auto_generated.q_a[24] -q_a[25] <= altsyncram_4ed1:auto_generated.q_a[25] -q_a[26] <= altsyncram_4ed1:auto_generated.q_a[26] -q_a[27] <= altsyncram_4ed1:auto_generated.q_a[27] -q_a[28] <= altsyncram_4ed1:auto_generated.q_a[28] -q_a[29] <= altsyncram_4ed1:auto_generated.q_a[29] -q_a[30] <= altsyncram_4ed1:auto_generated.q_a[30] -q_a[31] <= altsyncram_4ed1:auto_generated.q_a[31] -q_b[0] <= -eccstatus[0] <= -eccstatus[1] <= -eccstatus[2] <= - - -|lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated -address_a[0] => ram_block1a0.PORTAADDR -address_a[0] => ram_block1a1.PORTAADDR -address_a[0] => ram_block1a2.PORTAADDR -address_a[0] => ram_block1a3.PORTAADDR -address_a[0] => ram_block1a4.PORTAADDR -address_a[0] => ram_block1a5.PORTAADDR -address_a[0] => ram_block1a6.PORTAADDR -address_a[0] => ram_block1a7.PORTAADDR -address_a[0] => ram_block1a8.PORTAADDR -address_a[0] => ram_block1a9.PORTAADDR -address_a[0] => ram_block1a10.PORTAADDR -address_a[0] => ram_block1a11.PORTAADDR -address_a[0] => ram_block1a12.PORTAADDR -address_a[0] => ram_block1a13.PORTAADDR -address_a[0] => ram_block1a14.PORTAADDR -address_a[0] => ram_block1a15.PORTAADDR -address_a[0] => ram_block1a16.PORTAADDR -address_a[0] => ram_block1a17.PORTAADDR -address_a[0] => ram_block1a18.PORTAADDR -address_a[0] => ram_block1a19.PORTAADDR -address_a[0] => ram_block1a20.PORTAADDR -address_a[0] => ram_block1a21.PORTAADDR -address_a[0] => ram_block1a22.PORTAADDR -address_a[0] => ram_block1a23.PORTAADDR -address_a[0] => ram_block1a24.PORTAADDR -address_a[0] => ram_block1a25.PORTAADDR -address_a[0] => ram_block1a26.PORTAADDR -address_a[0] => ram_block1a27.PORTAADDR -address_a[0] => ram_block1a28.PORTAADDR -address_a[0] => ram_block1a29.PORTAADDR -address_a[0] => ram_block1a30.PORTAADDR -address_a[0] => ram_block1a31.PORTAADDR -address_a[0] => ram_block1a32.PORTAADDR -address_a[0] => ram_block1a33.PORTAADDR -address_a[0] => ram_block1a34.PORTAADDR -address_a[0] => ram_block1a35.PORTAADDR -address_a[0] => ram_block1a36.PORTAADDR -address_a[0] => ram_block1a37.PORTAADDR -address_a[0] => ram_block1a38.PORTAADDR -address_a[0] => ram_block1a39.PORTAADDR -address_a[0] => ram_block1a40.PORTAADDR -address_a[0] => ram_block1a41.PORTAADDR -address_a[0] => ram_block1a42.PORTAADDR -address_a[0] => ram_block1a43.PORTAADDR -address_a[0] => ram_block1a44.PORTAADDR -address_a[0] => ram_block1a45.PORTAADDR -address_a[0] => ram_block1a46.PORTAADDR -address_a[0] => ram_block1a47.PORTAADDR -address_a[0] => ram_block1a48.PORTAADDR -address_a[0] => ram_block1a49.PORTAADDR -address_a[0] => ram_block1a50.PORTAADDR -address_a[0] => ram_block1a51.PORTAADDR -address_a[0] => ram_block1a52.PORTAADDR -address_a[0] => ram_block1a53.PORTAADDR -address_a[0] => ram_block1a54.PORTAADDR -address_a[0] => ram_block1a55.PORTAADDR -address_a[0] => ram_block1a56.PORTAADDR -address_a[0] => ram_block1a57.PORTAADDR -address_a[0] => ram_block1a58.PORTAADDR -address_a[0] => ram_block1a59.PORTAADDR -address_a[0] => ram_block1a60.PORTAADDR -address_a[0] => ram_block1a61.PORTAADDR -address_a[0] => ram_block1a62.PORTAADDR -address_a[0] => ram_block1a63.PORTAADDR -address_a[0] => ram_block1a64.PORTAADDR -address_a[0] => ram_block1a65.PORTAADDR -address_a[0] => ram_block1a66.PORTAADDR -address_a[0] => ram_block1a67.PORTAADDR -address_a[0] => ram_block1a68.PORTAADDR -address_a[0] => ram_block1a69.PORTAADDR -address_a[0] => ram_block1a70.PORTAADDR -address_a[0] => ram_block1a71.PORTAADDR -address_a[0] => ram_block1a72.PORTAADDR -address_a[0] => ram_block1a73.PORTAADDR -address_a[0] => ram_block1a74.PORTAADDR -address_a[0] => ram_block1a75.PORTAADDR -address_a[0] => ram_block1a76.PORTAADDR -address_a[0] => ram_block1a77.PORTAADDR -address_a[0] => ram_block1a78.PORTAADDR -address_a[0] => ram_block1a79.PORTAADDR -address_a[0] => ram_block1a80.PORTAADDR -address_a[0] => ram_block1a81.PORTAADDR -address_a[0] => ram_block1a82.PORTAADDR -address_a[0] => ram_block1a83.PORTAADDR -address_a[0] => ram_block1a84.PORTAADDR -address_a[0] => ram_block1a85.PORTAADDR -address_a[0] => ram_block1a86.PORTAADDR -address_a[0] => ram_block1a87.PORTAADDR -address_a[0] => ram_block1a88.PORTAADDR -address_a[0] => ram_block1a89.PORTAADDR -address_a[0] => ram_block1a90.PORTAADDR -address_a[0] => ram_block1a91.PORTAADDR -address_a[0] => ram_block1a92.PORTAADDR -address_a[0] => ram_block1a93.PORTAADDR -address_a[0] => ram_block1a94.PORTAADDR -address_a[0] => ram_block1a95.PORTAADDR -address_a[0] => ram_block1a96.PORTAADDR -address_a[0] => ram_block1a97.PORTAADDR -address_a[0] => ram_block1a98.PORTAADDR -address_a[0] => ram_block1a99.PORTAADDR -address_a[0] => ram_block1a100.PORTAADDR -address_a[0] => ram_block1a101.PORTAADDR -address_a[0] => ram_block1a102.PORTAADDR -address_a[0] => ram_block1a103.PORTAADDR -address_a[0] => ram_block1a104.PORTAADDR -address_a[0] => ram_block1a105.PORTAADDR -address_a[0] => ram_block1a106.PORTAADDR -address_a[0] => ram_block1a107.PORTAADDR -address_a[0] => ram_block1a108.PORTAADDR -address_a[0] => ram_block1a109.PORTAADDR -address_a[0] => ram_block1a110.PORTAADDR -address_a[0] => ram_block1a111.PORTAADDR -address_a[0] => ram_block1a112.PORTAADDR -address_a[0] => ram_block1a113.PORTAADDR -address_a[0] => ram_block1a114.PORTAADDR -address_a[0] => ram_block1a115.PORTAADDR -address_a[0] => ram_block1a116.PORTAADDR -address_a[0] => ram_block1a117.PORTAADDR -address_a[0] => ram_block1a118.PORTAADDR -address_a[0] => ram_block1a119.PORTAADDR -address_a[0] => ram_block1a120.PORTAADDR -address_a[0] => ram_block1a121.PORTAADDR -address_a[0] => ram_block1a122.PORTAADDR -address_a[0] => ram_block1a123.PORTAADDR -address_a[0] => ram_block1a124.PORTAADDR -address_a[0] => ram_block1a125.PORTAADDR -address_a[0] => ram_block1a126.PORTAADDR -address_a[0] => ram_block1a127.PORTAADDR -address_a[0] => ram_block1a128.PORTAADDR -address_a[0] => ram_block1a129.PORTAADDR -address_a[0] => ram_block1a130.PORTAADDR -address_a[0] => ram_block1a131.PORTAADDR -address_a[0] => ram_block1a132.PORTAADDR -address_a[0] => ram_block1a133.PORTAADDR -address_a[0] => ram_block1a134.PORTAADDR -address_a[0] => ram_block1a135.PORTAADDR -address_a[0] => ram_block1a136.PORTAADDR -address_a[0] => ram_block1a137.PORTAADDR -address_a[0] => ram_block1a138.PORTAADDR -address_a[0] => ram_block1a139.PORTAADDR -address_a[0] => ram_block1a140.PORTAADDR -address_a[0] => ram_block1a141.PORTAADDR -address_a[0] => ram_block1a142.PORTAADDR -address_a[0] => ram_block1a143.PORTAADDR -address_a[0] => ram_block1a144.PORTAADDR -address_a[0] => ram_block1a145.PORTAADDR -address_a[0] => ram_block1a146.PORTAADDR -address_a[0] => ram_block1a147.PORTAADDR -address_a[0] => ram_block1a148.PORTAADDR -address_a[0] => ram_block1a149.PORTAADDR -address_a[0] => ram_block1a150.PORTAADDR -address_a[0] => ram_block1a151.PORTAADDR -address_a[0] => ram_block1a152.PORTAADDR -address_a[0] => ram_block1a153.PORTAADDR -address_a[0] => ram_block1a154.PORTAADDR -address_a[0] => ram_block1a155.PORTAADDR -address_a[0] => ram_block1a156.PORTAADDR -address_a[0] => ram_block1a157.PORTAADDR -address_a[0] => ram_block1a158.PORTAADDR -address_a[0] => ram_block1a159.PORTAADDR -address_a[0] => ram_block1a160.PORTAADDR -address_a[0] => ram_block1a161.PORTAADDR -address_a[0] => ram_block1a162.PORTAADDR -address_a[0] => ram_block1a163.PORTAADDR -address_a[0] => ram_block1a164.PORTAADDR -address_a[0] => ram_block1a165.PORTAADDR -address_a[0] => ram_block1a166.PORTAADDR -address_a[0] => ram_block1a167.PORTAADDR -address_a[0] => ram_block1a168.PORTAADDR -address_a[0] => ram_block1a169.PORTAADDR -address_a[0] => ram_block1a170.PORTAADDR -address_a[0] => ram_block1a171.PORTAADDR -address_a[0] => ram_block1a172.PORTAADDR -address_a[0] => ram_block1a173.PORTAADDR -address_a[0] => ram_block1a174.PORTAADDR -address_a[0] => ram_block1a175.PORTAADDR -address_a[0] => ram_block1a176.PORTAADDR -address_a[0] => ram_block1a177.PORTAADDR -address_a[0] => ram_block1a178.PORTAADDR -address_a[0] => ram_block1a179.PORTAADDR -address_a[0] => ram_block1a180.PORTAADDR -address_a[0] => ram_block1a181.PORTAADDR -address_a[0] => ram_block1a182.PORTAADDR -address_a[0] => ram_block1a183.PORTAADDR -address_a[0] => ram_block1a184.PORTAADDR -address_a[0] => ram_block1a185.PORTAADDR -address_a[0] => ram_block1a186.PORTAADDR -address_a[0] => ram_block1a187.PORTAADDR -address_a[0] => ram_block1a188.PORTAADDR -address_a[0] => ram_block1a189.PORTAADDR -address_a[0] => ram_block1a190.PORTAADDR -address_a[0] => ram_block1a191.PORTAADDR -address_a[0] => ram_block1a192.PORTAADDR -address_a[0] => ram_block1a193.PORTAADDR -address_a[0] => ram_block1a194.PORTAADDR -address_a[0] => ram_block1a195.PORTAADDR -address_a[0] => ram_block1a196.PORTAADDR -address_a[0] => ram_block1a197.PORTAADDR -address_a[0] => ram_block1a198.PORTAADDR -address_a[0] => ram_block1a199.PORTAADDR -address_a[0] => ram_block1a200.PORTAADDR -address_a[0] => ram_block1a201.PORTAADDR -address_a[0] => ram_block1a202.PORTAADDR -address_a[0] => ram_block1a203.PORTAADDR -address_a[0] => ram_block1a204.PORTAADDR -address_a[0] => ram_block1a205.PORTAADDR -address_a[0] => ram_block1a206.PORTAADDR -address_a[0] => ram_block1a207.PORTAADDR -address_a[0] => ram_block1a208.PORTAADDR -address_a[0] => ram_block1a209.PORTAADDR -address_a[0] => ram_block1a210.PORTAADDR -address_a[0] => ram_block1a211.PORTAADDR -address_a[0] => ram_block1a212.PORTAADDR -address_a[0] => ram_block1a213.PORTAADDR -address_a[0] => ram_block1a214.PORTAADDR -address_a[0] => ram_block1a215.PORTAADDR -address_a[0] => ram_block1a216.PORTAADDR -address_a[0] => ram_block1a217.PORTAADDR -address_a[0] => ram_block1a218.PORTAADDR -address_a[0] => ram_block1a219.PORTAADDR -address_a[0] => ram_block1a220.PORTAADDR -address_a[0] => ram_block1a221.PORTAADDR -address_a[0] => ram_block1a222.PORTAADDR -address_a[0] => ram_block1a223.PORTAADDR -address_a[1] => ram_block1a0.PORTAADDR1 -address_a[1] => ram_block1a1.PORTAADDR1 -address_a[1] => ram_block1a2.PORTAADDR1 -address_a[1] => ram_block1a3.PORTAADDR1 -address_a[1] => ram_block1a4.PORTAADDR1 -address_a[1] => ram_block1a5.PORTAADDR1 -address_a[1] => ram_block1a6.PORTAADDR1 -address_a[1] => ram_block1a7.PORTAADDR1 -address_a[1] => ram_block1a8.PORTAADDR1 -address_a[1] => ram_block1a9.PORTAADDR1 -address_a[1] => ram_block1a10.PORTAADDR1 -address_a[1] => ram_block1a11.PORTAADDR1 -address_a[1] => ram_block1a12.PORTAADDR1 -address_a[1] => ram_block1a13.PORTAADDR1 -address_a[1] => ram_block1a14.PORTAADDR1 -address_a[1] => ram_block1a15.PORTAADDR1 -address_a[1] => ram_block1a16.PORTAADDR1 -address_a[1] => ram_block1a17.PORTAADDR1 -address_a[1] => ram_block1a18.PORTAADDR1 -address_a[1] => ram_block1a19.PORTAADDR1 -address_a[1] => ram_block1a20.PORTAADDR1 -address_a[1] => ram_block1a21.PORTAADDR1 -address_a[1] => ram_block1a22.PORTAADDR1 -address_a[1] => ram_block1a23.PORTAADDR1 -address_a[1] => ram_block1a24.PORTAADDR1 -address_a[1] => ram_block1a25.PORTAADDR1 -address_a[1] => ram_block1a26.PORTAADDR1 -address_a[1] => ram_block1a27.PORTAADDR1 -address_a[1] => ram_block1a28.PORTAADDR1 -address_a[1] => ram_block1a29.PORTAADDR1 -address_a[1] => ram_block1a30.PORTAADDR1 -address_a[1] => ram_block1a31.PORTAADDR1 -address_a[1] => ram_block1a32.PORTAADDR1 -address_a[1] => ram_block1a33.PORTAADDR1 -address_a[1] => ram_block1a34.PORTAADDR1 -address_a[1] => ram_block1a35.PORTAADDR1 -address_a[1] => ram_block1a36.PORTAADDR1 -address_a[1] => ram_block1a37.PORTAADDR1 -address_a[1] => ram_block1a38.PORTAADDR1 -address_a[1] => ram_block1a39.PORTAADDR1 -address_a[1] => ram_block1a40.PORTAADDR1 -address_a[1] => ram_block1a41.PORTAADDR1 -address_a[1] => ram_block1a42.PORTAADDR1 -address_a[1] => ram_block1a43.PORTAADDR1 -address_a[1] => ram_block1a44.PORTAADDR1 -address_a[1] => ram_block1a45.PORTAADDR1 -address_a[1] => ram_block1a46.PORTAADDR1 -address_a[1] => ram_block1a47.PORTAADDR1 -address_a[1] => ram_block1a48.PORTAADDR1 -address_a[1] => ram_block1a49.PORTAADDR1 -address_a[1] => ram_block1a50.PORTAADDR1 -address_a[1] => ram_block1a51.PORTAADDR1 -address_a[1] => ram_block1a52.PORTAADDR1 -address_a[1] => ram_block1a53.PORTAADDR1 -address_a[1] => ram_block1a54.PORTAADDR1 -address_a[1] => ram_block1a55.PORTAADDR1 -address_a[1] => ram_block1a56.PORTAADDR1 -address_a[1] => ram_block1a57.PORTAADDR1 -address_a[1] => ram_block1a58.PORTAADDR1 -address_a[1] => ram_block1a59.PORTAADDR1 -address_a[1] => ram_block1a60.PORTAADDR1 -address_a[1] => ram_block1a61.PORTAADDR1 -address_a[1] => ram_block1a62.PORTAADDR1 -address_a[1] => ram_block1a63.PORTAADDR1 -address_a[1] => ram_block1a64.PORTAADDR1 -address_a[1] => ram_block1a65.PORTAADDR1 -address_a[1] => ram_block1a66.PORTAADDR1 -address_a[1] => ram_block1a67.PORTAADDR1 -address_a[1] => ram_block1a68.PORTAADDR1 -address_a[1] => ram_block1a69.PORTAADDR1 -address_a[1] => ram_block1a70.PORTAADDR1 -address_a[1] => ram_block1a71.PORTAADDR1 -address_a[1] => ram_block1a72.PORTAADDR1 -address_a[1] => ram_block1a73.PORTAADDR1 -address_a[1] => ram_block1a74.PORTAADDR1 -address_a[1] => ram_block1a75.PORTAADDR1 -address_a[1] => ram_block1a76.PORTAADDR1 -address_a[1] => ram_block1a77.PORTAADDR1 -address_a[1] => ram_block1a78.PORTAADDR1 -address_a[1] => ram_block1a79.PORTAADDR1 -address_a[1] => ram_block1a80.PORTAADDR1 -address_a[1] => ram_block1a81.PORTAADDR1 -address_a[1] => ram_block1a82.PORTAADDR1 -address_a[1] => ram_block1a83.PORTAADDR1 -address_a[1] => ram_block1a84.PORTAADDR1 -address_a[1] => ram_block1a85.PORTAADDR1 -address_a[1] => ram_block1a86.PORTAADDR1 -address_a[1] => ram_block1a87.PORTAADDR1 -address_a[1] => ram_block1a88.PORTAADDR1 -address_a[1] => ram_block1a89.PORTAADDR1 -address_a[1] => ram_block1a90.PORTAADDR1 -address_a[1] => ram_block1a91.PORTAADDR1 -address_a[1] => ram_block1a92.PORTAADDR1 -address_a[1] => ram_block1a93.PORTAADDR1 -address_a[1] => ram_block1a94.PORTAADDR1 -address_a[1] => ram_block1a95.PORTAADDR1 -address_a[1] => ram_block1a96.PORTAADDR1 -address_a[1] => ram_block1a97.PORTAADDR1 -address_a[1] => ram_block1a98.PORTAADDR1 -address_a[1] => ram_block1a99.PORTAADDR1 -address_a[1] => ram_block1a100.PORTAADDR1 -address_a[1] => ram_block1a101.PORTAADDR1 -address_a[1] => ram_block1a102.PORTAADDR1 -address_a[1] => ram_block1a103.PORTAADDR1 -address_a[1] => ram_block1a104.PORTAADDR1 -address_a[1] => ram_block1a105.PORTAADDR1 -address_a[1] => ram_block1a106.PORTAADDR1 -address_a[1] => ram_block1a107.PORTAADDR1 -address_a[1] => ram_block1a108.PORTAADDR1 -address_a[1] => ram_block1a109.PORTAADDR1 -address_a[1] => ram_block1a110.PORTAADDR1 -address_a[1] => ram_block1a111.PORTAADDR1 -address_a[1] => ram_block1a112.PORTAADDR1 -address_a[1] => ram_block1a113.PORTAADDR1 -address_a[1] => ram_block1a114.PORTAADDR1 -address_a[1] => ram_block1a115.PORTAADDR1 -address_a[1] => ram_block1a116.PORTAADDR1 -address_a[1] => ram_block1a117.PORTAADDR1 -address_a[1] => ram_block1a118.PORTAADDR1 -address_a[1] => ram_block1a119.PORTAADDR1 -address_a[1] => ram_block1a120.PORTAADDR1 -address_a[1] => ram_block1a121.PORTAADDR1 -address_a[1] => ram_block1a122.PORTAADDR1 -address_a[1] => ram_block1a123.PORTAADDR1 -address_a[1] => ram_block1a124.PORTAADDR1 -address_a[1] => ram_block1a125.PORTAADDR1 -address_a[1] => ram_block1a126.PORTAADDR1 -address_a[1] => ram_block1a127.PORTAADDR1 -address_a[1] => ram_block1a128.PORTAADDR1 -address_a[1] => ram_block1a129.PORTAADDR1 -address_a[1] => ram_block1a130.PORTAADDR1 -address_a[1] => ram_block1a131.PORTAADDR1 -address_a[1] => ram_block1a132.PORTAADDR1 -address_a[1] => ram_block1a133.PORTAADDR1 -address_a[1] => ram_block1a134.PORTAADDR1 -address_a[1] => ram_block1a135.PORTAADDR1 -address_a[1] => ram_block1a136.PORTAADDR1 -address_a[1] => ram_block1a137.PORTAADDR1 -address_a[1] => ram_block1a138.PORTAADDR1 -address_a[1] => ram_block1a139.PORTAADDR1 -address_a[1] => ram_block1a140.PORTAADDR1 -address_a[1] => ram_block1a141.PORTAADDR1 -address_a[1] => ram_block1a142.PORTAADDR1 -address_a[1] => ram_block1a143.PORTAADDR1 -address_a[1] => ram_block1a144.PORTAADDR1 -address_a[1] => ram_block1a145.PORTAADDR1 -address_a[1] => ram_block1a146.PORTAADDR1 -address_a[1] => ram_block1a147.PORTAADDR1 -address_a[1] => ram_block1a148.PORTAADDR1 -address_a[1] => ram_block1a149.PORTAADDR1 -address_a[1] => ram_block1a150.PORTAADDR1 -address_a[1] => ram_block1a151.PORTAADDR1 -address_a[1] => ram_block1a152.PORTAADDR1 -address_a[1] => ram_block1a153.PORTAADDR1 -address_a[1] => ram_block1a154.PORTAADDR1 -address_a[1] => ram_block1a155.PORTAADDR1 -address_a[1] => ram_block1a156.PORTAADDR1 -address_a[1] => ram_block1a157.PORTAADDR1 -address_a[1] => ram_block1a158.PORTAADDR1 -address_a[1] => ram_block1a159.PORTAADDR1 -address_a[1] => ram_block1a160.PORTAADDR1 -address_a[1] => ram_block1a161.PORTAADDR1 -address_a[1] => ram_block1a162.PORTAADDR1 -address_a[1] => ram_block1a163.PORTAADDR1 -address_a[1] => ram_block1a164.PORTAADDR1 -address_a[1] => ram_block1a165.PORTAADDR1 -address_a[1] => ram_block1a166.PORTAADDR1 -address_a[1] => ram_block1a167.PORTAADDR1 -address_a[1] => ram_block1a168.PORTAADDR1 -address_a[1] => ram_block1a169.PORTAADDR1 -address_a[1] => ram_block1a170.PORTAADDR1 -address_a[1] => ram_block1a171.PORTAADDR1 -address_a[1] => ram_block1a172.PORTAADDR1 -address_a[1] => ram_block1a173.PORTAADDR1 -address_a[1] => ram_block1a174.PORTAADDR1 -address_a[1] => ram_block1a175.PORTAADDR1 -address_a[1] => ram_block1a176.PORTAADDR1 -address_a[1] => ram_block1a177.PORTAADDR1 -address_a[1] => ram_block1a178.PORTAADDR1 -address_a[1] => ram_block1a179.PORTAADDR1 -address_a[1] => ram_block1a180.PORTAADDR1 -address_a[1] => ram_block1a181.PORTAADDR1 -address_a[1] => ram_block1a182.PORTAADDR1 -address_a[1] => ram_block1a183.PORTAADDR1 -address_a[1] => ram_block1a184.PORTAADDR1 -address_a[1] => ram_block1a185.PORTAADDR1 -address_a[1] => ram_block1a186.PORTAADDR1 -address_a[1] => ram_block1a187.PORTAADDR1 -address_a[1] => ram_block1a188.PORTAADDR1 -address_a[1] => ram_block1a189.PORTAADDR1 -address_a[1] => ram_block1a190.PORTAADDR1 -address_a[1] => ram_block1a191.PORTAADDR1 -address_a[1] => ram_block1a192.PORTAADDR1 -address_a[1] => ram_block1a193.PORTAADDR1 -address_a[1] => ram_block1a194.PORTAADDR1 -address_a[1] => ram_block1a195.PORTAADDR1 -address_a[1] => ram_block1a196.PORTAADDR1 -address_a[1] => ram_block1a197.PORTAADDR1 -address_a[1] => ram_block1a198.PORTAADDR1 -address_a[1] => ram_block1a199.PORTAADDR1 -address_a[1] => ram_block1a200.PORTAADDR1 -address_a[1] => ram_block1a201.PORTAADDR1 -address_a[1] => ram_block1a202.PORTAADDR1 -address_a[1] => ram_block1a203.PORTAADDR1 -address_a[1] => ram_block1a204.PORTAADDR1 -address_a[1] => ram_block1a205.PORTAADDR1 -address_a[1] => ram_block1a206.PORTAADDR1 -address_a[1] => ram_block1a207.PORTAADDR1 -address_a[1] => ram_block1a208.PORTAADDR1 -address_a[1] => ram_block1a209.PORTAADDR1 -address_a[1] => ram_block1a210.PORTAADDR1 -address_a[1] => ram_block1a211.PORTAADDR1 -address_a[1] => ram_block1a212.PORTAADDR1 -address_a[1] => ram_block1a213.PORTAADDR1 -address_a[1] => ram_block1a214.PORTAADDR1 -address_a[1] => ram_block1a215.PORTAADDR1 -address_a[1] => ram_block1a216.PORTAADDR1 -address_a[1] => ram_block1a217.PORTAADDR1 -address_a[1] => ram_block1a218.PORTAADDR1 -address_a[1] => ram_block1a219.PORTAADDR1 -address_a[1] => ram_block1a220.PORTAADDR1 -address_a[1] => ram_block1a221.PORTAADDR1 -address_a[1] => ram_block1a222.PORTAADDR1 -address_a[1] => ram_block1a223.PORTAADDR1 -address_a[2] => ram_block1a0.PORTAADDR2 -address_a[2] => ram_block1a1.PORTAADDR2 -address_a[2] => ram_block1a2.PORTAADDR2 -address_a[2] => ram_block1a3.PORTAADDR2 -address_a[2] => ram_block1a4.PORTAADDR2 -address_a[2] => ram_block1a5.PORTAADDR2 -address_a[2] => ram_block1a6.PORTAADDR2 -address_a[2] => ram_block1a7.PORTAADDR2 -address_a[2] => ram_block1a8.PORTAADDR2 -address_a[2] => ram_block1a9.PORTAADDR2 -address_a[2] => ram_block1a10.PORTAADDR2 -address_a[2] => ram_block1a11.PORTAADDR2 -address_a[2] => ram_block1a12.PORTAADDR2 -address_a[2] => ram_block1a13.PORTAADDR2 -address_a[2] => ram_block1a14.PORTAADDR2 -address_a[2] => ram_block1a15.PORTAADDR2 -address_a[2] => ram_block1a16.PORTAADDR2 -address_a[2] => ram_block1a17.PORTAADDR2 -address_a[2] => ram_block1a18.PORTAADDR2 -address_a[2] => ram_block1a19.PORTAADDR2 -address_a[2] => ram_block1a20.PORTAADDR2 -address_a[2] => ram_block1a21.PORTAADDR2 -address_a[2] => ram_block1a22.PORTAADDR2 -address_a[2] => ram_block1a23.PORTAADDR2 -address_a[2] => ram_block1a24.PORTAADDR2 -address_a[2] => ram_block1a25.PORTAADDR2 -address_a[2] => ram_block1a26.PORTAADDR2 -address_a[2] => ram_block1a27.PORTAADDR2 -address_a[2] => ram_block1a28.PORTAADDR2 -address_a[2] => ram_block1a29.PORTAADDR2 -address_a[2] => ram_block1a30.PORTAADDR2 -address_a[2] => ram_block1a31.PORTAADDR2 -address_a[2] => ram_block1a32.PORTAADDR2 -address_a[2] => ram_block1a33.PORTAADDR2 -address_a[2] => ram_block1a34.PORTAADDR2 -address_a[2] => ram_block1a35.PORTAADDR2 -address_a[2] => ram_block1a36.PORTAADDR2 -address_a[2] => ram_block1a37.PORTAADDR2 -address_a[2] => ram_block1a38.PORTAADDR2 -address_a[2] => ram_block1a39.PORTAADDR2 -address_a[2] => ram_block1a40.PORTAADDR2 -address_a[2] => ram_block1a41.PORTAADDR2 -address_a[2] => ram_block1a42.PORTAADDR2 -address_a[2] => ram_block1a43.PORTAADDR2 -address_a[2] => ram_block1a44.PORTAADDR2 -address_a[2] => ram_block1a45.PORTAADDR2 -address_a[2] => ram_block1a46.PORTAADDR2 -address_a[2] => ram_block1a47.PORTAADDR2 -address_a[2] => ram_block1a48.PORTAADDR2 -address_a[2] => ram_block1a49.PORTAADDR2 -address_a[2] => ram_block1a50.PORTAADDR2 -address_a[2] => ram_block1a51.PORTAADDR2 -address_a[2] => ram_block1a52.PORTAADDR2 -address_a[2] => ram_block1a53.PORTAADDR2 -address_a[2] => ram_block1a54.PORTAADDR2 -address_a[2] => ram_block1a55.PORTAADDR2 -address_a[2] => ram_block1a56.PORTAADDR2 -address_a[2] => ram_block1a57.PORTAADDR2 -address_a[2] => ram_block1a58.PORTAADDR2 -address_a[2] => ram_block1a59.PORTAADDR2 -address_a[2] => ram_block1a60.PORTAADDR2 -address_a[2] => ram_block1a61.PORTAADDR2 -address_a[2] => ram_block1a62.PORTAADDR2 -address_a[2] => ram_block1a63.PORTAADDR2 -address_a[2] => ram_block1a64.PORTAADDR2 -address_a[2] => ram_block1a65.PORTAADDR2 -address_a[2] => ram_block1a66.PORTAADDR2 -address_a[2] => ram_block1a67.PORTAADDR2 -address_a[2] => ram_block1a68.PORTAADDR2 -address_a[2] => ram_block1a69.PORTAADDR2 -address_a[2] => ram_block1a70.PORTAADDR2 -address_a[2] => ram_block1a71.PORTAADDR2 -address_a[2] => ram_block1a72.PORTAADDR2 -address_a[2] => ram_block1a73.PORTAADDR2 -address_a[2] => ram_block1a74.PORTAADDR2 -address_a[2] => ram_block1a75.PORTAADDR2 -address_a[2] => ram_block1a76.PORTAADDR2 -address_a[2] => ram_block1a77.PORTAADDR2 -address_a[2] => ram_block1a78.PORTAADDR2 -address_a[2] => ram_block1a79.PORTAADDR2 -address_a[2] => ram_block1a80.PORTAADDR2 -address_a[2] => ram_block1a81.PORTAADDR2 -address_a[2] => ram_block1a82.PORTAADDR2 -address_a[2] => ram_block1a83.PORTAADDR2 -address_a[2] => ram_block1a84.PORTAADDR2 -address_a[2] => ram_block1a85.PORTAADDR2 -address_a[2] => ram_block1a86.PORTAADDR2 -address_a[2] => ram_block1a87.PORTAADDR2 -address_a[2] => ram_block1a88.PORTAADDR2 -address_a[2] => ram_block1a89.PORTAADDR2 -address_a[2] => ram_block1a90.PORTAADDR2 -address_a[2] => ram_block1a91.PORTAADDR2 -address_a[2] => ram_block1a92.PORTAADDR2 -address_a[2] => ram_block1a93.PORTAADDR2 -address_a[2] => ram_block1a94.PORTAADDR2 -address_a[2] => ram_block1a95.PORTAADDR2 -address_a[2] => ram_block1a96.PORTAADDR2 -address_a[2] => ram_block1a97.PORTAADDR2 -address_a[2] => ram_block1a98.PORTAADDR2 -address_a[2] => ram_block1a99.PORTAADDR2 -address_a[2] => ram_block1a100.PORTAADDR2 -address_a[2] => ram_block1a101.PORTAADDR2 -address_a[2] => ram_block1a102.PORTAADDR2 -address_a[2] => ram_block1a103.PORTAADDR2 -address_a[2] => ram_block1a104.PORTAADDR2 -address_a[2] => ram_block1a105.PORTAADDR2 -address_a[2] => ram_block1a106.PORTAADDR2 -address_a[2] => ram_block1a107.PORTAADDR2 -address_a[2] => ram_block1a108.PORTAADDR2 -address_a[2] => ram_block1a109.PORTAADDR2 -address_a[2] => ram_block1a110.PORTAADDR2 -address_a[2] => ram_block1a111.PORTAADDR2 -address_a[2] => ram_block1a112.PORTAADDR2 -address_a[2] => ram_block1a113.PORTAADDR2 -address_a[2] => ram_block1a114.PORTAADDR2 -address_a[2] => ram_block1a115.PORTAADDR2 -address_a[2] => ram_block1a116.PORTAADDR2 -address_a[2] => ram_block1a117.PORTAADDR2 -address_a[2] => ram_block1a118.PORTAADDR2 -address_a[2] => ram_block1a119.PORTAADDR2 -address_a[2] => ram_block1a120.PORTAADDR2 -address_a[2] => ram_block1a121.PORTAADDR2 -address_a[2] => ram_block1a122.PORTAADDR2 -address_a[2] => ram_block1a123.PORTAADDR2 -address_a[2] => ram_block1a124.PORTAADDR2 -address_a[2] => ram_block1a125.PORTAADDR2 -address_a[2] => ram_block1a126.PORTAADDR2 -address_a[2] => ram_block1a127.PORTAADDR2 -address_a[2] => ram_block1a128.PORTAADDR2 -address_a[2] => ram_block1a129.PORTAADDR2 -address_a[2] => ram_block1a130.PORTAADDR2 -address_a[2] => ram_block1a131.PORTAADDR2 -address_a[2] => ram_block1a132.PORTAADDR2 -address_a[2] => ram_block1a133.PORTAADDR2 -address_a[2] => ram_block1a134.PORTAADDR2 -address_a[2] => ram_block1a135.PORTAADDR2 -address_a[2] => ram_block1a136.PORTAADDR2 -address_a[2] => ram_block1a137.PORTAADDR2 -address_a[2] => ram_block1a138.PORTAADDR2 -address_a[2] => ram_block1a139.PORTAADDR2 -address_a[2] => ram_block1a140.PORTAADDR2 -address_a[2] => ram_block1a141.PORTAADDR2 -address_a[2] => ram_block1a142.PORTAADDR2 -address_a[2] => ram_block1a143.PORTAADDR2 -address_a[2] => ram_block1a144.PORTAADDR2 -address_a[2] => ram_block1a145.PORTAADDR2 -address_a[2] => ram_block1a146.PORTAADDR2 -address_a[2] => ram_block1a147.PORTAADDR2 -address_a[2] => ram_block1a148.PORTAADDR2 -address_a[2] => ram_block1a149.PORTAADDR2 -address_a[2] => ram_block1a150.PORTAADDR2 -address_a[2] => ram_block1a151.PORTAADDR2 -address_a[2] => ram_block1a152.PORTAADDR2 -address_a[2] => ram_block1a153.PORTAADDR2 -address_a[2] => ram_block1a154.PORTAADDR2 -address_a[2] => ram_block1a155.PORTAADDR2 -address_a[2] => ram_block1a156.PORTAADDR2 -address_a[2] => ram_block1a157.PORTAADDR2 -address_a[2] => ram_block1a158.PORTAADDR2 -address_a[2] => ram_block1a159.PORTAADDR2 -address_a[2] => ram_block1a160.PORTAADDR2 -address_a[2] => ram_block1a161.PORTAADDR2 -address_a[2] => ram_block1a162.PORTAADDR2 -address_a[2] => ram_block1a163.PORTAADDR2 -address_a[2] => ram_block1a164.PORTAADDR2 -address_a[2] => ram_block1a165.PORTAADDR2 -address_a[2] => ram_block1a166.PORTAADDR2 -address_a[2] => ram_block1a167.PORTAADDR2 -address_a[2] => ram_block1a168.PORTAADDR2 -address_a[2] => ram_block1a169.PORTAADDR2 -address_a[2] => ram_block1a170.PORTAADDR2 -address_a[2] => ram_block1a171.PORTAADDR2 -address_a[2] => ram_block1a172.PORTAADDR2 -address_a[2] => ram_block1a173.PORTAADDR2 -address_a[2] => ram_block1a174.PORTAADDR2 -address_a[2] => ram_block1a175.PORTAADDR2 -address_a[2] => ram_block1a176.PORTAADDR2 -address_a[2] => ram_block1a177.PORTAADDR2 -address_a[2] => ram_block1a178.PORTAADDR2 -address_a[2] => ram_block1a179.PORTAADDR2 -address_a[2] => ram_block1a180.PORTAADDR2 -address_a[2] => ram_block1a181.PORTAADDR2 -address_a[2] => ram_block1a182.PORTAADDR2 -address_a[2] => ram_block1a183.PORTAADDR2 -address_a[2] => ram_block1a184.PORTAADDR2 -address_a[2] => ram_block1a185.PORTAADDR2 -address_a[2] => ram_block1a186.PORTAADDR2 -address_a[2] => ram_block1a187.PORTAADDR2 -address_a[2] => ram_block1a188.PORTAADDR2 -address_a[2] => ram_block1a189.PORTAADDR2 -address_a[2] => ram_block1a190.PORTAADDR2 -address_a[2] => ram_block1a191.PORTAADDR2 -address_a[2] => ram_block1a192.PORTAADDR2 -address_a[2] => ram_block1a193.PORTAADDR2 -address_a[2] => ram_block1a194.PORTAADDR2 -address_a[2] => ram_block1a195.PORTAADDR2 -address_a[2] => ram_block1a196.PORTAADDR2 -address_a[2] => ram_block1a197.PORTAADDR2 -address_a[2] => ram_block1a198.PORTAADDR2 -address_a[2] => ram_block1a199.PORTAADDR2 -address_a[2] => ram_block1a200.PORTAADDR2 -address_a[2] => ram_block1a201.PORTAADDR2 -address_a[2] => ram_block1a202.PORTAADDR2 -address_a[2] => ram_block1a203.PORTAADDR2 -address_a[2] => ram_block1a204.PORTAADDR2 -address_a[2] => ram_block1a205.PORTAADDR2 -address_a[2] => ram_block1a206.PORTAADDR2 -address_a[2] => ram_block1a207.PORTAADDR2 -address_a[2] => ram_block1a208.PORTAADDR2 -address_a[2] => ram_block1a209.PORTAADDR2 -address_a[2] => ram_block1a210.PORTAADDR2 -address_a[2] => ram_block1a211.PORTAADDR2 -address_a[2] => ram_block1a212.PORTAADDR2 -address_a[2] => ram_block1a213.PORTAADDR2 -address_a[2] => ram_block1a214.PORTAADDR2 -address_a[2] => ram_block1a215.PORTAADDR2 -address_a[2] => ram_block1a216.PORTAADDR2 -address_a[2] => ram_block1a217.PORTAADDR2 -address_a[2] => ram_block1a218.PORTAADDR2 -address_a[2] => ram_block1a219.PORTAADDR2 -address_a[2] => ram_block1a220.PORTAADDR2 -address_a[2] => ram_block1a221.PORTAADDR2 -address_a[2] => ram_block1a222.PORTAADDR2 -address_a[2] => ram_block1a223.PORTAADDR2 -address_a[3] => ram_block1a0.PORTAADDR3 -address_a[3] => ram_block1a1.PORTAADDR3 -address_a[3] => ram_block1a2.PORTAADDR3 -address_a[3] => ram_block1a3.PORTAADDR3 -address_a[3] => ram_block1a4.PORTAADDR3 -address_a[3] => ram_block1a5.PORTAADDR3 -address_a[3] => ram_block1a6.PORTAADDR3 -address_a[3] => ram_block1a7.PORTAADDR3 -address_a[3] => ram_block1a8.PORTAADDR3 -address_a[3] => ram_block1a9.PORTAADDR3 -address_a[3] => ram_block1a10.PORTAADDR3 -address_a[3] => ram_block1a11.PORTAADDR3 -address_a[3] => ram_block1a12.PORTAADDR3 -address_a[3] => ram_block1a13.PORTAADDR3 -address_a[3] => ram_block1a14.PORTAADDR3 -address_a[3] => ram_block1a15.PORTAADDR3 -address_a[3] => ram_block1a16.PORTAADDR3 -address_a[3] => ram_block1a17.PORTAADDR3 -address_a[3] => ram_block1a18.PORTAADDR3 -address_a[3] => ram_block1a19.PORTAADDR3 -address_a[3] => ram_block1a20.PORTAADDR3 -address_a[3] => ram_block1a21.PORTAADDR3 -address_a[3] => ram_block1a22.PORTAADDR3 -address_a[3] => ram_block1a23.PORTAADDR3 -address_a[3] => ram_block1a24.PORTAADDR3 -address_a[3] => ram_block1a25.PORTAADDR3 -address_a[3] => ram_block1a26.PORTAADDR3 -address_a[3] => ram_block1a27.PORTAADDR3 -address_a[3] => ram_block1a28.PORTAADDR3 -address_a[3] => ram_block1a29.PORTAADDR3 -address_a[3] => ram_block1a30.PORTAADDR3 -address_a[3] => ram_block1a31.PORTAADDR3 -address_a[3] => ram_block1a32.PORTAADDR3 -address_a[3] => ram_block1a33.PORTAADDR3 -address_a[3] => ram_block1a34.PORTAADDR3 -address_a[3] => ram_block1a35.PORTAADDR3 -address_a[3] => ram_block1a36.PORTAADDR3 -address_a[3] => ram_block1a37.PORTAADDR3 -address_a[3] => ram_block1a38.PORTAADDR3 -address_a[3] => ram_block1a39.PORTAADDR3 -address_a[3] => ram_block1a40.PORTAADDR3 -address_a[3] => ram_block1a41.PORTAADDR3 -address_a[3] => ram_block1a42.PORTAADDR3 -address_a[3] => ram_block1a43.PORTAADDR3 -address_a[3] => ram_block1a44.PORTAADDR3 -address_a[3] => ram_block1a45.PORTAADDR3 -address_a[3] => ram_block1a46.PORTAADDR3 -address_a[3] => ram_block1a47.PORTAADDR3 -address_a[3] => ram_block1a48.PORTAADDR3 -address_a[3] => ram_block1a49.PORTAADDR3 -address_a[3] => ram_block1a50.PORTAADDR3 -address_a[3] => ram_block1a51.PORTAADDR3 -address_a[3] => ram_block1a52.PORTAADDR3 -address_a[3] => ram_block1a53.PORTAADDR3 -address_a[3] => ram_block1a54.PORTAADDR3 -address_a[3] => ram_block1a55.PORTAADDR3 -address_a[3] => ram_block1a56.PORTAADDR3 -address_a[3] => ram_block1a57.PORTAADDR3 -address_a[3] => ram_block1a58.PORTAADDR3 -address_a[3] => ram_block1a59.PORTAADDR3 -address_a[3] => ram_block1a60.PORTAADDR3 -address_a[3] => ram_block1a61.PORTAADDR3 -address_a[3] => ram_block1a62.PORTAADDR3 -address_a[3] => ram_block1a63.PORTAADDR3 -address_a[3] => ram_block1a64.PORTAADDR3 -address_a[3] => ram_block1a65.PORTAADDR3 -address_a[3] => ram_block1a66.PORTAADDR3 -address_a[3] => ram_block1a67.PORTAADDR3 -address_a[3] => ram_block1a68.PORTAADDR3 -address_a[3] => ram_block1a69.PORTAADDR3 -address_a[3] => ram_block1a70.PORTAADDR3 -address_a[3] => ram_block1a71.PORTAADDR3 -address_a[3] => ram_block1a72.PORTAADDR3 -address_a[3] => ram_block1a73.PORTAADDR3 -address_a[3] => ram_block1a74.PORTAADDR3 -address_a[3] => ram_block1a75.PORTAADDR3 -address_a[3] => ram_block1a76.PORTAADDR3 -address_a[3] => ram_block1a77.PORTAADDR3 -address_a[3] => ram_block1a78.PORTAADDR3 -address_a[3] => ram_block1a79.PORTAADDR3 -address_a[3] => ram_block1a80.PORTAADDR3 -address_a[3] => ram_block1a81.PORTAADDR3 -address_a[3] => ram_block1a82.PORTAADDR3 -address_a[3] => ram_block1a83.PORTAADDR3 -address_a[3] => ram_block1a84.PORTAADDR3 -address_a[3] => ram_block1a85.PORTAADDR3 -address_a[3] => ram_block1a86.PORTAADDR3 -address_a[3] => ram_block1a87.PORTAADDR3 -address_a[3] => ram_block1a88.PORTAADDR3 -address_a[3] => ram_block1a89.PORTAADDR3 -address_a[3] => ram_block1a90.PORTAADDR3 -address_a[3] => ram_block1a91.PORTAADDR3 -address_a[3] => ram_block1a92.PORTAADDR3 -address_a[3] => ram_block1a93.PORTAADDR3 -address_a[3] => ram_block1a94.PORTAADDR3 -address_a[3] => ram_block1a95.PORTAADDR3 -address_a[3] => ram_block1a96.PORTAADDR3 -address_a[3] => ram_block1a97.PORTAADDR3 -address_a[3] => ram_block1a98.PORTAADDR3 -address_a[3] => ram_block1a99.PORTAADDR3 -address_a[3] => ram_block1a100.PORTAADDR3 -address_a[3] => ram_block1a101.PORTAADDR3 -address_a[3] => ram_block1a102.PORTAADDR3 -address_a[3] => ram_block1a103.PORTAADDR3 -address_a[3] => ram_block1a104.PORTAADDR3 -address_a[3] => ram_block1a105.PORTAADDR3 -address_a[3] => ram_block1a106.PORTAADDR3 -address_a[3] => ram_block1a107.PORTAADDR3 -address_a[3] => ram_block1a108.PORTAADDR3 -address_a[3] => ram_block1a109.PORTAADDR3 -address_a[3] => ram_block1a110.PORTAADDR3 -address_a[3] => ram_block1a111.PORTAADDR3 -address_a[3] => ram_block1a112.PORTAADDR3 -address_a[3] => ram_block1a113.PORTAADDR3 -address_a[3] => ram_block1a114.PORTAADDR3 -address_a[3] => ram_block1a115.PORTAADDR3 -address_a[3] => ram_block1a116.PORTAADDR3 -address_a[3] => ram_block1a117.PORTAADDR3 -address_a[3] => ram_block1a118.PORTAADDR3 -address_a[3] => ram_block1a119.PORTAADDR3 -address_a[3] => ram_block1a120.PORTAADDR3 -address_a[3] => ram_block1a121.PORTAADDR3 -address_a[3] => ram_block1a122.PORTAADDR3 -address_a[3] => ram_block1a123.PORTAADDR3 -address_a[3] => ram_block1a124.PORTAADDR3 -address_a[3] => ram_block1a125.PORTAADDR3 -address_a[3] => ram_block1a126.PORTAADDR3 -address_a[3] => ram_block1a127.PORTAADDR3 -address_a[3] => ram_block1a128.PORTAADDR3 -address_a[3] => ram_block1a129.PORTAADDR3 -address_a[3] => ram_block1a130.PORTAADDR3 -address_a[3] => ram_block1a131.PORTAADDR3 -address_a[3] => ram_block1a132.PORTAADDR3 -address_a[3] => ram_block1a133.PORTAADDR3 -address_a[3] => ram_block1a134.PORTAADDR3 -address_a[3] => ram_block1a135.PORTAADDR3 -address_a[3] => ram_block1a136.PORTAADDR3 -address_a[3] => ram_block1a137.PORTAADDR3 -address_a[3] => ram_block1a138.PORTAADDR3 -address_a[3] => ram_block1a139.PORTAADDR3 -address_a[3] => ram_block1a140.PORTAADDR3 -address_a[3] => ram_block1a141.PORTAADDR3 -address_a[3] => ram_block1a142.PORTAADDR3 -address_a[3] => ram_block1a143.PORTAADDR3 -address_a[3] => ram_block1a144.PORTAADDR3 -address_a[3] => ram_block1a145.PORTAADDR3 -address_a[3] => ram_block1a146.PORTAADDR3 -address_a[3] => ram_block1a147.PORTAADDR3 -address_a[3] => ram_block1a148.PORTAADDR3 -address_a[3] => ram_block1a149.PORTAADDR3 -address_a[3] => ram_block1a150.PORTAADDR3 -address_a[3] => ram_block1a151.PORTAADDR3 -address_a[3] => ram_block1a152.PORTAADDR3 -address_a[3] => ram_block1a153.PORTAADDR3 -address_a[3] => ram_block1a154.PORTAADDR3 -address_a[3] => ram_block1a155.PORTAADDR3 -address_a[3] => ram_block1a156.PORTAADDR3 -address_a[3] => ram_block1a157.PORTAADDR3 -address_a[3] => ram_block1a158.PORTAADDR3 -address_a[3] => ram_block1a159.PORTAADDR3 -address_a[3] => ram_block1a160.PORTAADDR3 -address_a[3] => ram_block1a161.PORTAADDR3 -address_a[3] => ram_block1a162.PORTAADDR3 -address_a[3] => ram_block1a163.PORTAADDR3 -address_a[3] => ram_block1a164.PORTAADDR3 -address_a[3] => ram_block1a165.PORTAADDR3 -address_a[3] => ram_block1a166.PORTAADDR3 -address_a[3] => ram_block1a167.PORTAADDR3 -address_a[3] => ram_block1a168.PORTAADDR3 -address_a[3] => ram_block1a169.PORTAADDR3 -address_a[3] => ram_block1a170.PORTAADDR3 -address_a[3] => ram_block1a171.PORTAADDR3 -address_a[3] => ram_block1a172.PORTAADDR3 -address_a[3] => ram_block1a173.PORTAADDR3 -address_a[3] => ram_block1a174.PORTAADDR3 -address_a[3] => ram_block1a175.PORTAADDR3 -address_a[3] => ram_block1a176.PORTAADDR3 -address_a[3] => ram_block1a177.PORTAADDR3 -address_a[3] => ram_block1a178.PORTAADDR3 -address_a[3] => ram_block1a179.PORTAADDR3 -address_a[3] => ram_block1a180.PORTAADDR3 -address_a[3] => ram_block1a181.PORTAADDR3 -address_a[3] => ram_block1a182.PORTAADDR3 -address_a[3] => ram_block1a183.PORTAADDR3 -address_a[3] => ram_block1a184.PORTAADDR3 -address_a[3] => ram_block1a185.PORTAADDR3 -address_a[3] => ram_block1a186.PORTAADDR3 -address_a[3] => ram_block1a187.PORTAADDR3 -address_a[3] => ram_block1a188.PORTAADDR3 -address_a[3] => ram_block1a189.PORTAADDR3 -address_a[3] => ram_block1a190.PORTAADDR3 -address_a[3] => ram_block1a191.PORTAADDR3 -address_a[3] => ram_block1a192.PORTAADDR3 -address_a[3] => ram_block1a193.PORTAADDR3 -address_a[3] => ram_block1a194.PORTAADDR3 -address_a[3] => ram_block1a195.PORTAADDR3 -address_a[3] => ram_block1a196.PORTAADDR3 -address_a[3] => ram_block1a197.PORTAADDR3 -address_a[3] => ram_block1a198.PORTAADDR3 -address_a[3] => ram_block1a199.PORTAADDR3 -address_a[3] => ram_block1a200.PORTAADDR3 -address_a[3] => ram_block1a201.PORTAADDR3 -address_a[3] => ram_block1a202.PORTAADDR3 -address_a[3] => ram_block1a203.PORTAADDR3 -address_a[3] => ram_block1a204.PORTAADDR3 -address_a[3] => ram_block1a205.PORTAADDR3 -address_a[3] => ram_block1a206.PORTAADDR3 -address_a[3] => ram_block1a207.PORTAADDR3 -address_a[3] => ram_block1a208.PORTAADDR3 -address_a[3] => ram_block1a209.PORTAADDR3 -address_a[3] => ram_block1a210.PORTAADDR3 -address_a[3] => ram_block1a211.PORTAADDR3 -address_a[3] => ram_block1a212.PORTAADDR3 -address_a[3] => ram_block1a213.PORTAADDR3 -address_a[3] => ram_block1a214.PORTAADDR3 -address_a[3] => ram_block1a215.PORTAADDR3 -address_a[3] => ram_block1a216.PORTAADDR3 -address_a[3] => ram_block1a217.PORTAADDR3 -address_a[3] => ram_block1a218.PORTAADDR3 -address_a[3] => ram_block1a219.PORTAADDR3 -address_a[3] => ram_block1a220.PORTAADDR3 -address_a[3] => ram_block1a221.PORTAADDR3 -address_a[3] => ram_block1a222.PORTAADDR3 -address_a[3] => ram_block1a223.PORTAADDR3 -address_a[4] => ram_block1a0.PORTAADDR4 -address_a[4] => ram_block1a1.PORTAADDR4 -address_a[4] => ram_block1a2.PORTAADDR4 -address_a[4] => ram_block1a3.PORTAADDR4 -address_a[4] => ram_block1a4.PORTAADDR4 -address_a[4] => ram_block1a5.PORTAADDR4 -address_a[4] => ram_block1a6.PORTAADDR4 -address_a[4] => ram_block1a7.PORTAADDR4 -address_a[4] => ram_block1a8.PORTAADDR4 -address_a[4] => ram_block1a9.PORTAADDR4 -address_a[4] => ram_block1a10.PORTAADDR4 -address_a[4] => ram_block1a11.PORTAADDR4 -address_a[4] => ram_block1a12.PORTAADDR4 -address_a[4] => ram_block1a13.PORTAADDR4 -address_a[4] => ram_block1a14.PORTAADDR4 -address_a[4] => ram_block1a15.PORTAADDR4 -address_a[4] => ram_block1a16.PORTAADDR4 -address_a[4] => ram_block1a17.PORTAADDR4 -address_a[4] => ram_block1a18.PORTAADDR4 -address_a[4] => ram_block1a19.PORTAADDR4 -address_a[4] => ram_block1a20.PORTAADDR4 -address_a[4] => ram_block1a21.PORTAADDR4 -address_a[4] => ram_block1a22.PORTAADDR4 -address_a[4] => ram_block1a23.PORTAADDR4 -address_a[4] => ram_block1a24.PORTAADDR4 -address_a[4] => ram_block1a25.PORTAADDR4 -address_a[4] => ram_block1a26.PORTAADDR4 -address_a[4] => ram_block1a27.PORTAADDR4 -address_a[4] => ram_block1a28.PORTAADDR4 -address_a[4] => ram_block1a29.PORTAADDR4 -address_a[4] => ram_block1a30.PORTAADDR4 -address_a[4] => ram_block1a31.PORTAADDR4 -address_a[4] => ram_block1a32.PORTAADDR4 -address_a[4] => ram_block1a33.PORTAADDR4 -address_a[4] => ram_block1a34.PORTAADDR4 -address_a[4] => ram_block1a35.PORTAADDR4 -address_a[4] => ram_block1a36.PORTAADDR4 -address_a[4] => ram_block1a37.PORTAADDR4 -address_a[4] => ram_block1a38.PORTAADDR4 -address_a[4] => ram_block1a39.PORTAADDR4 -address_a[4] => ram_block1a40.PORTAADDR4 -address_a[4] => ram_block1a41.PORTAADDR4 -address_a[4] => ram_block1a42.PORTAADDR4 -address_a[4] => ram_block1a43.PORTAADDR4 -address_a[4] => ram_block1a44.PORTAADDR4 -address_a[4] => ram_block1a45.PORTAADDR4 -address_a[4] => ram_block1a46.PORTAADDR4 -address_a[4] => ram_block1a47.PORTAADDR4 -address_a[4] => ram_block1a48.PORTAADDR4 -address_a[4] => ram_block1a49.PORTAADDR4 -address_a[4] => ram_block1a50.PORTAADDR4 -address_a[4] => ram_block1a51.PORTAADDR4 -address_a[4] => ram_block1a52.PORTAADDR4 -address_a[4] => ram_block1a53.PORTAADDR4 -address_a[4] => ram_block1a54.PORTAADDR4 -address_a[4] => ram_block1a55.PORTAADDR4 -address_a[4] => ram_block1a56.PORTAADDR4 -address_a[4] => ram_block1a57.PORTAADDR4 -address_a[4] => ram_block1a58.PORTAADDR4 -address_a[4] => ram_block1a59.PORTAADDR4 -address_a[4] => ram_block1a60.PORTAADDR4 -address_a[4] => ram_block1a61.PORTAADDR4 -address_a[4] => ram_block1a62.PORTAADDR4 -address_a[4] => ram_block1a63.PORTAADDR4 -address_a[4] => ram_block1a64.PORTAADDR4 -address_a[4] => ram_block1a65.PORTAADDR4 -address_a[4] => ram_block1a66.PORTAADDR4 -address_a[4] => ram_block1a67.PORTAADDR4 -address_a[4] => ram_block1a68.PORTAADDR4 -address_a[4] => ram_block1a69.PORTAADDR4 -address_a[4] => ram_block1a70.PORTAADDR4 -address_a[4] => ram_block1a71.PORTAADDR4 -address_a[4] => ram_block1a72.PORTAADDR4 -address_a[4] => ram_block1a73.PORTAADDR4 -address_a[4] => ram_block1a74.PORTAADDR4 -address_a[4] => ram_block1a75.PORTAADDR4 -address_a[4] => ram_block1a76.PORTAADDR4 -address_a[4] => ram_block1a77.PORTAADDR4 -address_a[4] => ram_block1a78.PORTAADDR4 -address_a[4] => ram_block1a79.PORTAADDR4 -address_a[4] => ram_block1a80.PORTAADDR4 -address_a[4] => ram_block1a81.PORTAADDR4 -address_a[4] => ram_block1a82.PORTAADDR4 -address_a[4] => ram_block1a83.PORTAADDR4 -address_a[4] => ram_block1a84.PORTAADDR4 -address_a[4] => ram_block1a85.PORTAADDR4 -address_a[4] => ram_block1a86.PORTAADDR4 -address_a[4] => ram_block1a87.PORTAADDR4 -address_a[4] => ram_block1a88.PORTAADDR4 -address_a[4] => ram_block1a89.PORTAADDR4 -address_a[4] => ram_block1a90.PORTAADDR4 -address_a[4] => ram_block1a91.PORTAADDR4 -address_a[4] => ram_block1a92.PORTAADDR4 -address_a[4] => ram_block1a93.PORTAADDR4 -address_a[4] => ram_block1a94.PORTAADDR4 -address_a[4] => ram_block1a95.PORTAADDR4 -address_a[4] => ram_block1a96.PORTAADDR4 -address_a[4] => ram_block1a97.PORTAADDR4 -address_a[4] => ram_block1a98.PORTAADDR4 -address_a[4] => ram_block1a99.PORTAADDR4 -address_a[4] => ram_block1a100.PORTAADDR4 -address_a[4] => ram_block1a101.PORTAADDR4 -address_a[4] => ram_block1a102.PORTAADDR4 -address_a[4] => ram_block1a103.PORTAADDR4 -address_a[4] => ram_block1a104.PORTAADDR4 -address_a[4] => ram_block1a105.PORTAADDR4 -address_a[4] => ram_block1a106.PORTAADDR4 -address_a[4] => ram_block1a107.PORTAADDR4 -address_a[4] => ram_block1a108.PORTAADDR4 -address_a[4] => ram_block1a109.PORTAADDR4 -address_a[4] => ram_block1a110.PORTAADDR4 -address_a[4] => ram_block1a111.PORTAADDR4 -address_a[4] => ram_block1a112.PORTAADDR4 -address_a[4] => ram_block1a113.PORTAADDR4 -address_a[4] => ram_block1a114.PORTAADDR4 -address_a[4] => ram_block1a115.PORTAADDR4 -address_a[4] => ram_block1a116.PORTAADDR4 -address_a[4] => ram_block1a117.PORTAADDR4 -address_a[4] => ram_block1a118.PORTAADDR4 -address_a[4] => ram_block1a119.PORTAADDR4 -address_a[4] => ram_block1a120.PORTAADDR4 -address_a[4] => ram_block1a121.PORTAADDR4 -address_a[4] => ram_block1a122.PORTAADDR4 -address_a[4] => ram_block1a123.PORTAADDR4 -address_a[4] => ram_block1a124.PORTAADDR4 -address_a[4] => ram_block1a125.PORTAADDR4 -address_a[4] => ram_block1a126.PORTAADDR4 -address_a[4] => ram_block1a127.PORTAADDR4 -address_a[4] => ram_block1a128.PORTAADDR4 -address_a[4] => ram_block1a129.PORTAADDR4 -address_a[4] => ram_block1a130.PORTAADDR4 -address_a[4] => ram_block1a131.PORTAADDR4 -address_a[4] => ram_block1a132.PORTAADDR4 -address_a[4] => ram_block1a133.PORTAADDR4 -address_a[4] => ram_block1a134.PORTAADDR4 -address_a[4] => ram_block1a135.PORTAADDR4 -address_a[4] => ram_block1a136.PORTAADDR4 -address_a[4] => ram_block1a137.PORTAADDR4 -address_a[4] => ram_block1a138.PORTAADDR4 -address_a[4] => ram_block1a139.PORTAADDR4 -address_a[4] => ram_block1a140.PORTAADDR4 -address_a[4] => ram_block1a141.PORTAADDR4 -address_a[4] => ram_block1a142.PORTAADDR4 -address_a[4] => ram_block1a143.PORTAADDR4 -address_a[4] => ram_block1a144.PORTAADDR4 -address_a[4] => ram_block1a145.PORTAADDR4 -address_a[4] => ram_block1a146.PORTAADDR4 -address_a[4] => ram_block1a147.PORTAADDR4 -address_a[4] => ram_block1a148.PORTAADDR4 -address_a[4] => ram_block1a149.PORTAADDR4 -address_a[4] => ram_block1a150.PORTAADDR4 -address_a[4] => ram_block1a151.PORTAADDR4 -address_a[4] => ram_block1a152.PORTAADDR4 -address_a[4] => ram_block1a153.PORTAADDR4 -address_a[4] => ram_block1a154.PORTAADDR4 -address_a[4] => ram_block1a155.PORTAADDR4 -address_a[4] => ram_block1a156.PORTAADDR4 -address_a[4] => ram_block1a157.PORTAADDR4 -address_a[4] => ram_block1a158.PORTAADDR4 -address_a[4] => ram_block1a159.PORTAADDR4 -address_a[4] => ram_block1a160.PORTAADDR4 -address_a[4] => ram_block1a161.PORTAADDR4 -address_a[4] => ram_block1a162.PORTAADDR4 -address_a[4] => ram_block1a163.PORTAADDR4 -address_a[4] => ram_block1a164.PORTAADDR4 -address_a[4] => ram_block1a165.PORTAADDR4 -address_a[4] => ram_block1a166.PORTAADDR4 -address_a[4] => ram_block1a167.PORTAADDR4 -address_a[4] => ram_block1a168.PORTAADDR4 -address_a[4] => ram_block1a169.PORTAADDR4 -address_a[4] => ram_block1a170.PORTAADDR4 -address_a[4] => ram_block1a171.PORTAADDR4 -address_a[4] => ram_block1a172.PORTAADDR4 -address_a[4] => ram_block1a173.PORTAADDR4 -address_a[4] => ram_block1a174.PORTAADDR4 -address_a[4] => ram_block1a175.PORTAADDR4 -address_a[4] => ram_block1a176.PORTAADDR4 -address_a[4] => ram_block1a177.PORTAADDR4 -address_a[4] => ram_block1a178.PORTAADDR4 -address_a[4] => ram_block1a179.PORTAADDR4 -address_a[4] => ram_block1a180.PORTAADDR4 -address_a[4] => ram_block1a181.PORTAADDR4 -address_a[4] => ram_block1a182.PORTAADDR4 -address_a[4] => ram_block1a183.PORTAADDR4 -address_a[4] => ram_block1a184.PORTAADDR4 -address_a[4] => ram_block1a185.PORTAADDR4 -address_a[4] => ram_block1a186.PORTAADDR4 -address_a[4] => ram_block1a187.PORTAADDR4 -address_a[4] => ram_block1a188.PORTAADDR4 -address_a[4] => ram_block1a189.PORTAADDR4 -address_a[4] => ram_block1a190.PORTAADDR4 -address_a[4] => ram_block1a191.PORTAADDR4 -address_a[4] => ram_block1a192.PORTAADDR4 -address_a[4] => ram_block1a193.PORTAADDR4 -address_a[4] => ram_block1a194.PORTAADDR4 -address_a[4] => ram_block1a195.PORTAADDR4 -address_a[4] => ram_block1a196.PORTAADDR4 -address_a[4] => ram_block1a197.PORTAADDR4 -address_a[4] => ram_block1a198.PORTAADDR4 -address_a[4] => ram_block1a199.PORTAADDR4 -address_a[4] => ram_block1a200.PORTAADDR4 -address_a[4] => ram_block1a201.PORTAADDR4 -address_a[4] => ram_block1a202.PORTAADDR4 -address_a[4] => ram_block1a203.PORTAADDR4 -address_a[4] => ram_block1a204.PORTAADDR4 -address_a[4] => ram_block1a205.PORTAADDR4 -address_a[4] => ram_block1a206.PORTAADDR4 -address_a[4] => ram_block1a207.PORTAADDR4 -address_a[4] => ram_block1a208.PORTAADDR4 -address_a[4] => ram_block1a209.PORTAADDR4 -address_a[4] => ram_block1a210.PORTAADDR4 -address_a[4] => ram_block1a211.PORTAADDR4 -address_a[4] => ram_block1a212.PORTAADDR4 -address_a[4] => ram_block1a213.PORTAADDR4 -address_a[4] => ram_block1a214.PORTAADDR4 -address_a[4] => ram_block1a215.PORTAADDR4 -address_a[4] => ram_block1a216.PORTAADDR4 -address_a[4] => ram_block1a217.PORTAADDR4 -address_a[4] => ram_block1a218.PORTAADDR4 -address_a[4] => ram_block1a219.PORTAADDR4 -address_a[4] => ram_block1a220.PORTAADDR4 -address_a[4] => ram_block1a221.PORTAADDR4 -address_a[4] => ram_block1a222.PORTAADDR4 -address_a[4] => ram_block1a223.PORTAADDR4 -address_a[5] => ram_block1a0.PORTAADDR5 -address_a[5] => ram_block1a1.PORTAADDR5 -address_a[5] => ram_block1a2.PORTAADDR5 -address_a[5] => ram_block1a3.PORTAADDR5 -address_a[5] => ram_block1a4.PORTAADDR5 -address_a[5] => ram_block1a5.PORTAADDR5 -address_a[5] => ram_block1a6.PORTAADDR5 -address_a[5] => ram_block1a7.PORTAADDR5 -address_a[5] => ram_block1a8.PORTAADDR5 -address_a[5] => ram_block1a9.PORTAADDR5 -address_a[5] => ram_block1a10.PORTAADDR5 -address_a[5] => ram_block1a11.PORTAADDR5 -address_a[5] => ram_block1a12.PORTAADDR5 -address_a[5] => ram_block1a13.PORTAADDR5 -address_a[5] => ram_block1a14.PORTAADDR5 -address_a[5] => ram_block1a15.PORTAADDR5 -address_a[5] => ram_block1a16.PORTAADDR5 -address_a[5] => ram_block1a17.PORTAADDR5 -address_a[5] => ram_block1a18.PORTAADDR5 -address_a[5] => ram_block1a19.PORTAADDR5 -address_a[5] => ram_block1a20.PORTAADDR5 -address_a[5] => ram_block1a21.PORTAADDR5 -address_a[5] => ram_block1a22.PORTAADDR5 -address_a[5] => ram_block1a23.PORTAADDR5 -address_a[5] => ram_block1a24.PORTAADDR5 -address_a[5] => ram_block1a25.PORTAADDR5 -address_a[5] => ram_block1a26.PORTAADDR5 -address_a[5] => ram_block1a27.PORTAADDR5 -address_a[5] => ram_block1a28.PORTAADDR5 -address_a[5] => ram_block1a29.PORTAADDR5 -address_a[5] => ram_block1a30.PORTAADDR5 -address_a[5] => ram_block1a31.PORTAADDR5 -address_a[5] => ram_block1a32.PORTAADDR5 -address_a[5] => ram_block1a33.PORTAADDR5 -address_a[5] => ram_block1a34.PORTAADDR5 -address_a[5] => ram_block1a35.PORTAADDR5 -address_a[5] => ram_block1a36.PORTAADDR5 -address_a[5] => ram_block1a37.PORTAADDR5 -address_a[5] => ram_block1a38.PORTAADDR5 -address_a[5] => ram_block1a39.PORTAADDR5 -address_a[5] => ram_block1a40.PORTAADDR5 -address_a[5] => ram_block1a41.PORTAADDR5 -address_a[5] => ram_block1a42.PORTAADDR5 -address_a[5] => ram_block1a43.PORTAADDR5 -address_a[5] => ram_block1a44.PORTAADDR5 -address_a[5] => ram_block1a45.PORTAADDR5 -address_a[5] => ram_block1a46.PORTAADDR5 -address_a[5] => ram_block1a47.PORTAADDR5 -address_a[5] => ram_block1a48.PORTAADDR5 -address_a[5] => ram_block1a49.PORTAADDR5 -address_a[5] => ram_block1a50.PORTAADDR5 -address_a[5] => ram_block1a51.PORTAADDR5 -address_a[5] => ram_block1a52.PORTAADDR5 -address_a[5] => ram_block1a53.PORTAADDR5 -address_a[5] => ram_block1a54.PORTAADDR5 -address_a[5] => ram_block1a55.PORTAADDR5 -address_a[5] => ram_block1a56.PORTAADDR5 -address_a[5] => ram_block1a57.PORTAADDR5 -address_a[5] => ram_block1a58.PORTAADDR5 -address_a[5] => ram_block1a59.PORTAADDR5 -address_a[5] => ram_block1a60.PORTAADDR5 -address_a[5] => ram_block1a61.PORTAADDR5 -address_a[5] => ram_block1a62.PORTAADDR5 -address_a[5] => ram_block1a63.PORTAADDR5 -address_a[5] => ram_block1a64.PORTAADDR5 -address_a[5] => ram_block1a65.PORTAADDR5 -address_a[5] => ram_block1a66.PORTAADDR5 -address_a[5] => ram_block1a67.PORTAADDR5 -address_a[5] => ram_block1a68.PORTAADDR5 -address_a[5] => ram_block1a69.PORTAADDR5 -address_a[5] => ram_block1a70.PORTAADDR5 -address_a[5] => ram_block1a71.PORTAADDR5 -address_a[5] => ram_block1a72.PORTAADDR5 -address_a[5] => ram_block1a73.PORTAADDR5 -address_a[5] => ram_block1a74.PORTAADDR5 -address_a[5] => ram_block1a75.PORTAADDR5 -address_a[5] => ram_block1a76.PORTAADDR5 -address_a[5] => ram_block1a77.PORTAADDR5 -address_a[5] => ram_block1a78.PORTAADDR5 -address_a[5] => ram_block1a79.PORTAADDR5 -address_a[5] => ram_block1a80.PORTAADDR5 -address_a[5] => ram_block1a81.PORTAADDR5 -address_a[5] => ram_block1a82.PORTAADDR5 -address_a[5] => ram_block1a83.PORTAADDR5 -address_a[5] => ram_block1a84.PORTAADDR5 -address_a[5] => ram_block1a85.PORTAADDR5 -address_a[5] => ram_block1a86.PORTAADDR5 -address_a[5] => ram_block1a87.PORTAADDR5 -address_a[5] => ram_block1a88.PORTAADDR5 -address_a[5] => ram_block1a89.PORTAADDR5 -address_a[5] => ram_block1a90.PORTAADDR5 -address_a[5] => ram_block1a91.PORTAADDR5 -address_a[5] => ram_block1a92.PORTAADDR5 -address_a[5] => ram_block1a93.PORTAADDR5 -address_a[5] => ram_block1a94.PORTAADDR5 -address_a[5] => ram_block1a95.PORTAADDR5 -address_a[5] => ram_block1a96.PORTAADDR5 -address_a[5] => ram_block1a97.PORTAADDR5 -address_a[5] => ram_block1a98.PORTAADDR5 -address_a[5] => ram_block1a99.PORTAADDR5 -address_a[5] => ram_block1a100.PORTAADDR5 -address_a[5] => ram_block1a101.PORTAADDR5 -address_a[5] => ram_block1a102.PORTAADDR5 -address_a[5] => ram_block1a103.PORTAADDR5 -address_a[5] => ram_block1a104.PORTAADDR5 -address_a[5] => ram_block1a105.PORTAADDR5 -address_a[5] => ram_block1a106.PORTAADDR5 -address_a[5] => ram_block1a107.PORTAADDR5 -address_a[5] => ram_block1a108.PORTAADDR5 -address_a[5] => ram_block1a109.PORTAADDR5 -address_a[5] => ram_block1a110.PORTAADDR5 -address_a[5] => ram_block1a111.PORTAADDR5 -address_a[5] => ram_block1a112.PORTAADDR5 -address_a[5] => ram_block1a113.PORTAADDR5 -address_a[5] => ram_block1a114.PORTAADDR5 -address_a[5] => ram_block1a115.PORTAADDR5 -address_a[5] => ram_block1a116.PORTAADDR5 -address_a[5] => ram_block1a117.PORTAADDR5 -address_a[5] => ram_block1a118.PORTAADDR5 -address_a[5] => ram_block1a119.PORTAADDR5 -address_a[5] => ram_block1a120.PORTAADDR5 -address_a[5] => ram_block1a121.PORTAADDR5 -address_a[5] => ram_block1a122.PORTAADDR5 -address_a[5] => ram_block1a123.PORTAADDR5 -address_a[5] => ram_block1a124.PORTAADDR5 -address_a[5] => ram_block1a125.PORTAADDR5 -address_a[5] => ram_block1a126.PORTAADDR5 -address_a[5] => ram_block1a127.PORTAADDR5 -address_a[5] => ram_block1a128.PORTAADDR5 -address_a[5] => ram_block1a129.PORTAADDR5 -address_a[5] => ram_block1a130.PORTAADDR5 -address_a[5] => ram_block1a131.PORTAADDR5 -address_a[5] => ram_block1a132.PORTAADDR5 -address_a[5] => ram_block1a133.PORTAADDR5 -address_a[5] => ram_block1a134.PORTAADDR5 -address_a[5] => ram_block1a135.PORTAADDR5 -address_a[5] => ram_block1a136.PORTAADDR5 -address_a[5] => ram_block1a137.PORTAADDR5 -address_a[5] => ram_block1a138.PORTAADDR5 -address_a[5] => ram_block1a139.PORTAADDR5 -address_a[5] => ram_block1a140.PORTAADDR5 -address_a[5] => ram_block1a141.PORTAADDR5 -address_a[5] => ram_block1a142.PORTAADDR5 -address_a[5] => ram_block1a143.PORTAADDR5 -address_a[5] => ram_block1a144.PORTAADDR5 -address_a[5] => ram_block1a145.PORTAADDR5 -address_a[5] => ram_block1a146.PORTAADDR5 -address_a[5] => ram_block1a147.PORTAADDR5 -address_a[5] => ram_block1a148.PORTAADDR5 -address_a[5] => ram_block1a149.PORTAADDR5 -address_a[5] => ram_block1a150.PORTAADDR5 -address_a[5] => ram_block1a151.PORTAADDR5 -address_a[5] => ram_block1a152.PORTAADDR5 -address_a[5] => ram_block1a153.PORTAADDR5 -address_a[5] => ram_block1a154.PORTAADDR5 -address_a[5] => ram_block1a155.PORTAADDR5 -address_a[5] => ram_block1a156.PORTAADDR5 -address_a[5] => ram_block1a157.PORTAADDR5 -address_a[5] => ram_block1a158.PORTAADDR5 -address_a[5] => ram_block1a159.PORTAADDR5 -address_a[5] => ram_block1a160.PORTAADDR5 -address_a[5] => ram_block1a161.PORTAADDR5 -address_a[5] => ram_block1a162.PORTAADDR5 -address_a[5] => ram_block1a163.PORTAADDR5 -address_a[5] => ram_block1a164.PORTAADDR5 -address_a[5] => ram_block1a165.PORTAADDR5 -address_a[5] => ram_block1a166.PORTAADDR5 -address_a[5] => ram_block1a167.PORTAADDR5 -address_a[5] => ram_block1a168.PORTAADDR5 -address_a[5] => ram_block1a169.PORTAADDR5 -address_a[5] => ram_block1a170.PORTAADDR5 -address_a[5] => ram_block1a171.PORTAADDR5 -address_a[5] => ram_block1a172.PORTAADDR5 -address_a[5] => ram_block1a173.PORTAADDR5 -address_a[5] => ram_block1a174.PORTAADDR5 -address_a[5] => ram_block1a175.PORTAADDR5 -address_a[5] => ram_block1a176.PORTAADDR5 -address_a[5] => ram_block1a177.PORTAADDR5 -address_a[5] => ram_block1a178.PORTAADDR5 -address_a[5] => ram_block1a179.PORTAADDR5 -address_a[5] => ram_block1a180.PORTAADDR5 -address_a[5] => ram_block1a181.PORTAADDR5 -address_a[5] => ram_block1a182.PORTAADDR5 -address_a[5] => ram_block1a183.PORTAADDR5 -address_a[5] => ram_block1a184.PORTAADDR5 -address_a[5] => ram_block1a185.PORTAADDR5 -address_a[5] => ram_block1a186.PORTAADDR5 -address_a[5] => ram_block1a187.PORTAADDR5 -address_a[5] => ram_block1a188.PORTAADDR5 -address_a[5] => ram_block1a189.PORTAADDR5 -address_a[5] => ram_block1a190.PORTAADDR5 -address_a[5] => ram_block1a191.PORTAADDR5 -address_a[5] => ram_block1a192.PORTAADDR5 -address_a[5] => ram_block1a193.PORTAADDR5 -address_a[5] => ram_block1a194.PORTAADDR5 -address_a[5] => ram_block1a195.PORTAADDR5 -address_a[5] => ram_block1a196.PORTAADDR5 -address_a[5] => ram_block1a197.PORTAADDR5 -address_a[5] => ram_block1a198.PORTAADDR5 -address_a[5] => ram_block1a199.PORTAADDR5 -address_a[5] => ram_block1a200.PORTAADDR5 -address_a[5] => ram_block1a201.PORTAADDR5 -address_a[5] => ram_block1a202.PORTAADDR5 -address_a[5] => ram_block1a203.PORTAADDR5 -address_a[5] => ram_block1a204.PORTAADDR5 -address_a[5] => ram_block1a205.PORTAADDR5 -address_a[5] => ram_block1a206.PORTAADDR5 -address_a[5] => ram_block1a207.PORTAADDR5 -address_a[5] => ram_block1a208.PORTAADDR5 -address_a[5] => ram_block1a209.PORTAADDR5 -address_a[5] => ram_block1a210.PORTAADDR5 -address_a[5] => ram_block1a211.PORTAADDR5 -address_a[5] => ram_block1a212.PORTAADDR5 -address_a[5] => ram_block1a213.PORTAADDR5 -address_a[5] => ram_block1a214.PORTAADDR5 -address_a[5] => ram_block1a215.PORTAADDR5 -address_a[5] => ram_block1a216.PORTAADDR5 -address_a[5] => ram_block1a217.PORTAADDR5 -address_a[5] => ram_block1a218.PORTAADDR5 -address_a[5] => ram_block1a219.PORTAADDR5 -address_a[5] => ram_block1a220.PORTAADDR5 -address_a[5] => ram_block1a221.PORTAADDR5 -address_a[5] => ram_block1a222.PORTAADDR5 -address_a[5] => ram_block1a223.PORTAADDR5 -address_a[6] => ram_block1a0.PORTAADDR6 -address_a[6] => ram_block1a1.PORTAADDR6 -address_a[6] => ram_block1a2.PORTAADDR6 -address_a[6] => ram_block1a3.PORTAADDR6 -address_a[6] => ram_block1a4.PORTAADDR6 -address_a[6] => ram_block1a5.PORTAADDR6 -address_a[6] => ram_block1a6.PORTAADDR6 -address_a[6] => ram_block1a7.PORTAADDR6 -address_a[6] => ram_block1a8.PORTAADDR6 -address_a[6] => ram_block1a9.PORTAADDR6 -address_a[6] => ram_block1a10.PORTAADDR6 -address_a[6] => ram_block1a11.PORTAADDR6 -address_a[6] => ram_block1a12.PORTAADDR6 -address_a[6] => ram_block1a13.PORTAADDR6 -address_a[6] => ram_block1a14.PORTAADDR6 -address_a[6] => ram_block1a15.PORTAADDR6 -address_a[6] => ram_block1a16.PORTAADDR6 -address_a[6] => ram_block1a17.PORTAADDR6 -address_a[6] => ram_block1a18.PORTAADDR6 -address_a[6] => ram_block1a19.PORTAADDR6 -address_a[6] => ram_block1a20.PORTAADDR6 -address_a[6] => ram_block1a21.PORTAADDR6 -address_a[6] => ram_block1a22.PORTAADDR6 -address_a[6] => ram_block1a23.PORTAADDR6 -address_a[6] => ram_block1a24.PORTAADDR6 -address_a[6] => ram_block1a25.PORTAADDR6 -address_a[6] => ram_block1a26.PORTAADDR6 -address_a[6] => ram_block1a27.PORTAADDR6 -address_a[6] => ram_block1a28.PORTAADDR6 -address_a[6] => ram_block1a29.PORTAADDR6 -address_a[6] => ram_block1a30.PORTAADDR6 -address_a[6] => ram_block1a31.PORTAADDR6 -address_a[6] => ram_block1a32.PORTAADDR6 -address_a[6] => ram_block1a33.PORTAADDR6 -address_a[6] => ram_block1a34.PORTAADDR6 -address_a[6] => ram_block1a35.PORTAADDR6 -address_a[6] => ram_block1a36.PORTAADDR6 -address_a[6] => ram_block1a37.PORTAADDR6 -address_a[6] => ram_block1a38.PORTAADDR6 -address_a[6] => ram_block1a39.PORTAADDR6 -address_a[6] => ram_block1a40.PORTAADDR6 -address_a[6] => ram_block1a41.PORTAADDR6 -address_a[6] => ram_block1a42.PORTAADDR6 -address_a[6] => ram_block1a43.PORTAADDR6 -address_a[6] => ram_block1a44.PORTAADDR6 -address_a[6] => ram_block1a45.PORTAADDR6 -address_a[6] => ram_block1a46.PORTAADDR6 -address_a[6] => ram_block1a47.PORTAADDR6 -address_a[6] => ram_block1a48.PORTAADDR6 -address_a[6] => ram_block1a49.PORTAADDR6 -address_a[6] => ram_block1a50.PORTAADDR6 -address_a[6] => ram_block1a51.PORTAADDR6 -address_a[6] => ram_block1a52.PORTAADDR6 -address_a[6] => ram_block1a53.PORTAADDR6 -address_a[6] => ram_block1a54.PORTAADDR6 -address_a[6] => ram_block1a55.PORTAADDR6 -address_a[6] => ram_block1a56.PORTAADDR6 -address_a[6] => ram_block1a57.PORTAADDR6 -address_a[6] => ram_block1a58.PORTAADDR6 -address_a[6] => ram_block1a59.PORTAADDR6 -address_a[6] => ram_block1a60.PORTAADDR6 -address_a[6] => ram_block1a61.PORTAADDR6 -address_a[6] => ram_block1a62.PORTAADDR6 -address_a[6] => ram_block1a63.PORTAADDR6 -address_a[6] => ram_block1a64.PORTAADDR6 -address_a[6] => ram_block1a65.PORTAADDR6 -address_a[6] => ram_block1a66.PORTAADDR6 -address_a[6] => ram_block1a67.PORTAADDR6 -address_a[6] => ram_block1a68.PORTAADDR6 -address_a[6] => ram_block1a69.PORTAADDR6 -address_a[6] => ram_block1a70.PORTAADDR6 -address_a[6] => ram_block1a71.PORTAADDR6 -address_a[6] => ram_block1a72.PORTAADDR6 -address_a[6] => ram_block1a73.PORTAADDR6 -address_a[6] => ram_block1a74.PORTAADDR6 -address_a[6] => ram_block1a75.PORTAADDR6 -address_a[6] => ram_block1a76.PORTAADDR6 -address_a[6] => ram_block1a77.PORTAADDR6 -address_a[6] => ram_block1a78.PORTAADDR6 -address_a[6] => ram_block1a79.PORTAADDR6 -address_a[6] => ram_block1a80.PORTAADDR6 -address_a[6] => ram_block1a81.PORTAADDR6 -address_a[6] => ram_block1a82.PORTAADDR6 -address_a[6] => ram_block1a83.PORTAADDR6 -address_a[6] => ram_block1a84.PORTAADDR6 -address_a[6] => ram_block1a85.PORTAADDR6 -address_a[6] => ram_block1a86.PORTAADDR6 -address_a[6] => ram_block1a87.PORTAADDR6 -address_a[6] => ram_block1a88.PORTAADDR6 -address_a[6] => ram_block1a89.PORTAADDR6 -address_a[6] => ram_block1a90.PORTAADDR6 -address_a[6] => ram_block1a91.PORTAADDR6 -address_a[6] => ram_block1a92.PORTAADDR6 -address_a[6] => ram_block1a93.PORTAADDR6 -address_a[6] => ram_block1a94.PORTAADDR6 -address_a[6] => ram_block1a95.PORTAADDR6 -address_a[6] => ram_block1a96.PORTAADDR6 -address_a[6] => ram_block1a97.PORTAADDR6 -address_a[6] => ram_block1a98.PORTAADDR6 -address_a[6] => ram_block1a99.PORTAADDR6 -address_a[6] => ram_block1a100.PORTAADDR6 -address_a[6] => ram_block1a101.PORTAADDR6 -address_a[6] => ram_block1a102.PORTAADDR6 -address_a[6] => ram_block1a103.PORTAADDR6 -address_a[6] => ram_block1a104.PORTAADDR6 -address_a[6] => ram_block1a105.PORTAADDR6 -address_a[6] => ram_block1a106.PORTAADDR6 -address_a[6] => ram_block1a107.PORTAADDR6 -address_a[6] => ram_block1a108.PORTAADDR6 -address_a[6] => ram_block1a109.PORTAADDR6 -address_a[6] => ram_block1a110.PORTAADDR6 -address_a[6] => ram_block1a111.PORTAADDR6 -address_a[6] => ram_block1a112.PORTAADDR6 -address_a[6] => ram_block1a113.PORTAADDR6 -address_a[6] => ram_block1a114.PORTAADDR6 -address_a[6] => ram_block1a115.PORTAADDR6 -address_a[6] => ram_block1a116.PORTAADDR6 -address_a[6] => ram_block1a117.PORTAADDR6 -address_a[6] => ram_block1a118.PORTAADDR6 -address_a[6] => ram_block1a119.PORTAADDR6 -address_a[6] => ram_block1a120.PORTAADDR6 -address_a[6] => ram_block1a121.PORTAADDR6 -address_a[6] => ram_block1a122.PORTAADDR6 -address_a[6] => ram_block1a123.PORTAADDR6 -address_a[6] => ram_block1a124.PORTAADDR6 -address_a[6] => ram_block1a125.PORTAADDR6 -address_a[6] => ram_block1a126.PORTAADDR6 -address_a[6] => ram_block1a127.PORTAADDR6 -address_a[6] => ram_block1a128.PORTAADDR6 -address_a[6] => ram_block1a129.PORTAADDR6 -address_a[6] => ram_block1a130.PORTAADDR6 -address_a[6] => ram_block1a131.PORTAADDR6 -address_a[6] => ram_block1a132.PORTAADDR6 -address_a[6] => ram_block1a133.PORTAADDR6 -address_a[6] => ram_block1a134.PORTAADDR6 -address_a[6] => ram_block1a135.PORTAADDR6 -address_a[6] => ram_block1a136.PORTAADDR6 -address_a[6] => ram_block1a137.PORTAADDR6 -address_a[6] => ram_block1a138.PORTAADDR6 -address_a[6] => ram_block1a139.PORTAADDR6 -address_a[6] => ram_block1a140.PORTAADDR6 -address_a[6] => ram_block1a141.PORTAADDR6 -address_a[6] => ram_block1a142.PORTAADDR6 -address_a[6] => ram_block1a143.PORTAADDR6 -address_a[6] => ram_block1a144.PORTAADDR6 -address_a[6] => ram_block1a145.PORTAADDR6 -address_a[6] => ram_block1a146.PORTAADDR6 -address_a[6] => ram_block1a147.PORTAADDR6 -address_a[6] => ram_block1a148.PORTAADDR6 -address_a[6] => ram_block1a149.PORTAADDR6 -address_a[6] => ram_block1a150.PORTAADDR6 -address_a[6] => ram_block1a151.PORTAADDR6 -address_a[6] => ram_block1a152.PORTAADDR6 -address_a[6] => ram_block1a153.PORTAADDR6 -address_a[6] => ram_block1a154.PORTAADDR6 -address_a[6] => ram_block1a155.PORTAADDR6 -address_a[6] => ram_block1a156.PORTAADDR6 -address_a[6] => ram_block1a157.PORTAADDR6 -address_a[6] => ram_block1a158.PORTAADDR6 -address_a[6] => ram_block1a159.PORTAADDR6 -address_a[6] => ram_block1a160.PORTAADDR6 -address_a[6] => ram_block1a161.PORTAADDR6 -address_a[6] => ram_block1a162.PORTAADDR6 -address_a[6] => ram_block1a163.PORTAADDR6 -address_a[6] => ram_block1a164.PORTAADDR6 -address_a[6] => ram_block1a165.PORTAADDR6 -address_a[6] => ram_block1a166.PORTAADDR6 -address_a[6] => ram_block1a167.PORTAADDR6 -address_a[6] => ram_block1a168.PORTAADDR6 -address_a[6] => ram_block1a169.PORTAADDR6 -address_a[6] => ram_block1a170.PORTAADDR6 -address_a[6] => ram_block1a171.PORTAADDR6 -address_a[6] => ram_block1a172.PORTAADDR6 -address_a[6] => ram_block1a173.PORTAADDR6 -address_a[6] => ram_block1a174.PORTAADDR6 -address_a[6] => ram_block1a175.PORTAADDR6 -address_a[6] => ram_block1a176.PORTAADDR6 -address_a[6] => ram_block1a177.PORTAADDR6 -address_a[6] => ram_block1a178.PORTAADDR6 -address_a[6] => ram_block1a179.PORTAADDR6 -address_a[6] => ram_block1a180.PORTAADDR6 -address_a[6] => ram_block1a181.PORTAADDR6 -address_a[6] => ram_block1a182.PORTAADDR6 -address_a[6] => ram_block1a183.PORTAADDR6 -address_a[6] => ram_block1a184.PORTAADDR6 -address_a[6] => ram_block1a185.PORTAADDR6 -address_a[6] => ram_block1a186.PORTAADDR6 -address_a[6] => ram_block1a187.PORTAADDR6 -address_a[6] => ram_block1a188.PORTAADDR6 -address_a[6] => ram_block1a189.PORTAADDR6 -address_a[6] => ram_block1a190.PORTAADDR6 -address_a[6] => ram_block1a191.PORTAADDR6 -address_a[6] => ram_block1a192.PORTAADDR6 -address_a[6] => ram_block1a193.PORTAADDR6 -address_a[6] => ram_block1a194.PORTAADDR6 -address_a[6] => ram_block1a195.PORTAADDR6 -address_a[6] => ram_block1a196.PORTAADDR6 -address_a[6] => ram_block1a197.PORTAADDR6 -address_a[6] => ram_block1a198.PORTAADDR6 -address_a[6] => ram_block1a199.PORTAADDR6 -address_a[6] => ram_block1a200.PORTAADDR6 -address_a[6] => ram_block1a201.PORTAADDR6 -address_a[6] => ram_block1a202.PORTAADDR6 -address_a[6] => ram_block1a203.PORTAADDR6 -address_a[6] => ram_block1a204.PORTAADDR6 -address_a[6] => ram_block1a205.PORTAADDR6 -address_a[6] => ram_block1a206.PORTAADDR6 -address_a[6] => ram_block1a207.PORTAADDR6 -address_a[6] => ram_block1a208.PORTAADDR6 -address_a[6] => ram_block1a209.PORTAADDR6 -address_a[6] => ram_block1a210.PORTAADDR6 -address_a[6] => ram_block1a211.PORTAADDR6 -address_a[6] => ram_block1a212.PORTAADDR6 -address_a[6] => ram_block1a213.PORTAADDR6 -address_a[6] => ram_block1a214.PORTAADDR6 -address_a[6] => ram_block1a215.PORTAADDR6 -address_a[6] => ram_block1a216.PORTAADDR6 -address_a[6] => ram_block1a217.PORTAADDR6 -address_a[6] => ram_block1a218.PORTAADDR6 -address_a[6] => ram_block1a219.PORTAADDR6 -address_a[6] => ram_block1a220.PORTAADDR6 -address_a[6] => ram_block1a221.PORTAADDR6 -address_a[6] => ram_block1a222.PORTAADDR6 -address_a[6] => ram_block1a223.PORTAADDR6 -address_a[7] => ram_block1a0.PORTAADDR7 -address_a[7] => ram_block1a1.PORTAADDR7 -address_a[7] => ram_block1a2.PORTAADDR7 -address_a[7] => ram_block1a3.PORTAADDR7 -address_a[7] => ram_block1a4.PORTAADDR7 -address_a[7] => ram_block1a5.PORTAADDR7 -address_a[7] => ram_block1a6.PORTAADDR7 -address_a[7] => ram_block1a7.PORTAADDR7 -address_a[7] => ram_block1a8.PORTAADDR7 -address_a[7] => ram_block1a9.PORTAADDR7 -address_a[7] => ram_block1a10.PORTAADDR7 -address_a[7] => ram_block1a11.PORTAADDR7 -address_a[7] => ram_block1a12.PORTAADDR7 -address_a[7] => ram_block1a13.PORTAADDR7 -address_a[7] => ram_block1a14.PORTAADDR7 -address_a[7] => ram_block1a15.PORTAADDR7 -address_a[7] => ram_block1a16.PORTAADDR7 -address_a[7] => ram_block1a17.PORTAADDR7 -address_a[7] => ram_block1a18.PORTAADDR7 -address_a[7] => ram_block1a19.PORTAADDR7 -address_a[7] => ram_block1a20.PORTAADDR7 -address_a[7] => ram_block1a21.PORTAADDR7 -address_a[7] => ram_block1a22.PORTAADDR7 -address_a[7] => ram_block1a23.PORTAADDR7 -address_a[7] => ram_block1a24.PORTAADDR7 -address_a[7] => ram_block1a25.PORTAADDR7 -address_a[7] => ram_block1a26.PORTAADDR7 -address_a[7] => ram_block1a27.PORTAADDR7 -address_a[7] => ram_block1a28.PORTAADDR7 -address_a[7] => ram_block1a29.PORTAADDR7 -address_a[7] => ram_block1a30.PORTAADDR7 -address_a[7] => ram_block1a31.PORTAADDR7 -address_a[7] => ram_block1a32.PORTAADDR7 -address_a[7] => ram_block1a33.PORTAADDR7 -address_a[7] => ram_block1a34.PORTAADDR7 -address_a[7] => ram_block1a35.PORTAADDR7 -address_a[7] => ram_block1a36.PORTAADDR7 -address_a[7] => ram_block1a37.PORTAADDR7 -address_a[7] => ram_block1a38.PORTAADDR7 -address_a[7] => ram_block1a39.PORTAADDR7 -address_a[7] => ram_block1a40.PORTAADDR7 -address_a[7] => ram_block1a41.PORTAADDR7 -address_a[7] => ram_block1a42.PORTAADDR7 -address_a[7] => ram_block1a43.PORTAADDR7 -address_a[7] => ram_block1a44.PORTAADDR7 -address_a[7] => ram_block1a45.PORTAADDR7 -address_a[7] => ram_block1a46.PORTAADDR7 -address_a[7] => ram_block1a47.PORTAADDR7 -address_a[7] => ram_block1a48.PORTAADDR7 -address_a[7] => ram_block1a49.PORTAADDR7 -address_a[7] => ram_block1a50.PORTAADDR7 -address_a[7] => ram_block1a51.PORTAADDR7 -address_a[7] => ram_block1a52.PORTAADDR7 -address_a[7] => ram_block1a53.PORTAADDR7 -address_a[7] => ram_block1a54.PORTAADDR7 -address_a[7] => ram_block1a55.PORTAADDR7 -address_a[7] => ram_block1a56.PORTAADDR7 -address_a[7] => ram_block1a57.PORTAADDR7 -address_a[7] => ram_block1a58.PORTAADDR7 -address_a[7] => ram_block1a59.PORTAADDR7 -address_a[7] => ram_block1a60.PORTAADDR7 -address_a[7] => ram_block1a61.PORTAADDR7 -address_a[7] => ram_block1a62.PORTAADDR7 -address_a[7] => ram_block1a63.PORTAADDR7 -address_a[7] => ram_block1a64.PORTAADDR7 -address_a[7] => ram_block1a65.PORTAADDR7 -address_a[7] => ram_block1a66.PORTAADDR7 -address_a[7] => ram_block1a67.PORTAADDR7 -address_a[7] => ram_block1a68.PORTAADDR7 -address_a[7] => ram_block1a69.PORTAADDR7 -address_a[7] => ram_block1a70.PORTAADDR7 -address_a[7] => ram_block1a71.PORTAADDR7 -address_a[7] => ram_block1a72.PORTAADDR7 -address_a[7] => ram_block1a73.PORTAADDR7 -address_a[7] => ram_block1a74.PORTAADDR7 -address_a[7] => ram_block1a75.PORTAADDR7 -address_a[7] => ram_block1a76.PORTAADDR7 -address_a[7] => ram_block1a77.PORTAADDR7 -address_a[7] => ram_block1a78.PORTAADDR7 -address_a[7] => ram_block1a79.PORTAADDR7 -address_a[7] => ram_block1a80.PORTAADDR7 -address_a[7] => ram_block1a81.PORTAADDR7 -address_a[7] => ram_block1a82.PORTAADDR7 -address_a[7] => ram_block1a83.PORTAADDR7 -address_a[7] => ram_block1a84.PORTAADDR7 -address_a[7] => ram_block1a85.PORTAADDR7 -address_a[7] => ram_block1a86.PORTAADDR7 -address_a[7] => ram_block1a87.PORTAADDR7 -address_a[7] => ram_block1a88.PORTAADDR7 -address_a[7] => ram_block1a89.PORTAADDR7 -address_a[7] => ram_block1a90.PORTAADDR7 -address_a[7] => ram_block1a91.PORTAADDR7 -address_a[7] => ram_block1a92.PORTAADDR7 -address_a[7] => ram_block1a93.PORTAADDR7 -address_a[7] => ram_block1a94.PORTAADDR7 -address_a[7] => ram_block1a95.PORTAADDR7 -address_a[7] => ram_block1a96.PORTAADDR7 -address_a[7] => ram_block1a97.PORTAADDR7 -address_a[7] => ram_block1a98.PORTAADDR7 -address_a[7] => ram_block1a99.PORTAADDR7 -address_a[7] => ram_block1a100.PORTAADDR7 -address_a[7] => ram_block1a101.PORTAADDR7 -address_a[7] => ram_block1a102.PORTAADDR7 -address_a[7] => ram_block1a103.PORTAADDR7 -address_a[7] => ram_block1a104.PORTAADDR7 -address_a[7] => ram_block1a105.PORTAADDR7 -address_a[7] => ram_block1a106.PORTAADDR7 -address_a[7] => ram_block1a107.PORTAADDR7 -address_a[7] => ram_block1a108.PORTAADDR7 -address_a[7] => ram_block1a109.PORTAADDR7 -address_a[7] => ram_block1a110.PORTAADDR7 -address_a[7] => ram_block1a111.PORTAADDR7 -address_a[7] => ram_block1a112.PORTAADDR7 -address_a[7] => ram_block1a113.PORTAADDR7 -address_a[7] => ram_block1a114.PORTAADDR7 -address_a[7] => ram_block1a115.PORTAADDR7 -address_a[7] => ram_block1a116.PORTAADDR7 -address_a[7] => ram_block1a117.PORTAADDR7 -address_a[7] => ram_block1a118.PORTAADDR7 -address_a[7] => ram_block1a119.PORTAADDR7 -address_a[7] => ram_block1a120.PORTAADDR7 -address_a[7] => ram_block1a121.PORTAADDR7 -address_a[7] => ram_block1a122.PORTAADDR7 -address_a[7] => ram_block1a123.PORTAADDR7 -address_a[7] => ram_block1a124.PORTAADDR7 -address_a[7] => ram_block1a125.PORTAADDR7 -address_a[7] => ram_block1a126.PORTAADDR7 -address_a[7] => ram_block1a127.PORTAADDR7 -address_a[7] => ram_block1a128.PORTAADDR7 -address_a[7] => ram_block1a129.PORTAADDR7 -address_a[7] => ram_block1a130.PORTAADDR7 -address_a[7] => ram_block1a131.PORTAADDR7 -address_a[7] => ram_block1a132.PORTAADDR7 -address_a[7] => ram_block1a133.PORTAADDR7 -address_a[7] => ram_block1a134.PORTAADDR7 -address_a[7] => ram_block1a135.PORTAADDR7 -address_a[7] => ram_block1a136.PORTAADDR7 -address_a[7] => ram_block1a137.PORTAADDR7 -address_a[7] => ram_block1a138.PORTAADDR7 -address_a[7] => ram_block1a139.PORTAADDR7 -address_a[7] => ram_block1a140.PORTAADDR7 -address_a[7] => ram_block1a141.PORTAADDR7 -address_a[7] => ram_block1a142.PORTAADDR7 -address_a[7] => ram_block1a143.PORTAADDR7 -address_a[7] => ram_block1a144.PORTAADDR7 -address_a[7] => ram_block1a145.PORTAADDR7 -address_a[7] => ram_block1a146.PORTAADDR7 -address_a[7] => ram_block1a147.PORTAADDR7 -address_a[7] => ram_block1a148.PORTAADDR7 -address_a[7] => ram_block1a149.PORTAADDR7 -address_a[7] => ram_block1a150.PORTAADDR7 -address_a[7] => ram_block1a151.PORTAADDR7 -address_a[7] => ram_block1a152.PORTAADDR7 -address_a[7] => ram_block1a153.PORTAADDR7 -address_a[7] => ram_block1a154.PORTAADDR7 -address_a[7] => ram_block1a155.PORTAADDR7 -address_a[7] => ram_block1a156.PORTAADDR7 -address_a[7] => ram_block1a157.PORTAADDR7 -address_a[7] => ram_block1a158.PORTAADDR7 -address_a[7] => ram_block1a159.PORTAADDR7 -address_a[7] => ram_block1a160.PORTAADDR7 -address_a[7] => ram_block1a161.PORTAADDR7 -address_a[7] => ram_block1a162.PORTAADDR7 -address_a[7] => ram_block1a163.PORTAADDR7 -address_a[7] => ram_block1a164.PORTAADDR7 -address_a[7] => ram_block1a165.PORTAADDR7 -address_a[7] => ram_block1a166.PORTAADDR7 -address_a[7] => ram_block1a167.PORTAADDR7 -address_a[7] => ram_block1a168.PORTAADDR7 -address_a[7] => ram_block1a169.PORTAADDR7 -address_a[7] => ram_block1a170.PORTAADDR7 -address_a[7] => ram_block1a171.PORTAADDR7 -address_a[7] => ram_block1a172.PORTAADDR7 -address_a[7] => ram_block1a173.PORTAADDR7 -address_a[7] => ram_block1a174.PORTAADDR7 -address_a[7] => ram_block1a175.PORTAADDR7 -address_a[7] => ram_block1a176.PORTAADDR7 -address_a[7] => ram_block1a177.PORTAADDR7 -address_a[7] => ram_block1a178.PORTAADDR7 -address_a[7] => ram_block1a179.PORTAADDR7 -address_a[7] => ram_block1a180.PORTAADDR7 -address_a[7] => ram_block1a181.PORTAADDR7 -address_a[7] => ram_block1a182.PORTAADDR7 -address_a[7] => ram_block1a183.PORTAADDR7 -address_a[7] => ram_block1a184.PORTAADDR7 -address_a[7] => ram_block1a185.PORTAADDR7 -address_a[7] => ram_block1a186.PORTAADDR7 -address_a[7] => ram_block1a187.PORTAADDR7 -address_a[7] => ram_block1a188.PORTAADDR7 -address_a[7] => ram_block1a189.PORTAADDR7 -address_a[7] => ram_block1a190.PORTAADDR7 -address_a[7] => ram_block1a191.PORTAADDR7 -address_a[7] => ram_block1a192.PORTAADDR7 -address_a[7] => ram_block1a193.PORTAADDR7 -address_a[7] => ram_block1a194.PORTAADDR7 -address_a[7] => ram_block1a195.PORTAADDR7 -address_a[7] => ram_block1a196.PORTAADDR7 -address_a[7] => ram_block1a197.PORTAADDR7 -address_a[7] => ram_block1a198.PORTAADDR7 -address_a[7] => ram_block1a199.PORTAADDR7 -address_a[7] => ram_block1a200.PORTAADDR7 -address_a[7] => ram_block1a201.PORTAADDR7 -address_a[7] => ram_block1a202.PORTAADDR7 -address_a[7] => ram_block1a203.PORTAADDR7 -address_a[7] => ram_block1a204.PORTAADDR7 -address_a[7] => ram_block1a205.PORTAADDR7 -address_a[7] => ram_block1a206.PORTAADDR7 -address_a[7] => ram_block1a207.PORTAADDR7 -address_a[7] => ram_block1a208.PORTAADDR7 -address_a[7] => ram_block1a209.PORTAADDR7 -address_a[7] => ram_block1a210.PORTAADDR7 -address_a[7] => ram_block1a211.PORTAADDR7 -address_a[7] => ram_block1a212.PORTAADDR7 -address_a[7] => ram_block1a213.PORTAADDR7 -address_a[7] => ram_block1a214.PORTAADDR7 -address_a[7] => ram_block1a215.PORTAADDR7 -address_a[7] => ram_block1a216.PORTAADDR7 -address_a[7] => ram_block1a217.PORTAADDR7 -address_a[7] => ram_block1a218.PORTAADDR7 -address_a[7] => ram_block1a219.PORTAADDR7 -address_a[7] => ram_block1a220.PORTAADDR7 -address_a[7] => ram_block1a221.PORTAADDR7 -address_a[7] => ram_block1a222.PORTAADDR7 -address_a[7] => ram_block1a223.PORTAADDR7 -address_a[8] => ram_block1a0.PORTAADDR8 -address_a[8] => ram_block1a1.PORTAADDR8 -address_a[8] => ram_block1a2.PORTAADDR8 -address_a[8] => ram_block1a3.PORTAADDR8 -address_a[8] => ram_block1a4.PORTAADDR8 -address_a[8] => ram_block1a5.PORTAADDR8 -address_a[8] => ram_block1a6.PORTAADDR8 -address_a[8] => ram_block1a7.PORTAADDR8 -address_a[8] => ram_block1a8.PORTAADDR8 -address_a[8] => ram_block1a9.PORTAADDR8 -address_a[8] => ram_block1a10.PORTAADDR8 -address_a[8] => ram_block1a11.PORTAADDR8 -address_a[8] => ram_block1a12.PORTAADDR8 -address_a[8] => ram_block1a13.PORTAADDR8 -address_a[8] => ram_block1a14.PORTAADDR8 -address_a[8] => ram_block1a15.PORTAADDR8 -address_a[8] => ram_block1a16.PORTAADDR8 -address_a[8] => ram_block1a17.PORTAADDR8 -address_a[8] => ram_block1a18.PORTAADDR8 -address_a[8] => ram_block1a19.PORTAADDR8 -address_a[8] => ram_block1a20.PORTAADDR8 -address_a[8] => ram_block1a21.PORTAADDR8 -address_a[8] => ram_block1a22.PORTAADDR8 -address_a[8] => ram_block1a23.PORTAADDR8 -address_a[8] => ram_block1a24.PORTAADDR8 -address_a[8] => ram_block1a25.PORTAADDR8 -address_a[8] => ram_block1a26.PORTAADDR8 -address_a[8] => ram_block1a27.PORTAADDR8 -address_a[8] => ram_block1a28.PORTAADDR8 -address_a[8] => ram_block1a29.PORTAADDR8 -address_a[8] => ram_block1a30.PORTAADDR8 -address_a[8] => ram_block1a31.PORTAADDR8 -address_a[8] => ram_block1a32.PORTAADDR8 -address_a[8] => ram_block1a33.PORTAADDR8 -address_a[8] => ram_block1a34.PORTAADDR8 -address_a[8] => ram_block1a35.PORTAADDR8 -address_a[8] => ram_block1a36.PORTAADDR8 -address_a[8] => ram_block1a37.PORTAADDR8 -address_a[8] => ram_block1a38.PORTAADDR8 -address_a[8] => ram_block1a39.PORTAADDR8 -address_a[8] => ram_block1a40.PORTAADDR8 -address_a[8] => ram_block1a41.PORTAADDR8 -address_a[8] => ram_block1a42.PORTAADDR8 -address_a[8] => ram_block1a43.PORTAADDR8 -address_a[8] => ram_block1a44.PORTAADDR8 -address_a[8] => ram_block1a45.PORTAADDR8 -address_a[8] => ram_block1a46.PORTAADDR8 -address_a[8] => ram_block1a47.PORTAADDR8 -address_a[8] => ram_block1a48.PORTAADDR8 -address_a[8] => ram_block1a49.PORTAADDR8 -address_a[8] => ram_block1a50.PORTAADDR8 -address_a[8] => ram_block1a51.PORTAADDR8 -address_a[8] => ram_block1a52.PORTAADDR8 -address_a[8] => ram_block1a53.PORTAADDR8 -address_a[8] => ram_block1a54.PORTAADDR8 -address_a[8] => ram_block1a55.PORTAADDR8 -address_a[8] => ram_block1a56.PORTAADDR8 -address_a[8] => ram_block1a57.PORTAADDR8 -address_a[8] => ram_block1a58.PORTAADDR8 -address_a[8] => ram_block1a59.PORTAADDR8 -address_a[8] => ram_block1a60.PORTAADDR8 -address_a[8] => ram_block1a61.PORTAADDR8 -address_a[8] => ram_block1a62.PORTAADDR8 -address_a[8] => ram_block1a63.PORTAADDR8 -address_a[8] => ram_block1a64.PORTAADDR8 -address_a[8] => ram_block1a65.PORTAADDR8 -address_a[8] => ram_block1a66.PORTAADDR8 -address_a[8] => ram_block1a67.PORTAADDR8 -address_a[8] => ram_block1a68.PORTAADDR8 -address_a[8] => ram_block1a69.PORTAADDR8 -address_a[8] => ram_block1a70.PORTAADDR8 -address_a[8] => ram_block1a71.PORTAADDR8 -address_a[8] => ram_block1a72.PORTAADDR8 -address_a[8] => ram_block1a73.PORTAADDR8 -address_a[8] => ram_block1a74.PORTAADDR8 -address_a[8] => ram_block1a75.PORTAADDR8 -address_a[8] => ram_block1a76.PORTAADDR8 -address_a[8] => ram_block1a77.PORTAADDR8 -address_a[8] => ram_block1a78.PORTAADDR8 -address_a[8] => ram_block1a79.PORTAADDR8 -address_a[8] => ram_block1a80.PORTAADDR8 -address_a[8] => ram_block1a81.PORTAADDR8 -address_a[8] => ram_block1a82.PORTAADDR8 -address_a[8] => ram_block1a83.PORTAADDR8 -address_a[8] => ram_block1a84.PORTAADDR8 -address_a[8] => ram_block1a85.PORTAADDR8 -address_a[8] => ram_block1a86.PORTAADDR8 -address_a[8] => ram_block1a87.PORTAADDR8 -address_a[8] => ram_block1a88.PORTAADDR8 -address_a[8] => ram_block1a89.PORTAADDR8 -address_a[8] => ram_block1a90.PORTAADDR8 -address_a[8] => ram_block1a91.PORTAADDR8 -address_a[8] => ram_block1a92.PORTAADDR8 -address_a[8] => ram_block1a93.PORTAADDR8 -address_a[8] => ram_block1a94.PORTAADDR8 -address_a[8] => ram_block1a95.PORTAADDR8 -address_a[8] => ram_block1a96.PORTAADDR8 -address_a[8] => ram_block1a97.PORTAADDR8 -address_a[8] => ram_block1a98.PORTAADDR8 -address_a[8] => ram_block1a99.PORTAADDR8 -address_a[8] => ram_block1a100.PORTAADDR8 -address_a[8] => ram_block1a101.PORTAADDR8 -address_a[8] => ram_block1a102.PORTAADDR8 -address_a[8] => ram_block1a103.PORTAADDR8 -address_a[8] => ram_block1a104.PORTAADDR8 -address_a[8] => ram_block1a105.PORTAADDR8 -address_a[8] => ram_block1a106.PORTAADDR8 -address_a[8] => ram_block1a107.PORTAADDR8 -address_a[8] => ram_block1a108.PORTAADDR8 -address_a[8] => ram_block1a109.PORTAADDR8 -address_a[8] => ram_block1a110.PORTAADDR8 -address_a[8] => ram_block1a111.PORTAADDR8 -address_a[8] => ram_block1a112.PORTAADDR8 -address_a[8] => ram_block1a113.PORTAADDR8 -address_a[8] => ram_block1a114.PORTAADDR8 -address_a[8] => ram_block1a115.PORTAADDR8 -address_a[8] => ram_block1a116.PORTAADDR8 -address_a[8] => ram_block1a117.PORTAADDR8 -address_a[8] => ram_block1a118.PORTAADDR8 -address_a[8] => ram_block1a119.PORTAADDR8 -address_a[8] => ram_block1a120.PORTAADDR8 -address_a[8] => ram_block1a121.PORTAADDR8 -address_a[8] => ram_block1a122.PORTAADDR8 -address_a[8] => ram_block1a123.PORTAADDR8 -address_a[8] => ram_block1a124.PORTAADDR8 -address_a[8] => ram_block1a125.PORTAADDR8 -address_a[8] => ram_block1a126.PORTAADDR8 -address_a[8] => ram_block1a127.PORTAADDR8 -address_a[8] => ram_block1a128.PORTAADDR8 -address_a[8] => ram_block1a129.PORTAADDR8 -address_a[8] => ram_block1a130.PORTAADDR8 -address_a[8] => ram_block1a131.PORTAADDR8 -address_a[8] => ram_block1a132.PORTAADDR8 -address_a[8] => ram_block1a133.PORTAADDR8 -address_a[8] => ram_block1a134.PORTAADDR8 -address_a[8] => ram_block1a135.PORTAADDR8 -address_a[8] => ram_block1a136.PORTAADDR8 -address_a[8] => ram_block1a137.PORTAADDR8 -address_a[8] => ram_block1a138.PORTAADDR8 -address_a[8] => ram_block1a139.PORTAADDR8 -address_a[8] => ram_block1a140.PORTAADDR8 -address_a[8] => ram_block1a141.PORTAADDR8 -address_a[8] => ram_block1a142.PORTAADDR8 -address_a[8] => ram_block1a143.PORTAADDR8 -address_a[8] => ram_block1a144.PORTAADDR8 -address_a[8] => ram_block1a145.PORTAADDR8 -address_a[8] => ram_block1a146.PORTAADDR8 -address_a[8] => ram_block1a147.PORTAADDR8 -address_a[8] => ram_block1a148.PORTAADDR8 -address_a[8] => ram_block1a149.PORTAADDR8 -address_a[8] => ram_block1a150.PORTAADDR8 -address_a[8] => ram_block1a151.PORTAADDR8 -address_a[8] => ram_block1a152.PORTAADDR8 -address_a[8] => ram_block1a153.PORTAADDR8 -address_a[8] => ram_block1a154.PORTAADDR8 -address_a[8] => ram_block1a155.PORTAADDR8 -address_a[8] => ram_block1a156.PORTAADDR8 -address_a[8] => ram_block1a157.PORTAADDR8 -address_a[8] => ram_block1a158.PORTAADDR8 -address_a[8] => ram_block1a159.PORTAADDR8 -address_a[8] => ram_block1a160.PORTAADDR8 -address_a[8] => ram_block1a161.PORTAADDR8 -address_a[8] => ram_block1a162.PORTAADDR8 -address_a[8] => ram_block1a163.PORTAADDR8 -address_a[8] => ram_block1a164.PORTAADDR8 -address_a[8] => ram_block1a165.PORTAADDR8 -address_a[8] => ram_block1a166.PORTAADDR8 -address_a[8] => ram_block1a167.PORTAADDR8 -address_a[8] => ram_block1a168.PORTAADDR8 -address_a[8] => ram_block1a169.PORTAADDR8 -address_a[8] => ram_block1a170.PORTAADDR8 -address_a[8] => ram_block1a171.PORTAADDR8 -address_a[8] => ram_block1a172.PORTAADDR8 -address_a[8] => ram_block1a173.PORTAADDR8 -address_a[8] => ram_block1a174.PORTAADDR8 -address_a[8] => ram_block1a175.PORTAADDR8 -address_a[8] => ram_block1a176.PORTAADDR8 -address_a[8] => ram_block1a177.PORTAADDR8 -address_a[8] => ram_block1a178.PORTAADDR8 -address_a[8] => ram_block1a179.PORTAADDR8 -address_a[8] => ram_block1a180.PORTAADDR8 -address_a[8] => ram_block1a181.PORTAADDR8 -address_a[8] => ram_block1a182.PORTAADDR8 -address_a[8] => ram_block1a183.PORTAADDR8 -address_a[8] => ram_block1a184.PORTAADDR8 -address_a[8] => ram_block1a185.PORTAADDR8 -address_a[8] => ram_block1a186.PORTAADDR8 -address_a[8] => ram_block1a187.PORTAADDR8 -address_a[8] => ram_block1a188.PORTAADDR8 -address_a[8] => ram_block1a189.PORTAADDR8 -address_a[8] => ram_block1a190.PORTAADDR8 -address_a[8] => ram_block1a191.PORTAADDR8 -address_a[8] => ram_block1a192.PORTAADDR8 -address_a[8] => ram_block1a193.PORTAADDR8 -address_a[8] => ram_block1a194.PORTAADDR8 -address_a[8] => ram_block1a195.PORTAADDR8 -address_a[8] => ram_block1a196.PORTAADDR8 -address_a[8] => ram_block1a197.PORTAADDR8 -address_a[8] => ram_block1a198.PORTAADDR8 -address_a[8] => ram_block1a199.PORTAADDR8 -address_a[8] => ram_block1a200.PORTAADDR8 -address_a[8] => ram_block1a201.PORTAADDR8 -address_a[8] => ram_block1a202.PORTAADDR8 -address_a[8] => ram_block1a203.PORTAADDR8 -address_a[8] => ram_block1a204.PORTAADDR8 -address_a[8] => ram_block1a205.PORTAADDR8 -address_a[8] => ram_block1a206.PORTAADDR8 -address_a[8] => ram_block1a207.PORTAADDR8 -address_a[8] => ram_block1a208.PORTAADDR8 -address_a[8] => ram_block1a209.PORTAADDR8 -address_a[8] => ram_block1a210.PORTAADDR8 -address_a[8] => ram_block1a211.PORTAADDR8 -address_a[8] => ram_block1a212.PORTAADDR8 -address_a[8] => ram_block1a213.PORTAADDR8 -address_a[8] => ram_block1a214.PORTAADDR8 -address_a[8] => ram_block1a215.PORTAADDR8 -address_a[8] => ram_block1a216.PORTAADDR8 -address_a[8] => ram_block1a217.PORTAADDR8 -address_a[8] => ram_block1a218.PORTAADDR8 -address_a[8] => ram_block1a219.PORTAADDR8 -address_a[8] => ram_block1a220.PORTAADDR8 -address_a[8] => ram_block1a221.PORTAADDR8 -address_a[8] => ram_block1a222.PORTAADDR8 -address_a[8] => ram_block1a223.PORTAADDR8 -address_a[9] => ram_block1a0.PORTAADDR9 -address_a[9] => ram_block1a1.PORTAADDR9 -address_a[9] => ram_block1a2.PORTAADDR9 -address_a[9] => ram_block1a3.PORTAADDR9 -address_a[9] => ram_block1a4.PORTAADDR9 -address_a[9] => ram_block1a5.PORTAADDR9 -address_a[9] => ram_block1a6.PORTAADDR9 -address_a[9] => ram_block1a7.PORTAADDR9 -address_a[9] => ram_block1a8.PORTAADDR9 -address_a[9] => ram_block1a9.PORTAADDR9 -address_a[9] => ram_block1a10.PORTAADDR9 -address_a[9] => ram_block1a11.PORTAADDR9 -address_a[9] => ram_block1a12.PORTAADDR9 -address_a[9] => ram_block1a13.PORTAADDR9 -address_a[9] => ram_block1a14.PORTAADDR9 -address_a[9] => ram_block1a15.PORTAADDR9 -address_a[9] => ram_block1a16.PORTAADDR9 -address_a[9] => ram_block1a17.PORTAADDR9 -address_a[9] => ram_block1a18.PORTAADDR9 -address_a[9] => ram_block1a19.PORTAADDR9 -address_a[9] => ram_block1a20.PORTAADDR9 -address_a[9] => ram_block1a21.PORTAADDR9 -address_a[9] => ram_block1a22.PORTAADDR9 -address_a[9] => ram_block1a23.PORTAADDR9 -address_a[9] => ram_block1a24.PORTAADDR9 -address_a[9] => ram_block1a25.PORTAADDR9 -address_a[9] => ram_block1a26.PORTAADDR9 -address_a[9] => ram_block1a27.PORTAADDR9 -address_a[9] => ram_block1a28.PORTAADDR9 -address_a[9] => ram_block1a29.PORTAADDR9 -address_a[9] => ram_block1a30.PORTAADDR9 -address_a[9] => ram_block1a31.PORTAADDR9 -address_a[9] => ram_block1a32.PORTAADDR9 -address_a[9] => ram_block1a33.PORTAADDR9 -address_a[9] => ram_block1a34.PORTAADDR9 -address_a[9] => ram_block1a35.PORTAADDR9 -address_a[9] => ram_block1a36.PORTAADDR9 -address_a[9] => ram_block1a37.PORTAADDR9 -address_a[9] => ram_block1a38.PORTAADDR9 -address_a[9] => ram_block1a39.PORTAADDR9 -address_a[9] => ram_block1a40.PORTAADDR9 -address_a[9] => ram_block1a41.PORTAADDR9 -address_a[9] => ram_block1a42.PORTAADDR9 -address_a[9] => ram_block1a43.PORTAADDR9 -address_a[9] => ram_block1a44.PORTAADDR9 -address_a[9] => ram_block1a45.PORTAADDR9 -address_a[9] => ram_block1a46.PORTAADDR9 -address_a[9] => ram_block1a47.PORTAADDR9 -address_a[9] => ram_block1a48.PORTAADDR9 -address_a[9] => ram_block1a49.PORTAADDR9 -address_a[9] => ram_block1a50.PORTAADDR9 -address_a[9] => ram_block1a51.PORTAADDR9 -address_a[9] => ram_block1a52.PORTAADDR9 -address_a[9] => ram_block1a53.PORTAADDR9 -address_a[9] => ram_block1a54.PORTAADDR9 -address_a[9] => ram_block1a55.PORTAADDR9 -address_a[9] => ram_block1a56.PORTAADDR9 -address_a[9] => ram_block1a57.PORTAADDR9 -address_a[9] => ram_block1a58.PORTAADDR9 -address_a[9] => ram_block1a59.PORTAADDR9 -address_a[9] => ram_block1a60.PORTAADDR9 -address_a[9] => ram_block1a61.PORTAADDR9 -address_a[9] => ram_block1a62.PORTAADDR9 -address_a[9] => ram_block1a63.PORTAADDR9 -address_a[9] => ram_block1a64.PORTAADDR9 -address_a[9] => ram_block1a65.PORTAADDR9 -address_a[9] => ram_block1a66.PORTAADDR9 -address_a[9] => ram_block1a67.PORTAADDR9 -address_a[9] => ram_block1a68.PORTAADDR9 -address_a[9] => ram_block1a69.PORTAADDR9 -address_a[9] => ram_block1a70.PORTAADDR9 -address_a[9] => ram_block1a71.PORTAADDR9 -address_a[9] => ram_block1a72.PORTAADDR9 -address_a[9] => ram_block1a73.PORTAADDR9 -address_a[9] => ram_block1a74.PORTAADDR9 -address_a[9] => ram_block1a75.PORTAADDR9 -address_a[9] => ram_block1a76.PORTAADDR9 -address_a[9] => ram_block1a77.PORTAADDR9 -address_a[9] => ram_block1a78.PORTAADDR9 -address_a[9] => ram_block1a79.PORTAADDR9 -address_a[9] => ram_block1a80.PORTAADDR9 -address_a[9] => ram_block1a81.PORTAADDR9 -address_a[9] => ram_block1a82.PORTAADDR9 -address_a[9] => ram_block1a83.PORTAADDR9 -address_a[9] => ram_block1a84.PORTAADDR9 -address_a[9] => ram_block1a85.PORTAADDR9 -address_a[9] => ram_block1a86.PORTAADDR9 -address_a[9] => ram_block1a87.PORTAADDR9 -address_a[9] => ram_block1a88.PORTAADDR9 -address_a[9] => ram_block1a89.PORTAADDR9 -address_a[9] => ram_block1a90.PORTAADDR9 -address_a[9] => ram_block1a91.PORTAADDR9 -address_a[9] => ram_block1a92.PORTAADDR9 -address_a[9] => ram_block1a93.PORTAADDR9 -address_a[9] => ram_block1a94.PORTAADDR9 -address_a[9] => ram_block1a95.PORTAADDR9 -address_a[9] => ram_block1a96.PORTAADDR9 -address_a[9] => ram_block1a97.PORTAADDR9 -address_a[9] => ram_block1a98.PORTAADDR9 -address_a[9] => ram_block1a99.PORTAADDR9 -address_a[9] => ram_block1a100.PORTAADDR9 -address_a[9] => ram_block1a101.PORTAADDR9 -address_a[9] => ram_block1a102.PORTAADDR9 -address_a[9] => ram_block1a103.PORTAADDR9 -address_a[9] => ram_block1a104.PORTAADDR9 -address_a[9] => ram_block1a105.PORTAADDR9 -address_a[9] => ram_block1a106.PORTAADDR9 -address_a[9] => ram_block1a107.PORTAADDR9 -address_a[9] => ram_block1a108.PORTAADDR9 -address_a[9] => ram_block1a109.PORTAADDR9 -address_a[9] => ram_block1a110.PORTAADDR9 -address_a[9] => ram_block1a111.PORTAADDR9 -address_a[9] => ram_block1a112.PORTAADDR9 -address_a[9] => ram_block1a113.PORTAADDR9 -address_a[9] => ram_block1a114.PORTAADDR9 -address_a[9] => ram_block1a115.PORTAADDR9 -address_a[9] => ram_block1a116.PORTAADDR9 -address_a[9] => ram_block1a117.PORTAADDR9 -address_a[9] => ram_block1a118.PORTAADDR9 -address_a[9] => ram_block1a119.PORTAADDR9 -address_a[9] => ram_block1a120.PORTAADDR9 -address_a[9] => ram_block1a121.PORTAADDR9 -address_a[9] => ram_block1a122.PORTAADDR9 -address_a[9] => ram_block1a123.PORTAADDR9 -address_a[9] => ram_block1a124.PORTAADDR9 -address_a[9] => ram_block1a125.PORTAADDR9 -address_a[9] => ram_block1a126.PORTAADDR9 -address_a[9] => ram_block1a127.PORTAADDR9 -address_a[9] => ram_block1a128.PORTAADDR9 -address_a[9] => ram_block1a129.PORTAADDR9 -address_a[9] => ram_block1a130.PORTAADDR9 -address_a[9] => ram_block1a131.PORTAADDR9 -address_a[9] => ram_block1a132.PORTAADDR9 -address_a[9] => ram_block1a133.PORTAADDR9 -address_a[9] => ram_block1a134.PORTAADDR9 -address_a[9] => ram_block1a135.PORTAADDR9 -address_a[9] => ram_block1a136.PORTAADDR9 -address_a[9] => ram_block1a137.PORTAADDR9 -address_a[9] => ram_block1a138.PORTAADDR9 -address_a[9] => ram_block1a139.PORTAADDR9 -address_a[9] => ram_block1a140.PORTAADDR9 -address_a[9] => ram_block1a141.PORTAADDR9 -address_a[9] => ram_block1a142.PORTAADDR9 -address_a[9] => ram_block1a143.PORTAADDR9 -address_a[9] => ram_block1a144.PORTAADDR9 -address_a[9] => ram_block1a145.PORTAADDR9 -address_a[9] => ram_block1a146.PORTAADDR9 -address_a[9] => ram_block1a147.PORTAADDR9 -address_a[9] => ram_block1a148.PORTAADDR9 -address_a[9] => ram_block1a149.PORTAADDR9 -address_a[9] => ram_block1a150.PORTAADDR9 -address_a[9] => ram_block1a151.PORTAADDR9 -address_a[9] => ram_block1a152.PORTAADDR9 -address_a[9] => ram_block1a153.PORTAADDR9 -address_a[9] => ram_block1a154.PORTAADDR9 -address_a[9] => ram_block1a155.PORTAADDR9 -address_a[9] => ram_block1a156.PORTAADDR9 -address_a[9] => ram_block1a157.PORTAADDR9 -address_a[9] => ram_block1a158.PORTAADDR9 -address_a[9] => ram_block1a159.PORTAADDR9 -address_a[9] => ram_block1a160.PORTAADDR9 -address_a[9] => ram_block1a161.PORTAADDR9 -address_a[9] => ram_block1a162.PORTAADDR9 -address_a[9] => ram_block1a163.PORTAADDR9 -address_a[9] => ram_block1a164.PORTAADDR9 -address_a[9] => ram_block1a165.PORTAADDR9 -address_a[9] => ram_block1a166.PORTAADDR9 -address_a[9] => ram_block1a167.PORTAADDR9 -address_a[9] => ram_block1a168.PORTAADDR9 -address_a[9] => ram_block1a169.PORTAADDR9 -address_a[9] => ram_block1a170.PORTAADDR9 -address_a[9] => ram_block1a171.PORTAADDR9 -address_a[9] => ram_block1a172.PORTAADDR9 -address_a[9] => ram_block1a173.PORTAADDR9 -address_a[9] => ram_block1a174.PORTAADDR9 -address_a[9] => ram_block1a175.PORTAADDR9 -address_a[9] => ram_block1a176.PORTAADDR9 -address_a[9] => ram_block1a177.PORTAADDR9 -address_a[9] => ram_block1a178.PORTAADDR9 -address_a[9] => ram_block1a179.PORTAADDR9 -address_a[9] => ram_block1a180.PORTAADDR9 -address_a[9] => ram_block1a181.PORTAADDR9 -address_a[9] => ram_block1a182.PORTAADDR9 -address_a[9] => ram_block1a183.PORTAADDR9 -address_a[9] => ram_block1a184.PORTAADDR9 -address_a[9] => ram_block1a185.PORTAADDR9 -address_a[9] => ram_block1a186.PORTAADDR9 -address_a[9] => ram_block1a187.PORTAADDR9 -address_a[9] => ram_block1a188.PORTAADDR9 -address_a[9] => ram_block1a189.PORTAADDR9 -address_a[9] => ram_block1a190.PORTAADDR9 -address_a[9] => ram_block1a191.PORTAADDR9 -address_a[9] => ram_block1a192.PORTAADDR9 -address_a[9] => ram_block1a193.PORTAADDR9 -address_a[9] => ram_block1a194.PORTAADDR9 -address_a[9] => ram_block1a195.PORTAADDR9 -address_a[9] => ram_block1a196.PORTAADDR9 -address_a[9] => ram_block1a197.PORTAADDR9 -address_a[9] => ram_block1a198.PORTAADDR9 -address_a[9] => ram_block1a199.PORTAADDR9 -address_a[9] => ram_block1a200.PORTAADDR9 -address_a[9] => ram_block1a201.PORTAADDR9 -address_a[9] => ram_block1a202.PORTAADDR9 -address_a[9] => ram_block1a203.PORTAADDR9 -address_a[9] => ram_block1a204.PORTAADDR9 -address_a[9] => ram_block1a205.PORTAADDR9 -address_a[9] => ram_block1a206.PORTAADDR9 -address_a[9] => ram_block1a207.PORTAADDR9 -address_a[9] => ram_block1a208.PORTAADDR9 -address_a[9] => ram_block1a209.PORTAADDR9 -address_a[9] => ram_block1a210.PORTAADDR9 -address_a[9] => ram_block1a211.PORTAADDR9 -address_a[9] => ram_block1a212.PORTAADDR9 -address_a[9] => ram_block1a213.PORTAADDR9 -address_a[9] => ram_block1a214.PORTAADDR9 -address_a[9] => ram_block1a215.PORTAADDR9 -address_a[9] => ram_block1a216.PORTAADDR9 -address_a[9] => ram_block1a217.PORTAADDR9 -address_a[9] => ram_block1a218.PORTAADDR9 -address_a[9] => ram_block1a219.PORTAADDR9 -address_a[9] => ram_block1a220.PORTAADDR9 -address_a[9] => ram_block1a221.PORTAADDR9 -address_a[9] => ram_block1a222.PORTAADDR9 -address_a[9] => ram_block1a223.PORTAADDR9 -address_a[10] => ram_block1a0.PORTAADDR10 -address_a[10] => ram_block1a1.PORTAADDR10 -address_a[10] => ram_block1a2.PORTAADDR10 -address_a[10] => ram_block1a3.PORTAADDR10 -address_a[10] => ram_block1a4.PORTAADDR10 -address_a[10] => ram_block1a5.PORTAADDR10 -address_a[10] => ram_block1a6.PORTAADDR10 -address_a[10] => ram_block1a7.PORTAADDR10 -address_a[10] => ram_block1a8.PORTAADDR10 -address_a[10] => ram_block1a9.PORTAADDR10 -address_a[10] => ram_block1a10.PORTAADDR10 -address_a[10] => ram_block1a11.PORTAADDR10 -address_a[10] => ram_block1a12.PORTAADDR10 -address_a[10] => ram_block1a13.PORTAADDR10 -address_a[10] => ram_block1a14.PORTAADDR10 -address_a[10] => ram_block1a15.PORTAADDR10 -address_a[10] => ram_block1a16.PORTAADDR10 -address_a[10] => ram_block1a17.PORTAADDR10 -address_a[10] => ram_block1a18.PORTAADDR10 -address_a[10] => ram_block1a19.PORTAADDR10 -address_a[10] => ram_block1a20.PORTAADDR10 -address_a[10] => ram_block1a21.PORTAADDR10 -address_a[10] => ram_block1a22.PORTAADDR10 -address_a[10] => ram_block1a23.PORTAADDR10 -address_a[10] => ram_block1a24.PORTAADDR10 -address_a[10] => ram_block1a25.PORTAADDR10 -address_a[10] => ram_block1a26.PORTAADDR10 -address_a[10] => ram_block1a27.PORTAADDR10 -address_a[10] => ram_block1a28.PORTAADDR10 -address_a[10] => ram_block1a29.PORTAADDR10 -address_a[10] => ram_block1a30.PORTAADDR10 -address_a[10] => ram_block1a31.PORTAADDR10 -address_a[10] => ram_block1a32.PORTAADDR10 -address_a[10] => ram_block1a33.PORTAADDR10 -address_a[10] => ram_block1a34.PORTAADDR10 -address_a[10] => ram_block1a35.PORTAADDR10 -address_a[10] => ram_block1a36.PORTAADDR10 -address_a[10] => ram_block1a37.PORTAADDR10 -address_a[10] => ram_block1a38.PORTAADDR10 -address_a[10] => ram_block1a39.PORTAADDR10 -address_a[10] => ram_block1a40.PORTAADDR10 -address_a[10] => ram_block1a41.PORTAADDR10 -address_a[10] => ram_block1a42.PORTAADDR10 -address_a[10] => ram_block1a43.PORTAADDR10 -address_a[10] => ram_block1a44.PORTAADDR10 -address_a[10] => ram_block1a45.PORTAADDR10 -address_a[10] => ram_block1a46.PORTAADDR10 -address_a[10] => ram_block1a47.PORTAADDR10 -address_a[10] => ram_block1a48.PORTAADDR10 -address_a[10] => ram_block1a49.PORTAADDR10 -address_a[10] => ram_block1a50.PORTAADDR10 -address_a[10] => ram_block1a51.PORTAADDR10 -address_a[10] => ram_block1a52.PORTAADDR10 -address_a[10] => ram_block1a53.PORTAADDR10 -address_a[10] => ram_block1a54.PORTAADDR10 -address_a[10] => ram_block1a55.PORTAADDR10 -address_a[10] => ram_block1a56.PORTAADDR10 -address_a[10] => ram_block1a57.PORTAADDR10 -address_a[10] => ram_block1a58.PORTAADDR10 -address_a[10] => ram_block1a59.PORTAADDR10 -address_a[10] => ram_block1a60.PORTAADDR10 -address_a[10] => ram_block1a61.PORTAADDR10 -address_a[10] => ram_block1a62.PORTAADDR10 -address_a[10] => ram_block1a63.PORTAADDR10 -address_a[10] => ram_block1a64.PORTAADDR10 -address_a[10] => ram_block1a65.PORTAADDR10 -address_a[10] => ram_block1a66.PORTAADDR10 -address_a[10] => ram_block1a67.PORTAADDR10 -address_a[10] => ram_block1a68.PORTAADDR10 -address_a[10] => ram_block1a69.PORTAADDR10 -address_a[10] => ram_block1a70.PORTAADDR10 -address_a[10] => ram_block1a71.PORTAADDR10 -address_a[10] => ram_block1a72.PORTAADDR10 -address_a[10] => ram_block1a73.PORTAADDR10 -address_a[10] => ram_block1a74.PORTAADDR10 -address_a[10] => ram_block1a75.PORTAADDR10 -address_a[10] => ram_block1a76.PORTAADDR10 -address_a[10] => ram_block1a77.PORTAADDR10 -address_a[10] => ram_block1a78.PORTAADDR10 -address_a[10] => ram_block1a79.PORTAADDR10 -address_a[10] => ram_block1a80.PORTAADDR10 -address_a[10] => ram_block1a81.PORTAADDR10 -address_a[10] => ram_block1a82.PORTAADDR10 -address_a[10] => ram_block1a83.PORTAADDR10 -address_a[10] => ram_block1a84.PORTAADDR10 -address_a[10] => ram_block1a85.PORTAADDR10 -address_a[10] => ram_block1a86.PORTAADDR10 -address_a[10] => ram_block1a87.PORTAADDR10 -address_a[10] => ram_block1a88.PORTAADDR10 -address_a[10] => ram_block1a89.PORTAADDR10 -address_a[10] => ram_block1a90.PORTAADDR10 -address_a[10] => ram_block1a91.PORTAADDR10 -address_a[10] => ram_block1a92.PORTAADDR10 -address_a[10] => ram_block1a93.PORTAADDR10 -address_a[10] => ram_block1a94.PORTAADDR10 -address_a[10] => ram_block1a95.PORTAADDR10 -address_a[10] => ram_block1a96.PORTAADDR10 -address_a[10] => ram_block1a97.PORTAADDR10 -address_a[10] => ram_block1a98.PORTAADDR10 -address_a[10] => ram_block1a99.PORTAADDR10 -address_a[10] => ram_block1a100.PORTAADDR10 -address_a[10] => ram_block1a101.PORTAADDR10 -address_a[10] => ram_block1a102.PORTAADDR10 -address_a[10] => ram_block1a103.PORTAADDR10 -address_a[10] => ram_block1a104.PORTAADDR10 -address_a[10] => ram_block1a105.PORTAADDR10 -address_a[10] => ram_block1a106.PORTAADDR10 -address_a[10] => ram_block1a107.PORTAADDR10 -address_a[10] => ram_block1a108.PORTAADDR10 -address_a[10] => ram_block1a109.PORTAADDR10 -address_a[10] => ram_block1a110.PORTAADDR10 -address_a[10] => ram_block1a111.PORTAADDR10 -address_a[10] => ram_block1a112.PORTAADDR10 -address_a[10] => ram_block1a113.PORTAADDR10 -address_a[10] => ram_block1a114.PORTAADDR10 -address_a[10] => ram_block1a115.PORTAADDR10 -address_a[10] => ram_block1a116.PORTAADDR10 -address_a[10] => ram_block1a117.PORTAADDR10 -address_a[10] => ram_block1a118.PORTAADDR10 -address_a[10] => ram_block1a119.PORTAADDR10 -address_a[10] => ram_block1a120.PORTAADDR10 -address_a[10] => ram_block1a121.PORTAADDR10 -address_a[10] => ram_block1a122.PORTAADDR10 -address_a[10] => ram_block1a123.PORTAADDR10 -address_a[10] => ram_block1a124.PORTAADDR10 -address_a[10] => ram_block1a125.PORTAADDR10 -address_a[10] => ram_block1a126.PORTAADDR10 -address_a[10] => ram_block1a127.PORTAADDR10 -address_a[10] => ram_block1a128.PORTAADDR10 -address_a[10] => ram_block1a129.PORTAADDR10 -address_a[10] => ram_block1a130.PORTAADDR10 -address_a[10] => ram_block1a131.PORTAADDR10 -address_a[10] => ram_block1a132.PORTAADDR10 -address_a[10] => ram_block1a133.PORTAADDR10 -address_a[10] => ram_block1a134.PORTAADDR10 -address_a[10] => ram_block1a135.PORTAADDR10 -address_a[10] => ram_block1a136.PORTAADDR10 -address_a[10] => ram_block1a137.PORTAADDR10 -address_a[10] => ram_block1a138.PORTAADDR10 -address_a[10] => ram_block1a139.PORTAADDR10 -address_a[10] => ram_block1a140.PORTAADDR10 -address_a[10] => ram_block1a141.PORTAADDR10 -address_a[10] => ram_block1a142.PORTAADDR10 -address_a[10] => ram_block1a143.PORTAADDR10 -address_a[10] => ram_block1a144.PORTAADDR10 -address_a[10] => ram_block1a145.PORTAADDR10 -address_a[10] => ram_block1a146.PORTAADDR10 -address_a[10] => ram_block1a147.PORTAADDR10 -address_a[10] => ram_block1a148.PORTAADDR10 -address_a[10] => ram_block1a149.PORTAADDR10 -address_a[10] => ram_block1a150.PORTAADDR10 -address_a[10] => ram_block1a151.PORTAADDR10 -address_a[10] => ram_block1a152.PORTAADDR10 -address_a[10] => ram_block1a153.PORTAADDR10 -address_a[10] => ram_block1a154.PORTAADDR10 -address_a[10] => ram_block1a155.PORTAADDR10 -address_a[10] => ram_block1a156.PORTAADDR10 -address_a[10] => ram_block1a157.PORTAADDR10 -address_a[10] => ram_block1a158.PORTAADDR10 -address_a[10] => ram_block1a159.PORTAADDR10 -address_a[10] => ram_block1a160.PORTAADDR10 -address_a[10] => ram_block1a161.PORTAADDR10 -address_a[10] => ram_block1a162.PORTAADDR10 -address_a[10] => ram_block1a163.PORTAADDR10 -address_a[10] => ram_block1a164.PORTAADDR10 -address_a[10] => ram_block1a165.PORTAADDR10 -address_a[10] => ram_block1a166.PORTAADDR10 -address_a[10] => ram_block1a167.PORTAADDR10 -address_a[10] => ram_block1a168.PORTAADDR10 -address_a[10] => ram_block1a169.PORTAADDR10 -address_a[10] => ram_block1a170.PORTAADDR10 -address_a[10] => ram_block1a171.PORTAADDR10 -address_a[10] => ram_block1a172.PORTAADDR10 -address_a[10] => ram_block1a173.PORTAADDR10 -address_a[10] => ram_block1a174.PORTAADDR10 -address_a[10] => ram_block1a175.PORTAADDR10 -address_a[10] => ram_block1a176.PORTAADDR10 -address_a[10] => ram_block1a177.PORTAADDR10 -address_a[10] => ram_block1a178.PORTAADDR10 -address_a[10] => ram_block1a179.PORTAADDR10 -address_a[10] => ram_block1a180.PORTAADDR10 -address_a[10] => ram_block1a181.PORTAADDR10 -address_a[10] => ram_block1a182.PORTAADDR10 -address_a[10] => ram_block1a183.PORTAADDR10 -address_a[10] => ram_block1a184.PORTAADDR10 -address_a[10] => ram_block1a185.PORTAADDR10 -address_a[10] => ram_block1a186.PORTAADDR10 -address_a[10] => ram_block1a187.PORTAADDR10 -address_a[10] => ram_block1a188.PORTAADDR10 -address_a[10] => ram_block1a189.PORTAADDR10 -address_a[10] => ram_block1a190.PORTAADDR10 -address_a[10] => ram_block1a191.PORTAADDR10 -address_a[10] => ram_block1a192.PORTAADDR10 -address_a[10] => ram_block1a193.PORTAADDR10 -address_a[10] => ram_block1a194.PORTAADDR10 -address_a[10] => ram_block1a195.PORTAADDR10 -address_a[10] => ram_block1a196.PORTAADDR10 -address_a[10] => ram_block1a197.PORTAADDR10 -address_a[10] => ram_block1a198.PORTAADDR10 -address_a[10] => ram_block1a199.PORTAADDR10 -address_a[10] => ram_block1a200.PORTAADDR10 -address_a[10] => ram_block1a201.PORTAADDR10 -address_a[10] => ram_block1a202.PORTAADDR10 -address_a[10] => ram_block1a203.PORTAADDR10 -address_a[10] => ram_block1a204.PORTAADDR10 -address_a[10] => ram_block1a205.PORTAADDR10 -address_a[10] => ram_block1a206.PORTAADDR10 -address_a[10] => ram_block1a207.PORTAADDR10 -address_a[10] => ram_block1a208.PORTAADDR10 -address_a[10] => ram_block1a209.PORTAADDR10 -address_a[10] => ram_block1a210.PORTAADDR10 -address_a[10] => ram_block1a211.PORTAADDR10 -address_a[10] => ram_block1a212.PORTAADDR10 -address_a[10] => ram_block1a213.PORTAADDR10 -address_a[10] => ram_block1a214.PORTAADDR10 -address_a[10] => ram_block1a215.PORTAADDR10 -address_a[10] => ram_block1a216.PORTAADDR10 -address_a[10] => ram_block1a217.PORTAADDR10 -address_a[10] => ram_block1a218.PORTAADDR10 -address_a[10] => ram_block1a219.PORTAADDR10 -address_a[10] => ram_block1a220.PORTAADDR10 -address_a[10] => ram_block1a221.PORTAADDR10 -address_a[10] => ram_block1a222.PORTAADDR10 -address_a[10] => ram_block1a223.PORTAADDR10 -address_a[11] => ram_block1a0.PORTAADDR11 -address_a[11] => ram_block1a1.PORTAADDR11 -address_a[11] => ram_block1a2.PORTAADDR11 -address_a[11] => ram_block1a3.PORTAADDR11 -address_a[11] => ram_block1a4.PORTAADDR11 -address_a[11] => ram_block1a5.PORTAADDR11 -address_a[11] => ram_block1a6.PORTAADDR11 -address_a[11] => ram_block1a7.PORTAADDR11 -address_a[11] => ram_block1a8.PORTAADDR11 -address_a[11] => ram_block1a9.PORTAADDR11 -address_a[11] => ram_block1a10.PORTAADDR11 -address_a[11] => ram_block1a11.PORTAADDR11 -address_a[11] => ram_block1a12.PORTAADDR11 -address_a[11] => ram_block1a13.PORTAADDR11 -address_a[11] => ram_block1a14.PORTAADDR11 -address_a[11] => ram_block1a15.PORTAADDR11 -address_a[11] => ram_block1a16.PORTAADDR11 -address_a[11] => ram_block1a17.PORTAADDR11 -address_a[11] => ram_block1a18.PORTAADDR11 -address_a[11] => ram_block1a19.PORTAADDR11 -address_a[11] => ram_block1a20.PORTAADDR11 -address_a[11] => ram_block1a21.PORTAADDR11 -address_a[11] => ram_block1a22.PORTAADDR11 -address_a[11] => ram_block1a23.PORTAADDR11 -address_a[11] => ram_block1a24.PORTAADDR11 -address_a[11] => ram_block1a25.PORTAADDR11 -address_a[11] => ram_block1a26.PORTAADDR11 -address_a[11] => ram_block1a27.PORTAADDR11 -address_a[11] => ram_block1a28.PORTAADDR11 -address_a[11] => ram_block1a29.PORTAADDR11 -address_a[11] => ram_block1a30.PORTAADDR11 -address_a[11] => ram_block1a31.PORTAADDR11 -address_a[11] => ram_block1a32.PORTAADDR11 -address_a[11] => ram_block1a33.PORTAADDR11 -address_a[11] => ram_block1a34.PORTAADDR11 -address_a[11] => ram_block1a35.PORTAADDR11 -address_a[11] => ram_block1a36.PORTAADDR11 -address_a[11] => ram_block1a37.PORTAADDR11 -address_a[11] => ram_block1a38.PORTAADDR11 -address_a[11] => ram_block1a39.PORTAADDR11 -address_a[11] => ram_block1a40.PORTAADDR11 -address_a[11] => ram_block1a41.PORTAADDR11 -address_a[11] => ram_block1a42.PORTAADDR11 -address_a[11] => ram_block1a43.PORTAADDR11 -address_a[11] => ram_block1a44.PORTAADDR11 -address_a[11] => ram_block1a45.PORTAADDR11 -address_a[11] => ram_block1a46.PORTAADDR11 -address_a[11] => ram_block1a47.PORTAADDR11 -address_a[11] => ram_block1a48.PORTAADDR11 -address_a[11] => ram_block1a49.PORTAADDR11 -address_a[11] => ram_block1a50.PORTAADDR11 -address_a[11] => ram_block1a51.PORTAADDR11 -address_a[11] => ram_block1a52.PORTAADDR11 -address_a[11] => ram_block1a53.PORTAADDR11 -address_a[11] => ram_block1a54.PORTAADDR11 -address_a[11] => ram_block1a55.PORTAADDR11 -address_a[11] => ram_block1a56.PORTAADDR11 -address_a[11] => ram_block1a57.PORTAADDR11 -address_a[11] => ram_block1a58.PORTAADDR11 -address_a[11] => ram_block1a59.PORTAADDR11 -address_a[11] => ram_block1a60.PORTAADDR11 -address_a[11] => ram_block1a61.PORTAADDR11 -address_a[11] => ram_block1a62.PORTAADDR11 -address_a[11] => ram_block1a63.PORTAADDR11 -address_a[11] => ram_block1a64.PORTAADDR11 -address_a[11] => ram_block1a65.PORTAADDR11 -address_a[11] => ram_block1a66.PORTAADDR11 -address_a[11] => ram_block1a67.PORTAADDR11 -address_a[11] => ram_block1a68.PORTAADDR11 -address_a[11] => ram_block1a69.PORTAADDR11 -address_a[11] => ram_block1a70.PORTAADDR11 -address_a[11] => ram_block1a71.PORTAADDR11 -address_a[11] => ram_block1a72.PORTAADDR11 -address_a[11] => ram_block1a73.PORTAADDR11 -address_a[11] => ram_block1a74.PORTAADDR11 -address_a[11] => ram_block1a75.PORTAADDR11 -address_a[11] => ram_block1a76.PORTAADDR11 -address_a[11] => ram_block1a77.PORTAADDR11 -address_a[11] => ram_block1a78.PORTAADDR11 -address_a[11] => ram_block1a79.PORTAADDR11 -address_a[11] => ram_block1a80.PORTAADDR11 -address_a[11] => ram_block1a81.PORTAADDR11 -address_a[11] => ram_block1a82.PORTAADDR11 -address_a[11] => ram_block1a83.PORTAADDR11 -address_a[11] => ram_block1a84.PORTAADDR11 -address_a[11] => ram_block1a85.PORTAADDR11 -address_a[11] => ram_block1a86.PORTAADDR11 -address_a[11] => ram_block1a87.PORTAADDR11 -address_a[11] => ram_block1a88.PORTAADDR11 -address_a[11] => ram_block1a89.PORTAADDR11 -address_a[11] => ram_block1a90.PORTAADDR11 -address_a[11] => ram_block1a91.PORTAADDR11 -address_a[11] => ram_block1a92.PORTAADDR11 -address_a[11] => ram_block1a93.PORTAADDR11 -address_a[11] => ram_block1a94.PORTAADDR11 -address_a[11] => ram_block1a95.PORTAADDR11 -address_a[11] => ram_block1a96.PORTAADDR11 -address_a[11] => ram_block1a97.PORTAADDR11 -address_a[11] => ram_block1a98.PORTAADDR11 -address_a[11] => ram_block1a99.PORTAADDR11 -address_a[11] => ram_block1a100.PORTAADDR11 -address_a[11] => ram_block1a101.PORTAADDR11 -address_a[11] => ram_block1a102.PORTAADDR11 -address_a[11] => ram_block1a103.PORTAADDR11 -address_a[11] => ram_block1a104.PORTAADDR11 -address_a[11] => ram_block1a105.PORTAADDR11 -address_a[11] => ram_block1a106.PORTAADDR11 -address_a[11] => ram_block1a107.PORTAADDR11 -address_a[11] => ram_block1a108.PORTAADDR11 -address_a[11] => ram_block1a109.PORTAADDR11 -address_a[11] => ram_block1a110.PORTAADDR11 -address_a[11] => ram_block1a111.PORTAADDR11 -address_a[11] => ram_block1a112.PORTAADDR11 -address_a[11] => ram_block1a113.PORTAADDR11 -address_a[11] => ram_block1a114.PORTAADDR11 -address_a[11] => ram_block1a115.PORTAADDR11 -address_a[11] => ram_block1a116.PORTAADDR11 -address_a[11] => ram_block1a117.PORTAADDR11 -address_a[11] => ram_block1a118.PORTAADDR11 -address_a[11] => ram_block1a119.PORTAADDR11 -address_a[11] => ram_block1a120.PORTAADDR11 -address_a[11] => ram_block1a121.PORTAADDR11 -address_a[11] => ram_block1a122.PORTAADDR11 -address_a[11] => ram_block1a123.PORTAADDR11 -address_a[11] => ram_block1a124.PORTAADDR11 -address_a[11] => ram_block1a125.PORTAADDR11 -address_a[11] => ram_block1a126.PORTAADDR11 -address_a[11] => ram_block1a127.PORTAADDR11 -address_a[11] => ram_block1a128.PORTAADDR11 -address_a[11] => ram_block1a129.PORTAADDR11 -address_a[11] => ram_block1a130.PORTAADDR11 -address_a[11] => ram_block1a131.PORTAADDR11 -address_a[11] => ram_block1a132.PORTAADDR11 -address_a[11] => ram_block1a133.PORTAADDR11 -address_a[11] => ram_block1a134.PORTAADDR11 -address_a[11] => ram_block1a135.PORTAADDR11 -address_a[11] => ram_block1a136.PORTAADDR11 -address_a[11] => ram_block1a137.PORTAADDR11 -address_a[11] => ram_block1a138.PORTAADDR11 -address_a[11] => ram_block1a139.PORTAADDR11 -address_a[11] => ram_block1a140.PORTAADDR11 -address_a[11] => ram_block1a141.PORTAADDR11 -address_a[11] => ram_block1a142.PORTAADDR11 -address_a[11] => ram_block1a143.PORTAADDR11 -address_a[11] => ram_block1a144.PORTAADDR11 -address_a[11] => ram_block1a145.PORTAADDR11 -address_a[11] => ram_block1a146.PORTAADDR11 -address_a[11] => ram_block1a147.PORTAADDR11 -address_a[11] => ram_block1a148.PORTAADDR11 -address_a[11] => ram_block1a149.PORTAADDR11 -address_a[11] => ram_block1a150.PORTAADDR11 -address_a[11] => ram_block1a151.PORTAADDR11 -address_a[11] => ram_block1a152.PORTAADDR11 -address_a[11] => ram_block1a153.PORTAADDR11 -address_a[11] => ram_block1a154.PORTAADDR11 -address_a[11] => ram_block1a155.PORTAADDR11 -address_a[11] => ram_block1a156.PORTAADDR11 -address_a[11] => ram_block1a157.PORTAADDR11 -address_a[11] => ram_block1a158.PORTAADDR11 -address_a[11] => ram_block1a159.PORTAADDR11 -address_a[11] => ram_block1a160.PORTAADDR11 -address_a[11] => ram_block1a161.PORTAADDR11 -address_a[11] => ram_block1a162.PORTAADDR11 -address_a[11] => ram_block1a163.PORTAADDR11 -address_a[11] => ram_block1a164.PORTAADDR11 -address_a[11] => ram_block1a165.PORTAADDR11 -address_a[11] => ram_block1a166.PORTAADDR11 -address_a[11] => ram_block1a167.PORTAADDR11 -address_a[11] => ram_block1a168.PORTAADDR11 -address_a[11] => ram_block1a169.PORTAADDR11 -address_a[11] => ram_block1a170.PORTAADDR11 -address_a[11] => ram_block1a171.PORTAADDR11 -address_a[11] => ram_block1a172.PORTAADDR11 -address_a[11] => ram_block1a173.PORTAADDR11 -address_a[11] => ram_block1a174.PORTAADDR11 -address_a[11] => ram_block1a175.PORTAADDR11 -address_a[11] => ram_block1a176.PORTAADDR11 -address_a[11] => ram_block1a177.PORTAADDR11 -address_a[11] => ram_block1a178.PORTAADDR11 -address_a[11] => ram_block1a179.PORTAADDR11 -address_a[11] => ram_block1a180.PORTAADDR11 -address_a[11] => ram_block1a181.PORTAADDR11 -address_a[11] => ram_block1a182.PORTAADDR11 -address_a[11] => ram_block1a183.PORTAADDR11 -address_a[11] => ram_block1a184.PORTAADDR11 -address_a[11] => ram_block1a185.PORTAADDR11 -address_a[11] => ram_block1a186.PORTAADDR11 -address_a[11] => ram_block1a187.PORTAADDR11 -address_a[11] => ram_block1a188.PORTAADDR11 -address_a[11] => ram_block1a189.PORTAADDR11 -address_a[11] => ram_block1a190.PORTAADDR11 -address_a[11] => ram_block1a191.PORTAADDR11 -address_a[12] => ram_block1a0.PORTAADDR12 -address_a[12] => ram_block1a1.PORTAADDR12 -address_a[12] => ram_block1a2.PORTAADDR12 -address_a[12] => ram_block1a3.PORTAADDR12 -address_a[12] => ram_block1a4.PORTAADDR12 -address_a[12] => ram_block1a5.PORTAADDR12 -address_a[12] => ram_block1a6.PORTAADDR12 -address_a[12] => ram_block1a7.PORTAADDR12 -address_a[12] => ram_block1a8.PORTAADDR12 -address_a[12] => ram_block1a9.PORTAADDR12 -address_a[12] => ram_block1a10.PORTAADDR12 -address_a[12] => ram_block1a11.PORTAADDR12 -address_a[12] => ram_block1a12.PORTAADDR12 -address_a[12] => ram_block1a13.PORTAADDR12 -address_a[12] => ram_block1a14.PORTAADDR12 -address_a[12] => ram_block1a15.PORTAADDR12 -address_a[12] => ram_block1a16.PORTAADDR12 -address_a[12] => ram_block1a17.PORTAADDR12 -address_a[12] => ram_block1a18.PORTAADDR12 -address_a[12] => ram_block1a19.PORTAADDR12 -address_a[12] => ram_block1a20.PORTAADDR12 -address_a[12] => ram_block1a21.PORTAADDR12 -address_a[12] => ram_block1a22.PORTAADDR12 -address_a[12] => ram_block1a23.PORTAADDR12 -address_a[12] => ram_block1a24.PORTAADDR12 -address_a[12] => ram_block1a25.PORTAADDR12 -address_a[12] => ram_block1a26.PORTAADDR12 -address_a[12] => ram_block1a27.PORTAADDR12 -address_a[12] => ram_block1a28.PORTAADDR12 -address_a[12] => ram_block1a29.PORTAADDR12 -address_a[12] => ram_block1a30.PORTAADDR12 -address_a[12] => ram_block1a31.PORTAADDR12 -address_a[12] => ram_block1a32.PORTAADDR12 -address_a[12] => ram_block1a33.PORTAADDR12 -address_a[12] => ram_block1a34.PORTAADDR12 -address_a[12] => ram_block1a35.PORTAADDR12 -address_a[12] => ram_block1a36.PORTAADDR12 -address_a[12] => ram_block1a37.PORTAADDR12 -address_a[12] => ram_block1a38.PORTAADDR12 -address_a[12] => ram_block1a39.PORTAADDR12 -address_a[12] => ram_block1a40.PORTAADDR12 -address_a[12] => ram_block1a41.PORTAADDR12 -address_a[12] => ram_block1a42.PORTAADDR12 -address_a[12] => ram_block1a43.PORTAADDR12 -address_a[12] => ram_block1a44.PORTAADDR12 -address_a[12] => ram_block1a45.PORTAADDR12 -address_a[12] => ram_block1a46.PORTAADDR12 -address_a[12] => ram_block1a47.PORTAADDR12 -address_a[12] => ram_block1a48.PORTAADDR12 -address_a[12] => ram_block1a49.PORTAADDR12 -address_a[12] => ram_block1a50.PORTAADDR12 -address_a[12] => ram_block1a51.PORTAADDR12 -address_a[12] => ram_block1a52.PORTAADDR12 -address_a[12] => ram_block1a53.PORTAADDR12 -address_a[12] => ram_block1a54.PORTAADDR12 -address_a[12] => ram_block1a55.PORTAADDR12 -address_a[12] => ram_block1a56.PORTAADDR12 -address_a[12] => ram_block1a57.PORTAADDR12 -address_a[12] => ram_block1a58.PORTAADDR12 -address_a[12] => ram_block1a59.PORTAADDR12 -address_a[12] => ram_block1a60.PORTAADDR12 -address_a[12] => ram_block1a61.PORTAADDR12 -address_a[12] => ram_block1a62.PORTAADDR12 -address_a[12] => ram_block1a63.PORTAADDR12 -address_a[12] => ram_block1a64.PORTAADDR12 -address_a[12] => ram_block1a65.PORTAADDR12 -address_a[12] => ram_block1a66.PORTAADDR12 -address_a[12] => ram_block1a67.PORTAADDR12 -address_a[12] => ram_block1a68.PORTAADDR12 -address_a[12] => ram_block1a69.PORTAADDR12 -address_a[12] => ram_block1a70.PORTAADDR12 -address_a[12] => ram_block1a71.PORTAADDR12 -address_a[12] => ram_block1a72.PORTAADDR12 -address_a[12] => ram_block1a73.PORTAADDR12 -address_a[12] => ram_block1a74.PORTAADDR12 -address_a[12] => ram_block1a75.PORTAADDR12 -address_a[12] => ram_block1a76.PORTAADDR12 -address_a[12] => ram_block1a77.PORTAADDR12 -address_a[12] => ram_block1a78.PORTAADDR12 -address_a[12] => ram_block1a79.PORTAADDR12 -address_a[12] => ram_block1a80.PORTAADDR12 -address_a[12] => ram_block1a81.PORTAADDR12 -address_a[12] => ram_block1a82.PORTAADDR12 -address_a[12] => ram_block1a83.PORTAADDR12 -address_a[12] => ram_block1a84.PORTAADDR12 -address_a[12] => ram_block1a85.PORTAADDR12 -address_a[12] => ram_block1a86.PORTAADDR12 -address_a[12] => ram_block1a87.PORTAADDR12 -address_a[12] => ram_block1a88.PORTAADDR12 -address_a[12] => ram_block1a89.PORTAADDR12 -address_a[12] => ram_block1a90.PORTAADDR12 -address_a[12] => ram_block1a91.PORTAADDR12 -address_a[12] => ram_block1a92.PORTAADDR12 -address_a[12] => ram_block1a93.PORTAADDR12 -address_a[12] => ram_block1a94.PORTAADDR12 -address_a[12] => ram_block1a95.PORTAADDR12 -address_a[12] => ram_block1a96.PORTAADDR12 -address_a[12] => ram_block1a97.PORTAADDR12 -address_a[12] => ram_block1a98.PORTAADDR12 -address_a[12] => ram_block1a99.PORTAADDR12 -address_a[12] => ram_block1a100.PORTAADDR12 -address_a[12] => ram_block1a101.PORTAADDR12 -address_a[12] => ram_block1a102.PORTAADDR12 -address_a[12] => ram_block1a103.PORTAADDR12 -address_a[12] => ram_block1a104.PORTAADDR12 -address_a[12] => ram_block1a105.PORTAADDR12 -address_a[12] => ram_block1a106.PORTAADDR12 -address_a[12] => ram_block1a107.PORTAADDR12 -address_a[12] => ram_block1a108.PORTAADDR12 -address_a[12] => ram_block1a109.PORTAADDR12 -address_a[12] => ram_block1a110.PORTAADDR12 -address_a[12] => ram_block1a111.PORTAADDR12 -address_a[12] => ram_block1a112.PORTAADDR12 -address_a[12] => ram_block1a113.PORTAADDR12 -address_a[12] => ram_block1a114.PORTAADDR12 -address_a[12] => ram_block1a115.PORTAADDR12 -address_a[12] => ram_block1a116.PORTAADDR12 -address_a[12] => ram_block1a117.PORTAADDR12 -address_a[12] => ram_block1a118.PORTAADDR12 -address_a[12] => ram_block1a119.PORTAADDR12 -address_a[12] => ram_block1a120.PORTAADDR12 -address_a[12] => ram_block1a121.PORTAADDR12 -address_a[12] => ram_block1a122.PORTAADDR12 -address_a[12] => ram_block1a123.PORTAADDR12 -address_a[12] => ram_block1a124.PORTAADDR12 -address_a[12] => ram_block1a125.PORTAADDR12 -address_a[12] => ram_block1a126.PORTAADDR12 -address_a[12] => ram_block1a127.PORTAADDR12 -address_a[12] => ram_block1a128.PORTAADDR12 -address_a[12] => ram_block1a129.PORTAADDR12 -address_a[12] => ram_block1a130.PORTAADDR12 -address_a[12] => ram_block1a131.PORTAADDR12 -address_a[12] => ram_block1a132.PORTAADDR12 -address_a[12] => ram_block1a133.PORTAADDR12 -address_a[12] => ram_block1a134.PORTAADDR12 -address_a[12] => ram_block1a135.PORTAADDR12 -address_a[12] => ram_block1a136.PORTAADDR12 -address_a[12] => ram_block1a137.PORTAADDR12 -address_a[12] => ram_block1a138.PORTAADDR12 -address_a[12] => ram_block1a139.PORTAADDR12 -address_a[12] => ram_block1a140.PORTAADDR12 -address_a[12] => ram_block1a141.PORTAADDR12 -address_a[12] => ram_block1a142.PORTAADDR12 -address_a[12] => ram_block1a143.PORTAADDR12 -address_a[12] => ram_block1a144.PORTAADDR12 -address_a[12] => ram_block1a145.PORTAADDR12 -address_a[12] => ram_block1a146.PORTAADDR12 -address_a[12] => ram_block1a147.PORTAADDR12 -address_a[12] => ram_block1a148.PORTAADDR12 -address_a[12] => ram_block1a149.PORTAADDR12 -address_a[12] => ram_block1a150.PORTAADDR12 -address_a[12] => ram_block1a151.PORTAADDR12 -address_a[12] => ram_block1a152.PORTAADDR12 -address_a[12] => ram_block1a153.PORTAADDR12 -address_a[12] => ram_block1a154.PORTAADDR12 -address_a[12] => ram_block1a155.PORTAADDR12 -address_a[12] => ram_block1a156.PORTAADDR12 -address_a[12] => ram_block1a157.PORTAADDR12 -address_a[12] => ram_block1a158.PORTAADDR12 -address_a[12] => ram_block1a159.PORTAADDR12 -address_a[12] => ram_block1a160.PORTAADDR12 -address_a[12] => ram_block1a161.PORTAADDR12 -address_a[12] => ram_block1a162.PORTAADDR12 -address_a[12] => ram_block1a163.PORTAADDR12 -address_a[12] => ram_block1a164.PORTAADDR12 -address_a[12] => ram_block1a165.PORTAADDR12 -address_a[12] => ram_block1a166.PORTAADDR12 -address_a[12] => ram_block1a167.PORTAADDR12 -address_a[12] => ram_block1a168.PORTAADDR12 -address_a[12] => ram_block1a169.PORTAADDR12 -address_a[12] => ram_block1a170.PORTAADDR12 -address_a[12] => ram_block1a171.PORTAADDR12 -address_a[12] => ram_block1a172.PORTAADDR12 -address_a[12] => ram_block1a173.PORTAADDR12 -address_a[12] => ram_block1a174.PORTAADDR12 -address_a[12] => ram_block1a175.PORTAADDR12 -address_a[12] => ram_block1a176.PORTAADDR12 -address_a[12] => ram_block1a177.PORTAADDR12 -address_a[12] => ram_block1a178.PORTAADDR12 -address_a[12] => ram_block1a179.PORTAADDR12 -address_a[12] => ram_block1a180.PORTAADDR12 -address_a[12] => ram_block1a181.PORTAADDR12 -address_a[12] => ram_block1a182.PORTAADDR12 -address_a[12] => ram_block1a183.PORTAADDR12 -address_a[12] => ram_block1a184.PORTAADDR12 -address_a[12] => ram_block1a185.PORTAADDR12 -address_a[12] => ram_block1a186.PORTAADDR12 -address_a[12] => ram_block1a187.PORTAADDR12 -address_a[12] => ram_block1a188.PORTAADDR12 -address_a[12] => ram_block1a189.PORTAADDR12 -address_a[12] => ram_block1a190.PORTAADDR12 -address_a[12] => ram_block1a191.PORTAADDR12 -address_a[13] => address_reg_a[0].DATAIN -address_a[13] => decode_qsa:decode3.data[0] -address_a[14] => address_reg_a[1].DATAIN -address_a[14] => decode_qsa:decode3.data[1] -address_a[15] => address_reg_a[2].DATAIN -address_a[15] => decode_qsa:decode3.data[2] -byteena_a[0] => ram_block1a0.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a1.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a2.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a3.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a4.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a5.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a6.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a7.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a32.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a33.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a34.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a35.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a36.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a37.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a38.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a39.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a64.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a65.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a66.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a67.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a68.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a69.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a70.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a71.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a96.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a97.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a98.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a99.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a100.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a101.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a102.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a103.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a128.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a129.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a130.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a131.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a132.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a133.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a134.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a135.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a160.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a161.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a162.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a163.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a164.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a165.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a166.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a167.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a192.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a193.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a194.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a195.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a196.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a197.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a198.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a199.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a8.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a9.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a10.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a11.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a12.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a13.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a14.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a15.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a40.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a41.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a42.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a43.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a44.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a45.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a46.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a47.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a72.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a73.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a74.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a75.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a76.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a77.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a78.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a79.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a104.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a105.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a106.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a107.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a108.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a109.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a110.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a111.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a136.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a137.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a138.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a139.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a140.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a141.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a142.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a143.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a168.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a169.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a170.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a171.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a172.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a173.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a174.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a175.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a200.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a201.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a202.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a203.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a204.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a205.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a206.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a207.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a16.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a17.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a18.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a19.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a20.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a21.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a22.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a23.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a48.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a49.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a50.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a51.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a52.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a53.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a54.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a55.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a80.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a81.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a82.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a83.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a84.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a85.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a86.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a87.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a112.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a113.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a114.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a115.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a116.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a117.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a118.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a119.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a144.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a145.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a146.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a147.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a148.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a149.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a150.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a151.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a176.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a177.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a178.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a179.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a180.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a181.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a182.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a183.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a208.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a209.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a210.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a211.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a212.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a213.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a214.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a215.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a24.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a25.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a26.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a27.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a28.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a29.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a30.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a31.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a56.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a57.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a58.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a59.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a60.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a61.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a62.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a63.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a88.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a89.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a90.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a91.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a92.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a93.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a94.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a95.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a120.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a121.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a122.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a123.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a124.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a125.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a126.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a127.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a152.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a153.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a154.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a155.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a156.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a157.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a158.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a159.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a184.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a185.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a186.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a187.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a188.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a189.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a190.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a191.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a216.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a217.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a218.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a219.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a220.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a221.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a222.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a223.PORTABYTEENAMASKS -clock0 => ram_block1a0.CLK0 -clock0 => ram_block1a1.CLK0 -clock0 => ram_block1a2.CLK0 -clock0 => ram_block1a3.CLK0 -clock0 => ram_block1a4.CLK0 -clock0 => ram_block1a5.CLK0 -clock0 => ram_block1a6.CLK0 -clock0 => ram_block1a7.CLK0 -clock0 => ram_block1a8.CLK0 -clock0 => ram_block1a9.CLK0 -clock0 => ram_block1a10.CLK0 -clock0 => ram_block1a11.CLK0 -clock0 => ram_block1a12.CLK0 -clock0 => ram_block1a13.CLK0 -clock0 => ram_block1a14.CLK0 -clock0 => ram_block1a15.CLK0 -clock0 => ram_block1a16.CLK0 -clock0 => ram_block1a17.CLK0 -clock0 => ram_block1a18.CLK0 -clock0 => ram_block1a19.CLK0 -clock0 => ram_block1a20.CLK0 -clock0 => ram_block1a21.CLK0 -clock0 => ram_block1a22.CLK0 -clock0 => ram_block1a23.CLK0 -clock0 => ram_block1a24.CLK0 -clock0 => ram_block1a25.CLK0 -clock0 => ram_block1a26.CLK0 -clock0 => ram_block1a27.CLK0 -clock0 => ram_block1a28.CLK0 -clock0 => ram_block1a29.CLK0 -clock0 => ram_block1a30.CLK0 -clock0 => ram_block1a31.CLK0 -clock0 => ram_block1a32.CLK0 -clock0 => ram_block1a33.CLK0 -clock0 => ram_block1a34.CLK0 -clock0 => ram_block1a35.CLK0 -clock0 => ram_block1a36.CLK0 -clock0 => ram_block1a37.CLK0 -clock0 => ram_block1a38.CLK0 -clock0 => ram_block1a39.CLK0 -clock0 => ram_block1a40.CLK0 -clock0 => ram_block1a41.CLK0 -clock0 => ram_block1a42.CLK0 -clock0 => ram_block1a43.CLK0 -clock0 => ram_block1a44.CLK0 -clock0 => ram_block1a45.CLK0 -clock0 => ram_block1a46.CLK0 -clock0 => ram_block1a47.CLK0 -clock0 => ram_block1a48.CLK0 -clock0 => ram_block1a49.CLK0 -clock0 => ram_block1a50.CLK0 -clock0 => ram_block1a51.CLK0 -clock0 => ram_block1a52.CLK0 -clock0 => ram_block1a53.CLK0 -clock0 => ram_block1a54.CLK0 -clock0 => ram_block1a55.CLK0 -clock0 => ram_block1a56.CLK0 -clock0 => ram_block1a57.CLK0 -clock0 => ram_block1a58.CLK0 -clock0 => ram_block1a59.CLK0 -clock0 => ram_block1a60.CLK0 -clock0 => ram_block1a61.CLK0 -clock0 => ram_block1a62.CLK0 -clock0 => ram_block1a63.CLK0 -clock0 => ram_block1a64.CLK0 -clock0 => ram_block1a65.CLK0 -clock0 => ram_block1a66.CLK0 -clock0 => ram_block1a67.CLK0 -clock0 => ram_block1a68.CLK0 -clock0 => ram_block1a69.CLK0 -clock0 => ram_block1a70.CLK0 -clock0 => ram_block1a71.CLK0 -clock0 => ram_block1a72.CLK0 -clock0 => ram_block1a73.CLK0 -clock0 => ram_block1a74.CLK0 -clock0 => ram_block1a75.CLK0 -clock0 => ram_block1a76.CLK0 -clock0 => ram_block1a77.CLK0 -clock0 => ram_block1a78.CLK0 -clock0 => ram_block1a79.CLK0 -clock0 => ram_block1a80.CLK0 -clock0 => ram_block1a81.CLK0 -clock0 => ram_block1a82.CLK0 -clock0 => ram_block1a83.CLK0 -clock0 => ram_block1a84.CLK0 -clock0 => ram_block1a85.CLK0 -clock0 => ram_block1a86.CLK0 -clock0 => ram_block1a87.CLK0 -clock0 => ram_block1a88.CLK0 -clock0 => ram_block1a89.CLK0 -clock0 => ram_block1a90.CLK0 -clock0 => ram_block1a91.CLK0 -clock0 => ram_block1a92.CLK0 -clock0 => ram_block1a93.CLK0 -clock0 => ram_block1a94.CLK0 -clock0 => ram_block1a95.CLK0 -clock0 => ram_block1a96.CLK0 -clock0 => ram_block1a97.CLK0 -clock0 => ram_block1a98.CLK0 -clock0 => ram_block1a99.CLK0 -clock0 => ram_block1a100.CLK0 -clock0 => ram_block1a101.CLK0 -clock0 => ram_block1a102.CLK0 -clock0 => ram_block1a103.CLK0 -clock0 => ram_block1a104.CLK0 -clock0 => ram_block1a105.CLK0 -clock0 => ram_block1a106.CLK0 -clock0 => ram_block1a107.CLK0 -clock0 => ram_block1a108.CLK0 -clock0 => ram_block1a109.CLK0 -clock0 => ram_block1a110.CLK0 -clock0 => ram_block1a111.CLK0 -clock0 => ram_block1a112.CLK0 -clock0 => ram_block1a113.CLK0 -clock0 => ram_block1a114.CLK0 -clock0 => ram_block1a115.CLK0 -clock0 => ram_block1a116.CLK0 -clock0 => ram_block1a117.CLK0 -clock0 => ram_block1a118.CLK0 -clock0 => ram_block1a119.CLK0 -clock0 => ram_block1a120.CLK0 -clock0 => ram_block1a121.CLK0 -clock0 => ram_block1a122.CLK0 -clock0 => ram_block1a123.CLK0 -clock0 => ram_block1a124.CLK0 -clock0 => ram_block1a125.CLK0 -clock0 => ram_block1a126.CLK0 -clock0 => ram_block1a127.CLK0 -clock0 => ram_block1a128.CLK0 -clock0 => ram_block1a129.CLK0 -clock0 => ram_block1a130.CLK0 -clock0 => ram_block1a131.CLK0 -clock0 => ram_block1a132.CLK0 -clock0 => ram_block1a133.CLK0 -clock0 => ram_block1a134.CLK0 -clock0 => ram_block1a135.CLK0 -clock0 => ram_block1a136.CLK0 -clock0 => ram_block1a137.CLK0 -clock0 => ram_block1a138.CLK0 -clock0 => ram_block1a139.CLK0 -clock0 => ram_block1a140.CLK0 -clock0 => ram_block1a141.CLK0 -clock0 => ram_block1a142.CLK0 -clock0 => ram_block1a143.CLK0 -clock0 => ram_block1a144.CLK0 -clock0 => ram_block1a145.CLK0 -clock0 => ram_block1a146.CLK0 -clock0 => ram_block1a147.CLK0 -clock0 => ram_block1a148.CLK0 -clock0 => ram_block1a149.CLK0 -clock0 => ram_block1a150.CLK0 -clock0 => ram_block1a151.CLK0 -clock0 => ram_block1a152.CLK0 -clock0 => ram_block1a153.CLK0 -clock0 => ram_block1a154.CLK0 -clock0 => ram_block1a155.CLK0 -clock0 => ram_block1a156.CLK0 -clock0 => ram_block1a157.CLK0 -clock0 => ram_block1a158.CLK0 -clock0 => ram_block1a159.CLK0 -clock0 => ram_block1a160.CLK0 -clock0 => ram_block1a161.CLK0 -clock0 => ram_block1a162.CLK0 -clock0 => ram_block1a163.CLK0 -clock0 => ram_block1a164.CLK0 -clock0 => ram_block1a165.CLK0 -clock0 => ram_block1a166.CLK0 -clock0 => ram_block1a167.CLK0 -clock0 => ram_block1a168.CLK0 -clock0 => ram_block1a169.CLK0 -clock0 => ram_block1a170.CLK0 -clock0 => ram_block1a171.CLK0 -clock0 => ram_block1a172.CLK0 -clock0 => ram_block1a173.CLK0 -clock0 => ram_block1a174.CLK0 -clock0 => ram_block1a175.CLK0 -clock0 => ram_block1a176.CLK0 -clock0 => ram_block1a177.CLK0 -clock0 => ram_block1a178.CLK0 -clock0 => ram_block1a179.CLK0 -clock0 => ram_block1a180.CLK0 -clock0 => ram_block1a181.CLK0 -clock0 => ram_block1a182.CLK0 -clock0 => ram_block1a183.CLK0 -clock0 => ram_block1a184.CLK0 -clock0 => ram_block1a185.CLK0 -clock0 => ram_block1a186.CLK0 -clock0 => ram_block1a187.CLK0 -clock0 => ram_block1a188.CLK0 -clock0 => ram_block1a189.CLK0 -clock0 => ram_block1a190.CLK0 -clock0 => ram_block1a191.CLK0 -clock0 => ram_block1a192.CLK0 -clock0 => ram_block1a193.CLK0 -clock0 => ram_block1a194.CLK0 -clock0 => ram_block1a195.CLK0 -clock0 => ram_block1a196.CLK0 -clock0 => ram_block1a197.CLK0 -clock0 => ram_block1a198.CLK0 -clock0 => ram_block1a199.CLK0 -clock0 => ram_block1a200.CLK0 -clock0 => ram_block1a201.CLK0 -clock0 => ram_block1a202.CLK0 -clock0 => ram_block1a203.CLK0 -clock0 => ram_block1a204.CLK0 -clock0 => ram_block1a205.CLK0 -clock0 => ram_block1a206.CLK0 -clock0 => ram_block1a207.CLK0 -clock0 => ram_block1a208.CLK0 -clock0 => ram_block1a209.CLK0 -clock0 => ram_block1a210.CLK0 -clock0 => ram_block1a211.CLK0 -clock0 => ram_block1a212.CLK0 -clock0 => ram_block1a213.CLK0 -clock0 => ram_block1a214.CLK0 -clock0 => ram_block1a215.CLK0 -clock0 => ram_block1a216.CLK0 -clock0 => ram_block1a217.CLK0 -clock0 => ram_block1a218.CLK0 -clock0 => ram_block1a219.CLK0 -clock0 => ram_block1a220.CLK0 -clock0 => ram_block1a221.CLK0 -clock0 => ram_block1a222.CLK0 -clock0 => ram_block1a223.CLK0 -clock0 => address_reg_a[2].CLK -clock0 => address_reg_a[1].CLK -clock0 => address_reg_a[0].CLK -clocken0 => ram_block1a0.ENA0 -clocken0 => ram_block1a1.ENA0 -clocken0 => ram_block1a2.ENA0 -clocken0 => ram_block1a3.ENA0 -clocken0 => ram_block1a4.ENA0 -clocken0 => ram_block1a5.ENA0 -clocken0 => ram_block1a6.ENA0 -clocken0 => ram_block1a7.ENA0 -clocken0 => ram_block1a8.ENA0 -clocken0 => ram_block1a9.ENA0 -clocken0 => ram_block1a10.ENA0 -clocken0 => ram_block1a11.ENA0 -clocken0 => ram_block1a12.ENA0 -clocken0 => ram_block1a13.ENA0 -clocken0 => ram_block1a14.ENA0 -clocken0 => ram_block1a15.ENA0 -clocken0 => ram_block1a16.ENA0 -clocken0 => ram_block1a17.ENA0 -clocken0 => ram_block1a18.ENA0 -clocken0 => ram_block1a19.ENA0 -clocken0 => ram_block1a20.ENA0 -clocken0 => ram_block1a21.ENA0 -clocken0 => ram_block1a22.ENA0 -clocken0 => ram_block1a23.ENA0 -clocken0 => ram_block1a24.ENA0 -clocken0 => ram_block1a25.ENA0 -clocken0 => ram_block1a26.ENA0 -clocken0 => ram_block1a27.ENA0 -clocken0 => ram_block1a28.ENA0 -clocken0 => ram_block1a29.ENA0 -clocken0 => ram_block1a30.ENA0 -clocken0 => ram_block1a31.ENA0 -clocken0 => ram_block1a32.ENA0 -clocken0 => ram_block1a33.ENA0 -clocken0 => ram_block1a34.ENA0 -clocken0 => ram_block1a35.ENA0 -clocken0 => ram_block1a36.ENA0 -clocken0 => ram_block1a37.ENA0 -clocken0 => ram_block1a38.ENA0 -clocken0 => ram_block1a39.ENA0 -clocken0 => ram_block1a40.ENA0 -clocken0 => ram_block1a41.ENA0 -clocken0 => ram_block1a42.ENA0 -clocken0 => ram_block1a43.ENA0 -clocken0 => ram_block1a44.ENA0 -clocken0 => ram_block1a45.ENA0 -clocken0 => ram_block1a46.ENA0 -clocken0 => ram_block1a47.ENA0 -clocken0 => ram_block1a48.ENA0 -clocken0 => ram_block1a49.ENA0 -clocken0 => ram_block1a50.ENA0 -clocken0 => ram_block1a51.ENA0 -clocken0 => ram_block1a52.ENA0 -clocken0 => ram_block1a53.ENA0 -clocken0 => ram_block1a54.ENA0 -clocken0 => ram_block1a55.ENA0 -clocken0 => ram_block1a56.ENA0 -clocken0 => ram_block1a57.ENA0 -clocken0 => ram_block1a58.ENA0 -clocken0 => ram_block1a59.ENA0 -clocken0 => ram_block1a60.ENA0 -clocken0 => ram_block1a61.ENA0 -clocken0 => ram_block1a62.ENA0 -clocken0 => ram_block1a63.ENA0 -clocken0 => ram_block1a64.ENA0 -clocken0 => ram_block1a65.ENA0 -clocken0 => ram_block1a66.ENA0 -clocken0 => ram_block1a67.ENA0 -clocken0 => ram_block1a68.ENA0 -clocken0 => ram_block1a69.ENA0 -clocken0 => ram_block1a70.ENA0 -clocken0 => ram_block1a71.ENA0 -clocken0 => ram_block1a72.ENA0 -clocken0 => ram_block1a73.ENA0 -clocken0 => ram_block1a74.ENA0 -clocken0 => ram_block1a75.ENA0 -clocken0 => ram_block1a76.ENA0 -clocken0 => ram_block1a77.ENA0 -clocken0 => ram_block1a78.ENA0 -clocken0 => ram_block1a79.ENA0 -clocken0 => ram_block1a80.ENA0 -clocken0 => ram_block1a81.ENA0 -clocken0 => ram_block1a82.ENA0 -clocken0 => ram_block1a83.ENA0 -clocken0 => ram_block1a84.ENA0 -clocken0 => ram_block1a85.ENA0 -clocken0 => ram_block1a86.ENA0 -clocken0 => ram_block1a87.ENA0 -clocken0 => ram_block1a88.ENA0 -clocken0 => ram_block1a89.ENA0 -clocken0 => ram_block1a90.ENA0 -clocken0 => ram_block1a91.ENA0 -clocken0 => ram_block1a92.ENA0 -clocken0 => ram_block1a93.ENA0 -clocken0 => ram_block1a94.ENA0 -clocken0 => ram_block1a95.ENA0 -clocken0 => ram_block1a96.ENA0 -clocken0 => ram_block1a97.ENA0 -clocken0 => ram_block1a98.ENA0 -clocken0 => ram_block1a99.ENA0 -clocken0 => ram_block1a100.ENA0 -clocken0 => ram_block1a101.ENA0 -clocken0 => ram_block1a102.ENA0 -clocken0 => ram_block1a103.ENA0 -clocken0 => ram_block1a104.ENA0 -clocken0 => ram_block1a105.ENA0 -clocken0 => ram_block1a106.ENA0 -clocken0 => ram_block1a107.ENA0 -clocken0 => ram_block1a108.ENA0 -clocken0 => ram_block1a109.ENA0 -clocken0 => ram_block1a110.ENA0 -clocken0 => ram_block1a111.ENA0 -clocken0 => ram_block1a112.ENA0 -clocken0 => ram_block1a113.ENA0 -clocken0 => ram_block1a114.ENA0 -clocken0 => ram_block1a115.ENA0 -clocken0 => ram_block1a116.ENA0 -clocken0 => ram_block1a117.ENA0 -clocken0 => ram_block1a118.ENA0 -clocken0 => ram_block1a119.ENA0 -clocken0 => ram_block1a120.ENA0 -clocken0 => ram_block1a121.ENA0 -clocken0 => ram_block1a122.ENA0 -clocken0 => ram_block1a123.ENA0 -clocken0 => ram_block1a124.ENA0 -clocken0 => ram_block1a125.ENA0 -clocken0 => ram_block1a126.ENA0 -clocken0 => ram_block1a127.ENA0 -clocken0 => ram_block1a128.ENA0 -clocken0 => ram_block1a129.ENA0 -clocken0 => ram_block1a130.ENA0 -clocken0 => ram_block1a131.ENA0 -clocken0 => ram_block1a132.ENA0 -clocken0 => ram_block1a133.ENA0 -clocken0 => ram_block1a134.ENA0 -clocken0 => ram_block1a135.ENA0 -clocken0 => ram_block1a136.ENA0 -clocken0 => ram_block1a137.ENA0 -clocken0 => ram_block1a138.ENA0 -clocken0 => ram_block1a139.ENA0 -clocken0 => ram_block1a140.ENA0 -clocken0 => ram_block1a141.ENA0 -clocken0 => ram_block1a142.ENA0 -clocken0 => ram_block1a143.ENA0 -clocken0 => ram_block1a144.ENA0 -clocken0 => ram_block1a145.ENA0 -clocken0 => ram_block1a146.ENA0 -clocken0 => ram_block1a147.ENA0 -clocken0 => ram_block1a148.ENA0 -clocken0 => ram_block1a149.ENA0 -clocken0 => ram_block1a150.ENA0 -clocken0 => ram_block1a151.ENA0 -clocken0 => ram_block1a152.ENA0 -clocken0 => ram_block1a153.ENA0 -clocken0 => ram_block1a154.ENA0 -clocken0 => ram_block1a155.ENA0 -clocken0 => ram_block1a156.ENA0 -clocken0 => ram_block1a157.ENA0 -clocken0 => ram_block1a158.ENA0 -clocken0 => ram_block1a159.ENA0 -clocken0 => ram_block1a160.ENA0 -clocken0 => ram_block1a161.ENA0 -clocken0 => ram_block1a162.ENA0 -clocken0 => ram_block1a163.ENA0 -clocken0 => ram_block1a164.ENA0 -clocken0 => ram_block1a165.ENA0 -clocken0 => ram_block1a166.ENA0 -clocken0 => ram_block1a167.ENA0 -clocken0 => ram_block1a168.ENA0 -clocken0 => ram_block1a169.ENA0 -clocken0 => ram_block1a170.ENA0 -clocken0 => ram_block1a171.ENA0 -clocken0 => ram_block1a172.ENA0 -clocken0 => ram_block1a173.ENA0 -clocken0 => ram_block1a174.ENA0 -clocken0 => ram_block1a175.ENA0 -clocken0 => ram_block1a176.ENA0 -clocken0 => ram_block1a177.ENA0 -clocken0 => ram_block1a178.ENA0 -clocken0 => ram_block1a179.ENA0 -clocken0 => ram_block1a180.ENA0 -clocken0 => ram_block1a181.ENA0 -clocken0 => ram_block1a182.ENA0 -clocken0 => ram_block1a183.ENA0 -clocken0 => ram_block1a184.ENA0 -clocken0 => ram_block1a185.ENA0 -clocken0 => ram_block1a186.ENA0 -clocken0 => ram_block1a187.ENA0 -clocken0 => ram_block1a188.ENA0 -clocken0 => ram_block1a189.ENA0 -clocken0 => ram_block1a190.ENA0 -clocken0 => ram_block1a191.ENA0 -clocken0 => ram_block1a192.ENA0 -clocken0 => ram_block1a193.ENA0 -clocken0 => ram_block1a194.ENA0 -clocken0 => ram_block1a195.ENA0 -clocken0 => ram_block1a196.ENA0 -clocken0 => ram_block1a197.ENA0 -clocken0 => ram_block1a198.ENA0 -clocken0 => ram_block1a199.ENA0 -clocken0 => ram_block1a200.ENA0 -clocken0 => ram_block1a201.ENA0 -clocken0 => ram_block1a202.ENA0 -clocken0 => ram_block1a203.ENA0 -clocken0 => ram_block1a204.ENA0 -clocken0 => ram_block1a205.ENA0 -clocken0 => ram_block1a206.ENA0 -clocken0 => ram_block1a207.ENA0 -clocken0 => ram_block1a208.ENA0 -clocken0 => ram_block1a209.ENA0 -clocken0 => ram_block1a210.ENA0 -clocken0 => ram_block1a211.ENA0 -clocken0 => ram_block1a212.ENA0 -clocken0 => ram_block1a213.ENA0 -clocken0 => ram_block1a214.ENA0 -clocken0 => ram_block1a215.ENA0 -clocken0 => ram_block1a216.ENA0 -clocken0 => ram_block1a217.ENA0 -clocken0 => ram_block1a218.ENA0 -clocken0 => ram_block1a219.ENA0 -clocken0 => ram_block1a220.ENA0 -clocken0 => ram_block1a221.ENA0 -clocken0 => ram_block1a222.ENA0 -clocken0 => ram_block1a223.ENA0 -clocken0 => address_reg_a[2].ENA -clocken0 => address_reg_a[1].ENA -clocken0 => address_reg_a[0].ENA -data_a[0] => ram_block1a0.PORTADATAIN -data_a[0] => ram_block1a32.PORTADATAIN -data_a[0] => ram_block1a64.PORTADATAIN -data_a[0] => ram_block1a96.PORTADATAIN -data_a[0] => ram_block1a128.PORTADATAIN -data_a[0] => ram_block1a160.PORTADATAIN -data_a[0] => ram_block1a192.PORTADATAIN -data_a[1] => ram_block1a1.PORTADATAIN -data_a[1] => ram_block1a33.PORTADATAIN -data_a[1] => ram_block1a65.PORTADATAIN -data_a[1] => ram_block1a97.PORTADATAIN -data_a[1] => ram_block1a129.PORTADATAIN -data_a[1] => ram_block1a161.PORTADATAIN -data_a[1] => ram_block1a193.PORTADATAIN -data_a[2] => ram_block1a2.PORTADATAIN -data_a[2] => ram_block1a34.PORTADATAIN -data_a[2] => ram_block1a66.PORTADATAIN -data_a[2] => ram_block1a98.PORTADATAIN -data_a[2] => ram_block1a130.PORTADATAIN -data_a[2] => ram_block1a162.PORTADATAIN -data_a[2] => ram_block1a194.PORTADATAIN -data_a[3] => ram_block1a3.PORTADATAIN -data_a[3] => ram_block1a35.PORTADATAIN -data_a[3] => ram_block1a67.PORTADATAIN -data_a[3] => ram_block1a99.PORTADATAIN -data_a[3] => ram_block1a131.PORTADATAIN -data_a[3] => ram_block1a163.PORTADATAIN -data_a[3] => ram_block1a195.PORTADATAIN -data_a[4] => ram_block1a4.PORTADATAIN -data_a[4] => ram_block1a36.PORTADATAIN -data_a[4] => ram_block1a68.PORTADATAIN -data_a[4] => ram_block1a100.PORTADATAIN -data_a[4] => ram_block1a132.PORTADATAIN -data_a[4] => ram_block1a164.PORTADATAIN -data_a[4] => ram_block1a196.PORTADATAIN -data_a[5] => ram_block1a5.PORTADATAIN -data_a[5] => ram_block1a37.PORTADATAIN -data_a[5] => ram_block1a69.PORTADATAIN -data_a[5] => ram_block1a101.PORTADATAIN -data_a[5] => ram_block1a133.PORTADATAIN -data_a[5] => ram_block1a165.PORTADATAIN -data_a[5] => ram_block1a197.PORTADATAIN -data_a[6] => ram_block1a6.PORTADATAIN -data_a[6] => ram_block1a38.PORTADATAIN -data_a[6] => ram_block1a70.PORTADATAIN -data_a[6] => ram_block1a102.PORTADATAIN -data_a[6] => ram_block1a134.PORTADATAIN -data_a[6] => ram_block1a166.PORTADATAIN -data_a[6] => ram_block1a198.PORTADATAIN -data_a[7] => ram_block1a7.PORTADATAIN -data_a[7] => ram_block1a39.PORTADATAIN -data_a[7] => ram_block1a71.PORTADATAIN -data_a[7] => ram_block1a103.PORTADATAIN -data_a[7] => ram_block1a135.PORTADATAIN -data_a[7] => ram_block1a167.PORTADATAIN -data_a[7] => ram_block1a199.PORTADATAIN -data_a[8] => ram_block1a8.PORTADATAIN -data_a[8] => ram_block1a40.PORTADATAIN -data_a[8] => ram_block1a72.PORTADATAIN -data_a[8] => ram_block1a104.PORTADATAIN -data_a[8] => ram_block1a136.PORTADATAIN -data_a[8] => ram_block1a168.PORTADATAIN -data_a[8] => ram_block1a200.PORTADATAIN -data_a[9] => ram_block1a9.PORTADATAIN -data_a[9] => ram_block1a41.PORTADATAIN -data_a[9] => ram_block1a73.PORTADATAIN -data_a[9] => ram_block1a105.PORTADATAIN -data_a[9] => ram_block1a137.PORTADATAIN -data_a[9] => ram_block1a169.PORTADATAIN -data_a[9] => ram_block1a201.PORTADATAIN -data_a[10] => ram_block1a10.PORTADATAIN -data_a[10] => ram_block1a42.PORTADATAIN -data_a[10] => ram_block1a74.PORTADATAIN -data_a[10] => ram_block1a106.PORTADATAIN -data_a[10] => ram_block1a138.PORTADATAIN -data_a[10] => ram_block1a170.PORTADATAIN -data_a[10] => ram_block1a202.PORTADATAIN -data_a[11] => ram_block1a11.PORTADATAIN -data_a[11] => ram_block1a43.PORTADATAIN -data_a[11] => ram_block1a75.PORTADATAIN -data_a[11] => ram_block1a107.PORTADATAIN -data_a[11] => ram_block1a139.PORTADATAIN -data_a[11] => ram_block1a171.PORTADATAIN -data_a[11] => ram_block1a203.PORTADATAIN -data_a[12] => ram_block1a12.PORTADATAIN -data_a[12] => ram_block1a44.PORTADATAIN -data_a[12] => ram_block1a76.PORTADATAIN -data_a[12] => ram_block1a108.PORTADATAIN -data_a[12] => ram_block1a140.PORTADATAIN -data_a[12] => ram_block1a172.PORTADATAIN -data_a[12] => ram_block1a204.PORTADATAIN -data_a[13] => ram_block1a13.PORTADATAIN -data_a[13] => ram_block1a45.PORTADATAIN -data_a[13] => ram_block1a77.PORTADATAIN -data_a[13] => ram_block1a109.PORTADATAIN -data_a[13] => ram_block1a141.PORTADATAIN -data_a[13] => ram_block1a173.PORTADATAIN -data_a[13] => ram_block1a205.PORTADATAIN -data_a[14] => ram_block1a14.PORTADATAIN -data_a[14] => ram_block1a46.PORTADATAIN -data_a[14] => ram_block1a78.PORTADATAIN -data_a[14] => ram_block1a110.PORTADATAIN -data_a[14] => ram_block1a142.PORTADATAIN -data_a[14] => ram_block1a174.PORTADATAIN -data_a[14] => ram_block1a206.PORTADATAIN -data_a[15] => ram_block1a15.PORTADATAIN -data_a[15] => ram_block1a47.PORTADATAIN -data_a[15] => ram_block1a79.PORTADATAIN -data_a[15] => ram_block1a111.PORTADATAIN -data_a[15] => ram_block1a143.PORTADATAIN -data_a[15] => ram_block1a175.PORTADATAIN -data_a[15] => ram_block1a207.PORTADATAIN -data_a[16] => ram_block1a16.PORTADATAIN -data_a[16] => ram_block1a48.PORTADATAIN -data_a[16] => ram_block1a80.PORTADATAIN -data_a[16] => ram_block1a112.PORTADATAIN -data_a[16] => ram_block1a144.PORTADATAIN -data_a[16] => ram_block1a176.PORTADATAIN -data_a[16] => ram_block1a208.PORTADATAIN -data_a[17] => ram_block1a17.PORTADATAIN -data_a[17] => ram_block1a49.PORTADATAIN -data_a[17] => ram_block1a81.PORTADATAIN -data_a[17] => ram_block1a113.PORTADATAIN -data_a[17] => ram_block1a145.PORTADATAIN -data_a[17] => ram_block1a177.PORTADATAIN -data_a[17] => ram_block1a209.PORTADATAIN -data_a[18] => ram_block1a18.PORTADATAIN -data_a[18] => ram_block1a50.PORTADATAIN -data_a[18] => ram_block1a82.PORTADATAIN -data_a[18] => ram_block1a114.PORTADATAIN -data_a[18] => ram_block1a146.PORTADATAIN -data_a[18] => ram_block1a178.PORTADATAIN -data_a[18] => ram_block1a210.PORTADATAIN -data_a[19] => ram_block1a19.PORTADATAIN -data_a[19] => ram_block1a51.PORTADATAIN -data_a[19] => ram_block1a83.PORTADATAIN -data_a[19] => ram_block1a115.PORTADATAIN -data_a[19] => ram_block1a147.PORTADATAIN -data_a[19] => ram_block1a179.PORTADATAIN -data_a[19] => ram_block1a211.PORTADATAIN -data_a[20] => ram_block1a20.PORTADATAIN -data_a[20] => ram_block1a52.PORTADATAIN -data_a[20] => ram_block1a84.PORTADATAIN -data_a[20] => ram_block1a116.PORTADATAIN -data_a[20] => ram_block1a148.PORTADATAIN -data_a[20] => ram_block1a180.PORTADATAIN -data_a[20] => ram_block1a212.PORTADATAIN -data_a[21] => ram_block1a21.PORTADATAIN -data_a[21] => ram_block1a53.PORTADATAIN -data_a[21] => ram_block1a85.PORTADATAIN -data_a[21] => ram_block1a117.PORTADATAIN -data_a[21] => ram_block1a149.PORTADATAIN -data_a[21] => ram_block1a181.PORTADATAIN -data_a[21] => ram_block1a213.PORTADATAIN -data_a[22] => ram_block1a22.PORTADATAIN -data_a[22] => ram_block1a54.PORTADATAIN -data_a[22] => ram_block1a86.PORTADATAIN -data_a[22] => ram_block1a118.PORTADATAIN -data_a[22] => ram_block1a150.PORTADATAIN -data_a[22] => ram_block1a182.PORTADATAIN -data_a[22] => ram_block1a214.PORTADATAIN -data_a[23] => ram_block1a23.PORTADATAIN -data_a[23] => ram_block1a55.PORTADATAIN -data_a[23] => ram_block1a87.PORTADATAIN -data_a[23] => ram_block1a119.PORTADATAIN -data_a[23] => ram_block1a151.PORTADATAIN -data_a[23] => ram_block1a183.PORTADATAIN -data_a[23] => ram_block1a215.PORTADATAIN -data_a[24] => ram_block1a24.PORTADATAIN -data_a[24] => ram_block1a56.PORTADATAIN -data_a[24] => ram_block1a88.PORTADATAIN -data_a[24] => ram_block1a120.PORTADATAIN -data_a[24] => ram_block1a152.PORTADATAIN -data_a[24] => ram_block1a184.PORTADATAIN -data_a[24] => ram_block1a216.PORTADATAIN -data_a[25] => ram_block1a25.PORTADATAIN -data_a[25] => ram_block1a57.PORTADATAIN -data_a[25] => ram_block1a89.PORTADATAIN -data_a[25] => ram_block1a121.PORTADATAIN -data_a[25] => ram_block1a153.PORTADATAIN -data_a[25] => ram_block1a185.PORTADATAIN -data_a[25] => ram_block1a217.PORTADATAIN -data_a[26] => ram_block1a26.PORTADATAIN -data_a[26] => ram_block1a58.PORTADATAIN -data_a[26] => ram_block1a90.PORTADATAIN -data_a[26] => ram_block1a122.PORTADATAIN -data_a[26] => ram_block1a154.PORTADATAIN -data_a[26] => ram_block1a186.PORTADATAIN -data_a[26] => ram_block1a218.PORTADATAIN -data_a[27] => ram_block1a27.PORTADATAIN -data_a[27] => ram_block1a59.PORTADATAIN -data_a[27] => ram_block1a91.PORTADATAIN -data_a[27] => ram_block1a123.PORTADATAIN -data_a[27] => ram_block1a155.PORTADATAIN -data_a[27] => ram_block1a187.PORTADATAIN -data_a[27] => ram_block1a219.PORTADATAIN -data_a[28] => ram_block1a28.PORTADATAIN -data_a[28] => ram_block1a60.PORTADATAIN -data_a[28] => ram_block1a92.PORTADATAIN -data_a[28] => ram_block1a124.PORTADATAIN -data_a[28] => ram_block1a156.PORTADATAIN -data_a[28] => ram_block1a188.PORTADATAIN -data_a[28] => ram_block1a220.PORTADATAIN -data_a[29] => ram_block1a29.PORTADATAIN -data_a[29] => ram_block1a61.PORTADATAIN -data_a[29] => ram_block1a93.PORTADATAIN -data_a[29] => ram_block1a125.PORTADATAIN -data_a[29] => ram_block1a157.PORTADATAIN -data_a[29] => ram_block1a189.PORTADATAIN -data_a[29] => ram_block1a221.PORTADATAIN -data_a[30] => ram_block1a30.PORTADATAIN -data_a[30] => ram_block1a62.PORTADATAIN -data_a[30] => ram_block1a94.PORTADATAIN -data_a[30] => ram_block1a126.PORTADATAIN -data_a[30] => ram_block1a158.PORTADATAIN -data_a[30] => ram_block1a190.PORTADATAIN -data_a[30] => ram_block1a222.PORTADATAIN -data_a[31] => ram_block1a31.PORTADATAIN -data_a[31] => ram_block1a63.PORTADATAIN -data_a[31] => ram_block1a95.PORTADATAIN -data_a[31] => ram_block1a127.PORTADATAIN -data_a[31] => ram_block1a159.PORTADATAIN -data_a[31] => ram_block1a191.PORTADATAIN -data_a[31] => ram_block1a223.PORTADATAIN -q_a[0] <= mux_nob:mux2.result[0] -q_a[1] <= mux_nob:mux2.result[1] -q_a[2] <= mux_nob:mux2.result[2] -q_a[3] <= mux_nob:mux2.result[3] -q_a[4] <= mux_nob:mux2.result[4] -q_a[5] <= mux_nob:mux2.result[5] -q_a[6] <= mux_nob:mux2.result[6] -q_a[7] <= mux_nob:mux2.result[7] -q_a[8] <= mux_nob:mux2.result[8] -q_a[9] <= mux_nob:mux2.result[9] -q_a[10] <= mux_nob:mux2.result[10] -q_a[11] <= mux_nob:mux2.result[11] -q_a[12] <= mux_nob:mux2.result[12] -q_a[13] <= mux_nob:mux2.result[13] -q_a[14] <= mux_nob:mux2.result[14] -q_a[15] <= mux_nob:mux2.result[15] -q_a[16] <= mux_nob:mux2.result[16] -q_a[17] <= mux_nob:mux2.result[17] -q_a[18] <= mux_nob:mux2.result[18] -q_a[19] <= mux_nob:mux2.result[19] -q_a[20] <= mux_nob:mux2.result[20] -q_a[21] <= mux_nob:mux2.result[21] -q_a[22] <= mux_nob:mux2.result[22] -q_a[23] <= mux_nob:mux2.result[23] -q_a[24] <= mux_nob:mux2.result[24] -q_a[25] <= mux_nob:mux2.result[25] -q_a[26] <= mux_nob:mux2.result[26] -q_a[27] <= mux_nob:mux2.result[27] -q_a[28] <= mux_nob:mux2.result[28] -q_a[29] <= mux_nob:mux2.result[29] -q_a[30] <= mux_nob:mux2.result[30] -q_a[31] <= mux_nob:mux2.result[31] -wren_a => decode_qsa:decode3.enable - - -|lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3 -data[0] => w_anode1849w[1].IN0 -data[0] => w_anode1866w[1].IN1 -data[0] => w_anode1876w[1].IN0 -data[0] => w_anode1886w[1].IN1 -data[0] => w_anode1896w[1].IN0 -data[0] => w_anode1906w[1].IN1 -data[0] => w_anode1916w[1].IN0 -data[0] => w_anode1926w[1].IN1 -data[1] => w_anode1849w[2].IN0 -data[1] => w_anode1866w[2].IN0 -data[1] => w_anode1876w[2].IN1 -data[1] => w_anode1886w[2].IN1 -data[1] => w_anode1896w[2].IN0 -data[1] => w_anode1906w[2].IN0 -data[1] => w_anode1916w[2].IN1 -data[1] => w_anode1926w[2].IN1 -data[2] => w_anode1849w[3].IN0 -data[2] => w_anode1866w[3].IN0 -data[2] => w_anode1876w[3].IN0 -data[2] => w_anode1886w[3].IN0 -data[2] => w_anode1896w[3].IN1 -data[2] => w_anode1906w[3].IN1 -data[2] => w_anode1916w[3].IN1 -data[2] => w_anode1926w[3].IN1 -enable => w_anode1849w[1].IN0 -enable => w_anode1866w[1].IN0 -enable => w_anode1876w[1].IN0 -enable => w_anode1886w[1].IN0 -enable => w_anode1896w[1].IN0 -enable => w_anode1906w[1].IN0 -enable => w_anode1916w[1].IN0 -enable => w_anode1926w[1].IN0 -eq[0] <= w_anode1849w[3].DB_MAX_OUTPUT_PORT_TYPE -eq[1] <= w_anode1866w[3].DB_MAX_OUTPUT_PORT_TYPE -eq[2] <= w_anode1876w[3].DB_MAX_OUTPUT_PORT_TYPE -eq[3] <= w_anode1886w[3].DB_MAX_OUTPUT_PORT_TYPE -eq[4] <= w_anode1896w[3].DB_MAX_OUTPUT_PORT_TYPE -eq[5] <= w_anode1906w[3].DB_MAX_OUTPUT_PORT_TYPE -eq[6] <= w_anode1916w[3].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2 -data[0] => _.IN0 -data[0] => _.IN0 -data[1] => _.IN0 -data[1] => _.IN0 -data[2] => _.IN0 -data[2] => _.IN0 -data[3] => _.IN0 -data[3] => _.IN0 -data[4] => _.IN0 -data[4] => _.IN0 -data[5] => _.IN0 -data[5] => _.IN0 -data[6] => _.IN0 -data[6] => _.IN0 -data[7] => _.IN0 -data[7] => _.IN0 -data[8] => _.IN0 -data[8] => _.IN0 -data[9] => _.IN0 -data[9] => _.IN0 -data[10] => _.IN0 -data[10] => _.IN0 -data[11] => _.IN0 -data[11] => _.IN0 -data[12] => _.IN0 -data[12] => _.IN0 -data[13] => _.IN0 -data[13] => _.IN0 -data[14] => _.IN0 -data[14] => _.IN0 -data[15] => _.IN0 -data[15] => _.IN0 -data[16] => _.IN0 -data[16] => _.IN0 -data[17] => _.IN0 -data[17] => _.IN0 -data[18] => _.IN0 -data[18] => _.IN0 -data[19] => _.IN0 -data[19] => _.IN0 -data[20] => _.IN0 -data[20] => _.IN0 -data[21] => _.IN0 -data[21] => _.IN0 -data[22] => _.IN0 -data[22] => _.IN0 -data[23] => _.IN0 -data[23] => _.IN0 -data[24] => _.IN0 -data[24] => _.IN0 -data[25] => _.IN0 -data[25] => _.IN0 -data[26] => _.IN0 -data[26] => _.IN0 -data[27] => _.IN0 -data[27] => _.IN0 -data[28] => _.IN0 -data[28] => _.IN0 -data[29] => _.IN0 -data[29] => _.IN0 -data[30] => _.IN0 -data[30] => _.IN0 -data[31] => _.IN0 -data[31] => _.IN0 -data[32] => _.IN0 -data[33] => _.IN0 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_.IN1 -data[75] => _.IN1 -data[76] => _.IN1 -data[76] => _.IN1 -data[77] => _.IN1 -data[77] => _.IN1 -data[78] => _.IN1 -data[78] => _.IN1 -data[79] => _.IN1 -data[79] => _.IN1 -data[80] => _.IN1 -data[80] => _.IN1 -data[81] => _.IN1 -data[81] => _.IN1 -data[82] => _.IN1 -data[82] => _.IN1 -data[83] => _.IN1 -data[83] => _.IN1 -data[84] => _.IN1 -data[84] => _.IN1 -data[85] => _.IN1 -data[85] => _.IN1 -data[86] => _.IN1 -data[86] => _.IN1 -data[87] => _.IN1 -data[87] => _.IN1 -data[88] => _.IN1 -data[88] => _.IN1 -data[89] => _.IN1 -data[89] => _.IN1 -data[90] => _.IN1 -data[90] => _.IN1 -data[91] => _.IN1 -data[91] => _.IN1 -data[92] => _.IN1 -data[92] => _.IN1 -data[93] => _.IN1 -data[93] => _.IN1 -data[94] => _.IN1 -data[94] => _.IN1 -data[95] => _.IN1 -data[95] => _.IN1 -data[96] => _.IN0 -data[97] => _.IN0 -data[98] => _.IN0 -data[99] => _.IN0 -data[100] => _.IN0 -data[101] => _.IN0 -data[102] => _.IN0 -data[103] => _.IN0 -data[104] => _.IN0 -data[105] => _.IN0 -data[106] => _.IN0 -data[107] => _.IN0 -data[108] => _.IN0 -data[109] => _.IN0 -data[110] => _.IN0 -data[111] => _.IN0 -data[112] => _.IN0 -data[113] => _.IN0 -data[114] => _.IN0 -data[115] => _.IN0 -data[116] => _.IN0 -data[117] => _.IN0 -data[118] => _.IN0 -data[119] => _.IN0 -data[120] => _.IN0 -data[121] => _.IN0 -data[122] => _.IN0 -data[123] => _.IN0 -data[124] => _.IN0 -data[125] => _.IN0 -data[126] => _.IN0 -data[127] => _.IN0 -data[128] => _.IN0 -data[128] => _.IN0 -data[129] => _.IN0 -data[129] => _.IN0 -data[130] => _.IN0 -data[130] => _.IN0 -data[131] => _.IN0 -data[131] => _.IN0 -data[132] => _.IN0 -data[132] => _.IN0 -data[133] => _.IN0 -data[133] => _.IN0 -data[134] => _.IN0 -data[134] => _.IN0 -data[135] => _.IN0 -data[135] => _.IN0 -data[136] => _.IN0 -data[136] => _.IN0 -data[137] => _.IN0 -data[137] => _.IN0 -data[138] => _.IN0 -data[138] => _.IN0 -data[139] => _.IN0 -data[139] => _.IN0 -data[140] => _.IN0 -data[140] => _.IN0 -data[141] => _.IN0 -data[141] => _.IN0 -data[142] => _.IN0 -data[142] => _.IN0 -data[143] => _.IN0 -data[143] => _.IN0 -data[144] => _.IN0 -data[144] => _.IN0 -data[145] => _.IN0 -data[145] => _.IN0 -data[146] => _.IN0 -data[146] => _.IN0 -data[147] => _.IN0 -data[147] => _.IN0 -data[148] => _.IN0 -data[148] => _.IN0 -data[149] => _.IN0 -data[149] => _.IN0 -data[150] => _.IN0 -data[150] => _.IN0 -data[151] => _.IN0 -data[151] => _.IN0 -data[152] => _.IN0 -data[152] => _.IN0 -data[153] => _.IN0 -data[153] => _.IN0 -data[154] => _.IN0 -data[154] => _.IN0 -data[155] => _.IN0 -data[155] => _.IN0 -data[156] => _.IN0 -data[156] => _.IN0 -data[157] => _.IN0 -data[157] => _.IN0 -data[158] => _.IN0 -data[158] => _.IN0 -data[159] => _.IN0 -data[159] => _.IN0 -data[160] => _.IN0 -data[161] => _.IN0 -data[162] => _.IN0 -data[163] => _.IN0 -data[164] => _.IN0 -data[165] => _.IN0 -data[166] => _.IN0 -data[167] => _.IN0 -data[168] => _.IN0 -data[169] => _.IN0 -data[170] => _.IN0 -data[171] => _.IN0 -data[172] => _.IN0 -data[173] => _.IN0 -data[174] => _.IN0 -data[175] => _.IN0 -data[176] => _.IN0 -data[177] => _.IN0 -data[178] => _.IN0 -data[179] => _.IN0 -data[180] => _.IN0 -data[181] => _.IN0 -data[182] => _.IN0 -data[183] => _.IN0 -data[184] => _.IN0 -data[185] => _.IN0 -data[186] => _.IN0 -data[187] => _.IN0 -data[188] => _.IN0 -data[189] => _.IN0 -data[190] => _.IN0 -data[191] => _.IN0 -data[192] => _.IN1 -data[192] => _.IN1 -data[193] => _.IN1 -data[193] => _.IN1 -data[194] => _.IN1 -data[194] => _.IN1 -data[195] => _.IN1 -data[195] => _.IN1 -data[196] => _.IN1 -data[196] => _.IN1 -data[197] => _.IN1 -data[197] => _.IN1 -data[198] => _.IN1 -data[198] => _.IN1 -data[199] => _.IN1 -data[199] => _.IN1 -data[200] => _.IN1 -data[200] => _.IN1 -data[201] => _.IN1 -data[201] => _.IN1 -data[202] => _.IN1 -data[202] => _.IN1 -data[203] => _.IN1 -data[203] => _.IN1 -data[204] => _.IN1 -data[204] => _.IN1 -data[205] => _.IN1 -data[205] => _.IN1 -data[206] => _.IN1 -data[206] => _.IN1 -data[207] => _.IN1 -data[207] => _.IN1 -data[208] => _.IN1 -data[208] => _.IN1 -data[209] => _.IN1 -data[209] => _.IN1 -data[210] => _.IN1 -data[210] => _.IN1 -data[211] => _.IN1 -data[211] => _.IN1 -data[212] => _.IN1 -data[212] => _.IN1 -data[213] => _.IN1 -data[213] => _.IN1 -data[214] => _.IN1 -data[214] => _.IN1 -data[215] => _.IN1 -data[215] => _.IN1 -data[216] => _.IN1 -data[216] => _.IN1 -data[217] => _.IN1 -data[217] => _.IN1 -data[218] => _.IN1 -data[218] => _.IN1 -data[219] => _.IN1 -data[219] => _.IN1 -data[220] => _.IN1 -data[220] => _.IN1 -data[221] => _.IN1 -data[221] => _.IN1 -data[222] => _.IN1 -data[222] => _.IN1 -data[223] => _.IN1 -data[223] => _.IN1 -result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE -result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE -result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE -result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE -result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE -result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE -result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE -result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE -result[8] <= result_node[8].DB_MAX_OUTPUT_PORT_TYPE -result[9] <= result_node[9].DB_MAX_OUTPUT_PORT_TYPE -result[10] <= result_node[10].DB_MAX_OUTPUT_PORT_TYPE -result[11] <= result_node[11].DB_MAX_OUTPUT_PORT_TYPE -result[12] <= result_node[12].DB_MAX_OUTPUT_PORT_TYPE -result[13] <= result_node[13].DB_MAX_OUTPUT_PORT_TYPE -result[14] <= result_node[14].DB_MAX_OUTPUT_PORT_TYPE -result[15] <= result_node[15].DB_MAX_OUTPUT_PORT_TYPE -result[16] <= result_node[16].DB_MAX_OUTPUT_PORT_TYPE -result[17] <= result_node[17].DB_MAX_OUTPUT_PORT_TYPE -result[18] <= result_node[18].DB_MAX_OUTPUT_PORT_TYPE -result[19] <= result_node[19].DB_MAX_OUTPUT_PORT_TYPE -result[20] <= result_node[20].DB_MAX_OUTPUT_PORT_TYPE -result[21] <= result_node[21].DB_MAX_OUTPUT_PORT_TYPE -result[22] <= result_node[22].DB_MAX_OUTPUT_PORT_TYPE -result[23] <= result_node[23].DB_MAX_OUTPUT_PORT_TYPE -result[24] <= result_node[24].DB_MAX_OUTPUT_PORT_TYPE -result[25] <= result_node[25].DB_MAX_OUTPUT_PORT_TYPE -result[26] <= result_node[26].DB_MAX_OUTPUT_PORT_TYPE -result[27] <= result_node[27].DB_MAX_OUTPUT_PORT_TYPE -result[28] <= result_node[28].DB_MAX_OUTPUT_PORT_TYPE -result[29] <= result_node[29].DB_MAX_OUTPUT_PORT_TYPE -result[30] <= result_node[30].DB_MAX_OUTPUT_PORT_TYPE -result[31] <= result_node[31].DB_MAX_OUTPUT_PORT_TYPE -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => 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=> _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 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_.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[2] => result_node[31].IN0 -sel[2] => _.IN0 -sel[2] => result_node[30].IN0 -sel[2] => _.IN0 -sel[2] => result_node[29].IN0 -sel[2] => _.IN0 -sel[2] => result_node[28].IN0 -sel[2] => _.IN0 -sel[2] => result_node[27].IN0 -sel[2] => _.IN0 -sel[2] => result_node[26].IN0 -sel[2] => _.IN0 -sel[2] => result_node[25].IN0 -sel[2] => _.IN0 -sel[2] => result_node[24].IN0 -sel[2] => _.IN0 -sel[2] => result_node[23].IN0 -sel[2] => _.IN0 -sel[2] => result_node[22].IN0 -sel[2] => _.IN0 -sel[2] => result_node[21].IN0 -sel[2] => _.IN0 -sel[2] => result_node[20].IN0 -sel[2] => _.IN0 -sel[2] => result_node[19].IN0 -sel[2] => _.IN0 -sel[2] => result_node[18].IN0 -sel[2] => _.IN0 -sel[2] => result_node[17].IN0 -sel[2] => _.IN0 -sel[2] => result_node[16].IN0 -sel[2] => _.IN0 -sel[2] => result_node[15].IN0 -sel[2] => _.IN0 -sel[2] => result_node[14].IN0 -sel[2] => _.IN0 -sel[2] => result_node[13].IN0 -sel[2] => _.IN0 -sel[2] => result_node[12].IN0 -sel[2] => _.IN0 -sel[2] => result_node[11].IN0 -sel[2] => _.IN0 -sel[2] => result_node[10].IN0 -sel[2] => _.IN0 -sel[2] => result_node[9].IN0 -sel[2] => _.IN0 -sel[2] => result_node[8].IN0 -sel[2] => _.IN0 -sel[2] => result_node[7].IN0 -sel[2] => _.IN0 -sel[2] => result_node[6].IN0 -sel[2] => _.IN0 -sel[2] => result_node[5].IN0 -sel[2] => _.IN0 -sel[2] => result_node[4].IN0 -sel[2] => _.IN0 -sel[2] => result_node[3].IN0 -sel[2] => _.IN0 -sel[2] => result_node[2].IN0 -sel[2] => _.IN0 -sel[2] => result_node[1].IN0 -sel[2] => _.IN0 -sel[2] => result_node[0].IN0 -sel[2] => _.IN0 - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart -av_address => ien_AF.OUTPUTSELECT -av_address => ien_AE.OUTPUTSELECT -av_address => ac.OUTPUTSELECT -av_address => fifo_wr.OUTPUTSELECT -av_address => woverflow.OUTPUTSELECT -av_address => rvalid.OUTPUTSELECT -av_address => read_0.DATAB -av_address => fifo_rd.IN1 -av_chipselect => av_waitrequest.IN1 -av_chipselect => always2.IN0 -av_chipselect => always2.IN0 -av_chipselect => fifo_rd.IN0 -av_read_n => always2.IN1 -av_read_n => av_waitrequest.IN0 -av_read_n => fifo_rd.IN1 -av_write_n => always2.IN1 -av_write_n => av_waitrequest.IN1 -av_writedata[0] => fifo_wdata[0].IN1 -av_writedata[1] => fifo_wdata[1].IN1 -av_writedata[2] => fifo_wdata[2].IN1 -av_writedata[3] => fifo_wdata[3].IN1 -av_writedata[4] => fifo_wdata[4].IN1 -av_writedata[5] => fifo_wdata[5].IN1 -av_writedata[6] => fifo_wdata[6].IN1 -av_writedata[7] => fifo_wdata[7].IN1 -av_writedata[8] => ~NO_FANOUT~ -av_writedata[9] => ~NO_FANOUT~ -av_writedata[10] => always2.IN1 -av_writedata[11] => ~NO_FANOUT~ -av_writedata[12] => ~NO_FANOUT~ -av_writedata[13] => ~NO_FANOUT~ -av_writedata[14] => ~NO_FANOUT~ -av_writedata[15] => ~NO_FANOUT~ -av_writedata[16] => ~NO_FANOUT~ -av_writedata[17] => ~NO_FANOUT~ -av_writedata[18] => ~NO_FANOUT~ -av_writedata[19] => ~NO_FANOUT~ -av_writedata[20] => ~NO_FANOUT~ -av_writedata[21] => ~NO_FANOUT~ -av_writedata[22] => ~NO_FANOUT~ -av_writedata[23] => ~NO_FANOUT~ -av_writedata[24] => ~NO_FANOUT~ -av_writedata[25] => ~NO_FANOUT~ -av_writedata[26] => ~NO_FANOUT~ -av_writedata[27] => ~NO_FANOUT~ -av_writedata[28] => ~NO_FANOUT~ -av_writedata[29] => ~NO_FANOUT~ -av_writedata[30] => ~NO_FANOUT~ -av_writedata[31] => ~NO_FANOUT~ -clk => clk.IN3 -rst_n => rst_n.IN2 -av_irq <= av_irq.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[1] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[2] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[3] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[4] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[5] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[6] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[7] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[8] <= ipen_AF.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[9] <= ipen_AE.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[10] <= ac.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[11] <= -av_readdata[12] <= nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r.fifo_EF -av_readdata[13] <= nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w.fifo_FF -av_readdata[14] <= woverflow.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[15] <= rvalid.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[16] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[17] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[18] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[19] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[20] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[21] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[22] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[23] <= -av_readdata[24] <= -av_readdata[25] <= -av_readdata[26] <= -av_readdata[27] <= -av_readdata[28] <= -av_readdata[29] <= -av_readdata[30] <= -av_readdata[31] <= -av_waitrequest <= av_waitrequest~reg0.DB_MAX_OUTPUT_PORT_TYPE -dataavailable <= dataavailable~reg0.DB_MAX_OUTPUT_PORT_TYPE -readyfordata <= readyfordata~reg0.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w -clk => clk.IN1 -fifo_clear => fifo_clear.IN1 -fifo_wdata[0] => fifo_wdata[0].IN1 -fifo_wdata[1] => fifo_wdata[1].IN1 -fifo_wdata[2] => fifo_wdata[2].IN1 -fifo_wdata[3] => fifo_wdata[3].IN1 -fifo_wdata[4] => fifo_wdata[4].IN1 -fifo_wdata[5] => fifo_wdata[5].IN1 -fifo_wdata[6] => fifo_wdata[6].IN1 -fifo_wdata[7] => fifo_wdata[7].IN1 -fifo_wr => fifo_wr.IN1 -rd_wfifo => rd_wfifo.IN1 -fifo_FF <= scfifo:wfifo.full -r_dat[0] <= scfifo:wfifo.q -r_dat[1] <= scfifo:wfifo.q -r_dat[2] <= scfifo:wfifo.q -r_dat[3] <= scfifo:wfifo.q -r_dat[4] <= scfifo:wfifo.q -r_dat[5] <= scfifo:wfifo.q -r_dat[6] <= scfifo:wfifo.q -r_dat[7] <= scfifo:wfifo.q -wfifo_empty <= scfifo:wfifo.empty -wfifo_used[0] <= scfifo:wfifo.usedw -wfifo_used[1] <= scfifo:wfifo.usedw -wfifo_used[2] <= scfifo:wfifo.usedw -wfifo_used[3] <= scfifo:wfifo.usedw -wfifo_used[4] <= scfifo:wfifo.usedw -wfifo_used[5] <= scfifo:wfifo.usedw - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo -data[0] => scfifo_jr21:auto_generated.data[0] -data[1] => scfifo_jr21:auto_generated.data[1] -data[2] => scfifo_jr21:auto_generated.data[2] -data[3] => scfifo_jr21:auto_generated.data[3] -data[4] => scfifo_jr21:auto_generated.data[4] -data[5] => scfifo_jr21:auto_generated.data[5] -data[6] => scfifo_jr21:auto_generated.data[6] -data[7] => scfifo_jr21:auto_generated.data[7] -q[0] <= scfifo_jr21:auto_generated.q[0] -q[1] <= scfifo_jr21:auto_generated.q[1] -q[2] <= scfifo_jr21:auto_generated.q[2] -q[3] <= scfifo_jr21:auto_generated.q[3] -q[4] <= scfifo_jr21:auto_generated.q[4] -q[5] <= scfifo_jr21:auto_generated.q[5] -q[6] <= scfifo_jr21:auto_generated.q[6] -q[7] <= scfifo_jr21:auto_generated.q[7] -wrreq => scfifo_jr21:auto_generated.wrreq -rdreq => scfifo_jr21:auto_generated.rdreq -clock => scfifo_jr21:auto_generated.clock -aclr => scfifo_jr21:auto_generated.aclr -sclr => ~NO_FANOUT~ -empty <= scfifo_jr21:auto_generated.empty -full <= scfifo_jr21:auto_generated.full -almost_full <= -almost_empty <= -usedw[0] <= scfifo_jr21:auto_generated.usedw[0] -usedw[1] <= scfifo_jr21:auto_generated.usedw[1] -usedw[2] <= scfifo_jr21:auto_generated.usedw[2] -usedw[3] <= scfifo_jr21:auto_generated.usedw[3] -usedw[4] <= scfifo_jr21:auto_generated.usedw[4] -usedw[5] <= scfifo_jr21:auto_generated.usedw[5] - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated -aclr => a_dpfifo_q131:dpfifo.aclr -clock => a_dpfifo_q131:dpfifo.clock -data[0] => a_dpfifo_q131:dpfifo.data[0] -data[1] => a_dpfifo_q131:dpfifo.data[1] -data[2] => a_dpfifo_q131:dpfifo.data[2] -data[3] => a_dpfifo_q131:dpfifo.data[3] -data[4] => a_dpfifo_q131:dpfifo.data[4] -data[5] => a_dpfifo_q131:dpfifo.data[5] -data[6] => a_dpfifo_q131:dpfifo.data[6] -data[7] => a_dpfifo_q131:dpfifo.data[7] -empty <= a_dpfifo_q131:dpfifo.empty -full <= a_dpfifo_q131:dpfifo.full -q[0] <= a_dpfifo_q131:dpfifo.q[0] -q[1] <= a_dpfifo_q131:dpfifo.q[1] -q[2] <= a_dpfifo_q131:dpfifo.q[2] -q[3] <= a_dpfifo_q131:dpfifo.q[3] -q[4] <= a_dpfifo_q131:dpfifo.q[4] -q[5] <= a_dpfifo_q131:dpfifo.q[5] -q[6] <= a_dpfifo_q131:dpfifo.q[6] -q[7] <= a_dpfifo_q131:dpfifo.q[7] -rdreq => a_dpfifo_q131:dpfifo.rreq -usedw[0] <= a_dpfifo_q131:dpfifo.usedw[0] -usedw[1] <= a_dpfifo_q131:dpfifo.usedw[1] -usedw[2] <= a_dpfifo_q131:dpfifo.usedw[2] -usedw[3] <= a_dpfifo_q131:dpfifo.usedw[3] -usedw[4] <= a_dpfifo_q131:dpfifo.usedw[4] -usedw[5] <= a_dpfifo_q131:dpfifo.usedw[5] -wrreq => a_dpfifo_q131:dpfifo.wreq - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo -aclr => a_fefifo_7cf:fifo_state.aclr -aclr => cntr_1ob:rd_ptr_count.aclr -aclr => cntr_1ob:wr_ptr.aclr -clock => a_fefifo_7cf:fifo_state.clock -clock => dpram_nl21:FIFOram.inclock -clock => dpram_nl21:FIFOram.outclock -clock => cntr_1ob:rd_ptr_count.clock -clock => cntr_1ob:wr_ptr.clock -data[0] => dpram_nl21:FIFOram.data[0] -data[1] => dpram_nl21:FIFOram.data[1] -data[2] => dpram_nl21:FIFOram.data[2] -data[3] => dpram_nl21:FIFOram.data[3] -data[4] => dpram_nl21:FIFOram.data[4] -data[5] => dpram_nl21:FIFOram.data[5] -data[6] => dpram_nl21:FIFOram.data[6] -data[7] => dpram_nl21:FIFOram.data[7] -empty <= a_fefifo_7cf:fifo_state.empty -full <= a_fefifo_7cf:fifo_state.full -q[0] <= dpram_nl21:FIFOram.q[0] -q[1] <= dpram_nl21:FIFOram.q[1] -q[2] <= dpram_nl21:FIFOram.q[2] -q[3] <= dpram_nl21:FIFOram.q[3] -q[4] <= dpram_nl21:FIFOram.q[4] -q[5] <= dpram_nl21:FIFOram.q[5] -q[6] <= dpram_nl21:FIFOram.q[6] -q[7] <= dpram_nl21:FIFOram.q[7] -rreq => a_fefifo_7cf:fifo_state.rreq -rreq => _.IN0 -rreq => cntr_1ob:rd_ptr_count.cnt_en -sclr => a_fefifo_7cf:fifo_state.sclr -sclr => _.IN1 -sclr => _.IN0 -sclr => cntr_1ob:rd_ptr_count.sclr -sclr => cntr_1ob:wr_ptr.sclr -usedw[0] <= a_fefifo_7cf:fifo_state.usedw_out[0] -usedw[1] <= a_fefifo_7cf:fifo_state.usedw_out[1] -usedw[2] <= a_fefifo_7cf:fifo_state.usedw_out[2] -usedw[3] <= a_fefifo_7cf:fifo_state.usedw_out[3] -usedw[4] <= a_fefifo_7cf:fifo_state.usedw_out[4] -usedw[5] <= a_fefifo_7cf:fifo_state.usedw_out[5] -wreq => a_fefifo_7cf:fifo_state.wreq -wreq => dpram_nl21:FIFOram.wren -wreq => cntr_1ob:wr_ptr.cnt_en - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state -aclr => b_full.IN0 -aclr => b_non_empty.IN0 -aclr => cntr_do7:count_usedw.aclr -clock => cntr_do7:count_usedw.clock -clock => b_full.CLK -clock => b_non_empty.CLK -empty <= empty.DB_MAX_OUTPUT_PORT_TYPE -full <= b_full.DB_MAX_OUTPUT_PORT_TYPE -rreq => _.IN1 -rreq => _.IN0 -rreq => _.IN1 -rreq => _.IN1 -sclr => _.IN0 -sclr => _.IN0 -sclr => _.IN1 -sclr => _.IN0 -sclr => _.IN0 -sclr => cntr_do7:count_usedw.sclr -usedw_out[0] <= usedw[0].DB_MAX_OUTPUT_PORT_TYPE -usedw_out[1] <= usedw[1].DB_MAX_OUTPUT_PORT_TYPE -usedw_out[2] <= usedw[2].DB_MAX_OUTPUT_PORT_TYPE -usedw_out[3] <= usedw[3].DB_MAX_OUTPUT_PORT_TYPE -usedw_out[4] <= usedw[4].DB_MAX_OUTPUT_PORT_TYPE -usedw_out[5] <= usedw[5].DB_MAX_OUTPUT_PORT_TYPE -wreq => _.IN1 -wreq => _.IN1 -wreq => _.IN0 -wreq => _.IN0 -wreq => cntr_do7:count_usedw.updown - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw -aclr => counter_reg_bit[5].IN0 -clock => counter_reg_bit[5].CLK -clock => counter_reg_bit[4].CLK -clock => counter_reg_bit[3].CLK -clock => counter_reg_bit[2].CLK -clock => counter_reg_bit[1].CLK -clock => counter_reg_bit[0].CLK -cnt_en => _.IN1 -q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE -q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE -q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE -q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE -q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE -q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE -sclr => _.IN0 -sclr => _.IN0 -sclr => _.IN0 -updown => counter_comb_bita0.DATAB -updown => counter_comb_bita1.DATAB -updown => counter_comb_bita2.DATAB -updown => counter_comb_bita3.DATAB -updown => counter_comb_bita4.DATAB -updown => counter_comb_bita5.DATAB - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram -data[0] => altsyncram_r1m1:altsyncram1.data_a[0] -data[1] => altsyncram_r1m1:altsyncram1.data_a[1] -data[2] => altsyncram_r1m1:altsyncram1.data_a[2] -data[3] => altsyncram_r1m1:altsyncram1.data_a[3] -data[4] => altsyncram_r1m1:altsyncram1.data_a[4] -data[5] => altsyncram_r1m1:altsyncram1.data_a[5] -data[6] => altsyncram_r1m1:altsyncram1.data_a[6] -data[7] => altsyncram_r1m1:altsyncram1.data_a[7] -inclock => altsyncram_r1m1:altsyncram1.clock0 -outclock => altsyncram_r1m1:altsyncram1.clock1 -outclocken => altsyncram_r1m1:altsyncram1.clocken1 -q[0] <= altsyncram_r1m1:altsyncram1.q_b[0] -q[1] <= altsyncram_r1m1:altsyncram1.q_b[1] -q[2] <= altsyncram_r1m1:altsyncram1.q_b[2] -q[3] <= altsyncram_r1m1:altsyncram1.q_b[3] -q[4] <= altsyncram_r1m1:altsyncram1.q_b[4] -q[5] <= altsyncram_r1m1:altsyncram1.q_b[5] -q[6] <= altsyncram_r1m1:altsyncram1.q_b[6] -q[7] <= altsyncram_r1m1:altsyncram1.q_b[7] -rdaddress[0] => altsyncram_r1m1:altsyncram1.address_b[0] -rdaddress[1] => altsyncram_r1m1:altsyncram1.address_b[1] -rdaddress[2] => altsyncram_r1m1:altsyncram1.address_b[2] -rdaddress[3] => altsyncram_r1m1:altsyncram1.address_b[3] -rdaddress[4] => altsyncram_r1m1:altsyncram1.address_b[4] -rdaddress[5] => altsyncram_r1m1:altsyncram1.address_b[5] -wraddress[0] => altsyncram_r1m1:altsyncram1.address_a[0] -wraddress[1] => altsyncram_r1m1:altsyncram1.address_a[1] -wraddress[2] => altsyncram_r1m1:altsyncram1.address_a[2] -wraddress[3] => altsyncram_r1m1:altsyncram1.address_a[3] -wraddress[4] => altsyncram_r1m1:altsyncram1.address_a[4] -wraddress[5] => altsyncram_r1m1:altsyncram1.address_a[5] -wren => altsyncram_r1m1:altsyncram1.wren_a - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 -address_a[0] => ram_block2a0.PORTAADDR -address_a[0] => ram_block2a1.PORTAADDR -address_a[0] => ram_block2a2.PORTAADDR -address_a[0] => ram_block2a3.PORTAADDR -address_a[0] => ram_block2a4.PORTAADDR -address_a[0] => ram_block2a5.PORTAADDR -address_a[0] => ram_block2a6.PORTAADDR -address_a[0] => ram_block2a7.PORTAADDR -address_a[1] => ram_block2a0.PORTAADDR1 -address_a[1] => ram_block2a1.PORTAADDR1 -address_a[1] => ram_block2a2.PORTAADDR1 -address_a[1] => ram_block2a3.PORTAADDR1 -address_a[1] => ram_block2a4.PORTAADDR1 -address_a[1] => ram_block2a5.PORTAADDR1 -address_a[1] => ram_block2a6.PORTAADDR1 -address_a[1] => ram_block2a7.PORTAADDR1 -address_a[2] => ram_block2a0.PORTAADDR2 -address_a[2] => ram_block2a1.PORTAADDR2 -address_a[2] => ram_block2a2.PORTAADDR2 -address_a[2] => ram_block2a3.PORTAADDR2 -address_a[2] => ram_block2a4.PORTAADDR2 -address_a[2] => ram_block2a5.PORTAADDR2 -address_a[2] => ram_block2a6.PORTAADDR2 -address_a[2] => ram_block2a7.PORTAADDR2 -address_a[3] => ram_block2a0.PORTAADDR3 -address_a[3] => ram_block2a1.PORTAADDR3 -address_a[3] => ram_block2a2.PORTAADDR3 -address_a[3] => ram_block2a3.PORTAADDR3 -address_a[3] => ram_block2a4.PORTAADDR3 -address_a[3] => ram_block2a5.PORTAADDR3 -address_a[3] => ram_block2a6.PORTAADDR3 -address_a[3] => ram_block2a7.PORTAADDR3 -address_a[4] => ram_block2a0.PORTAADDR4 -address_a[4] => ram_block2a1.PORTAADDR4 -address_a[4] => ram_block2a2.PORTAADDR4 -address_a[4] => ram_block2a3.PORTAADDR4 -address_a[4] => ram_block2a4.PORTAADDR4 -address_a[4] => ram_block2a5.PORTAADDR4 -address_a[4] => ram_block2a6.PORTAADDR4 -address_a[4] => ram_block2a7.PORTAADDR4 -address_a[5] => ram_block2a0.PORTAADDR5 -address_a[5] => ram_block2a1.PORTAADDR5 -address_a[5] => ram_block2a2.PORTAADDR5 -address_a[5] => ram_block2a3.PORTAADDR5 -address_a[5] => ram_block2a4.PORTAADDR5 -address_a[5] => ram_block2a5.PORTAADDR5 -address_a[5] => ram_block2a6.PORTAADDR5 -address_a[5] => ram_block2a7.PORTAADDR5 -address_b[0] => ram_block2a0.PORTBADDR -address_b[0] => ram_block2a1.PORTBADDR -address_b[0] => ram_block2a2.PORTBADDR -address_b[0] => ram_block2a3.PORTBADDR -address_b[0] => ram_block2a4.PORTBADDR -address_b[0] => ram_block2a5.PORTBADDR -address_b[0] => ram_block2a6.PORTBADDR -address_b[0] => ram_block2a7.PORTBADDR -address_b[1] => ram_block2a0.PORTBADDR1 -address_b[1] => ram_block2a1.PORTBADDR1 -address_b[1] => ram_block2a2.PORTBADDR1 -address_b[1] => ram_block2a3.PORTBADDR1 -address_b[1] => ram_block2a4.PORTBADDR1 -address_b[1] => ram_block2a5.PORTBADDR1 -address_b[1] => ram_block2a6.PORTBADDR1 -address_b[1] => ram_block2a7.PORTBADDR1 -address_b[2] => ram_block2a0.PORTBADDR2 -address_b[2] => ram_block2a1.PORTBADDR2 -address_b[2] => ram_block2a2.PORTBADDR2 -address_b[2] => ram_block2a3.PORTBADDR2 -address_b[2] => ram_block2a4.PORTBADDR2 -address_b[2] => ram_block2a5.PORTBADDR2 -address_b[2] => ram_block2a6.PORTBADDR2 -address_b[2] => ram_block2a7.PORTBADDR2 -address_b[3] => ram_block2a0.PORTBADDR3 -address_b[3] => ram_block2a1.PORTBADDR3 -address_b[3] => ram_block2a2.PORTBADDR3 -address_b[3] => ram_block2a3.PORTBADDR3 -address_b[3] => ram_block2a4.PORTBADDR3 -address_b[3] => ram_block2a5.PORTBADDR3 -address_b[3] => ram_block2a6.PORTBADDR3 -address_b[3] => ram_block2a7.PORTBADDR3 -address_b[4] => ram_block2a0.PORTBADDR4 -address_b[4] => ram_block2a1.PORTBADDR4 -address_b[4] => ram_block2a2.PORTBADDR4 -address_b[4] => ram_block2a3.PORTBADDR4 -address_b[4] => ram_block2a4.PORTBADDR4 -address_b[4] => ram_block2a5.PORTBADDR4 -address_b[4] => ram_block2a6.PORTBADDR4 -address_b[4] => ram_block2a7.PORTBADDR4 -address_b[5] => ram_block2a0.PORTBADDR5 -address_b[5] => ram_block2a1.PORTBADDR5 -address_b[5] => ram_block2a2.PORTBADDR5 -address_b[5] => ram_block2a3.PORTBADDR5 -address_b[5] => ram_block2a4.PORTBADDR5 -address_b[5] => ram_block2a5.PORTBADDR5 -address_b[5] => ram_block2a6.PORTBADDR5 -address_b[5] => ram_block2a7.PORTBADDR5 -clock0 => ram_block2a0.CLK0 -clock0 => ram_block2a1.CLK0 -clock0 => ram_block2a2.CLK0 -clock0 => ram_block2a3.CLK0 -clock0 => ram_block2a4.CLK0 -clock0 => ram_block2a5.CLK0 -clock0 => ram_block2a6.CLK0 -clock0 => ram_block2a7.CLK0 -clock1 => ram_block2a0.CLK1 -clock1 => ram_block2a1.CLK1 -clock1 => ram_block2a2.CLK1 -clock1 => ram_block2a3.CLK1 -clock1 => ram_block2a4.CLK1 -clock1 => ram_block2a5.CLK1 -clock1 => ram_block2a6.CLK1 -clock1 => ram_block2a7.CLK1 -clocken1 => ram_block2a0.ENA1 -clocken1 => ram_block2a1.ENA1 -clocken1 => ram_block2a2.ENA1 -clocken1 => ram_block2a3.ENA1 -clocken1 => ram_block2a4.ENA1 -clocken1 => ram_block2a5.ENA1 -clocken1 => ram_block2a6.ENA1 -clocken1 => ram_block2a7.ENA1 -data_a[0] => ram_block2a0.PORTADATAIN -data_a[1] => ram_block2a1.PORTADATAIN -data_a[2] => ram_block2a2.PORTADATAIN -data_a[3] => ram_block2a3.PORTADATAIN -data_a[4] => ram_block2a4.PORTADATAIN -data_a[5] => ram_block2a5.PORTADATAIN -data_a[6] => ram_block2a6.PORTADATAIN -data_a[7] => ram_block2a7.PORTADATAIN -q_b[0] <= ram_block2a0.PORTBDATAOUT -q_b[1] <= ram_block2a1.PORTBDATAOUT -q_b[2] <= ram_block2a2.PORTBDATAOUT -q_b[3] <= ram_block2a3.PORTBDATAOUT -q_b[4] <= ram_block2a4.PORTBDATAOUT -q_b[5] <= ram_block2a5.PORTBDATAOUT -q_b[6] <= ram_block2a6.PORTBDATAOUT -q_b[7] <= ram_block2a7.PORTBDATAOUT -wren_a => ram_block2a0.PORTAWE -wren_a => ram_block2a0.ENA0 -wren_a => ram_block2a1.PORTAWE -wren_a => ram_block2a1.ENA0 -wren_a => ram_block2a2.PORTAWE -wren_a => ram_block2a2.ENA0 -wren_a => ram_block2a3.PORTAWE -wren_a => ram_block2a3.ENA0 -wren_a => ram_block2a4.PORTAWE -wren_a => ram_block2a4.ENA0 -wren_a => ram_block2a5.PORTAWE -wren_a => ram_block2a5.ENA0 -wren_a => ram_block2a6.PORTAWE -wren_a => ram_block2a6.ENA0 -wren_a => ram_block2a7.PORTAWE -wren_a => ram_block2a7.ENA0 - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count -aclr => counter_reg_bit[5].IN0 -clock => counter_reg_bit[5].CLK -clock => counter_reg_bit[4].CLK -clock => counter_reg_bit[3].CLK -clock => counter_reg_bit[2].CLK -clock => counter_reg_bit[1].CLK -clock => counter_reg_bit[0].CLK -cnt_en => _.IN1 -q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE -q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE -q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE -q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE -q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE -q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE -sclr => _.IN0 -sclr => _.IN0 -sclr => _.IN0 - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr -aclr => counter_reg_bit[5].IN0 -clock => counter_reg_bit[5].CLK -clock => counter_reg_bit[4].CLK -clock => counter_reg_bit[3].CLK -clock => counter_reg_bit[2].CLK -clock => counter_reg_bit[1].CLK -clock => counter_reg_bit[0].CLK -cnt_en => _.IN1 -q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE -q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE -q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE -q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE -q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE -q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE -sclr => _.IN0 -sclr => _.IN0 -sclr => _.IN0 - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r -clk => clk.IN1 -fifo_clear => fifo_clear.IN1 -fifo_rd => fifo_rd.IN1 -rst_n => ~NO_FANOUT~ -t_dat[0] => t_dat[0].IN1 -t_dat[1] => t_dat[1].IN1 -t_dat[2] => t_dat[2].IN1 -t_dat[3] => t_dat[3].IN1 -t_dat[4] => t_dat[4].IN1 -t_dat[5] => t_dat[5].IN1 -t_dat[6] => t_dat[6].IN1 -t_dat[7] => t_dat[7].IN1 -wr_rfifo => wr_rfifo.IN1 -fifo_EF <= scfifo:rfifo.empty -fifo_rdata[0] <= scfifo:rfifo.q -fifo_rdata[1] <= scfifo:rfifo.q -fifo_rdata[2] <= scfifo:rfifo.q -fifo_rdata[3] <= scfifo:rfifo.q -fifo_rdata[4] <= scfifo:rfifo.q -fifo_rdata[5] <= scfifo:rfifo.q -fifo_rdata[6] <= scfifo:rfifo.q -fifo_rdata[7] <= scfifo:rfifo.q -rfifo_full <= scfifo:rfifo.full -rfifo_used[0] <= scfifo:rfifo.usedw -rfifo_used[1] <= scfifo:rfifo.usedw -rfifo_used[2] <= scfifo:rfifo.usedw -rfifo_used[3] <= scfifo:rfifo.usedw -rfifo_used[4] <= scfifo:rfifo.usedw -rfifo_used[5] <= scfifo:rfifo.usedw - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo -data[0] => scfifo_jr21:auto_generated.data[0] -data[1] => scfifo_jr21:auto_generated.data[1] -data[2] => scfifo_jr21:auto_generated.data[2] -data[3] => scfifo_jr21:auto_generated.data[3] -data[4] => scfifo_jr21:auto_generated.data[4] -data[5] => scfifo_jr21:auto_generated.data[5] -data[6] => scfifo_jr21:auto_generated.data[6] -data[7] => scfifo_jr21:auto_generated.data[7] -q[0] <= scfifo_jr21:auto_generated.q[0] -q[1] <= scfifo_jr21:auto_generated.q[1] -q[2] <= scfifo_jr21:auto_generated.q[2] -q[3] <= scfifo_jr21:auto_generated.q[3] -q[4] <= scfifo_jr21:auto_generated.q[4] -q[5] <= scfifo_jr21:auto_generated.q[5] -q[6] <= scfifo_jr21:auto_generated.q[6] -q[7] <= scfifo_jr21:auto_generated.q[7] -wrreq => scfifo_jr21:auto_generated.wrreq -rdreq => scfifo_jr21:auto_generated.rdreq -clock => scfifo_jr21:auto_generated.clock -aclr => scfifo_jr21:auto_generated.aclr -sclr => ~NO_FANOUT~ -empty <= scfifo_jr21:auto_generated.empty -full <= scfifo_jr21:auto_generated.full -almost_full <= -almost_empty <= -usedw[0] <= scfifo_jr21:auto_generated.usedw[0] -usedw[1] <= scfifo_jr21:auto_generated.usedw[1] -usedw[2] <= scfifo_jr21:auto_generated.usedw[2] -usedw[3] <= scfifo_jr21:auto_generated.usedw[3] -usedw[4] <= scfifo_jr21:auto_generated.usedw[4] -usedw[5] <= scfifo_jr21:auto_generated.usedw[5] - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated -aclr => a_dpfifo_q131:dpfifo.aclr -clock => a_dpfifo_q131:dpfifo.clock -data[0] => a_dpfifo_q131:dpfifo.data[0] -data[1] => a_dpfifo_q131:dpfifo.data[1] -data[2] => a_dpfifo_q131:dpfifo.data[2] -data[3] => a_dpfifo_q131:dpfifo.data[3] -data[4] => a_dpfifo_q131:dpfifo.data[4] -data[5] => a_dpfifo_q131:dpfifo.data[5] -data[6] => a_dpfifo_q131:dpfifo.data[6] -data[7] => a_dpfifo_q131:dpfifo.data[7] -empty <= a_dpfifo_q131:dpfifo.empty -full <= a_dpfifo_q131:dpfifo.full -q[0] <= a_dpfifo_q131:dpfifo.q[0] -q[1] <= a_dpfifo_q131:dpfifo.q[1] -q[2] <= a_dpfifo_q131:dpfifo.q[2] -q[3] <= a_dpfifo_q131:dpfifo.q[3] -q[4] <= a_dpfifo_q131:dpfifo.q[4] -q[5] <= a_dpfifo_q131:dpfifo.q[5] -q[6] <= a_dpfifo_q131:dpfifo.q[6] -q[7] <= a_dpfifo_q131:dpfifo.q[7] -rdreq => a_dpfifo_q131:dpfifo.rreq -usedw[0] <= a_dpfifo_q131:dpfifo.usedw[0] -usedw[1] <= a_dpfifo_q131:dpfifo.usedw[1] -usedw[2] <= a_dpfifo_q131:dpfifo.usedw[2] -usedw[3] <= a_dpfifo_q131:dpfifo.usedw[3] -usedw[4] <= a_dpfifo_q131:dpfifo.usedw[4] -usedw[5] <= a_dpfifo_q131:dpfifo.usedw[5] -wrreq => a_dpfifo_q131:dpfifo.wreq - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo -aclr => a_fefifo_7cf:fifo_state.aclr -aclr => cntr_1ob:rd_ptr_count.aclr -aclr => cntr_1ob:wr_ptr.aclr -clock => a_fefifo_7cf:fifo_state.clock -clock => dpram_nl21:FIFOram.inclock -clock => dpram_nl21:FIFOram.outclock -clock => cntr_1ob:rd_ptr_count.clock -clock => cntr_1ob:wr_ptr.clock -data[0] => dpram_nl21:FIFOram.data[0] -data[1] => dpram_nl21:FIFOram.data[1] -data[2] => dpram_nl21:FIFOram.data[2] -data[3] => dpram_nl21:FIFOram.data[3] -data[4] => dpram_nl21:FIFOram.data[4] -data[5] => dpram_nl21:FIFOram.data[5] -data[6] => dpram_nl21:FIFOram.data[6] -data[7] => dpram_nl21:FIFOram.data[7] -empty <= a_fefifo_7cf:fifo_state.empty -full <= a_fefifo_7cf:fifo_state.full -q[0] <= dpram_nl21:FIFOram.q[0] -q[1] <= dpram_nl21:FIFOram.q[1] -q[2] <= dpram_nl21:FIFOram.q[2] -q[3] <= dpram_nl21:FIFOram.q[3] -q[4] <= dpram_nl21:FIFOram.q[4] -q[5] <= dpram_nl21:FIFOram.q[5] -q[6] <= dpram_nl21:FIFOram.q[6] -q[7] <= dpram_nl21:FIFOram.q[7] -rreq => a_fefifo_7cf:fifo_state.rreq -rreq => _.IN0 -rreq => cntr_1ob:rd_ptr_count.cnt_en -sclr => a_fefifo_7cf:fifo_state.sclr -sclr => _.IN1 -sclr => _.IN0 -sclr => cntr_1ob:rd_ptr_count.sclr -sclr => cntr_1ob:wr_ptr.sclr -usedw[0] <= a_fefifo_7cf:fifo_state.usedw_out[0] -usedw[1] <= a_fefifo_7cf:fifo_state.usedw_out[1] -usedw[2] <= a_fefifo_7cf:fifo_state.usedw_out[2] -usedw[3] <= a_fefifo_7cf:fifo_state.usedw_out[3] -usedw[4] <= a_fefifo_7cf:fifo_state.usedw_out[4] -usedw[5] <= a_fefifo_7cf:fifo_state.usedw_out[5] -wreq => a_fefifo_7cf:fifo_state.wreq -wreq => dpram_nl21:FIFOram.wren -wreq => cntr_1ob:wr_ptr.cnt_en - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state -aclr => b_full.IN0 -aclr => b_non_empty.IN0 -aclr => cntr_do7:count_usedw.aclr -clock => cntr_do7:count_usedw.clock -clock => b_full.CLK -clock => b_non_empty.CLK -empty <= empty.DB_MAX_OUTPUT_PORT_TYPE -full <= b_full.DB_MAX_OUTPUT_PORT_TYPE -rreq => _.IN1 -rreq => _.IN0 -rreq => _.IN1 -rreq => _.IN1 -sclr => _.IN0 -sclr => _.IN0 -sclr => _.IN1 -sclr => _.IN0 -sclr => _.IN0 -sclr => cntr_do7:count_usedw.sclr -usedw_out[0] <= usedw[0].DB_MAX_OUTPUT_PORT_TYPE -usedw_out[1] <= usedw[1].DB_MAX_OUTPUT_PORT_TYPE -usedw_out[2] <= usedw[2].DB_MAX_OUTPUT_PORT_TYPE -usedw_out[3] <= usedw[3].DB_MAX_OUTPUT_PORT_TYPE -usedw_out[4] <= usedw[4].DB_MAX_OUTPUT_PORT_TYPE -usedw_out[5] <= usedw[5].DB_MAX_OUTPUT_PORT_TYPE -wreq => _.IN1 -wreq => _.IN1 -wreq => _.IN0 -wreq => _.IN0 -wreq => cntr_do7:count_usedw.updown - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw -aclr => counter_reg_bit[5].IN0 -clock => counter_reg_bit[5].CLK -clock => counter_reg_bit[4].CLK -clock => counter_reg_bit[3].CLK -clock => counter_reg_bit[2].CLK -clock => counter_reg_bit[1].CLK -clock => counter_reg_bit[0].CLK -cnt_en => _.IN1 -q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE -q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE -q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE -q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE -q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE -q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE -sclr => _.IN0 -sclr => _.IN0 -sclr => _.IN0 -updown => counter_comb_bita0.DATAB -updown => counter_comb_bita1.DATAB -updown => counter_comb_bita2.DATAB -updown => counter_comb_bita3.DATAB -updown => counter_comb_bita4.DATAB -updown => counter_comb_bita5.DATAB - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram -data[0] => altsyncram_r1m1:altsyncram1.data_a[0] -data[1] => altsyncram_r1m1:altsyncram1.data_a[1] -data[2] => altsyncram_r1m1:altsyncram1.data_a[2] -data[3] => altsyncram_r1m1:altsyncram1.data_a[3] -data[4] => altsyncram_r1m1:altsyncram1.data_a[4] -data[5] => altsyncram_r1m1:altsyncram1.data_a[5] -data[6] => altsyncram_r1m1:altsyncram1.data_a[6] -data[7] => altsyncram_r1m1:altsyncram1.data_a[7] -inclock => altsyncram_r1m1:altsyncram1.clock0 -outclock => altsyncram_r1m1:altsyncram1.clock1 -outclocken => altsyncram_r1m1:altsyncram1.clocken1 -q[0] <= altsyncram_r1m1:altsyncram1.q_b[0] -q[1] <= altsyncram_r1m1:altsyncram1.q_b[1] -q[2] <= altsyncram_r1m1:altsyncram1.q_b[2] -q[3] <= altsyncram_r1m1:altsyncram1.q_b[3] -q[4] <= altsyncram_r1m1:altsyncram1.q_b[4] -q[5] <= altsyncram_r1m1:altsyncram1.q_b[5] -q[6] <= altsyncram_r1m1:altsyncram1.q_b[6] -q[7] <= altsyncram_r1m1:altsyncram1.q_b[7] -rdaddress[0] => altsyncram_r1m1:altsyncram1.address_b[0] -rdaddress[1] => altsyncram_r1m1:altsyncram1.address_b[1] -rdaddress[2] => altsyncram_r1m1:altsyncram1.address_b[2] -rdaddress[3] => altsyncram_r1m1:altsyncram1.address_b[3] -rdaddress[4] => altsyncram_r1m1:altsyncram1.address_b[4] -rdaddress[5] => altsyncram_r1m1:altsyncram1.address_b[5] -wraddress[0] => altsyncram_r1m1:altsyncram1.address_a[0] -wraddress[1] => altsyncram_r1m1:altsyncram1.address_a[1] -wraddress[2] => altsyncram_r1m1:altsyncram1.address_a[2] -wraddress[3] => altsyncram_r1m1:altsyncram1.address_a[3] -wraddress[4] => altsyncram_r1m1:altsyncram1.address_a[4] -wraddress[5] => altsyncram_r1m1:altsyncram1.address_a[5] -wren => altsyncram_r1m1:altsyncram1.wren_a - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 -address_a[0] => ram_block2a0.PORTAADDR -address_a[0] => ram_block2a1.PORTAADDR -address_a[0] => ram_block2a2.PORTAADDR -address_a[0] => ram_block2a3.PORTAADDR -address_a[0] => ram_block2a4.PORTAADDR -address_a[0] => ram_block2a5.PORTAADDR -address_a[0] => ram_block2a6.PORTAADDR -address_a[0] => ram_block2a7.PORTAADDR -address_a[1] => ram_block2a0.PORTAADDR1 -address_a[1] => ram_block2a1.PORTAADDR1 -address_a[1] => ram_block2a2.PORTAADDR1 -address_a[1] => ram_block2a3.PORTAADDR1 -address_a[1] => ram_block2a4.PORTAADDR1 -address_a[1] => ram_block2a5.PORTAADDR1 -address_a[1] => ram_block2a6.PORTAADDR1 -address_a[1] => ram_block2a7.PORTAADDR1 -address_a[2] => ram_block2a0.PORTAADDR2 -address_a[2] => ram_block2a1.PORTAADDR2 -address_a[2] => ram_block2a2.PORTAADDR2 -address_a[2] => ram_block2a3.PORTAADDR2 -address_a[2] => ram_block2a4.PORTAADDR2 -address_a[2] => ram_block2a5.PORTAADDR2 -address_a[2] => ram_block2a6.PORTAADDR2 -address_a[2] => ram_block2a7.PORTAADDR2 -address_a[3] => ram_block2a0.PORTAADDR3 -address_a[3] => ram_block2a1.PORTAADDR3 -address_a[3] => ram_block2a2.PORTAADDR3 -address_a[3] => ram_block2a3.PORTAADDR3 -address_a[3] => ram_block2a4.PORTAADDR3 -address_a[3] => ram_block2a5.PORTAADDR3 -address_a[3] => ram_block2a6.PORTAADDR3 -address_a[3] => ram_block2a7.PORTAADDR3 -address_a[4] => ram_block2a0.PORTAADDR4 -address_a[4] => ram_block2a1.PORTAADDR4 -address_a[4] => ram_block2a2.PORTAADDR4 -address_a[4] => ram_block2a3.PORTAADDR4 -address_a[4] => ram_block2a4.PORTAADDR4 -address_a[4] => ram_block2a5.PORTAADDR4 -address_a[4] => ram_block2a6.PORTAADDR4 -address_a[4] => ram_block2a7.PORTAADDR4 -address_a[5] => ram_block2a0.PORTAADDR5 -address_a[5] => ram_block2a1.PORTAADDR5 -address_a[5] => ram_block2a2.PORTAADDR5 -address_a[5] => ram_block2a3.PORTAADDR5 -address_a[5] => ram_block2a4.PORTAADDR5 -address_a[5] => ram_block2a5.PORTAADDR5 -address_a[5] => ram_block2a6.PORTAADDR5 -address_a[5] => ram_block2a7.PORTAADDR5 -address_b[0] => ram_block2a0.PORTBADDR -address_b[0] => ram_block2a1.PORTBADDR -address_b[0] => ram_block2a2.PORTBADDR -address_b[0] => ram_block2a3.PORTBADDR -address_b[0] => ram_block2a4.PORTBADDR -address_b[0] => ram_block2a5.PORTBADDR -address_b[0] => ram_block2a6.PORTBADDR -address_b[0] => ram_block2a7.PORTBADDR -address_b[1] => ram_block2a0.PORTBADDR1 -address_b[1] => ram_block2a1.PORTBADDR1 -address_b[1] => ram_block2a2.PORTBADDR1 -address_b[1] => ram_block2a3.PORTBADDR1 -address_b[1] => ram_block2a4.PORTBADDR1 -address_b[1] => ram_block2a5.PORTBADDR1 -address_b[1] => ram_block2a6.PORTBADDR1 -address_b[1] => ram_block2a7.PORTBADDR1 -address_b[2] => ram_block2a0.PORTBADDR2 -address_b[2] => ram_block2a1.PORTBADDR2 -address_b[2] => ram_block2a2.PORTBADDR2 -address_b[2] => ram_block2a3.PORTBADDR2 -address_b[2] => ram_block2a4.PORTBADDR2 -address_b[2] => ram_block2a5.PORTBADDR2 -address_b[2] => ram_block2a6.PORTBADDR2 -address_b[2] => ram_block2a7.PORTBADDR2 -address_b[3] => ram_block2a0.PORTBADDR3 -address_b[3] => ram_block2a1.PORTBADDR3 -address_b[3] => ram_block2a2.PORTBADDR3 -address_b[3] => ram_block2a3.PORTBADDR3 -address_b[3] => ram_block2a4.PORTBADDR3 -address_b[3] => ram_block2a5.PORTBADDR3 -address_b[3] => ram_block2a6.PORTBADDR3 -address_b[3] => ram_block2a7.PORTBADDR3 -address_b[4] => ram_block2a0.PORTBADDR4 -address_b[4] => ram_block2a1.PORTBADDR4 -address_b[4] => ram_block2a2.PORTBADDR4 -address_b[4] => ram_block2a3.PORTBADDR4 -address_b[4] => ram_block2a4.PORTBADDR4 -address_b[4] => ram_block2a5.PORTBADDR4 -address_b[4] => ram_block2a6.PORTBADDR4 -address_b[4] => ram_block2a7.PORTBADDR4 -address_b[5] => ram_block2a0.PORTBADDR5 -address_b[5] => ram_block2a1.PORTBADDR5 -address_b[5] => ram_block2a2.PORTBADDR5 -address_b[5] => ram_block2a3.PORTBADDR5 -address_b[5] => ram_block2a4.PORTBADDR5 -address_b[5] => ram_block2a5.PORTBADDR5 -address_b[5] => ram_block2a6.PORTBADDR5 -address_b[5] => ram_block2a7.PORTBADDR5 -clock0 => ram_block2a0.CLK0 -clock0 => ram_block2a1.CLK0 -clock0 => ram_block2a2.CLK0 -clock0 => ram_block2a3.CLK0 -clock0 => ram_block2a4.CLK0 -clock0 => ram_block2a5.CLK0 -clock0 => ram_block2a6.CLK0 -clock0 => ram_block2a7.CLK0 -clock1 => ram_block2a0.CLK1 -clock1 => ram_block2a1.CLK1 -clock1 => ram_block2a2.CLK1 -clock1 => ram_block2a3.CLK1 -clock1 => ram_block2a4.CLK1 -clock1 => ram_block2a5.CLK1 -clock1 => ram_block2a6.CLK1 -clock1 => ram_block2a7.CLK1 -clocken1 => ram_block2a0.ENA1 -clocken1 => ram_block2a1.ENA1 -clocken1 => ram_block2a2.ENA1 -clocken1 => ram_block2a3.ENA1 -clocken1 => ram_block2a4.ENA1 -clocken1 => ram_block2a5.ENA1 -clocken1 => ram_block2a6.ENA1 -clocken1 => ram_block2a7.ENA1 -data_a[0] => ram_block2a0.PORTADATAIN -data_a[1] => ram_block2a1.PORTADATAIN -data_a[2] => ram_block2a2.PORTADATAIN -data_a[3] => ram_block2a3.PORTADATAIN -data_a[4] => ram_block2a4.PORTADATAIN -data_a[5] => ram_block2a5.PORTADATAIN -data_a[6] => ram_block2a6.PORTADATAIN -data_a[7] => ram_block2a7.PORTADATAIN -q_b[0] <= ram_block2a0.PORTBDATAOUT -q_b[1] <= ram_block2a1.PORTBDATAOUT -q_b[2] <= ram_block2a2.PORTBDATAOUT -q_b[3] <= ram_block2a3.PORTBDATAOUT -q_b[4] <= ram_block2a4.PORTBDATAOUT -q_b[5] <= ram_block2a5.PORTBDATAOUT -q_b[6] <= ram_block2a6.PORTBDATAOUT -q_b[7] <= ram_block2a7.PORTBDATAOUT -wren_a => ram_block2a0.PORTAWE -wren_a => ram_block2a0.ENA0 -wren_a => ram_block2a1.PORTAWE -wren_a => ram_block2a1.ENA0 -wren_a => ram_block2a2.PORTAWE -wren_a => ram_block2a2.ENA0 -wren_a => ram_block2a3.PORTAWE -wren_a => ram_block2a3.ENA0 -wren_a => ram_block2a4.PORTAWE -wren_a => ram_block2a4.ENA0 -wren_a => ram_block2a5.PORTAWE -wren_a => ram_block2a5.ENA0 -wren_a => ram_block2a6.PORTAWE -wren_a => ram_block2a6.ENA0 -wren_a => ram_block2a7.PORTAWE -wren_a => ram_block2a7.ENA0 - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count -aclr => counter_reg_bit[5].IN0 -clock => counter_reg_bit[5].CLK -clock => counter_reg_bit[4].CLK -clock => counter_reg_bit[3].CLK -clock => counter_reg_bit[2].CLK -clock => counter_reg_bit[1].CLK -clock => counter_reg_bit[0].CLK -cnt_en => _.IN1 -q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE -q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE -q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE -q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE -q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE -q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE -sclr => _.IN0 -sclr => _.IN0 -sclr => _.IN0 - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr -aclr => counter_reg_bit[5].IN0 -clock => counter_reg_bit[5].CLK -clock => counter_reg_bit[4].CLK -clock => counter_reg_bit[3].CLK -clock => counter_reg_bit[2].CLK -clock => counter_reg_bit[1].CLK -clock => counter_reg_bit[0].CLK -cnt_en => _.IN1 -q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE -q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE -q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE -q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE -q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE -q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE -sclr => _.IN0 -sclr => _.IN0 -sclr => _.IN0 - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic -raw_tck => write_stalled.CLK -raw_tck => wdata[0].CLK -raw_tck => wdata[1].CLK -raw_tck => wdata[2].CLK -raw_tck => wdata[3].CLK -raw_tck => wdata[4].CLK -raw_tck => wdata[5].CLK -raw_tck => wdata[6].CLK -raw_tck => wdata[7].CLK -raw_tck => write.CLK -raw_tck => read.CLK -raw_tck => read_req.CLK -raw_tck => write_valid.CLK -raw_tck => count[0].CLK -raw_tck => count[1].CLK -raw_tck => count[2].CLK -raw_tck => count[3].CLK -raw_tck => count[4].CLK -raw_tck => count[5].CLK -raw_tck => count[6].CLK -raw_tck => count[7].CLK -raw_tck => count[8].CLK -raw_tck => count[9].CLK -raw_tck => state.CLK -raw_tck => user_saw_rvalid.CLK -raw_tck => td_shift[0].CLK -raw_tck => td_shift[1].CLK -raw_tck => td_shift[2].CLK -raw_tck => td_shift[3].CLK -raw_tck => td_shift[4].CLK -raw_tck => td_shift[5].CLK -raw_tck => td_shift[6].CLK -raw_tck => td_shift[7].CLK -raw_tck => td_shift[8].CLK -raw_tck => td_shift[9].CLK -raw_tck => td_shift[10].CLK -raw_tck => tck_t_dav.CLK -raw_tck => jupdate.CLK -raw_tck => tdo~reg0.CLK -tck => ~NO_FANOUT~ -tdi => td_shift.OUTPUTSELECT -tdi => count.OUTPUTSELECT -tdi => state.OUTPUTSELECT -tdi => wdata.DATAB -tdi => always0.IN1 -tdi => wdata.DATAB -tdi => td_shift.DATAB -rti => ~NO_FANOUT~ -shift => ~NO_FANOUT~ -update => ~NO_FANOUT~ -usr1 => always0.IN0 -clr => jupdate.ACLR -clr => tdo~reg0.ACLR -clr => write_stalled.ACLR -clr => wdata[0].ACLR -clr => wdata[1].ACLR -clr => wdata[2].ACLR -clr => wdata[3].ACLR -clr => wdata[4].ACLR -clr => wdata[5].ACLR -clr => wdata[6].ACLR -clr => wdata[7].ACLR -clr => write.ACLR -clr => read.ACLR -clr => read_req.ACLR -clr => write_valid.ACLR -clr => count[0].ACLR -clr => count[1].ACLR -clr => count[2].ACLR -clr => count[3].ACLR -clr => count[4].ACLR -clr => count[5].ACLR -clr => count[6].ACLR -clr => count[7].ACLR -clr => count[8].ACLR -clr => count[9].PRESET -clr => state.ACLR -clr => user_saw_rvalid.ACLR -clr => td_shift[0].ACLR -clr => td_shift[1].ACLR -clr => td_shift[2].ACLR -clr => td_shift[3].ACLR -clr => td_shift[4].ACLR -clr => td_shift[5].ACLR -clr => td_shift[6].ACLR -clr => td_shift[7].ACLR -clr => td_shift[8].ACLR -clr => td_shift[9].ACLR -clr => td_shift[10].ACLR -clr => tck_t_dav.ACLR -ena => always0.IN1 -ir_in[0] => Decoder1.IN0 -ir_in[0] => ir_out[0].DATAIN -tdo <= tdo~reg0.DB_MAX_OUTPUT_PORT_TYPE -irq <= -ir_out[0] <= ir_in[0].DB_MAX_OUTPUT_PORT_TYPE -jtag_state_cdr => state.OUTPUTSELECT -jtag_state_cdr => count.OUTPUTSELECT -jtag_state_cdr => count.OUTPUTSELECT -jtag_state_cdr => count.OUTPUTSELECT -jtag_state_cdr => count.OUTPUTSELECT -jtag_state_cdr => count.OUTPUTSELECT -jtag_state_cdr => count.OUTPUTSELECT -jtag_state_cdr => count.OUTPUTSELECT -jtag_state_cdr => count.OUTPUTSELECT -jtag_state_cdr => count.OUTPUTSELECT -jtag_state_cdr => count.OUTPUTSELECT -jtag_state_cdr => td_shift.OUTPUTSELECT -jtag_state_cdr => td_shift.OUTPUTSELECT -jtag_state_cdr => td_shift.OUTPUTSELECT -jtag_state_cdr => td_shift.OUTPUTSELECT -jtag_state_cdr => td_shift.OUTPUTSELECT -jtag_state_cdr => td_shift.OUTPUTSELECT -jtag_state_cdr => td_shift.OUTPUTSELECT -jtag_state_cdr => td_shift.OUTPUTSELECT -jtag_state_cdr => td_shift.OUTPUTSELECT -jtag_state_cdr => td_shift.OUTPUTSELECT -jtag_state_cdr => td_shift.OUTPUTSELECT -jtag_state_sdr => count.OUTPUTSELECT -jtag_state_sdr => count.OUTPUTSELECT -jtag_state_sdr => count.OUTPUTSELECT -jtag_state_sdr => count.OUTPUTSELECT -jtag_state_sdr => count.OUTPUTSELECT -jtag_state_sdr => count.OUTPUTSELECT -jtag_state_sdr => count.OUTPUTSELECT -jtag_state_sdr => count.OUTPUTSELECT -jtag_state_sdr => count.OUTPUTSELECT -jtag_state_sdr => count.OUTPUTSELECT -jtag_state_sdr => td_shift.OUTPUTSELECT -jtag_state_sdr => td_shift.OUTPUTSELECT -jtag_state_sdr => td_shift.OUTPUTSELECT -jtag_state_sdr => td_shift.OUTPUTSELECT -jtag_state_sdr => td_shift.OUTPUTSELECT -jtag_state_sdr => td_shift.OUTPUTSELECT -jtag_state_sdr => td_shift.OUTPUTSELECT -jtag_state_sdr => td_shift.OUTPUTSELECT -jtag_state_sdr => td_shift.OUTPUTSELECT -jtag_state_sdr => td_shift.OUTPUTSELECT -jtag_state_sdr => td_shift.OUTPUTSELECT -jtag_state_sdr => write.OUTPUTSELECT -jtag_state_sdr => wdata.OUTPUTSELECT -jtag_state_sdr => wdata.OUTPUTSELECT -jtag_state_sdr => wdata.OUTPUTSELECT -jtag_state_sdr => wdata.OUTPUTSELECT -jtag_state_sdr => wdata.OUTPUTSELECT -jtag_state_sdr => wdata.OUTPUTSELECT -jtag_state_sdr => wdata.OUTPUTSELECT -jtag_state_sdr => wdata.OUTPUTSELECT -jtag_state_sdr => user_saw_rvalid.OUTPUTSELECT -jtag_state_sdr => read.OUTPUTSELECT -jtag_state_sdr => write_valid.OUTPUTSELECT -jtag_state_sdr => read_req.OUTPUTSELECT -jtag_state_sdr => write_stalled.OUTPUTSELECT -jtag_state_sdr => state.OUTPUTSELECT -jtag_state_udr => jupdate.OUTPUTSELECT -clk => t_pause~reg0.CLK -clk => t_ena~reg0.CLK -clk => rdata[0].CLK -clk => rdata[1].CLK -clk => rdata[2].CLK -clk => rdata[3].CLK -clk => rdata[4].CLK -clk => rdata[5].CLK -clk => rdata[6].CLK -clk => rdata[7].CLK -clk => rvalid.CLK -clk => rvalid0.CLK -clk => r_ena1.CLK -clk => jupdate2.CLK -clk => jupdate1.CLK -clk => write2.CLK -clk => write1.CLK -clk => read2.CLK -clk => read1.CLK -clk => rst2.CLK -clk => rst1.CLK -rst_n => t_pause~reg0.ACLR -rst_n => t_ena~reg0.ACLR -rst_n => rdata[0].ACLR -rst_n => rdata[1].ACLR -rst_n => rdata[2].ACLR -rst_n => rdata[3].ACLR -rst_n => rdata[4].ACLR -rst_n => rdata[5].ACLR -rst_n => rdata[6].ACLR -rst_n => rdata[7].ACLR -rst_n => rvalid.ACLR -rst_n => rvalid0.ACLR -rst_n => r_ena1.ACLR -rst_n => jupdate2.ACLR -rst_n => jupdate1.ACLR -rst_n => write2.ACLR -rst_n => write1.ACLR -rst_n => read2.ACLR -rst_n => read1.ACLR -rst_n => rst2.PRESET -rst_n => rst1.PRESET -r_ena <= r_ena.DB_MAX_OUTPUT_PORT_TYPE -r_val => r_ena.IN1 -r_dat[0] => rdata[0].DATAIN -r_dat[1] => rdata[1].DATAIN -r_dat[2] => rdata[2].DATAIN -r_dat[3] => rdata[3].DATAIN -r_dat[4] => rdata[4].DATAIN -r_dat[5] => rdata[5].DATAIN -r_dat[6] => rdata[6].DATAIN -r_dat[7] => rdata[7].DATAIN -t_dav => always2.IN1 -t_dav => tck_t_dav.DATAIN -t_ena <= t_ena~reg0.DB_MAX_OUTPUT_PORT_TYPE -t_dat[0] <= t_dat[0].DB_MAX_OUTPUT_PORT_TYPE -t_dat[1] <= t_dat[1].DB_MAX_OUTPUT_PORT_TYPE -t_dat[2] <= t_dat[2].DB_MAX_OUTPUT_PORT_TYPE -t_dat[3] <= t_dat[3].DB_MAX_OUTPUT_PORT_TYPE -t_dat[4] <= t_dat[4].DB_MAX_OUTPUT_PORT_TYPE -t_dat[5] <= t_dat[5].DB_MAX_OUTPUT_PORT_TYPE -t_dat[6] <= t_dat[6].DB_MAX_OUTPUT_PORT_TYPE -t_dat[7] <= t_dat[7].DB_MAX_OUTPUT_PORT_TYPE -t_pause <= t_pause~reg0.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_LEDs:leds -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -chipselect => always0.IN0 -clk => data_out[0].CLK -clk => data_out[1].CLK -clk => data_out[2].CLK -clk => data_out[3].CLK -clk => data_out[4].CLK -clk => data_out[5].CLK -clk => data_out[6].CLK -clk => data_out[7].CLK -reset_n => data_out[0].ACLR -reset_n => data_out[1].ACLR -reset_n => data_out[2].ACLR -reset_n => data_out[3].ACLR -reset_n => data_out[4].ACLR -reset_n => data_out[5].ACLR -reset_n => data_out[6].ACLR -reset_n => data_out[7].ACLR -write_n => always0.IN1 -writedata[0] => data_out[0].DATAIN -writedata[1] => data_out[1].DATAIN -writedata[2] => data_out[2].DATAIN -writedata[3] => data_out[3].DATAIN -writedata[4] => data_out[4].DATAIN -writedata[5] => data_out[5].DATAIN -writedata[6] => data_out[6].DATAIN -writedata[7] => data_out[7].DATAIN -writedata[8] => ~NO_FANOUT~ -writedata[9] => ~NO_FANOUT~ -writedata[10] => ~NO_FANOUT~ -writedata[11] => ~NO_FANOUT~ -writedata[12] => ~NO_FANOUT~ -writedata[13] => ~NO_FANOUT~ -writedata[14] => ~NO_FANOUT~ -writedata[15] => ~NO_FANOUT~ -writedata[16] => ~NO_FANOUT~ -writedata[17] => ~NO_FANOUT~ -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE -out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE -out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE -out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE -out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE -out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE -out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE -out_port[7] <= data_out[7].DB_MAX_OUTPUT_PORT_TYPE -readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[8] <= -readdata[9] <= -readdata[10] <= -readdata[11] <= -readdata[12] <= -readdata[13] <= -readdata[14] <= -readdata[15] <= -readdata[16] <= -readdata[17] <= -readdata[18] <= -readdata[19] <= -readdata[20] <= -readdata[21] <= -readdata[22] <= -readdata[23] <= -readdata[24] <= -readdata[25] <= -readdata[26] <= -readdata[27] <= -readdata[28] <= -readdata[29] <= -readdata[30] <= -readdata[31] <= - - -|lights|nios_system:NiosII|nios_system_LEDRs:ledrs -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -chipselect => always0.IN0 -clk => data_out[0].CLK -clk => data_out[1].CLK -clk => data_out[2].CLK -clk => data_out[3].CLK -clk => data_out[4].CLK -clk => data_out[5].CLK -clk => data_out[6].CLK -clk => data_out[7].CLK -clk => data_out[8].CLK -clk => data_out[9].CLK -clk => data_out[10].CLK -clk => data_out[11].CLK -clk => data_out[12].CLK -clk => data_out[13].CLK -clk => data_out[14].CLK -clk => data_out[15].CLK -clk => data_out[16].CLK -clk => data_out[17].CLK -reset_n => data_out[0].ACLR -reset_n => data_out[1].ACLR -reset_n => data_out[2].ACLR -reset_n => data_out[3].ACLR -reset_n => data_out[4].ACLR -reset_n => data_out[5].ACLR -reset_n => data_out[6].ACLR -reset_n => data_out[7].ACLR -reset_n => data_out[8].ACLR -reset_n => data_out[9].ACLR -reset_n => data_out[10].ACLR -reset_n => data_out[11].ACLR -reset_n => data_out[12].ACLR -reset_n => data_out[13].ACLR -reset_n => data_out[14].ACLR -reset_n => data_out[15].ACLR -reset_n => data_out[16].ACLR -reset_n => data_out[17].ACLR -write_n => always0.IN1 -writedata[0] => data_out[0].DATAIN -writedata[1] => data_out[1].DATAIN -writedata[2] => data_out[2].DATAIN -writedata[3] => data_out[3].DATAIN -writedata[4] => data_out[4].DATAIN -writedata[5] => data_out[5].DATAIN -writedata[6] => data_out[6].DATAIN -writedata[7] => data_out[7].DATAIN -writedata[8] => data_out[8].DATAIN -writedata[9] => data_out[9].DATAIN -writedata[10] => data_out[10].DATAIN -writedata[11] => data_out[11].DATAIN -writedata[12] => data_out[12].DATAIN -writedata[13] => data_out[13].DATAIN -writedata[14] => data_out[14].DATAIN -writedata[15] => data_out[15].DATAIN -writedata[16] => data_out[16].DATAIN -writedata[17] => data_out[17].DATAIN -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE -out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE -out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE -out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE -out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE -out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE -out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE -out_port[7] <= data_out[7].DB_MAX_OUTPUT_PORT_TYPE -out_port[8] <= data_out[8].DB_MAX_OUTPUT_PORT_TYPE -out_port[9] <= data_out[9].DB_MAX_OUTPUT_PORT_TYPE -out_port[10] <= data_out[10].DB_MAX_OUTPUT_PORT_TYPE -out_port[11] <= data_out[11].DB_MAX_OUTPUT_PORT_TYPE -out_port[12] <= data_out[12].DB_MAX_OUTPUT_PORT_TYPE -out_port[13] <= data_out[13].DB_MAX_OUTPUT_PORT_TYPE -out_port[14] <= data_out[14].DB_MAX_OUTPUT_PORT_TYPE -out_port[15] <= data_out[15].DB_MAX_OUTPUT_PORT_TYPE -out_port[16] <= data_out[16].DB_MAX_OUTPUT_PORT_TYPE -out_port[17] <= data_out[17].DB_MAX_OUTPUT_PORT_TYPE -readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[8] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[9] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[10] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[11] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[12] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[13] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[14] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[15] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[16] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[17] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[18] <= -readdata[19] <= -readdata[20] <= -readdata[21] <= -readdata[22] <= -readdata[23] <= -readdata[24] <= -readdata[25] <= -readdata[26] <= -readdata[27] <= -readdata[28] <= -readdata[29] <= -readdata[30] <= -readdata[31] <= - - -|lights|nios_system:NiosII|nios_system_switches:switches -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -clk => readdata[0]~reg0.CLK -clk => readdata[1]~reg0.CLK -clk => readdata[2]~reg0.CLK -clk => readdata[3]~reg0.CLK -clk => readdata[4]~reg0.CLK -clk => readdata[5]~reg0.CLK -clk => readdata[6]~reg0.CLK -clk => readdata[7]~reg0.CLK -clk => readdata[8]~reg0.CLK -clk => readdata[9]~reg0.CLK -clk => readdata[10]~reg0.CLK -clk => readdata[11]~reg0.CLK -clk => readdata[12]~reg0.CLK -clk => readdata[13]~reg0.CLK -clk => readdata[14]~reg0.CLK -clk => readdata[15]~reg0.CLK -clk => readdata[16]~reg0.CLK -clk => readdata[17]~reg0.CLK -clk => readdata[18]~reg0.CLK -clk => readdata[19]~reg0.CLK -clk => readdata[20]~reg0.CLK -clk => readdata[21]~reg0.CLK -clk => readdata[22]~reg0.CLK -clk => readdata[23]~reg0.CLK -clk => readdata[24]~reg0.CLK -clk => readdata[25]~reg0.CLK -clk => readdata[26]~reg0.CLK -clk => readdata[27]~reg0.CLK -clk => readdata[28]~reg0.CLK -clk => readdata[29]~reg0.CLK -clk => readdata[30]~reg0.CLK -clk => readdata[31]~reg0.CLK -in_port[0] => read_mux_out[0].IN1 -in_port[1] => read_mux_out[1].IN1 -in_port[2] => read_mux_out[2].IN1 -in_port[3] => read_mux_out[3].IN1 -in_port[4] => read_mux_out[4].IN1 -in_port[5] => read_mux_out[5].IN1 -in_port[6] => read_mux_out[6].IN1 -in_port[7] => read_mux_out[7].IN1 -in_port[8] => read_mux_out[8].IN1 -in_port[9] => read_mux_out[9].IN1 -in_port[10] => read_mux_out[10].IN1 -in_port[11] => read_mux_out[11].IN1 -in_port[12] => read_mux_out[12].IN1 -in_port[13] => read_mux_out[13].IN1 -in_port[14] => read_mux_out[14].IN1 -in_port[15] => read_mux_out[15].IN1 -in_port[16] => read_mux_out[16].IN1 -in_port[17] => read_mux_out[17].IN1 -reset_n => readdata[0]~reg0.ACLR -reset_n => readdata[1]~reg0.ACLR -reset_n => readdata[2]~reg0.ACLR -reset_n => readdata[3]~reg0.ACLR -reset_n => readdata[4]~reg0.ACLR -reset_n => readdata[5]~reg0.ACLR -reset_n => readdata[6]~reg0.ACLR -reset_n => readdata[7]~reg0.ACLR -reset_n => readdata[8]~reg0.ACLR -reset_n => readdata[9]~reg0.ACLR -reset_n => readdata[10]~reg0.ACLR -reset_n => readdata[11]~reg0.ACLR -reset_n => readdata[12]~reg0.ACLR -reset_n => readdata[13]~reg0.ACLR -reset_n => readdata[14]~reg0.ACLR -reset_n => readdata[15]~reg0.ACLR -reset_n => readdata[16]~reg0.ACLR -reset_n => readdata[17]~reg0.ACLR -reset_n => readdata[18]~reg0.ACLR -reset_n => readdata[19]~reg0.ACLR -reset_n => readdata[20]~reg0.ACLR -reset_n => readdata[21]~reg0.ACLR -reset_n => readdata[22]~reg0.ACLR -reset_n => readdata[23]~reg0.ACLR -reset_n => readdata[24]~reg0.ACLR -reset_n => readdata[25]~reg0.ACLR -reset_n => readdata[26]~reg0.ACLR -reset_n => readdata[27]~reg0.ACLR -reset_n => readdata[28]~reg0.ACLR -reset_n => readdata[29]~reg0.ACLR -reset_n => readdata[30]~reg0.ACLR -reset_n => readdata[31]~reg0.ACLR -readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[10] <= readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[11] <= readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[12] <= readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[13] <= readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[14] <= readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[15] <= readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[16] <= readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[17] <= readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[18] <= readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[19] <= readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[20] <= readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[21] <= readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[22] <= readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[23] <= readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[24] <= readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[25] <= readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[26] <= readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[27] <= readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[28] <= readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[29] <= readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[30] <= readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[31] <= readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_push_switches:push_switches -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -clk => readdata[0]~reg0.CLK -clk => readdata[1]~reg0.CLK -clk => readdata[2]~reg0.CLK -clk => readdata[3]~reg0.CLK -clk => readdata[4]~reg0.CLK -clk => readdata[5]~reg0.CLK -clk => readdata[6]~reg0.CLK -clk => readdata[7]~reg0.CLK -clk => readdata[8]~reg0.CLK -clk => readdata[9]~reg0.CLK -clk => readdata[10]~reg0.CLK -clk => readdata[11]~reg0.CLK -clk => readdata[12]~reg0.CLK -clk => readdata[13]~reg0.CLK -clk => readdata[14]~reg0.CLK -clk => readdata[15]~reg0.CLK -clk => readdata[16]~reg0.CLK -clk => readdata[17]~reg0.CLK -clk => readdata[18]~reg0.CLK -clk => readdata[19]~reg0.CLK -clk => readdata[20]~reg0.CLK -clk => readdata[21]~reg0.CLK -clk => readdata[22]~reg0.CLK -clk => readdata[23]~reg0.CLK -clk => readdata[24]~reg0.CLK -clk => readdata[25]~reg0.CLK -clk => readdata[26]~reg0.CLK -clk => readdata[27]~reg0.CLK -clk => readdata[28]~reg0.CLK -clk => readdata[29]~reg0.CLK -clk => readdata[30]~reg0.CLK -clk => readdata[31]~reg0.CLK -in_port[0] => read_mux_out[0].IN1 -in_port[1] => read_mux_out[1].IN1 -in_port[2] => read_mux_out[2].IN1 -reset_n => readdata[0]~reg0.ACLR -reset_n => readdata[1]~reg0.ACLR -reset_n => readdata[2]~reg0.ACLR -reset_n => readdata[3]~reg0.ACLR -reset_n => readdata[4]~reg0.ACLR -reset_n => readdata[5]~reg0.ACLR -reset_n => readdata[6]~reg0.ACLR -reset_n => readdata[7]~reg0.ACLR -reset_n => readdata[8]~reg0.ACLR -reset_n => readdata[9]~reg0.ACLR -reset_n => readdata[10]~reg0.ACLR -reset_n => readdata[11]~reg0.ACLR -reset_n => readdata[12]~reg0.ACLR -reset_n => readdata[13]~reg0.ACLR -reset_n => readdata[14]~reg0.ACLR -reset_n => readdata[15]~reg0.ACLR -reset_n => readdata[16]~reg0.ACLR -reset_n => readdata[17]~reg0.ACLR -reset_n => readdata[18]~reg0.ACLR -reset_n => readdata[19]~reg0.ACLR -reset_n => readdata[20]~reg0.ACLR -reset_n => readdata[21]~reg0.ACLR -reset_n => readdata[22]~reg0.ACLR -reset_n => readdata[23]~reg0.ACLR -reset_n => readdata[24]~reg0.ACLR -reset_n => readdata[25]~reg0.ACLR -reset_n => readdata[26]~reg0.ACLR -reset_n => readdata[27]~reg0.ACLR -reset_n => readdata[28]~reg0.ACLR -reset_n => readdata[29]~reg0.ACLR -reset_n => readdata[30]~reg0.ACLR -reset_n => readdata[31]~reg0.ACLR -readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[10] <= readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[11] <= readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[12] <= readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[13] <= readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[14] <= readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[15] <= readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[16] <= readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[17] <= readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[18] <= readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[19] <= readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[20] <= readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[21] <= readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[22] <= readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[23] <= readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[24] <= readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[25] <= readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[26] <= readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[27] <= readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[28] <= readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[29] <= readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[30] <= readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[31] <= readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_hex0:hex0 -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -chipselect => always0.IN0 -clk => data_out[0].CLK -clk => data_out[1].CLK -clk => data_out[2].CLK -clk => data_out[3].CLK -clk => data_out[4].CLK -clk => data_out[5].CLK -clk => data_out[6].CLK -reset_n => data_out[0].ACLR -reset_n => data_out[1].ACLR -reset_n => data_out[2].ACLR -reset_n => data_out[3].ACLR -reset_n => data_out[4].ACLR -reset_n => data_out[5].ACLR -reset_n => data_out[6].ACLR -write_n => always0.IN1 -writedata[0] => data_out[0].DATAIN -writedata[1] => data_out[1].DATAIN -writedata[2] => data_out[2].DATAIN -writedata[3] => data_out[3].DATAIN -writedata[4] => data_out[4].DATAIN -writedata[5] => data_out[5].DATAIN -writedata[6] => data_out[6].DATAIN -writedata[7] => ~NO_FANOUT~ -writedata[8] => ~NO_FANOUT~ -writedata[9] => ~NO_FANOUT~ -writedata[10] => ~NO_FANOUT~ -writedata[11] => ~NO_FANOUT~ -writedata[12] => ~NO_FANOUT~ -writedata[13] => ~NO_FANOUT~ -writedata[14] => ~NO_FANOUT~ -writedata[15] => ~NO_FANOUT~ -writedata[16] => ~NO_FANOUT~ -writedata[17] => ~NO_FANOUT~ -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE -out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE -out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE -out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE -out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE -out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE -out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE -readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= -readdata[8] <= -readdata[9] <= -readdata[10] <= -readdata[11] <= -readdata[12] <= -readdata[13] <= -readdata[14] <= -readdata[15] <= -readdata[16] <= -readdata[17] <= -readdata[18] <= -readdata[19] <= -readdata[20] <= -readdata[21] <= -readdata[22] <= -readdata[23] <= -readdata[24] <= -readdata[25] <= -readdata[26] <= -readdata[27] <= -readdata[28] <= -readdata[29] <= -readdata[30] <= -readdata[31] <= - - -|lights|nios_system:NiosII|nios_system_hex0:hex1 -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -chipselect => always0.IN0 -clk => data_out[0].CLK -clk => data_out[1].CLK -clk => data_out[2].CLK -clk => data_out[3].CLK -clk => data_out[4].CLK -clk => data_out[5].CLK -clk => data_out[6].CLK -reset_n => data_out[0].ACLR -reset_n => data_out[1].ACLR -reset_n => data_out[2].ACLR -reset_n => data_out[3].ACLR -reset_n => data_out[4].ACLR -reset_n => data_out[5].ACLR -reset_n => data_out[6].ACLR -write_n => always0.IN1 -writedata[0] => data_out[0].DATAIN -writedata[1] => data_out[1].DATAIN -writedata[2] => data_out[2].DATAIN -writedata[3] => data_out[3].DATAIN -writedata[4] => data_out[4].DATAIN -writedata[5] => data_out[5].DATAIN -writedata[6] => data_out[6].DATAIN -writedata[7] => ~NO_FANOUT~ -writedata[8] => ~NO_FANOUT~ -writedata[9] => ~NO_FANOUT~ -writedata[10] => ~NO_FANOUT~ -writedata[11] => ~NO_FANOUT~ -writedata[12] => ~NO_FANOUT~ -writedata[13] => ~NO_FANOUT~ -writedata[14] => ~NO_FANOUT~ -writedata[15] => ~NO_FANOUT~ -writedata[16] => ~NO_FANOUT~ -writedata[17] => ~NO_FANOUT~ -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE -out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE -out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE -out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE -out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE -out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE -out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE -readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= -readdata[8] <= -readdata[9] <= -readdata[10] <= -readdata[11] <= -readdata[12] <= -readdata[13] <= -readdata[14] <= -readdata[15] <= -readdata[16] <= -readdata[17] <= -readdata[18] <= -readdata[19] <= -readdata[20] <= -readdata[21] <= -readdata[22] <= -readdata[23] <= -readdata[24] <= -readdata[25] <= -readdata[26] <= -readdata[27] <= -readdata[28] <= -readdata[29] <= -readdata[30] <= -readdata[31] <= - - -|lights|nios_system:NiosII|nios_system_hex0:hex2 -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -chipselect => always0.IN0 -clk => data_out[0].CLK -clk => data_out[1].CLK -clk => data_out[2].CLK -clk => data_out[3].CLK -clk => data_out[4].CLK -clk => data_out[5].CLK -clk => data_out[6].CLK -reset_n => data_out[0].ACLR -reset_n => data_out[1].ACLR -reset_n => data_out[2].ACLR -reset_n => data_out[3].ACLR -reset_n => data_out[4].ACLR -reset_n => data_out[5].ACLR -reset_n => data_out[6].ACLR -write_n => always0.IN1 -writedata[0] => data_out[0].DATAIN -writedata[1] => data_out[1].DATAIN -writedata[2] => data_out[2].DATAIN -writedata[3] => data_out[3].DATAIN -writedata[4] => data_out[4].DATAIN -writedata[5] => data_out[5].DATAIN -writedata[6] => data_out[6].DATAIN -writedata[7] => ~NO_FANOUT~ -writedata[8] => ~NO_FANOUT~ -writedata[9] => ~NO_FANOUT~ -writedata[10] => ~NO_FANOUT~ -writedata[11] => ~NO_FANOUT~ -writedata[12] => ~NO_FANOUT~ -writedata[13] => ~NO_FANOUT~ -writedata[14] => ~NO_FANOUT~ -writedata[15] => ~NO_FANOUT~ -writedata[16] => ~NO_FANOUT~ -writedata[17] => ~NO_FANOUT~ -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE -out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE -out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE -out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE -out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE -out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE -out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE -readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= -readdata[8] <= -readdata[9] <= -readdata[10] <= -readdata[11] <= -readdata[12] <= -readdata[13] <= -readdata[14] <= -readdata[15] <= -readdata[16] <= -readdata[17] <= -readdata[18] <= -readdata[19] <= -readdata[20] <= -readdata[21] <= -readdata[22] <= -readdata[23] <= -readdata[24] <= -readdata[25] <= -readdata[26] <= -readdata[27] <= -readdata[28] <= -readdata[29] <= -readdata[30] <= -readdata[31] <= - - -|lights|nios_system:NiosII|nios_system_hex0:hex3 -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -chipselect => always0.IN0 -clk => data_out[0].CLK -clk => data_out[1].CLK -clk => data_out[2].CLK -clk => data_out[3].CLK -clk => data_out[4].CLK -clk => data_out[5].CLK -clk => data_out[6].CLK -reset_n => data_out[0].ACLR -reset_n => data_out[1].ACLR -reset_n => data_out[2].ACLR -reset_n => data_out[3].ACLR -reset_n => data_out[4].ACLR -reset_n => data_out[5].ACLR -reset_n => data_out[6].ACLR -write_n => always0.IN1 -writedata[0] => data_out[0].DATAIN -writedata[1] => data_out[1].DATAIN -writedata[2] => data_out[2].DATAIN -writedata[3] => data_out[3].DATAIN -writedata[4] => data_out[4].DATAIN -writedata[5] => data_out[5].DATAIN -writedata[6] => data_out[6].DATAIN -writedata[7] => ~NO_FANOUT~ -writedata[8] => ~NO_FANOUT~ -writedata[9] => ~NO_FANOUT~ -writedata[10] => ~NO_FANOUT~ -writedata[11] => ~NO_FANOUT~ -writedata[12] => ~NO_FANOUT~ -writedata[13] => ~NO_FANOUT~ -writedata[14] => ~NO_FANOUT~ -writedata[15] => ~NO_FANOUT~ -writedata[16] => ~NO_FANOUT~ -writedata[17] => ~NO_FANOUT~ -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE -out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE -out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE -out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE -out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE -out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE -out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE -readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= -readdata[8] <= -readdata[9] <= -readdata[10] <= -readdata[11] <= -readdata[12] <= -readdata[13] <= -readdata[14] <= -readdata[15] <= -readdata[16] <= -readdata[17] <= -readdata[18] <= -readdata[19] <= -readdata[20] <= -readdata[21] <= -readdata[22] <= -readdata[23] <= -readdata[24] <= -readdata[25] <= -readdata[26] <= -readdata[27] <= -readdata[28] <= -readdata[29] <= -readdata[30] <= -readdata[31] <= - - -|lights|nios_system:NiosII|nios_system_hex0:hex4 -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -chipselect => always0.IN0 -clk => data_out[0].CLK -clk => data_out[1].CLK -clk => data_out[2].CLK -clk => data_out[3].CLK -clk => data_out[4].CLK -clk => data_out[5].CLK -clk => data_out[6].CLK -reset_n => data_out[0].ACLR -reset_n => data_out[1].ACLR -reset_n => data_out[2].ACLR -reset_n => data_out[3].ACLR -reset_n => data_out[4].ACLR -reset_n => data_out[5].ACLR -reset_n => data_out[6].ACLR -write_n => always0.IN1 -writedata[0] => data_out[0].DATAIN -writedata[1] => data_out[1].DATAIN -writedata[2] => data_out[2].DATAIN -writedata[3] => data_out[3].DATAIN -writedata[4] => data_out[4].DATAIN -writedata[5] => data_out[5].DATAIN -writedata[6] => data_out[6].DATAIN -writedata[7] => ~NO_FANOUT~ -writedata[8] => ~NO_FANOUT~ -writedata[9] => ~NO_FANOUT~ -writedata[10] => ~NO_FANOUT~ -writedata[11] => ~NO_FANOUT~ -writedata[12] => ~NO_FANOUT~ -writedata[13] => ~NO_FANOUT~ -writedata[14] => ~NO_FANOUT~ -writedata[15] => ~NO_FANOUT~ -writedata[16] => ~NO_FANOUT~ -writedata[17] => ~NO_FANOUT~ -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE -out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE -out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE -out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE -out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE -out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE -out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE -readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= -readdata[8] <= -readdata[9] <= -readdata[10] <= -readdata[11] <= -readdata[12] <= -readdata[13] <= -readdata[14] <= -readdata[15] <= -readdata[16] <= -readdata[17] <= -readdata[18] <= -readdata[19] <= -readdata[20] <= -readdata[21] <= -readdata[22] <= -readdata[23] <= -readdata[24] <= -readdata[25] <= -readdata[26] <= -readdata[27] <= -readdata[28] <= -readdata[29] <= -readdata[30] <= -readdata[31] <= - - -|lights|nios_system:NiosII|nios_system_hex0:hex5 -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -chipselect => always0.IN0 -clk => data_out[0].CLK -clk => data_out[1].CLK -clk => data_out[2].CLK -clk => data_out[3].CLK -clk => data_out[4].CLK -clk => data_out[5].CLK -clk => data_out[6].CLK -reset_n => data_out[0].ACLR -reset_n => data_out[1].ACLR -reset_n => data_out[2].ACLR -reset_n => data_out[3].ACLR -reset_n => data_out[4].ACLR -reset_n => data_out[5].ACLR -reset_n => data_out[6].ACLR -write_n => always0.IN1 -writedata[0] => data_out[0].DATAIN -writedata[1] => data_out[1].DATAIN -writedata[2] => data_out[2].DATAIN -writedata[3] => data_out[3].DATAIN -writedata[4] => data_out[4].DATAIN -writedata[5] => data_out[5].DATAIN -writedata[6] => data_out[6].DATAIN -writedata[7] => ~NO_FANOUT~ -writedata[8] => ~NO_FANOUT~ -writedata[9] => ~NO_FANOUT~ -writedata[10] => ~NO_FANOUT~ -writedata[11] => ~NO_FANOUT~ -writedata[12] => ~NO_FANOUT~ -writedata[13] => ~NO_FANOUT~ -writedata[14] => ~NO_FANOUT~ -writedata[15] => ~NO_FANOUT~ -writedata[16] => ~NO_FANOUT~ -writedata[17] => ~NO_FANOUT~ -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE -out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE -out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE -out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE -out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE -out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE -out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE -readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= -readdata[8] <= -readdata[9] <= -readdata[10] <= -readdata[11] <= -readdata[12] <= -readdata[13] <= -readdata[14] <= -readdata[15] <= -readdata[16] <= -readdata[17] <= -readdata[18] <= -readdata[19] <= -readdata[20] <= -readdata[21] <= -readdata[22] <= -readdata[23] <= -readdata[24] <= -readdata[25] <= -readdata[26] <= -readdata[27] <= -readdata[28] <= -readdata[29] <= -readdata[30] <= -readdata[31] <= - - -|lights|nios_system:NiosII|nios_system_hex0:hex6 -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -chipselect => always0.IN0 -clk => data_out[0].CLK -clk => data_out[1].CLK -clk => data_out[2].CLK -clk => data_out[3].CLK -clk => data_out[4].CLK -clk => data_out[5].CLK -clk => data_out[6].CLK -reset_n => data_out[0].ACLR -reset_n => data_out[1].ACLR -reset_n => data_out[2].ACLR -reset_n => data_out[3].ACLR -reset_n => data_out[4].ACLR -reset_n => data_out[5].ACLR -reset_n => data_out[6].ACLR -write_n => always0.IN1 -writedata[0] => data_out[0].DATAIN -writedata[1] => data_out[1].DATAIN -writedata[2] => data_out[2].DATAIN -writedata[3] => data_out[3].DATAIN -writedata[4] => data_out[4].DATAIN -writedata[5] => data_out[5].DATAIN -writedata[6] => data_out[6].DATAIN -writedata[7] => ~NO_FANOUT~ -writedata[8] => ~NO_FANOUT~ -writedata[9] => ~NO_FANOUT~ -writedata[10] => ~NO_FANOUT~ -writedata[11] => ~NO_FANOUT~ -writedata[12] => ~NO_FANOUT~ -writedata[13] => ~NO_FANOUT~ -writedata[14] => ~NO_FANOUT~ -writedata[15] => ~NO_FANOUT~ -writedata[16] => ~NO_FANOUT~ -writedata[17] => ~NO_FANOUT~ -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE -out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE -out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE -out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE -out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE -out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE -out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE -readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= -readdata[8] <= -readdata[9] <= -readdata[10] <= -readdata[11] <= -readdata[12] <= -readdata[13] <= -readdata[14] <= -readdata[15] <= -readdata[16] <= -readdata[17] <= -readdata[18] <= -readdata[19] <= -readdata[20] <= -readdata[21] <= -readdata[22] <= -readdata[23] <= -readdata[24] <= -readdata[25] <= -readdata[26] <= -readdata[27] <= -readdata[28] <= -readdata[29] <= -readdata[30] <= -readdata[31] <= - - -|lights|nios_system:NiosII|nios_system_hex0:hex7 -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -chipselect => always0.IN0 -clk => data_out[0].CLK -clk => data_out[1].CLK -clk => data_out[2].CLK -clk => data_out[3].CLK -clk => data_out[4].CLK -clk => data_out[5].CLK -clk => data_out[6].CLK -reset_n => data_out[0].ACLR -reset_n => data_out[1].ACLR -reset_n => data_out[2].ACLR -reset_n => data_out[3].ACLR -reset_n => data_out[4].ACLR -reset_n => data_out[5].ACLR -reset_n => data_out[6].ACLR -write_n => always0.IN1 -writedata[0] => data_out[0].DATAIN -writedata[1] => data_out[1].DATAIN -writedata[2] => data_out[2].DATAIN -writedata[3] => data_out[3].DATAIN -writedata[4] => data_out[4].DATAIN -writedata[5] => data_out[5].DATAIN -writedata[6] => data_out[6].DATAIN -writedata[7] => ~NO_FANOUT~ -writedata[8] => ~NO_FANOUT~ -writedata[9] => ~NO_FANOUT~ -writedata[10] => ~NO_FANOUT~ -writedata[11] => ~NO_FANOUT~ -writedata[12] => ~NO_FANOUT~ -writedata[13] => ~NO_FANOUT~ -writedata[14] => ~NO_FANOUT~ -writedata[15] => ~NO_FANOUT~ -writedata[16] => ~NO_FANOUT~ -writedata[17] => ~NO_FANOUT~ -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE -out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE -out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE -out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE -out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE -out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE -out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE -readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= -readdata[8] <= -readdata[9] <= -readdata[10] <= -readdata[11] <= -readdata[12] <= -readdata[13] <= -readdata[14] <= -readdata[15] <= -readdata[16] <= -readdata[17] <= -readdata[18] <= -readdata[19] <= -readdata[20] <= -readdata[21] <= -readdata[22] <= -readdata[23] <= -readdata[24] <= -readdata[25] <= -readdata[26] <= -readdata[27] <= -readdata[28] <= -readdata[29] <= -readdata[30] <= -readdata[31] <= - - -|lights|nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0 -address[0] => LCD_RW.DATAIN -address[0] => LCD_data[7].OE -address[0] => LCD_data[6].OE -address[0] => LCD_data[5].OE -address[0] => LCD_data[4].OE -address[0] => LCD_data[3].OE -address[0] => LCD_data[2].OE -address[0] => LCD_data[1].OE -address[0] => LCD_data[0].OE -address[1] => LCD_RS.DATAIN -begintransfer => ~NO_FANOUT~ -clk => ~NO_FANOUT~ -read => LCD_E.IN0 -reset_n => ~NO_FANOUT~ -write => LCD_E.IN1 -writedata[0] => LCD_data[0].DATAIN -writedata[1] => LCD_data[1].DATAIN -writedata[2] => LCD_data[2].DATAIN -writedata[3] => LCD_data[3].DATAIN -writedata[4] => LCD_data[4].DATAIN -writedata[5] => LCD_data[5].DATAIN -writedata[6] => LCD_data[6].DATAIN -writedata[7] => LCD_data[7].DATAIN -LCD_E <= LCD_E.DB_MAX_OUTPUT_PORT_TYPE -LCD_RS <= address[1].DB_MAX_OUTPUT_PORT_TYPE -LCD_RW <= address[0].DB_MAX_OUTPUT_PORT_TYPE -LCD_data[0] <> LCD_data[0] -LCD_data[1] <> LCD_data[1] -LCD_data[2] <> LCD_data[2] -LCD_data[3] <> LCD_data[3] -LCD_data[4] <> LCD_data[4] -LCD_data[5] <> LCD_data[5] -LCD_data[6] <> LCD_data[6] -LCD_data[7] <> LCD_data[7] -readdata[0] <= readdata[0].DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= readdata[1].DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= readdata[2].DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= readdata[3].DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= readdata[4].DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= readdata[5].DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= readdata[6].DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= readdata[7].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_lcd_on:lcd_on -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -chipselect => always0.IN0 -clk => data_out.CLK -reset_n => data_out.ACLR -write_n => always0.IN1 -writedata[0] => data_out.DATAIN -writedata[1] => ~NO_FANOUT~ -writedata[2] => ~NO_FANOUT~ -writedata[3] => ~NO_FANOUT~ -writedata[4] => ~NO_FANOUT~ -writedata[5] => ~NO_FANOUT~ -writedata[6] => ~NO_FANOUT~ -writedata[7] => ~NO_FANOUT~ -writedata[8] => ~NO_FANOUT~ -writedata[9] => ~NO_FANOUT~ -writedata[10] => ~NO_FANOUT~ -writedata[11] => ~NO_FANOUT~ -writedata[12] => ~NO_FANOUT~ -writedata[13] => ~NO_FANOUT~ -writedata[14] => ~NO_FANOUT~ -writedata[15] => ~NO_FANOUT~ -writedata[16] => ~NO_FANOUT~ -writedata[17] => ~NO_FANOUT~ -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -out_port <= data_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= -readdata[2] <= -readdata[3] <= -readdata[4] <= -readdata[5] <= -readdata[6] <= -readdata[7] <= -readdata[8] <= -readdata[9] <= -readdata[10] <= -readdata[11] <= -readdata[12] <= -readdata[13] <= -readdata[14] <= -readdata[15] <= -readdata[16] <= -readdata[17] <= -readdata[18] <= -readdata[19] <= -readdata[20] <= -readdata[21] <= -readdata[22] <= -readdata[23] <= -readdata[24] <= -readdata[25] <= -readdata[26] <= -readdata[27] <= -readdata[28] <= -readdata[29] <= -readdata[30] <= -readdata[31] <= - - -|lights|nios_system:NiosII|nios_system_lcd_on:lcd_blon -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -chipselect => always0.IN0 -clk => data_out.CLK -reset_n => data_out.ACLR -write_n => always0.IN1 -writedata[0] => data_out.DATAIN -writedata[1] => ~NO_FANOUT~ -writedata[2] => ~NO_FANOUT~ -writedata[3] => ~NO_FANOUT~ -writedata[4] => ~NO_FANOUT~ -writedata[5] => ~NO_FANOUT~ -writedata[6] => ~NO_FANOUT~ -writedata[7] => ~NO_FANOUT~ -writedata[8] => ~NO_FANOUT~ -writedata[9] => ~NO_FANOUT~ -writedata[10] => ~NO_FANOUT~ -writedata[11] => ~NO_FANOUT~ -writedata[12] => ~NO_FANOUT~ -writedata[13] => ~NO_FANOUT~ -writedata[14] => ~NO_FANOUT~ -writedata[15] => ~NO_FANOUT~ -writedata[16] => ~NO_FANOUT~ -writedata[17] => ~NO_FANOUT~ -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -out_port <= data_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= -readdata[2] <= -readdata[3] <= -readdata[4] <= -readdata[5] <= -readdata[6] <= -readdata[7] <= -readdata[8] <= -readdata[9] <= -readdata[10] <= -readdata[11] <= -readdata[12] <= -readdata[13] <= -readdata[14] <= -readdata[15] <= -readdata[16] <= -readdata[17] <= -readdata[18] <= -readdata[19] <= -readdata[20] <= -readdata[21] <= -readdata[22] <= -readdata[23] <= -readdata[24] <= -readdata[25] <= -readdata[26] <= -readdata[27] <= -readdata[28] <= -readdata[29] <= -readdata[30] <= -readdata[31] <= - - -|lights|nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator -clk => read_accepted.CLK -reset => read_accepted.ACLR -uav_write <= -uav_read <= uav_read.DB_MAX_OUTPUT_PORT_TYPE -uav_address[0] <= av_address[0].DB_MAX_OUTPUT_PORT_TYPE -uav_address[1] <= av_address[1].DB_MAX_OUTPUT_PORT_TYPE -uav_address[2] <= av_address[2].DB_MAX_OUTPUT_PORT_TYPE -uav_address[3] <= av_address[3].DB_MAX_OUTPUT_PORT_TYPE -uav_address[4] <= av_address[4].DB_MAX_OUTPUT_PORT_TYPE -uav_address[5] <= av_address[5].DB_MAX_OUTPUT_PORT_TYPE -uav_address[6] <= av_address[6].DB_MAX_OUTPUT_PORT_TYPE -uav_address[7] <= av_address[7].DB_MAX_OUTPUT_PORT_TYPE -uav_address[8] <= av_address[8].DB_MAX_OUTPUT_PORT_TYPE -uav_address[9] <= av_address[9].DB_MAX_OUTPUT_PORT_TYPE -uav_address[10] <= av_address[10].DB_MAX_OUTPUT_PORT_TYPE -uav_address[11] <= av_address[11].DB_MAX_OUTPUT_PORT_TYPE -uav_address[12] <= av_address[12].DB_MAX_OUTPUT_PORT_TYPE -uav_address[13] <= av_address[13].DB_MAX_OUTPUT_PORT_TYPE -uav_address[14] <= av_address[14].DB_MAX_OUTPUT_PORT_TYPE -uav_address[15] <= av_address[15].DB_MAX_OUTPUT_PORT_TYPE -uav_address[16] <= av_address[16].DB_MAX_OUTPUT_PORT_TYPE -uav_address[17] <= av_address[17].DB_MAX_OUTPUT_PORT_TYPE -uav_address[18] <= av_address[18].DB_MAX_OUTPUT_PORT_TYPE -uav_burstcount[0] <= -uav_burstcount[1] <= -uav_burstcount[2] <= -uav_byteenable[0] <= av_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -uav_byteenable[1] <= av_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE -uav_byteenable[2] <= av_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE -uav_byteenable[3] <= av_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[0] <= av_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[1] <= av_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[2] <= av_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[3] <= av_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[4] <= av_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[5] <= av_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[6] <= av_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[7] <= av_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[8] <= av_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[9] <= av_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[10] <= av_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[11] <= av_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[12] <= av_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[13] <= av_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[14] <= av_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[15] <= av_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[16] <= av_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[17] <= av_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[18] <= av_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[19] <= av_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[20] <= av_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[21] <= av_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[22] <= av_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[23] <= av_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[24] <= av_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[25] <= av_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[26] <= av_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[27] <= av_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[28] <= av_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[29] <= av_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[30] <= av_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[31] <= av_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -uav_lock <= av_lock.DB_MAX_OUTPUT_PORT_TYPE -uav_debugaccess <= av_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -uav_clken <= av_clken.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] => av_readdata[0].DATAIN -uav_readdata[1] => av_readdata[1].DATAIN -uav_readdata[2] => av_readdata[2].DATAIN -uav_readdata[3] => av_readdata[3].DATAIN -uav_readdata[4] => av_readdata[4].DATAIN -uav_readdata[5] => av_readdata[5].DATAIN -uav_readdata[6] => av_readdata[6].DATAIN -uav_readdata[7] => av_readdata[7].DATAIN -uav_readdata[8] => av_readdata[8].DATAIN -uav_readdata[9] => av_readdata[9].DATAIN -uav_readdata[10] => av_readdata[10].DATAIN -uav_readdata[11] => av_readdata[11].DATAIN -uav_readdata[12] => av_readdata[12].DATAIN -uav_readdata[13] => av_readdata[13].DATAIN -uav_readdata[14] => av_readdata[14].DATAIN -uav_readdata[15] => av_readdata[15].DATAIN -uav_readdata[16] => av_readdata[16].DATAIN -uav_readdata[17] => av_readdata[17].DATAIN -uav_readdata[18] => av_readdata[18].DATAIN -uav_readdata[19] => av_readdata[19].DATAIN -uav_readdata[20] => av_readdata[20].DATAIN -uav_readdata[21] => av_readdata[21].DATAIN -uav_readdata[22] => av_readdata[22].DATAIN -uav_readdata[23] => av_readdata[23].DATAIN -uav_readdata[24] => av_readdata[24].DATAIN -uav_readdata[25] => av_readdata[25].DATAIN -uav_readdata[26] => av_readdata[26].DATAIN -uav_readdata[27] => av_readdata[27].DATAIN -uav_readdata[28] => av_readdata[28].DATAIN -uav_readdata[29] => av_readdata[29].DATAIN -uav_readdata[30] => av_readdata[30].DATAIN -uav_readdata[31] => av_readdata[31].DATAIN -uav_readdatavalid => always5.IN1 -uav_readdatavalid => av_readdatavalid.DATAIN -uav_readdatavalid => av_waitrequest.DATAB -uav_waitrequest => av_waitrequest.DATAA -uav_waitrequest => read_accepted.IN0 -uav_response[0] => ~NO_FANOUT~ -uav_response[1] => ~NO_FANOUT~ -uav_writeresponserequest <= -uav_writeresponsevalid => ~NO_FANOUT~ -av_write => ~NO_FANOUT~ -av_read => read_accepted.IN1 -av_read => av_waitrequest.OUTPUTSELECT -av_read => uav_read.IN1 -av_address[0] => uav_address[0].DATAIN -av_address[1] => uav_address[1].DATAIN -av_address[2] => uav_address[2].DATAIN -av_address[3] => uav_address[3].DATAIN -av_address[4] => uav_address[4].DATAIN -av_address[5] => uav_address[5].DATAIN -av_address[6] => uav_address[6].DATAIN -av_address[7] => uav_address[7].DATAIN -av_address[8] => uav_address[8].DATAIN -av_address[9] => uav_address[9].DATAIN -av_address[10] => uav_address[10].DATAIN -av_address[11] => uav_address[11].DATAIN -av_address[12] => uav_address[12].DATAIN -av_address[13] => uav_address[13].DATAIN -av_address[14] => uav_address[14].DATAIN -av_address[15] => uav_address[15].DATAIN -av_address[16] => uav_address[16].DATAIN -av_address[17] => uav_address[17].DATAIN -av_address[18] => uav_address[18].DATAIN -av_byteenable[0] => uav_byteenable[0].DATAIN -av_byteenable[1] => uav_byteenable[1].DATAIN -av_byteenable[2] => uav_byteenable[2].DATAIN -av_byteenable[3] => uav_byteenable[3].DATAIN -av_burstcount[0] => ~NO_FANOUT~ -av_writedata[0] => uav_writedata[0].DATAIN -av_writedata[1] => uav_writedata[1].DATAIN -av_writedata[2] => uav_writedata[2].DATAIN -av_writedata[3] => uav_writedata[3].DATAIN -av_writedata[4] => uav_writedata[4].DATAIN -av_writedata[5] => uav_writedata[5].DATAIN -av_writedata[6] => uav_writedata[6].DATAIN -av_writedata[7] => uav_writedata[7].DATAIN -av_writedata[8] => uav_writedata[8].DATAIN -av_writedata[9] => uav_writedata[9].DATAIN -av_writedata[10] => uav_writedata[10].DATAIN -av_writedata[11] => uav_writedata[11].DATAIN -av_writedata[12] => uav_writedata[12].DATAIN -av_writedata[13] => uav_writedata[13].DATAIN -av_writedata[14] => uav_writedata[14].DATAIN -av_writedata[15] => uav_writedata[15].DATAIN -av_writedata[16] => uav_writedata[16].DATAIN -av_writedata[17] => uav_writedata[17].DATAIN -av_writedata[18] => uav_writedata[18].DATAIN -av_writedata[19] => uav_writedata[19].DATAIN -av_writedata[20] => uav_writedata[20].DATAIN -av_writedata[21] => uav_writedata[21].DATAIN -av_writedata[22] => uav_writedata[22].DATAIN -av_writedata[23] => uav_writedata[23].DATAIN -av_writedata[24] => uav_writedata[24].DATAIN -av_writedata[25] => uav_writedata[25].DATAIN -av_writedata[26] => uav_writedata[26].DATAIN -av_writedata[27] => uav_writedata[27].DATAIN -av_writedata[28] => uav_writedata[28].DATAIN -av_writedata[29] => uav_writedata[29].DATAIN -av_writedata[30] => uav_writedata[30].DATAIN -av_writedata[31] => uav_writedata[31].DATAIN -av_begintransfer => ~NO_FANOUT~ -av_beginbursttransfer => ~NO_FANOUT~ -av_lock => uav_lock.DATAIN -av_chipselect => ~NO_FANOUT~ -av_debugaccess => uav_debugaccess.DATAIN -av_clken => uav_clken.DATAIN -av_readdata[0] <= uav_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[1] <= uav_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[2] <= uav_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[3] <= uav_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[4] <= uav_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[5] <= uav_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[6] <= uav_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[7] <= uav_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[8] <= uav_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[9] <= uav_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[10] <= uav_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[11] <= uav_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[12] <= uav_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[13] <= uav_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[14] <= uav_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[15] <= uav_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[16] <= uav_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[17] <= uav_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[18] <= uav_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[19] <= uav_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[20] <= uav_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[21] <= uav_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[22] <= uav_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[23] <= uav_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[24] <= uav_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[25] <= uav_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[26] <= uav_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[27] <= uav_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[28] <= uav_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[29] <= uav_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[30] <= uav_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[31] <= uav_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -av_readdatavalid <= uav_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE -av_waitrequest <= av_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -av_response[0] <= -av_response[1] <= -av_writeresponserequest => ~NO_FANOUT~ -av_writeresponsevalid <= - - -|lights|nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator -clk => end_begintransfer.CLK -clk => write_accepted.CLK -clk => read_accepted.CLK -reset => end_begintransfer.ACLR -reset => write_accepted.ACLR -reset => read_accepted.ACLR -uav_write <= uav_write.DB_MAX_OUTPUT_PORT_TYPE -uav_read <= uav_read.DB_MAX_OUTPUT_PORT_TYPE -uav_address[0] <= av_address[0].DB_MAX_OUTPUT_PORT_TYPE -uav_address[1] <= av_address[1].DB_MAX_OUTPUT_PORT_TYPE -uav_address[2] <= av_address[2].DB_MAX_OUTPUT_PORT_TYPE -uav_address[3] <= av_address[3].DB_MAX_OUTPUT_PORT_TYPE -uav_address[4] <= av_address[4].DB_MAX_OUTPUT_PORT_TYPE -uav_address[5] <= av_address[5].DB_MAX_OUTPUT_PORT_TYPE -uav_address[6] <= av_address[6].DB_MAX_OUTPUT_PORT_TYPE -uav_address[7] <= av_address[7].DB_MAX_OUTPUT_PORT_TYPE -uav_address[8] <= av_address[8].DB_MAX_OUTPUT_PORT_TYPE -uav_address[9] <= av_address[9].DB_MAX_OUTPUT_PORT_TYPE -uav_address[10] <= av_address[10].DB_MAX_OUTPUT_PORT_TYPE -uav_address[11] <= av_address[11].DB_MAX_OUTPUT_PORT_TYPE -uav_address[12] <= av_address[12].DB_MAX_OUTPUT_PORT_TYPE -uav_address[13] <= av_address[13].DB_MAX_OUTPUT_PORT_TYPE -uav_address[14] <= av_address[14].DB_MAX_OUTPUT_PORT_TYPE -uav_address[15] <= av_address[15].DB_MAX_OUTPUT_PORT_TYPE -uav_address[16] <= av_address[16].DB_MAX_OUTPUT_PORT_TYPE -uav_address[17] <= av_address[17].DB_MAX_OUTPUT_PORT_TYPE -uav_address[18] <= av_address[18].DB_MAX_OUTPUT_PORT_TYPE -uav_burstcount[0] <= -uav_burstcount[1] <= -uav_burstcount[2] <= -uav_byteenable[0] <= av_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -uav_byteenable[1] <= av_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE -uav_byteenable[2] <= av_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE -uav_byteenable[3] <= av_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[0] <= av_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[1] <= av_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[2] <= av_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[3] <= av_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[4] <= av_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[5] <= av_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[6] <= av_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[7] <= av_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[8] <= av_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[9] <= av_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[10] <= av_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[11] <= av_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[12] <= av_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[13] <= av_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[14] <= av_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[15] <= av_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[16] <= av_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[17] <= av_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[18] <= av_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[19] <= av_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[20] <= av_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[21] <= av_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[22] <= av_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[23] <= av_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[24] <= av_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[25] <= av_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[26] <= av_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[27] <= av_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[28] <= av_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[29] <= av_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[30] <= av_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[31] <= av_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -uav_lock <= av_lock.DB_MAX_OUTPUT_PORT_TYPE -uav_debugaccess <= av_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -uav_clken <= av_clken.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] => av_readdata[0].DATAIN -uav_readdata[1] => av_readdata[1].DATAIN -uav_readdata[2] => av_readdata[2].DATAIN -uav_readdata[3] => av_readdata[3].DATAIN -uav_readdata[4] => av_readdata[4].DATAIN -uav_readdata[5] => av_readdata[5].DATAIN -uav_readdata[6] => av_readdata[6].DATAIN -uav_readdata[7] => av_readdata[7].DATAIN -uav_readdata[8] => av_readdata[8].DATAIN -uav_readdata[9] => av_readdata[9].DATAIN -uav_readdata[10] => av_readdata[10].DATAIN -uav_readdata[11] => av_readdata[11].DATAIN -uav_readdata[12] => av_readdata[12].DATAIN -uav_readdata[13] => av_readdata[13].DATAIN -uav_readdata[14] => av_readdata[14].DATAIN -uav_readdata[15] => av_readdata[15].DATAIN -uav_readdata[16] => av_readdata[16].DATAIN -uav_readdata[17] => av_readdata[17].DATAIN -uav_readdata[18] => av_readdata[18].DATAIN -uav_readdata[19] => av_readdata[19].DATAIN -uav_readdata[20] => av_readdata[20].DATAIN -uav_readdata[21] => av_readdata[21].DATAIN -uav_readdata[22] => av_readdata[22].DATAIN -uav_readdata[23] => av_readdata[23].DATAIN -uav_readdata[24] => av_readdata[24].DATAIN -uav_readdata[25] => av_readdata[25].DATAIN -uav_readdata[26] => av_readdata[26].DATAIN -uav_readdata[27] => av_readdata[27].DATAIN -uav_readdata[28] => av_readdata[28].DATAIN -uav_readdata[29] => av_readdata[29].DATAIN -uav_readdata[30] => av_readdata[30].DATAIN -uav_readdata[31] => av_readdata[31].DATAIN -uav_readdatavalid => always5.IN1 -uav_readdatavalid => av_readdatavalid.DATAIN -uav_readdatavalid => av_waitrequest.DATAB -uav_waitrequest => av_waitrequest.IN1 -uav_waitrequest => always10.IN1 -uav_waitrequest => end_begintransfer.OUTPUTSELECT -uav_waitrequest => read_accepted.IN0 -uav_waitrequest => write_accepted.IN1 -uav_response[0] => ~NO_FANOUT~ -uav_response[1] => ~NO_FANOUT~ -uav_writeresponserequest <= -uav_writeresponsevalid => ~NO_FANOUT~ -av_write => av_waitrequest.OUTPUTSELECT -av_write => uav_write.IN1 -av_read => read_accepted.IN1 -av_read => av_waitrequest.OUTPUTSELECT -av_read => uav_read.IN1 -av_address[0] => uav_address[0].DATAIN -av_address[1] => uav_address[1].DATAIN -av_address[2] => uav_address[2].DATAIN -av_address[3] => uav_address[3].DATAIN -av_address[4] => uav_address[4].DATAIN -av_address[5] => uav_address[5].DATAIN -av_address[6] => uav_address[6].DATAIN -av_address[7] => uav_address[7].DATAIN -av_address[8] => uav_address[8].DATAIN -av_address[9] => uav_address[9].DATAIN -av_address[10] => uav_address[10].DATAIN -av_address[11] => uav_address[11].DATAIN -av_address[12] => uav_address[12].DATAIN -av_address[13] => uav_address[13].DATAIN -av_address[14] => uav_address[14].DATAIN -av_address[15] => uav_address[15].DATAIN -av_address[16] => uav_address[16].DATAIN -av_address[17] => uav_address[17].DATAIN -av_address[18] => uav_address[18].DATAIN -av_byteenable[0] => uav_byteenable[0].DATAIN -av_byteenable[1] => uav_byteenable[1].DATAIN -av_byteenable[2] => uav_byteenable[2].DATAIN -av_byteenable[3] => uav_byteenable[3].DATAIN -av_burstcount[0] => ~NO_FANOUT~ -av_writedata[0] => uav_writedata[0].DATAIN -av_writedata[1] => uav_writedata[1].DATAIN -av_writedata[2] => uav_writedata[2].DATAIN -av_writedata[3] => uav_writedata[3].DATAIN -av_writedata[4] => uav_writedata[4].DATAIN -av_writedata[5] => uav_writedata[5].DATAIN -av_writedata[6] => uav_writedata[6].DATAIN -av_writedata[7] => uav_writedata[7].DATAIN -av_writedata[8] => uav_writedata[8].DATAIN -av_writedata[9] => uav_writedata[9].DATAIN -av_writedata[10] => uav_writedata[10].DATAIN -av_writedata[11] => uav_writedata[11].DATAIN -av_writedata[12] => uav_writedata[12].DATAIN -av_writedata[13] => uav_writedata[13].DATAIN -av_writedata[14] => uav_writedata[14].DATAIN -av_writedata[15] => uav_writedata[15].DATAIN -av_writedata[16] => uav_writedata[16].DATAIN -av_writedata[17] => uav_writedata[17].DATAIN -av_writedata[18] => uav_writedata[18].DATAIN -av_writedata[19] => uav_writedata[19].DATAIN -av_writedata[20] => uav_writedata[20].DATAIN -av_writedata[21] => uav_writedata[21].DATAIN -av_writedata[22] => uav_writedata[22].DATAIN -av_writedata[23] => uav_writedata[23].DATAIN -av_writedata[24] => uav_writedata[24].DATAIN -av_writedata[25] => uav_writedata[25].DATAIN -av_writedata[26] => uav_writedata[26].DATAIN -av_writedata[27] => uav_writedata[27].DATAIN -av_writedata[28] => uav_writedata[28].DATAIN -av_writedata[29] => uav_writedata[29].DATAIN -av_writedata[30] => uav_writedata[30].DATAIN -av_writedata[31] => uav_writedata[31].DATAIN -av_begintransfer => ~NO_FANOUT~ -av_beginbursttransfer => ~NO_FANOUT~ -av_lock => uav_lock.DATAIN -av_chipselect => ~NO_FANOUT~ -av_debugaccess => uav_debugaccess.DATAIN -av_clken => uav_clken.DATAIN -av_readdata[0] <= uav_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[1] <= uav_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[2] <= uav_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[3] <= uav_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[4] <= uav_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[5] <= uav_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[6] <= uav_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[7] <= uav_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[8] <= uav_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[9] <= uav_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[10] <= uav_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[11] <= uav_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[12] <= uav_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[13] <= uav_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[14] <= uav_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[15] <= uav_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[16] <= uav_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[17] <= uav_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[18] <= uav_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[19] <= uav_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[20] <= uav_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[21] <= uav_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[22] <= uav_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[23] <= uav_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[24] <= uav_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[25] <= uav_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[26] <= uav_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[27] <= uav_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[28] <= uav_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[29] <= uav_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[30] <= uav_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[31] <= uav_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -av_readdatavalid <= uav_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE -av_waitrequest <= av_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -av_response[0] <= -av_response[1] <= -av_writeresponserequest => ~NO_FANOUT~ -av_writeresponsevalid <= - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => av_address[2].DATAIN -uav_address[5] => av_address[3].DATAIN -uav_address[6] => av_address[4].DATAIN -uav_address[7] => av_address[5].DATAIN -uav_address[8] => av_address[6].DATAIN -uav_address[9] => av_address[7].DATAIN -uav_address[10] => av_address[8].DATAIN -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_writebyteenable.IN0 -uav_write => av_writebyteenable.IN0 -uav_write => av_writebyteenable.IN0 -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_write => av_write.DATAIN -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_read => av_read.DATAIN -uav_burstcount[0] => Equal0.IN3 -uav_burstcount[1] => Equal0.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal0.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => av_writebyteenable.IN1 -uav_byteenable[1] => av_byteenable[1].DATAIN -uav_byteenable[2] => av_writebyteenable.IN1 -uav_byteenable[2] => av_byteenable[2].DATAIN -uav_byteenable[3] => av_writebyteenable.IN1 -uav_byteenable[3] => av_byteenable[3].DATAIN -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= av_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_address[2] <= uav_address[4].DB_MAX_OUTPUT_PORT_TYPE -av_address[3] <= uav_address[5].DB_MAX_OUTPUT_PORT_TYPE -av_address[4] <= uav_address[6].DB_MAX_OUTPUT_PORT_TYPE -av_address[5] <= uav_address[7].DB_MAX_OUTPUT_PORT_TYPE -av_address[6] <= uav_address[8].DB_MAX_OUTPUT_PORT_TYPE -av_address[7] <= uav_address[9].DB_MAX_OUTPUT_PORT_TYPE -av_address[8] <= uav_address[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= uav_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= uav_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[1] <= uav_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[2] <= uav_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[3] <= uav_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[1] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[2] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[3] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => always18.IN1 -av_waitrequest => end_begintransfer.OUTPUTSELECT -av_waitrequest => uav_waitrequest.DATAIN -av_waitrequest => read_latency_shift_reg.IN1 -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => waitrequest_reset_override.CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => waitrequest_reset_override.PRESET -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => av_address[2].DATAIN -uav_address[5] => av_address[3].DATAIN -uav_address[6] => av_address[4].DATAIN -uav_address[7] => av_address[5].DATAIN -uav_address[8] => av_address[6].DATAIN -uav_address[9] => av_address[7].DATAIN -uav_address[10] => av_address[8].DATAIN -uav_address[11] => av_address[9].DATAIN -uav_address[12] => av_address[10].DATAIN -uav_address[13] => av_address[11].DATAIN -uav_address[14] => av_address[12].DATAIN -uav_address[15] => av_address[13].DATAIN -uav_address[16] => av_address[14].DATAIN -uav_address[17] => av_address[15].DATAIN -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_writebyteenable.IN0 -uav_write => av_writebyteenable.IN0 -uav_write => av_writebyteenable.IN0 -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_write => av_write.DATAIN -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_read => av_read.DATAIN -uav_read => av_outputenable_pre.DATAIN -uav_burstcount[0] => Equal0.IN3 -uav_burstcount[1] => Equal0.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal0.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => av_writebyteenable.IN1 -uav_byteenable[1] => av_byteenable[1].DATAIN -uav_byteenable[2] => av_writebyteenable.IN1 -uav_byteenable[2] => av_byteenable[2].DATAIN -uav_byteenable[3] => av_writebyteenable.IN1 -uav_byteenable[3] => av_byteenable[3].DATAIN -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= waitrequest_reset_override.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_address[2] <= uav_address[4].DB_MAX_OUTPUT_PORT_TYPE -av_address[3] <= uav_address[5].DB_MAX_OUTPUT_PORT_TYPE -av_address[4] <= uav_address[6].DB_MAX_OUTPUT_PORT_TYPE -av_address[5] <= uav_address[7].DB_MAX_OUTPUT_PORT_TYPE -av_address[6] <= uav_address[8].DB_MAX_OUTPUT_PORT_TYPE -av_address[7] <= uav_address[9].DB_MAX_OUTPUT_PORT_TYPE -av_address[8] <= uav_address[10].DB_MAX_OUTPUT_PORT_TYPE -av_address[9] <= uav_address[11].DB_MAX_OUTPUT_PORT_TYPE -av_address[10] <= uav_address[12].DB_MAX_OUTPUT_PORT_TYPE -av_address[11] <= uav_address[13].DB_MAX_OUTPUT_PORT_TYPE -av_address[12] <= uav_address[14].DB_MAX_OUTPUT_PORT_TYPE -av_address[13] <= uav_address[15].DB_MAX_OUTPUT_PORT_TYPE -av_address[14] <= uav_address[16].DB_MAX_OUTPUT_PORT_TYPE -av_address[15] <= uav_address[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= uav_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= uav_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[1] <= uav_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[2] <= uav_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[3] <= uav_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[1] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[2] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[3] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => uav_readdata[0].DATAIN -av_readdata[1] => uav_readdata[1].DATAIN -av_readdata[2] => uav_readdata[2].DATAIN -av_readdata[3] => uav_readdata[3].DATAIN -av_readdata[4] => uav_readdata[4].DATAIN -av_readdata[5] => uav_readdata[5].DATAIN -av_readdata[6] => uav_readdata[6].DATAIN -av_readdata[7] => uav_readdata[7].DATAIN -av_readdata[8] => uav_readdata[8].DATAIN -av_readdata[9] => uav_readdata[9].DATAIN -av_readdata[10] => uav_readdata[10].DATAIN -av_readdata[11] => uav_readdata[11].DATAIN -av_readdata[12] => uav_readdata[12].DATAIN -av_readdata[13] => uav_readdata[13].DATAIN -av_readdata[14] => uav_readdata[14].DATAIN -av_readdata[15] => uav_readdata[15].DATAIN -av_readdata[16] => uav_readdata[16].DATAIN -av_readdata[17] => uav_readdata[17].DATAIN -av_readdata[18] => uav_readdata[18].DATAIN -av_readdata[19] => uav_readdata[19].DATAIN -av_readdata[20] => uav_readdata[20].DATAIN -av_readdata[21] => uav_readdata[21].DATAIN -av_readdata[22] => uav_readdata[22].DATAIN -av_readdata[23] => uav_readdata[23].DATAIN -av_readdata[24] => uav_readdata[24].DATAIN -av_readdata[25] => uav_readdata[25].DATAIN -av_readdata[26] => uav_readdata[26].DATAIN -av_readdata[27] => uav_readdata[27].DATAIN -av_readdata[28] => uav_readdata[28].DATAIN -av_readdata[29] => uav_readdata[29].DATAIN -av_readdata[30] => uav_readdata[30].DATAIN -av_readdata[31] => uav_readdata[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => ~NO_FANOUT~ -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_write => av_write.DATAIN -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_read => av_read.DATAIN -uav_burstcount[0] => Equal0.IN3 -uav_burstcount[1] => Equal0.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal0.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= av_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= uav_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= uav_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => always18.IN1 -av_waitrequest => end_begintransfer.OUTPUTSELECT -av_waitrequest => uav_waitrequest.DATAIN -av_waitrequest => read_latency_shift_reg.IN1 -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -clk => wait_latency_counter[2].CLK -clk => wait_latency_counter[3].CLK -clk => wait_latency_counter[4].CLK -clk => wait_latency_counter[5].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -reset => wait_latency_counter[2].ACLR -reset => wait_latency_counter[3].ACLR -reset => wait_latency_counter[4].ACLR -reset => wait_latency_counter[5].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => ~NO_FANOUT~ -uav_writedata[9] => ~NO_FANOUT~ -uav_writedata[10] => ~NO_FANOUT~ -uav_writedata[11] => ~NO_FANOUT~ -uav_writedata[12] => ~NO_FANOUT~ -uav_writedata[13] => ~NO_FANOUT~ -uav_writedata[14] => ~NO_FANOUT~ -uav_writedata[15] => ~NO_FANOUT~ -uav_writedata[16] => ~NO_FANOUT~ -uav_writedata[17] => ~NO_FANOUT~ -uav_writedata[18] => ~NO_FANOUT~ -uav_writedata[19] => ~NO_FANOUT~ -uav_writedata[20] => ~NO_FANOUT~ -uav_writedata[21] => ~NO_FANOUT~ -uav_writedata[22] => ~NO_FANOUT~ -uav_writedata[23] => ~NO_FANOUT~ -uav_writedata[24] => ~NO_FANOUT~ -uav_writedata[25] => ~NO_FANOUT~ -uav_writedata[26] => ~NO_FANOUT~ -uav_writedata[27] => ~NO_FANOUT~ -uav_writedata[28] => ~NO_FANOUT~ -uav_writedata[29] => ~NO_FANOUT~ -uav_writedata[30] => ~NO_FANOUT~ -uav_writedata[31] => ~NO_FANOUT~ -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= -uav_readdata[9] <= -uav_readdata[10] <= -uav_readdata[11] <= -uav_readdata[12] <= -uav_readdata[13] <= -uav_readdata[14] <= -uav_readdata[15] <= -uav_readdata[16] <= -uav_readdata[17] <= -uav_readdata[18] <= -uav_readdata[19] <= -uav_readdata[20] <= -uav_readdata[21] <= -uav_readdata[22] <= -uav_readdata[23] <= -uav_readdata[24] <= -uav_readdata[25] <= -uav_readdata[26] <= -uav_readdata[27] <= -uav_readdata[28] <= -uav_readdata[29] <= -uav_readdata[30] <= -uav_readdata[31] <= -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent -clk => hold_waitrequest.CLK -reset => hold_waitrequest.PRESET -av_address[0] => ~NO_FANOUT~ -av_address[1] => ~NO_FANOUT~ -av_address[2] => cp_data[38].DATAIN -av_address[3] => cp_data[39].DATAIN -av_address[4] => cp_data[40].DATAIN -av_address[5] => cp_data[41].DATAIN -av_address[6] => cp_data[42].DATAIN -av_address[7] => cp_data[43].DATAIN -av_address[8] => cp_data[44].DATAIN -av_address[9] => cp_data[45].DATAIN -av_address[10] => cp_data[46].DATAIN -av_address[11] => cp_data[47].DATAIN -av_address[12] => cp_data[48].DATAIN -av_address[13] => cp_data[49].DATAIN -av_address[14] => cp_data[50].DATAIN -av_address[15] => cp_data[51].DATAIN -av_address[16] => cp_data[52].DATAIN -av_address[17] => cp_data[53].DATAIN -av_address[18] => cp_data[54].DATAIN -av_write => cp_data.IN0 -av_write => always1.IN0 -av_write => cp_data[57].DATAIN -av_read => always1.IN1 -av_read => cp_data[58].DATAIN -av_writedata[0] => cp_data[0].DATAIN -av_writedata[1] => cp_data[1].DATAIN -av_writedata[2] => cp_data[2].DATAIN -av_writedata[3] => cp_data[3].DATAIN -av_writedata[4] => cp_data[4].DATAIN -av_writedata[5] => cp_data[5].DATAIN -av_writedata[6] => cp_data[6].DATAIN -av_writedata[7] => cp_data[7].DATAIN -av_writedata[8] => cp_data[8].DATAIN -av_writedata[9] => cp_data[9].DATAIN -av_writedata[10] => cp_data[10].DATAIN -av_writedata[11] => cp_data[11].DATAIN -av_writedata[12] => cp_data[12].DATAIN -av_writedata[13] => cp_data[13].DATAIN -av_writedata[14] => cp_data[14].DATAIN -av_writedata[15] => cp_data[15].DATAIN -av_writedata[16] => cp_data[16].DATAIN -av_writedata[17] => cp_data[17].DATAIN -av_writedata[18] => cp_data[18].DATAIN -av_writedata[19] => cp_data[19].DATAIN -av_writedata[20] => cp_data[20].DATAIN -av_writedata[21] => cp_data[21].DATAIN -av_writedata[22] => cp_data[22].DATAIN -av_writedata[23] => cp_data[23].DATAIN -av_writedata[24] => cp_data[24].DATAIN -av_writedata[25] => cp_data[25].DATAIN -av_writedata[26] => cp_data[26].DATAIN -av_writedata[27] => cp_data[27].DATAIN -av_writedata[28] => cp_data[28].DATAIN -av_writedata[29] => cp_data[29].DATAIN -av_writedata[30] => cp_data[30].DATAIN -av_writedata[31] => cp_data[31].DATAIN -av_readdata[0] <= rp_data[0].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[1] <= rp_data[1].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[2] <= rp_data[2].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[3] <= rp_data[3].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[4] <= rp_data[4].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[5] <= rp_data[5].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[6] <= rp_data[6].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[7] <= rp_data[7].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[8] <= rp_data[8].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[9] <= rp_data[9].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[10] <= rp_data[10].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[11] <= rp_data[11].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[12] <= rp_data[12].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[13] <= rp_data[13].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[14] <= rp_data[14].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[15] <= rp_data[15].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[16] <= rp_data[16].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[17] <= rp_data[17].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[18] <= rp_data[18].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[19] <= rp_data[19].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[20] <= rp_data[20].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[21] <= rp_data[21].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[22] <= rp_data[22].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[23] <= rp_data[23].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[24] <= rp_data[24].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[25] <= rp_data[25].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[26] <= rp_data[26].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[27] <= rp_data[27].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[28] <= rp_data[28].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[29] <= rp_data[29].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[30] <= rp_data[30].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[31] <= rp_data[31].DB_MAX_OUTPUT_PORT_TYPE -av_waitrequest <= av_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -av_readdatavalid <= av_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] => cp_data[32].DATAIN -av_byteenable[1] => cp_data[33].DATAIN -av_byteenable[2] => cp_data[34].DATAIN -av_byteenable[3] => cp_data[35].DATAIN -av_burstcount[0] => cp_data[61].DATAIN -av_burstcount[1] => cp_data[62].DATAIN -av_burstcount[2] => cp_data[63].DATAIN -av_debugaccess => cp_data[87].DATAIN -av_lock => cp_data[59].DATAIN -av_response[0] <= -av_response[1] <= -av_writeresponserequest => cp_data.IN1 -av_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -cp_valid <= always1.DB_MAX_OUTPUT_PORT_TYPE -cp_data[0] <= av_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -cp_data[1] <= av_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -cp_data[2] <= av_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -cp_data[3] <= av_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -cp_data[4] <= av_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -cp_data[5] <= av_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -cp_data[6] <= av_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -cp_data[7] <= av_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -cp_data[8] <= av_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -cp_data[9] <= av_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -cp_data[10] <= av_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -cp_data[11] <= av_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -cp_data[12] <= av_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -cp_data[13] <= av_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -cp_data[14] <= av_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -cp_data[15] <= av_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -cp_data[16] <= av_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -cp_data[17] <= av_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -cp_data[18] <= av_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -cp_data[19] <= av_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -cp_data[20] <= av_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -cp_data[21] <= av_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -cp_data[22] <= av_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -cp_data[23] <= av_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -cp_data[24] <= av_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -cp_data[25] <= av_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -cp_data[26] <= av_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -cp_data[27] <= av_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -cp_data[28] <= av_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -cp_data[29] <= av_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -cp_data[30] <= av_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -cp_data[31] <= av_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -cp_data[32] <= av_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -cp_data[33] <= av_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE -cp_data[34] <= av_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE -cp_data[35] <= av_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE -cp_data[36] <= -cp_data[37] <= -cp_data[38] <= av_address[2].DB_MAX_OUTPUT_PORT_TYPE -cp_data[39] <= av_address[3].DB_MAX_OUTPUT_PORT_TYPE -cp_data[40] <= av_address[4].DB_MAX_OUTPUT_PORT_TYPE -cp_data[41] <= av_address[5].DB_MAX_OUTPUT_PORT_TYPE -cp_data[42] <= av_address[6].DB_MAX_OUTPUT_PORT_TYPE -cp_data[43] <= av_address[7].DB_MAX_OUTPUT_PORT_TYPE -cp_data[44] <= av_address[8].DB_MAX_OUTPUT_PORT_TYPE -cp_data[45] <= av_address[9].DB_MAX_OUTPUT_PORT_TYPE -cp_data[46] <= av_address[10].DB_MAX_OUTPUT_PORT_TYPE -cp_data[47] <= av_address[11].DB_MAX_OUTPUT_PORT_TYPE -cp_data[48] <= av_address[12].DB_MAX_OUTPUT_PORT_TYPE -cp_data[49] <= av_address[13].DB_MAX_OUTPUT_PORT_TYPE -cp_data[50] <= av_address[14].DB_MAX_OUTPUT_PORT_TYPE -cp_data[51] <= av_address[15].DB_MAX_OUTPUT_PORT_TYPE -cp_data[52] <= av_address[16].DB_MAX_OUTPUT_PORT_TYPE -cp_data[53] <= av_address[17].DB_MAX_OUTPUT_PORT_TYPE -cp_data[54] <= av_address[18].DB_MAX_OUTPUT_PORT_TYPE -cp_data[55] <= -cp_data[56] <= cp_data.DB_MAX_OUTPUT_PORT_TYPE -cp_data[57] <= av_write.DB_MAX_OUTPUT_PORT_TYPE -cp_data[58] <= av_read.DB_MAX_OUTPUT_PORT_TYPE -cp_data[59] <= av_lock.DB_MAX_OUTPUT_PORT_TYPE -cp_data[60] <= -cp_data[61] <= av_burstcount[0].DB_MAX_OUTPUT_PORT_TYPE -cp_data[62] <= av_burstcount[1].DB_MAX_OUTPUT_PORT_TYPE -cp_data[63] <= av_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -cp_data[64] <= -cp_data[65] <= -cp_data[66] <= -cp_data[67] <= -cp_data[68] <= -cp_data[69] <= -cp_data[70] <= -cp_data[71] <= -cp_data[72] <= -cp_data[73] <= -cp_data[74] <= -cp_data[75] <= -cp_data[76] <= -cp_data[77] <= -cp_data[78] <= -cp_data[79] <= -cp_data[80] <= -cp_data[81] <= -cp_data[82] <= -cp_data[83] <= -cp_data[84] <= -cp_data[85] <= -cp_data[86] <= -cp_data[87] <= av_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -cp_data[88] <= -cp_data[89] <= -cp_data[90] <= -cp_data[91] <= -cp_data[92] <= -cp_data[93] <= -cp_data[94] <= -cp_data[95] <= -cp_startofpacket <= -cp_endofpacket <= -cp_ready => av_waitrequest.IN1 -rp_valid => av_writeresponsevalid.DATAB -rp_valid => av_readdatavalid.DATAA -rp_data[0] => av_readdata[0].DATAIN -rp_data[1] => av_readdata[1].DATAIN -rp_data[2] => av_readdata[2].DATAIN -rp_data[3] => av_readdata[3].DATAIN -rp_data[4] => av_readdata[4].DATAIN -rp_data[5] => av_readdata[5].DATAIN -rp_data[6] => av_readdata[6].DATAIN -rp_data[7] => av_readdata[7].DATAIN -rp_data[8] => av_readdata[8].DATAIN -rp_data[9] => av_readdata[9].DATAIN -rp_data[10] => av_readdata[10].DATAIN -rp_data[11] => av_readdata[11].DATAIN -rp_data[12] => av_readdata[12].DATAIN -rp_data[13] => av_readdata[13].DATAIN -rp_data[14] => av_readdata[14].DATAIN -rp_data[15] => av_readdata[15].DATAIN -rp_data[16] => av_readdata[16].DATAIN -rp_data[17] => av_readdata[17].DATAIN -rp_data[18] => av_readdata[18].DATAIN -rp_data[19] => av_readdata[19].DATAIN -rp_data[20] => av_readdata[20].DATAIN -rp_data[21] => av_readdata[21].DATAIN -rp_data[22] => av_readdata[22].DATAIN -rp_data[23] => av_readdata[23].DATAIN -rp_data[24] => av_readdata[24].DATAIN -rp_data[25] => av_readdata[25].DATAIN -rp_data[26] => av_readdata[26].DATAIN -rp_data[27] => av_readdata[27].DATAIN -rp_data[28] => av_readdata[28].DATAIN -rp_data[29] => av_readdata[29].DATAIN -rp_data[30] => av_readdata[30].DATAIN -rp_data[31] => av_readdata[31].DATAIN -rp_data[32] => ~NO_FANOUT~ -rp_data[33] => ~NO_FANOUT~ -rp_data[34] => ~NO_FANOUT~ -rp_data[35] => ~NO_FANOUT~ -rp_data[36] => ~NO_FANOUT~ -rp_data[37] => ~NO_FANOUT~ -rp_data[38] => ~NO_FANOUT~ -rp_data[39] => ~NO_FANOUT~ -rp_data[40] => ~NO_FANOUT~ -rp_data[41] => ~NO_FANOUT~ -rp_data[42] => ~NO_FANOUT~ -rp_data[43] => ~NO_FANOUT~ -rp_data[44] => ~NO_FANOUT~ -rp_data[45] => ~NO_FANOUT~ -rp_data[46] => ~NO_FANOUT~ -rp_data[47] => ~NO_FANOUT~ -rp_data[48] => ~NO_FANOUT~ -rp_data[49] => ~NO_FANOUT~ -rp_data[50] => ~NO_FANOUT~ -rp_data[51] => ~NO_FANOUT~ -rp_data[52] => ~NO_FANOUT~ -rp_data[53] => ~NO_FANOUT~ -rp_data[54] => ~NO_FANOUT~ -rp_data[55] => ~NO_FANOUT~ -rp_data[56] => ~NO_FANOUT~ -rp_data[57] => av_writeresponsevalid.OUTPUTSELECT -rp_data[57] => av_readdatavalid.OUTPUTSELECT -rp_data[58] => ~NO_FANOUT~ -rp_data[59] => ~NO_FANOUT~ -rp_data[60] => ~NO_FANOUT~ -rp_data[61] => ~NO_FANOUT~ -rp_data[62] => ~NO_FANOUT~ -rp_data[63] => ~NO_FANOUT~ -rp_data[64] => ~NO_FANOUT~ -rp_data[65] => ~NO_FANOUT~ -rp_data[66] => ~NO_FANOUT~ -rp_data[67] => ~NO_FANOUT~ -rp_data[68] => ~NO_FANOUT~ -rp_data[69] => ~NO_FANOUT~ -rp_data[70] => ~NO_FANOUT~ -rp_data[71] => ~NO_FANOUT~ -rp_data[72] => ~NO_FANOUT~ -rp_data[73] => ~NO_FANOUT~ -rp_data[74] => ~NO_FANOUT~ -rp_data[75] => ~NO_FANOUT~ -rp_data[76] => ~NO_FANOUT~ -rp_data[77] => ~NO_FANOUT~ -rp_data[78] => ~NO_FANOUT~ -rp_data[79] => ~NO_FANOUT~ -rp_data[80] => ~NO_FANOUT~ -rp_data[81] => ~NO_FANOUT~ -rp_data[82] => ~NO_FANOUT~ -rp_data[83] => ~NO_FANOUT~ -rp_data[84] => ~NO_FANOUT~ -rp_data[85] => ~NO_FANOUT~ -rp_data[86] => ~NO_FANOUT~ -rp_data[87] => ~NO_FANOUT~ -rp_data[88] => ~NO_FANOUT~ -rp_data[89] => ~NO_FANOUT~ -rp_data[90] => ~NO_FANOUT~ -rp_data[91] => ~NO_FANOUT~ -rp_data[92] => ~NO_FANOUT~ -rp_data[93] => ~NO_FANOUT~ -rp_data[94] => ~NO_FANOUT~ -rp_data[95] => ~NO_FANOUT~ -rp_channel[0] => ~NO_FANOUT~ -rp_channel[1] => ~NO_FANOUT~ -rp_channel[2] => ~NO_FANOUT~ -rp_channel[3] => ~NO_FANOUT~ -rp_channel[4] => ~NO_FANOUT~ -rp_channel[5] => ~NO_FANOUT~ -rp_channel[6] => ~NO_FANOUT~ -rp_channel[7] => ~NO_FANOUT~ -rp_channel[8] => ~NO_FANOUT~ -rp_channel[9] => ~NO_FANOUT~ -rp_channel[10] => ~NO_FANOUT~ -rp_channel[11] => ~NO_FANOUT~ -rp_channel[12] => ~NO_FANOUT~ -rp_channel[13] => ~NO_FANOUT~ -rp_channel[14] => ~NO_FANOUT~ -rp_channel[15] => ~NO_FANOUT~ -rp_channel[16] => ~NO_FANOUT~ -rp_channel[17] => ~NO_FANOUT~ -rp_startofpacket => ~NO_FANOUT~ -rp_endofpacket => ~NO_FANOUT~ -rp_ready <= - - -|lights|nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent -clk => hold_waitrequest.CLK -reset => hold_waitrequest.PRESET -av_address[0] => ~NO_FANOUT~ -av_address[1] => ~NO_FANOUT~ -av_address[2] => cp_data[38].DATAIN -av_address[3] => cp_data[39].DATAIN -av_address[4] => cp_data[40].DATAIN -av_address[5] => cp_data[41].DATAIN -av_address[6] => cp_data[42].DATAIN -av_address[7] => cp_data[43].DATAIN -av_address[8] => cp_data[44].DATAIN -av_address[9] => cp_data[45].DATAIN -av_address[10] => cp_data[46].DATAIN -av_address[11] => cp_data[47].DATAIN -av_address[12] => cp_data[48].DATAIN -av_address[13] => cp_data[49].DATAIN -av_address[14] => cp_data[50].DATAIN -av_address[15] => cp_data[51].DATAIN -av_address[16] => cp_data[52].DATAIN -av_address[17] => cp_data[53].DATAIN -av_address[18] => cp_data[54].DATAIN -av_write => cp_data.IN0 -av_write => always1.IN0 -av_write => cp_data[57].DATAIN -av_read => always1.IN1 -av_read => cp_data[58].DATAIN -av_writedata[0] => cp_data[0].DATAIN -av_writedata[1] => cp_data[1].DATAIN -av_writedata[2] => cp_data[2].DATAIN -av_writedata[3] => cp_data[3].DATAIN -av_writedata[4] => cp_data[4].DATAIN -av_writedata[5] => cp_data[5].DATAIN -av_writedata[6] => cp_data[6].DATAIN -av_writedata[7] => cp_data[7].DATAIN -av_writedata[8] => cp_data[8].DATAIN -av_writedata[9] => cp_data[9].DATAIN -av_writedata[10] => cp_data[10].DATAIN -av_writedata[11] => cp_data[11].DATAIN -av_writedata[12] => cp_data[12].DATAIN -av_writedata[13] => cp_data[13].DATAIN -av_writedata[14] => cp_data[14].DATAIN -av_writedata[15] => cp_data[15].DATAIN -av_writedata[16] => cp_data[16].DATAIN -av_writedata[17] => cp_data[17].DATAIN -av_writedata[18] => cp_data[18].DATAIN -av_writedata[19] => cp_data[19].DATAIN -av_writedata[20] => cp_data[20].DATAIN -av_writedata[21] => cp_data[21].DATAIN -av_writedata[22] => cp_data[22].DATAIN -av_writedata[23] => cp_data[23].DATAIN -av_writedata[24] => cp_data[24].DATAIN -av_writedata[25] => cp_data[25].DATAIN -av_writedata[26] => cp_data[26].DATAIN -av_writedata[27] => cp_data[27].DATAIN -av_writedata[28] => cp_data[28].DATAIN -av_writedata[29] => cp_data[29].DATAIN -av_writedata[30] => cp_data[30].DATAIN -av_writedata[31] => cp_data[31].DATAIN -av_readdata[0] <= rp_data[0].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[1] <= rp_data[1].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[2] <= rp_data[2].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[3] <= rp_data[3].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[4] <= rp_data[4].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[5] <= rp_data[5].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[6] <= rp_data[6].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[7] <= rp_data[7].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[8] <= rp_data[8].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[9] <= rp_data[9].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[10] <= rp_data[10].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[11] <= rp_data[11].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[12] <= rp_data[12].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[13] <= rp_data[13].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[14] <= rp_data[14].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[15] <= rp_data[15].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[16] <= rp_data[16].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[17] <= rp_data[17].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[18] <= rp_data[18].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[19] <= rp_data[19].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[20] <= rp_data[20].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[21] <= rp_data[21].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[22] <= rp_data[22].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[23] <= rp_data[23].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[24] <= rp_data[24].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[25] <= rp_data[25].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[26] <= rp_data[26].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[27] <= rp_data[27].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[28] <= rp_data[28].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[29] <= rp_data[29].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[30] <= rp_data[30].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[31] <= rp_data[31].DB_MAX_OUTPUT_PORT_TYPE -av_waitrequest <= av_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -av_readdatavalid <= av_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] => cp_data[32].DATAIN -av_byteenable[1] => cp_data[33].DATAIN -av_byteenable[2] => cp_data[34].DATAIN -av_byteenable[3] => cp_data[35].DATAIN -av_burstcount[0] => cp_data[61].DATAIN -av_burstcount[1] => cp_data[62].DATAIN -av_burstcount[2] => cp_data[63].DATAIN -av_debugaccess => cp_data[87].DATAIN -av_lock => cp_data[59].DATAIN -av_response[0] <= -av_response[1] <= -av_writeresponserequest => cp_data.IN1 -av_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -cp_valid <= always1.DB_MAX_OUTPUT_PORT_TYPE -cp_data[0] <= av_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -cp_data[1] <= av_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -cp_data[2] <= av_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -cp_data[3] <= av_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -cp_data[4] <= av_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -cp_data[5] <= av_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -cp_data[6] <= av_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -cp_data[7] <= av_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -cp_data[8] <= av_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -cp_data[9] <= av_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -cp_data[10] <= av_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -cp_data[11] <= av_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -cp_data[12] <= av_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -cp_data[13] <= av_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -cp_data[14] <= av_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -cp_data[15] <= av_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -cp_data[16] <= av_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -cp_data[17] <= av_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -cp_data[18] <= av_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -cp_data[19] <= av_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -cp_data[20] <= av_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -cp_data[21] <= av_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -cp_data[22] <= av_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -cp_data[23] <= av_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -cp_data[24] <= av_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -cp_data[25] <= av_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -cp_data[26] <= av_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -cp_data[27] <= av_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -cp_data[28] <= av_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -cp_data[29] <= av_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -cp_data[30] <= av_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -cp_data[31] <= av_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -cp_data[32] <= av_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -cp_data[33] <= av_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE -cp_data[34] <= av_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE -cp_data[35] <= av_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE -cp_data[36] <= -cp_data[37] <= -cp_data[38] <= av_address[2].DB_MAX_OUTPUT_PORT_TYPE -cp_data[39] <= av_address[3].DB_MAX_OUTPUT_PORT_TYPE -cp_data[40] <= av_address[4].DB_MAX_OUTPUT_PORT_TYPE -cp_data[41] <= av_address[5].DB_MAX_OUTPUT_PORT_TYPE -cp_data[42] <= av_address[6].DB_MAX_OUTPUT_PORT_TYPE -cp_data[43] <= av_address[7].DB_MAX_OUTPUT_PORT_TYPE -cp_data[44] <= av_address[8].DB_MAX_OUTPUT_PORT_TYPE -cp_data[45] <= av_address[9].DB_MAX_OUTPUT_PORT_TYPE -cp_data[46] <= av_address[10].DB_MAX_OUTPUT_PORT_TYPE -cp_data[47] <= av_address[11].DB_MAX_OUTPUT_PORT_TYPE -cp_data[48] <= av_address[12].DB_MAX_OUTPUT_PORT_TYPE -cp_data[49] <= av_address[13].DB_MAX_OUTPUT_PORT_TYPE -cp_data[50] <= av_address[14].DB_MAX_OUTPUT_PORT_TYPE -cp_data[51] <= av_address[15].DB_MAX_OUTPUT_PORT_TYPE -cp_data[52] <= av_address[16].DB_MAX_OUTPUT_PORT_TYPE -cp_data[53] <= av_address[17].DB_MAX_OUTPUT_PORT_TYPE -cp_data[54] <= av_address[18].DB_MAX_OUTPUT_PORT_TYPE -cp_data[55] <= -cp_data[56] <= cp_data.DB_MAX_OUTPUT_PORT_TYPE -cp_data[57] <= av_write.DB_MAX_OUTPUT_PORT_TYPE -cp_data[58] <= av_read.DB_MAX_OUTPUT_PORT_TYPE -cp_data[59] <= av_lock.DB_MAX_OUTPUT_PORT_TYPE -cp_data[60] <= -cp_data[61] <= av_burstcount[0].DB_MAX_OUTPUT_PORT_TYPE -cp_data[62] <= av_burstcount[1].DB_MAX_OUTPUT_PORT_TYPE -cp_data[63] <= av_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -cp_data[64] <= -cp_data[65] <= -cp_data[66] <= -cp_data[67] <= -cp_data[68] <= -cp_data[69] <= -cp_data[70] <= -cp_data[71] <= -cp_data[72] <= -cp_data[73] <= -cp_data[74] <= -cp_data[75] <= -cp_data[76] <= -cp_data[77] <= -cp_data[78] <= -cp_data[79] <= -cp_data[80] <= -cp_data[81] <= -cp_data[82] <= -cp_data[83] <= -cp_data[84] <= -cp_data[85] <= -cp_data[86] <= -cp_data[87] <= av_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -cp_data[88] <= -cp_data[89] <= -cp_data[90] <= -cp_data[91] <= -cp_data[92] <= -cp_data[93] <= -cp_data[94] <= -cp_data[95] <= -cp_startofpacket <= -cp_endofpacket <= -cp_ready => av_waitrequest.IN1 -rp_valid => av_writeresponsevalid.DATAB -rp_valid => av_readdatavalid.DATAA -rp_data[0] => av_readdata[0].DATAIN -rp_data[1] => av_readdata[1].DATAIN -rp_data[2] => av_readdata[2].DATAIN -rp_data[3] => av_readdata[3].DATAIN -rp_data[4] => av_readdata[4].DATAIN -rp_data[5] => av_readdata[5].DATAIN -rp_data[6] => av_readdata[6].DATAIN -rp_data[7] => av_readdata[7].DATAIN -rp_data[8] => av_readdata[8].DATAIN -rp_data[9] => av_readdata[9].DATAIN -rp_data[10] => av_readdata[10].DATAIN -rp_data[11] => av_readdata[11].DATAIN -rp_data[12] => av_readdata[12].DATAIN -rp_data[13] => av_readdata[13].DATAIN -rp_data[14] => av_readdata[14].DATAIN -rp_data[15] => av_readdata[15].DATAIN -rp_data[16] => av_readdata[16].DATAIN -rp_data[17] => av_readdata[17].DATAIN -rp_data[18] => av_readdata[18].DATAIN -rp_data[19] => av_readdata[19].DATAIN -rp_data[20] => av_readdata[20].DATAIN -rp_data[21] => av_readdata[21].DATAIN -rp_data[22] => av_readdata[22].DATAIN -rp_data[23] => av_readdata[23].DATAIN -rp_data[24] => av_readdata[24].DATAIN -rp_data[25] => av_readdata[25].DATAIN -rp_data[26] => av_readdata[26].DATAIN -rp_data[27] => av_readdata[27].DATAIN -rp_data[28] => av_readdata[28].DATAIN -rp_data[29] => av_readdata[29].DATAIN -rp_data[30] => av_readdata[30].DATAIN -rp_data[31] => av_readdata[31].DATAIN -rp_data[32] => ~NO_FANOUT~ -rp_data[33] => ~NO_FANOUT~ -rp_data[34] => ~NO_FANOUT~ -rp_data[35] => ~NO_FANOUT~ -rp_data[36] => ~NO_FANOUT~ -rp_data[37] => ~NO_FANOUT~ -rp_data[38] => ~NO_FANOUT~ -rp_data[39] => ~NO_FANOUT~ -rp_data[40] => ~NO_FANOUT~ -rp_data[41] => ~NO_FANOUT~ -rp_data[42] => ~NO_FANOUT~ -rp_data[43] => ~NO_FANOUT~ -rp_data[44] => ~NO_FANOUT~ -rp_data[45] => ~NO_FANOUT~ -rp_data[46] => ~NO_FANOUT~ -rp_data[47] => ~NO_FANOUT~ -rp_data[48] => ~NO_FANOUT~ -rp_data[49] => ~NO_FANOUT~ -rp_data[50] => ~NO_FANOUT~ -rp_data[51] => ~NO_FANOUT~ -rp_data[52] => ~NO_FANOUT~ -rp_data[53] => ~NO_FANOUT~ -rp_data[54] => ~NO_FANOUT~ -rp_data[55] => ~NO_FANOUT~ -rp_data[56] => ~NO_FANOUT~ -rp_data[57] => av_writeresponsevalid.OUTPUTSELECT -rp_data[57] => av_readdatavalid.OUTPUTSELECT -rp_data[58] => ~NO_FANOUT~ -rp_data[59] => ~NO_FANOUT~ -rp_data[60] => ~NO_FANOUT~ -rp_data[61] => ~NO_FANOUT~ -rp_data[62] => ~NO_FANOUT~ -rp_data[63] => ~NO_FANOUT~ -rp_data[64] => ~NO_FANOUT~ -rp_data[65] => ~NO_FANOUT~ -rp_data[66] => ~NO_FANOUT~ -rp_data[67] => ~NO_FANOUT~ -rp_data[68] => ~NO_FANOUT~ -rp_data[69] => ~NO_FANOUT~ -rp_data[70] => ~NO_FANOUT~ -rp_data[71] => ~NO_FANOUT~ -rp_data[72] => ~NO_FANOUT~ -rp_data[73] => ~NO_FANOUT~ -rp_data[74] => ~NO_FANOUT~ -rp_data[75] => ~NO_FANOUT~ -rp_data[76] => ~NO_FANOUT~ -rp_data[77] => ~NO_FANOUT~ -rp_data[78] => ~NO_FANOUT~ -rp_data[79] => ~NO_FANOUT~ -rp_data[80] => ~NO_FANOUT~ -rp_data[81] => ~NO_FANOUT~ -rp_data[82] => ~NO_FANOUT~ -rp_data[83] => ~NO_FANOUT~ -rp_data[84] => ~NO_FANOUT~ -rp_data[85] => ~NO_FANOUT~ -rp_data[86] => ~NO_FANOUT~ -rp_data[87] => ~NO_FANOUT~ -rp_data[88] => ~NO_FANOUT~ -rp_data[89] => ~NO_FANOUT~ -rp_data[90] => ~NO_FANOUT~ -rp_data[91] => ~NO_FANOUT~ -rp_data[92] => ~NO_FANOUT~ -rp_data[93] => ~NO_FANOUT~ -rp_data[94] => ~NO_FANOUT~ -rp_data[95] => ~NO_FANOUT~ -rp_channel[0] => ~NO_FANOUT~ -rp_channel[1] => ~NO_FANOUT~ -rp_channel[2] => ~NO_FANOUT~ -rp_channel[3] => ~NO_FANOUT~ -rp_channel[4] => ~NO_FANOUT~ -rp_channel[5] => ~NO_FANOUT~ -rp_channel[6] => ~NO_FANOUT~ -rp_channel[7] => ~NO_FANOUT~ -rp_channel[8] => ~NO_FANOUT~ -rp_channel[9] => ~NO_FANOUT~ -rp_channel[10] => ~NO_FANOUT~ -rp_channel[11] => ~NO_FANOUT~ -rp_channel[12] => ~NO_FANOUT~ -rp_channel[13] => ~NO_FANOUT~ -rp_channel[14] => ~NO_FANOUT~ -rp_channel[15] => ~NO_FANOUT~ -rp_channel[16] => ~NO_FANOUT~ -rp_channel[17] => ~NO_FANOUT~ -rp_startofpacket => ~NO_FANOUT~ -rp_endofpacket => ~NO_FANOUT~ -rp_ready <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|nios_system_addr_router:addr_router -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[47] => Equal0.IN1 -sink_data[48] => src_data[48].DATAIN -sink_data[48] => Equal0.IN7 -sink_data[49] => src_data[49].DATAIN -sink_data[49] => Equal0.IN6 -sink_data[50] => src_data[50].DATAIN -sink_data[50] => Equal0.IN5 -sink_data[51] => src_data[51].DATAIN -sink_data[51] => Equal0.IN4 -sink_data[52] => src_data[52].DATAIN -sink_data[52] => Equal0.IN3 -sink_data[53] => src_data[53].DATAIN -sink_data[53] => Equal0.IN2 -sink_data[54] => src_data[54].DATAIN -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_data.OUTPUTSELECT -sink_data[54] => src_data.OUTPUTSELECT -sink_data[54] => src_data.OUTPUTSELECT -sink_data[54] => src_data.OUTPUTSELECT -sink_data[54] => src_data.OUTPUTSELECT -sink_data[54] => Equal0.IN0 -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => ~NO_FANOUT~ -sink_data[82] => ~NO_FANOUT~ -sink_data[83] => ~NO_FANOUT~ -sink_data[84] => ~NO_FANOUT~ -sink_data[85] => ~NO_FANOUT~ -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= src_data.DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= src_data.DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= src_data.DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= src_data.DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= src_data.DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_addr_router:addr_router|nios_system_addr_router_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_addr_router_001:addr_router_001 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[39] => Equal16.IN15 -sink_data[40] => src_data[40].DATAIN -sink_data[40] => Equal1.IN2 -sink_data[40] => Equal2.IN14 -sink_data[40] => Equal3.IN3 -sink_data[40] => Equal4.IN14 -sink_data[40] => Equal5.IN3 -sink_data[40] => Equal6.IN14 -sink_data[40] => Equal7.IN4 -sink_data[40] => Equal8.IN14 -sink_data[40] => Equal9.IN3 -sink_data[40] => Equal10.IN14 -sink_data[40] => Equal11.IN4 -sink_data[40] => Equal12.IN14 -sink_data[40] => Equal13.IN4 -sink_data[40] => Equal14.IN14 -sink_data[40] => Equal15.IN5 -sink_data[40] => Equal16.IN14 -sink_data[41] => src_data[41].DATAIN -sink_data[41] => Equal1.IN14 -sink_data[41] => Equal2.IN2 -sink_data[41] => Equal3.IN2 -sink_data[41] => Equal4.IN13 -sink_data[41] => Equal5.IN14 -sink_data[41] => Equal6.IN3 -sink_data[41] => Equal7.IN3 -sink_data[41] => Equal8.IN13 -sink_data[41] => Equal9.IN14 -sink_data[41] => Equal10.IN3 -sink_data[41] => Equal11.IN3 -sink_data[41] => Equal12.IN13 -sink_data[41] => Equal13.IN14 -sink_data[41] => Equal14.IN4 -sink_data[41] => Equal15.IN4 -sink_data[41] => Equal16.IN13 -sink_data[42] => src_data[42].DATAIN -sink_data[42] => Equal1.IN13 -sink_data[42] => Equal2.IN13 -sink_data[42] => Equal3.IN14 -sink_data[42] => Equal4.IN2 -sink_data[42] => Equal5.IN2 -sink_data[42] => Equal6.IN2 -sink_data[42] => Equal7.IN2 -sink_data[42] => Equal8.IN12 -sink_data[42] => Equal9.IN13 -sink_data[42] => Equal10.IN13 -sink_data[42] => Equal11.IN14 -sink_data[42] => Equal12.IN3 -sink_data[42] => Equal13.IN3 -sink_data[42] => Equal14.IN3 -sink_data[42] => Equal15.IN3 -sink_data[42] => Equal16.IN12 -sink_data[43] => src_data[43].DATAIN -sink_data[43] => Equal1.IN12 -sink_data[43] => Equal2.IN12 -sink_data[43] => Equal3.IN13 -sink_data[43] => Equal4.IN12 -sink_data[43] => Equal5.IN13 -sink_data[43] => Equal6.IN13 -sink_data[43] => Equal7.IN14 -sink_data[43] => Equal8.IN2 -sink_data[43] => Equal9.IN2 -sink_data[43] => Equal10.IN2 -sink_data[43] => Equal11.IN2 -sink_data[43] => Equal12.IN2 -sink_data[43] => Equal13.IN2 -sink_data[43] => Equal14.IN2 -sink_data[43] => Equal15.IN2 -sink_data[43] => Equal16.IN11 -sink_data[44] => src_data[44].DATAIN -sink_data[44] => Equal1.IN11 -sink_data[44] => Equal2.IN11 -sink_data[44] => Equal3.IN12 -sink_data[44] => Equal4.IN11 -sink_data[44] => Equal5.IN12 -sink_data[44] => Equal6.IN12 -sink_data[44] => Equal7.IN13 -sink_data[44] => Equal8.IN11 -sink_data[44] => Equal9.IN12 -sink_data[44] => Equal10.IN12 -sink_data[44] => Equal11.IN13 -sink_data[44] => Equal12.IN12 -sink_data[44] => Equal13.IN13 -sink_data[44] => Equal14.IN13 -sink_data[44] => Equal15.IN14 -sink_data[44] => Equal16.IN2 -sink_data[45] => src_data[45].DATAIN -sink_data[45] => Equal1.IN10 -sink_data[45] => Equal2.IN10 -sink_data[45] => Equal3.IN11 -sink_data[45] => Equal4.IN10 -sink_data[45] => Equal5.IN11 -sink_data[45] => Equal6.IN11 -sink_data[45] => Equal7.IN12 -sink_data[45] => Equal8.IN10 -sink_data[45] => Equal9.IN11 -sink_data[45] => Equal10.IN11 -sink_data[45] => Equal11.IN12 -sink_data[45] => Equal12.IN11 -sink_data[45] => Equal13.IN12 -sink_data[45] => Equal14.IN12 -sink_data[45] => Equal15.IN13 -sink_data[45] => Equal16.IN10 -sink_data[46] => src_data[46].DATAIN -sink_data[46] => Equal1.IN9 -sink_data[46] => Equal2.IN9 -sink_data[46] => Equal3.IN10 -sink_data[46] => Equal4.IN9 -sink_data[46] => Equal5.IN10 -sink_data[46] => Equal6.IN10 -sink_data[46] => Equal7.IN11 -sink_data[46] => Equal8.IN9 -sink_data[46] => Equal9.IN10 -sink_data[46] => Equal10.IN10 -sink_data[46] => Equal11.IN11 -sink_data[46] => Equal12.IN10 -sink_data[46] => Equal13.IN11 -sink_data[46] => Equal14.IN11 -sink_data[46] => Equal15.IN12 -sink_data[46] => Equal16.IN9 -sink_data[47] => src_data[47].DATAIN -sink_data[47] => Equal0.IN1 -sink_data[47] => Equal1.IN8 -sink_data[47] => Equal2.IN8 -sink_data[47] => Equal3.IN9 -sink_data[47] => Equal4.IN8 -sink_data[47] => Equal5.IN9 -sink_data[47] => Equal6.IN9 -sink_data[47] => Equal7.IN10 -sink_data[47] => Equal8.IN8 -sink_data[47] => Equal9.IN9 -sink_data[47] => Equal10.IN9 -sink_data[47] => Equal11.IN10 -sink_data[47] => Equal12.IN9 -sink_data[47] => Equal13.IN10 -sink_data[47] => Equal14.IN10 -sink_data[47] => Equal15.IN11 -sink_data[47] => Equal16.IN8 -sink_data[48] => src_data[48].DATAIN -sink_data[48] => Equal0.IN7 -sink_data[48] => Equal1.IN1 -sink_data[48] => Equal2.IN1 -sink_data[48] => Equal3.IN1 -sink_data[48] => Equal4.IN1 -sink_data[48] => Equal5.IN1 -sink_data[48] => Equal6.IN1 -sink_data[48] => Equal7.IN1 -sink_data[48] => Equal8.IN1 -sink_data[48] => Equal9.IN1 -sink_data[48] => Equal10.IN1 -sink_data[48] => Equal11.IN1 -sink_data[48] => Equal12.IN1 -sink_data[48] => Equal13.IN1 -sink_data[48] => Equal14.IN1 -sink_data[48] => Equal15.IN1 -sink_data[48] => Equal16.IN1 -sink_data[49] => src_data[49].DATAIN -sink_data[49] => Equal0.IN6 -sink_data[49] => Equal1.IN7 -sink_data[49] => Equal2.IN7 -sink_data[49] => Equal3.IN8 -sink_data[49] => Equal4.IN7 -sink_data[49] => Equal5.IN8 -sink_data[49] => Equal6.IN8 -sink_data[49] => Equal7.IN9 -sink_data[49] => Equal8.IN7 -sink_data[49] => Equal9.IN8 -sink_data[49] => Equal10.IN8 -sink_data[49] => Equal11.IN9 -sink_data[49] => Equal12.IN8 -sink_data[49] => Equal13.IN9 -sink_data[49] => Equal14.IN9 -sink_data[49] => Equal15.IN10 -sink_data[49] => Equal16.IN7 -sink_data[50] => src_data[50].DATAIN -sink_data[50] => Equal0.IN5 -sink_data[50] => Equal1.IN6 -sink_data[50] => Equal2.IN6 -sink_data[50] => Equal3.IN7 -sink_data[50] => Equal4.IN6 -sink_data[50] => Equal5.IN7 -sink_data[50] => Equal6.IN7 -sink_data[50] => Equal7.IN8 -sink_data[50] => Equal8.IN6 -sink_data[50] => Equal9.IN7 -sink_data[50] => Equal10.IN7 -sink_data[50] => Equal11.IN8 -sink_data[50] => Equal12.IN7 -sink_data[50] => Equal13.IN8 -sink_data[50] => Equal14.IN8 -sink_data[50] => Equal15.IN9 -sink_data[50] => Equal16.IN6 -sink_data[51] => src_data[51].DATAIN -sink_data[51] => Equal0.IN4 -sink_data[51] => Equal1.IN5 -sink_data[51] => Equal2.IN5 -sink_data[51] => Equal3.IN6 -sink_data[51] => Equal4.IN5 -sink_data[51] => Equal5.IN6 -sink_data[51] => Equal6.IN6 -sink_data[51] => Equal7.IN7 -sink_data[51] => Equal8.IN5 -sink_data[51] => Equal9.IN6 -sink_data[51] => Equal10.IN6 -sink_data[51] => Equal11.IN7 -sink_data[51] => Equal12.IN6 -sink_data[51] => Equal13.IN7 -sink_data[51] => Equal14.IN7 -sink_data[51] => Equal15.IN8 -sink_data[51] => Equal16.IN5 -sink_data[52] => src_data[52].DATAIN -sink_data[52] => Equal0.IN3 -sink_data[52] => Equal1.IN4 -sink_data[52] => Equal2.IN4 -sink_data[52] => Equal3.IN5 -sink_data[52] => Equal4.IN4 -sink_data[52] => Equal5.IN5 -sink_data[52] => Equal6.IN5 -sink_data[52] => Equal7.IN6 -sink_data[52] => Equal8.IN4 -sink_data[52] => Equal9.IN5 -sink_data[52] => Equal10.IN5 -sink_data[52] => Equal11.IN6 -sink_data[52] => Equal12.IN5 -sink_data[52] => Equal13.IN6 -sink_data[52] => Equal14.IN6 -sink_data[52] => Equal15.IN7 -sink_data[52] => Equal16.IN4 -sink_data[53] => src_data[53].DATAIN -sink_data[53] => Equal0.IN2 -sink_data[53] => Equal1.IN3 -sink_data[53] => Equal2.IN3 -sink_data[53] => Equal3.IN4 -sink_data[53] => Equal4.IN3 -sink_data[53] => Equal5.IN4 -sink_data[53] => Equal6.IN4 -sink_data[53] => Equal7.IN5 -sink_data[53] => Equal8.IN3 -sink_data[53] => Equal9.IN4 -sink_data[53] => Equal10.IN4 -sink_data[53] => Equal11.IN5 -sink_data[53] => Equal12.IN4 -sink_data[53] => Equal13.IN5 -sink_data[53] => Equal14.IN5 -sink_data[53] => Equal15.IN6 -sink_data[53] => Equal16.IN3 -sink_data[54] => src_data[54].DATAIN -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_data.OUTPUTSELECT -sink_data[54] => src_data.OUTPUTSELECT -sink_data[54] => src_data.OUTPUTSELECT -sink_data[54] => src_data.OUTPUTSELECT -sink_data[54] => src_data.OUTPUTSELECT -sink_data[54] => Equal0.IN0 -sink_data[54] => Equal1.IN0 -sink_data[54] => Equal2.IN0 -sink_data[54] => Equal3.IN0 -sink_data[54] => Equal4.IN0 -sink_data[54] => Equal5.IN0 -sink_data[54] => Equal6.IN0 -sink_data[54] => Equal7.IN0 -sink_data[54] => Equal8.IN0 -sink_data[54] => Equal9.IN0 -sink_data[54] => Equal10.IN0 -sink_data[54] => Equal11.IN0 -sink_data[54] => Equal12.IN0 -sink_data[54] => Equal13.IN0 -sink_data[54] => Equal14.IN0 -sink_data[54] => Equal15.IN0 -sink_data[54] => Equal16.IN0 -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => ~NO_FANOUT~ -sink_data[82] => ~NO_FANOUT~ -sink_data[83] => ~NO_FANOUT~ -sink_data[84] => ~NO_FANOUT~ -sink_data[85] => ~NO_FANOUT~ -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= src_data.DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= src_data.DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= src_data.DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= src_data.DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= src_data.DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_addr_router_001:addr_router_001|nios_system_addr_router_001_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router:id_router -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN0 -sink_data[81] => Equal1.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN31 -sink_data[82] => Equal1.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN30 -sink_data[83] => Equal1.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN29 -sink_data[84] => Equal1.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN28 -sink_data[85] => Equal1.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router:id_router|nios_system_id_router_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router:id_router_001 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN0 -sink_data[81] => Equal1.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN31 -sink_data[82] => Equal1.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN30 -sink_data[83] => Equal1.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN29 -sink_data[84] => Equal1.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN28 -sink_data[85] => Equal1.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router:id_router_001|nios_system_id_router_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_002 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_002|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_003 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_003|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_004 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_004|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_005 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_005|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_006 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_006|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_007 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_007|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_008 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_008|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_009 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_009|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_010 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_010|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_011 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_011|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_012 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_012|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_013 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_013|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_014 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_014|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_015 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_015|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_016 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_016|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_017 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_017|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|altera_reset_controller:rst_controller -reset_in0 => merged_reset.IN0 -reset_in1 => merged_reset.IN1 -reset_in2 => merged_reset.IN1 -reset_in3 => merged_reset.IN1 -reset_in4 => merged_reset.IN1 -reset_in5 => merged_reset.IN1 -reset_in6 => merged_reset.IN1 -reset_in7 => merged_reset.IN1 -reset_in8 => merged_reset.IN1 -reset_in9 => merged_reset.IN1 -reset_in10 => merged_reset.IN1 -reset_in11 => merged_reset.IN1 -reset_in12 => merged_reset.IN1 -reset_in13 => merged_reset.IN1 -reset_in14 => merged_reset.IN1 -reset_in15 => merged_reset.IN1 -clk => clk.IN1 -reset_out <= r_sync_rst.DB_MAX_OUTPUT_PORT_TYPE -reset_req <= r_early_rst.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 -reset_in => altera_reset_synchronizer_int_chain_out.PRESET -reset_in => altera_reset_synchronizer_int_chain[0].PRESET -reset_in => altera_reset_synchronizer_int_chain[1].PRESET -clk => altera_reset_synchronizer_int_chain_out.CLK -clk => altera_reset_synchronizer_int_chain[0].CLK -clk => altera_reset_synchronizer_int_chain[1].CLK -reset_out <= altera_reset_synchronizer_int_chain_out.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_cmd_xbar_demux:cmd_xbar_demux -sink_valid[0] => src0_valid.IN0 -sink_valid[0] => src1_valid.IN0 -sink_data[0] => src1_data[0].DATAIN -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src1_data[1].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src1_data[2].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src1_data[3].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src1_data[4].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src1_data[5].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src1_data[6].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src1_data[7].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src1_data[8].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src1_data[9].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src1_data[10].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src1_data[11].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src1_data[12].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src1_data[13].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src1_data[14].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src1_data[15].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src1_data[16].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src1_data[17].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src1_data[18].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src1_data[19].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src1_data[20].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src1_data[21].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src1_data[22].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src1_data[23].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src1_data[24].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src1_data[25].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src1_data[26].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src1_data[27].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src1_data[28].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src1_data[29].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src1_data[30].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src1_data[31].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src1_data[32].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src1_data[33].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src1_data[34].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src1_data[35].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src1_data[36].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src1_data[37].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src1_data[38].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src1_data[39].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src1_data[40].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src1_data[41].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src1_data[42].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src1_data[43].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src1_data[44].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src1_data[45].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src1_data[46].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src1_data[47].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src1_data[48].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src1_data[49].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src1_data[50].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src1_data[51].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src1_data[52].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src1_data[53].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src1_data[54].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src1_data[55].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src1_data[56].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src1_data[57].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src1_data[58].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src1_data[59].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src1_data[60].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src1_data[61].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src1_data[62].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src1_data[63].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src1_data[64].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src1_data[65].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src1_data[66].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src1_data[67].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src1_data[68].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src1_data[69].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src1_data[70].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src1_data[71].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src1_data[72].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src1_data[73].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src1_data[74].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src1_data[75].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src1_data[76].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src1_data[77].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src1_data[78].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src1_data[79].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src1_data[80].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src1_data[81].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src1_data[82].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src1_data[83].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src1_data[84].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src1_data[85].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src1_data[86].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src1_data[87].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src1_data[88].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src1_data[89].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src1_data[90].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src1_data[91].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src1_data[92].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src1_data[93].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src1_data[94].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src1_data[95].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src1_valid.IN1 -sink_channel[1] => sink_ready.IN0 -sink_channel[2] => src1_channel[0].DATAIN -sink_channel[2] => src0_channel[0].DATAIN -sink_channel[3] => src1_channel[1].DATAIN -sink_channel[3] => src0_channel[1].DATAIN -sink_channel[4] => src1_channel[2].DATAIN -sink_channel[4] => src0_channel[2].DATAIN -sink_channel[5] => src1_channel[3].DATAIN -sink_channel[5] => src0_channel[3].DATAIN -sink_channel[6] => src1_channel[4].DATAIN -sink_channel[6] => src0_channel[4].DATAIN -sink_channel[7] => src1_channel[5].DATAIN -sink_channel[7] => src0_channel[5].DATAIN -sink_channel[8] => src1_channel[6].DATAIN -sink_channel[8] => src0_channel[6].DATAIN -sink_channel[9] => src1_channel[7].DATAIN -sink_channel[9] => src0_channel[7].DATAIN -sink_channel[10] => src1_channel[8].DATAIN -sink_channel[10] => src0_channel[8].DATAIN -sink_channel[11] => src1_channel[9].DATAIN -sink_channel[11] => src0_channel[9].DATAIN -sink_channel[12] => src1_channel[10].DATAIN -sink_channel[12] => src0_channel[10].DATAIN -sink_channel[13] => src1_channel[11].DATAIN -sink_channel[13] => src0_channel[11].DATAIN -sink_channel[14] => src1_channel[12].DATAIN -sink_channel[14] => src0_channel[12].DATAIN -sink_channel[15] => src1_channel[13].DATAIN -sink_channel[15] => src0_channel[13].DATAIN -sink_channel[16] => src1_channel[14].DATAIN -sink_channel[16] => src0_channel[14].DATAIN -sink_channel[17] => src1_channel[15].DATAIN -sink_channel[17] => src0_channel[15].DATAIN -sink_startofpacket => src1_startofpacket.DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src1_endofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -src1_valid <= src1_valid.DB_MAX_OUTPUT_PORT_TYPE -src1_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src1_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src1_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src1_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src1_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src1_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src1_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src1_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src1_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src1_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src1_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src1_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src1_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src1_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src1_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src1_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src1_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src1_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src1_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src1_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src1_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src1_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src1_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src1_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src1_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src1_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src1_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src1_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src1_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src1_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src1_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src1_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src1_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src1_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src1_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src1_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src1_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src1_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src1_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src1_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src1_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src1_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src1_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src1_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src1_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src1_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src1_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src1_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src1_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src1_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src1_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src1_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src1_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src1_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src1_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src1_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src1_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src1_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src1_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src1_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src1_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src1_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src1_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src1_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src1_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src1_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src1_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src1_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src1_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src1_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src1_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src1_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src1_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src1_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src1_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src1_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src1_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src1_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src1_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src1_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src1_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src1_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src1_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src1_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src1_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src1_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src1_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src1_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src1_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src1_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src1_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src1_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src1_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src1_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src1_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src1_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[0] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[1] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[2] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[3] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[4] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[5] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[6] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[7] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[8] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[9] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[10] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[11] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[12] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[13] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[14] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[15] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[16] <= -src1_channel[17] <= -src1_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src1_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src1_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001 -sink_valid[0] => src0_valid.IN0 -sink_valid[0] => src1_valid.IN0 -sink_valid[0] => src2_valid.IN0 -sink_valid[0] => src3_valid.IN0 -sink_valid[0] => src4_valid.IN0 -sink_valid[0] => src5_valid.IN0 -sink_valid[0] => src6_valid.IN0 -sink_valid[0] => src7_valid.IN0 -sink_valid[0] => src8_valid.IN0 -sink_valid[0] => src9_valid.IN0 -sink_valid[0] => src10_valid.IN0 -sink_valid[0] => src11_valid.IN0 -sink_valid[0] => src12_valid.IN0 -sink_valid[0] => src13_valid.IN0 -sink_valid[0] => src14_valid.IN0 -sink_valid[0] => src15_valid.IN0 -sink_valid[0] => src16_valid.IN0 -sink_valid[0] => src17_valid.IN0 -sink_data[0] => src17_data[0].DATAIN -sink_data[0] => src0_data[0].DATAIN -sink_data[0] => src1_data[0].DATAIN -sink_data[0] => src2_data[0].DATAIN -sink_data[0] => src3_data[0].DATAIN -sink_data[0] => src4_data[0].DATAIN -sink_data[0] => src5_data[0].DATAIN -sink_data[0] => src6_data[0].DATAIN -sink_data[0] => src7_data[0].DATAIN -sink_data[0] => src8_data[0].DATAIN -sink_data[0] => src9_data[0].DATAIN -sink_data[0] => src10_data[0].DATAIN -sink_data[0] => src11_data[0].DATAIN -sink_data[0] => src12_data[0].DATAIN -sink_data[0] => src13_data[0].DATAIN -sink_data[0] => src14_data[0].DATAIN -sink_data[0] => src15_data[0].DATAIN -sink_data[0] => src16_data[0].DATAIN -sink_data[1] => src17_data[1].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[1] => src1_data[1].DATAIN -sink_data[1] => src2_data[1].DATAIN -sink_data[1] => src3_data[1].DATAIN -sink_data[1] => src4_data[1].DATAIN -sink_data[1] => src5_data[1].DATAIN -sink_data[1] => src6_data[1].DATAIN -sink_data[1] => src7_data[1].DATAIN -sink_data[1] => src8_data[1].DATAIN -sink_data[1] => src9_data[1].DATAIN -sink_data[1] => src10_data[1].DATAIN -sink_data[1] => src11_data[1].DATAIN -sink_data[1] => src12_data[1].DATAIN -sink_data[1] => src13_data[1].DATAIN -sink_data[1] => src14_data[1].DATAIN -sink_data[1] => src15_data[1].DATAIN -sink_data[1] => src16_data[1].DATAIN -sink_data[2] => src17_data[2].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[2] => src1_data[2].DATAIN -sink_data[2] => src2_data[2].DATAIN -sink_data[2] => src3_data[2].DATAIN -sink_data[2] => src4_data[2].DATAIN -sink_data[2] => src5_data[2].DATAIN -sink_data[2] => src6_data[2].DATAIN -sink_data[2] => src7_data[2].DATAIN -sink_data[2] => src8_data[2].DATAIN -sink_data[2] => src9_data[2].DATAIN -sink_data[2] => src10_data[2].DATAIN -sink_data[2] => src11_data[2].DATAIN -sink_data[2] => src12_data[2].DATAIN -sink_data[2] => src13_data[2].DATAIN -sink_data[2] => src14_data[2].DATAIN -sink_data[2] => src15_data[2].DATAIN -sink_data[2] => src16_data[2].DATAIN -sink_data[3] => src17_data[3].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[3] => src1_data[3].DATAIN -sink_data[3] => src2_data[3].DATAIN -sink_data[3] => src3_data[3].DATAIN -sink_data[3] => src4_data[3].DATAIN -sink_data[3] => src5_data[3].DATAIN -sink_data[3] => src6_data[3].DATAIN -sink_data[3] => src7_data[3].DATAIN -sink_data[3] => src8_data[3].DATAIN -sink_data[3] => src9_data[3].DATAIN -sink_data[3] => src10_data[3].DATAIN -sink_data[3] => src11_data[3].DATAIN -sink_data[3] => src12_data[3].DATAIN -sink_data[3] => src13_data[3].DATAIN -sink_data[3] => src14_data[3].DATAIN -sink_data[3] => src15_data[3].DATAIN -sink_data[3] => src16_data[3].DATAIN -sink_data[4] => src17_data[4].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[4] => src1_data[4].DATAIN -sink_data[4] => src2_data[4].DATAIN -sink_data[4] => src3_data[4].DATAIN -sink_data[4] => src4_data[4].DATAIN -sink_data[4] => src5_data[4].DATAIN -sink_data[4] => src6_data[4].DATAIN -sink_data[4] => src7_data[4].DATAIN -sink_data[4] => src8_data[4].DATAIN -sink_data[4] => src9_data[4].DATAIN -sink_data[4] => src10_data[4].DATAIN -sink_data[4] => src11_data[4].DATAIN -sink_data[4] => src12_data[4].DATAIN -sink_data[4] => src13_data[4].DATAIN -sink_data[4] => src14_data[4].DATAIN -sink_data[4] => src15_data[4].DATAIN -sink_data[4] => src16_data[4].DATAIN -sink_data[5] => src17_data[5].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[5] => src1_data[5].DATAIN -sink_data[5] => src2_data[5].DATAIN -sink_data[5] => src3_data[5].DATAIN -sink_data[5] => src4_data[5].DATAIN -sink_data[5] => src5_data[5].DATAIN -sink_data[5] => src6_data[5].DATAIN -sink_data[5] => src7_data[5].DATAIN -sink_data[5] => src8_data[5].DATAIN -sink_data[5] => src9_data[5].DATAIN -sink_data[5] => src10_data[5].DATAIN -sink_data[5] => src11_data[5].DATAIN -sink_data[5] => src12_data[5].DATAIN -sink_data[5] => src13_data[5].DATAIN -sink_data[5] => src14_data[5].DATAIN -sink_data[5] => src15_data[5].DATAIN -sink_data[5] => src16_data[5].DATAIN -sink_data[6] => src17_data[6].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[6] => src1_data[6].DATAIN -sink_data[6] => src2_data[6].DATAIN -sink_data[6] => src3_data[6].DATAIN -sink_data[6] => src4_data[6].DATAIN -sink_data[6] => src5_data[6].DATAIN -sink_data[6] => src6_data[6].DATAIN -sink_data[6] => src7_data[6].DATAIN -sink_data[6] => src8_data[6].DATAIN -sink_data[6] => src9_data[6].DATAIN -sink_data[6] => src10_data[6].DATAIN -sink_data[6] => src11_data[6].DATAIN -sink_data[6] => src12_data[6].DATAIN -sink_data[6] => src13_data[6].DATAIN -sink_data[6] => src14_data[6].DATAIN -sink_data[6] => src15_data[6].DATAIN -sink_data[6] => src16_data[6].DATAIN -sink_data[7] => src17_data[7].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[7] => src1_data[7].DATAIN -sink_data[7] => src2_data[7].DATAIN -sink_data[7] => src3_data[7].DATAIN -sink_data[7] => src4_data[7].DATAIN -sink_data[7] => src5_data[7].DATAIN -sink_data[7] => src6_data[7].DATAIN -sink_data[7] => src7_data[7].DATAIN -sink_data[7] => src8_data[7].DATAIN -sink_data[7] => src9_data[7].DATAIN -sink_data[7] => src10_data[7].DATAIN -sink_data[7] => src11_data[7].DATAIN -sink_data[7] => src12_data[7].DATAIN -sink_data[7] => src13_data[7].DATAIN -sink_data[7] => src14_data[7].DATAIN -sink_data[7] => src15_data[7].DATAIN -sink_data[7] => src16_data[7].DATAIN -sink_data[8] => src17_data[8].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[8] => src1_data[8].DATAIN -sink_data[8] => src2_data[8].DATAIN -sink_data[8] => src3_data[8].DATAIN -sink_data[8] => src4_data[8].DATAIN -sink_data[8] => src5_data[8].DATAIN -sink_data[8] => src6_data[8].DATAIN -sink_data[8] => src7_data[8].DATAIN -sink_data[8] => src8_data[8].DATAIN -sink_data[8] => src9_data[8].DATAIN -sink_data[8] => src10_data[8].DATAIN -sink_data[8] => src11_data[8].DATAIN -sink_data[8] => src12_data[8].DATAIN -sink_data[8] => src13_data[8].DATAIN -sink_data[8] => src14_data[8].DATAIN -sink_data[8] => src15_data[8].DATAIN -sink_data[8] => src16_data[8].DATAIN -sink_data[9] => src17_data[9].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[9] => src1_data[9].DATAIN -sink_data[9] => src2_data[9].DATAIN -sink_data[9] => src3_data[9].DATAIN -sink_data[9] => src4_data[9].DATAIN -sink_data[9] => src5_data[9].DATAIN -sink_data[9] => src6_data[9].DATAIN -sink_data[9] => src7_data[9].DATAIN -sink_data[9] => src8_data[9].DATAIN -sink_data[9] => src9_data[9].DATAIN -sink_data[9] => src10_data[9].DATAIN -sink_data[9] => src11_data[9].DATAIN -sink_data[9] => src12_data[9].DATAIN -sink_data[9] => src13_data[9].DATAIN -sink_data[9] => src14_data[9].DATAIN -sink_data[9] => src15_data[9].DATAIN -sink_data[9] => src16_data[9].DATAIN -sink_data[10] => src17_data[10].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[10] => src1_data[10].DATAIN -sink_data[10] => src2_data[10].DATAIN -sink_data[10] => src3_data[10].DATAIN -sink_data[10] => src4_data[10].DATAIN -sink_data[10] => src5_data[10].DATAIN -sink_data[10] => src6_data[10].DATAIN -sink_data[10] => src7_data[10].DATAIN -sink_data[10] => src8_data[10].DATAIN -sink_data[10] => src9_data[10].DATAIN -sink_data[10] => src10_data[10].DATAIN -sink_data[10] => src11_data[10].DATAIN -sink_data[10] => src12_data[10].DATAIN -sink_data[10] => src13_data[10].DATAIN -sink_data[10] => src14_data[10].DATAIN -sink_data[10] => src15_data[10].DATAIN -sink_data[10] => src16_data[10].DATAIN -sink_data[11] => src17_data[11].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[11] => src1_data[11].DATAIN -sink_data[11] => src2_data[11].DATAIN -sink_data[11] => src3_data[11].DATAIN -sink_data[11] => src4_data[11].DATAIN -sink_data[11] => src5_data[11].DATAIN -sink_data[11] => src6_data[11].DATAIN -sink_data[11] => src7_data[11].DATAIN -sink_data[11] => src8_data[11].DATAIN -sink_data[11] => src9_data[11].DATAIN -sink_data[11] => src10_data[11].DATAIN -sink_data[11] => src11_data[11].DATAIN -sink_data[11] => src12_data[11].DATAIN -sink_data[11] => src13_data[11].DATAIN -sink_data[11] => src14_data[11].DATAIN -sink_data[11] => src15_data[11].DATAIN -sink_data[11] => src16_data[11].DATAIN -sink_data[12] => src17_data[12].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[12] => src1_data[12].DATAIN -sink_data[12] => src2_data[12].DATAIN -sink_data[12] => src3_data[12].DATAIN -sink_data[12] => src4_data[12].DATAIN -sink_data[12] => src5_data[12].DATAIN -sink_data[12] => src6_data[12].DATAIN -sink_data[12] => src7_data[12].DATAIN -sink_data[12] => src8_data[12].DATAIN -sink_data[12] => src9_data[12].DATAIN -sink_data[12] => src10_data[12].DATAIN -sink_data[12] => src11_data[12].DATAIN -sink_data[12] => src12_data[12].DATAIN -sink_data[12] => src13_data[12].DATAIN -sink_data[12] => src14_data[12].DATAIN -sink_data[12] => src15_data[12].DATAIN -sink_data[12] => src16_data[12].DATAIN -sink_data[13] => src17_data[13].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[13] => src1_data[13].DATAIN -sink_data[13] => src2_data[13].DATAIN -sink_data[13] => src3_data[13].DATAIN -sink_data[13] => src4_data[13].DATAIN -sink_data[13] => src5_data[13].DATAIN -sink_data[13] => src6_data[13].DATAIN -sink_data[13] => src7_data[13].DATAIN -sink_data[13] => src8_data[13].DATAIN -sink_data[13] => src9_data[13].DATAIN -sink_data[13] => src10_data[13].DATAIN -sink_data[13] => src11_data[13].DATAIN -sink_data[13] => src12_data[13].DATAIN -sink_data[13] => src13_data[13].DATAIN -sink_data[13] => src14_data[13].DATAIN -sink_data[13] => src15_data[13].DATAIN -sink_data[13] => src16_data[13].DATAIN -sink_data[14] => src17_data[14].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[14] => src1_data[14].DATAIN -sink_data[14] => src2_data[14].DATAIN -sink_data[14] => src3_data[14].DATAIN -sink_data[14] => src4_data[14].DATAIN -sink_data[14] => src5_data[14].DATAIN -sink_data[14] => src6_data[14].DATAIN -sink_data[14] => src7_data[14].DATAIN -sink_data[14] => src8_data[14].DATAIN -sink_data[14] => src9_data[14].DATAIN -sink_data[14] => src10_data[14].DATAIN -sink_data[14] => src11_data[14].DATAIN -sink_data[14] => src12_data[14].DATAIN -sink_data[14] => src13_data[14].DATAIN -sink_data[14] => src14_data[14].DATAIN -sink_data[14] => src15_data[14].DATAIN -sink_data[14] => src16_data[14].DATAIN -sink_data[15] => src17_data[15].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[15] => src1_data[15].DATAIN -sink_data[15] => src2_data[15].DATAIN -sink_data[15] => src3_data[15].DATAIN -sink_data[15] => src4_data[15].DATAIN -sink_data[15] => src5_data[15].DATAIN -sink_data[15] => src6_data[15].DATAIN -sink_data[15] => src7_data[15].DATAIN -sink_data[15] => src8_data[15].DATAIN -sink_data[15] => src9_data[15].DATAIN -sink_data[15] => src10_data[15].DATAIN -sink_data[15] => src11_data[15].DATAIN -sink_data[15] => src12_data[15].DATAIN -sink_data[15] => src13_data[15].DATAIN -sink_data[15] => src14_data[15].DATAIN -sink_data[15] => src15_data[15].DATAIN -sink_data[15] => src16_data[15].DATAIN -sink_data[16] => src17_data[16].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[16] => src1_data[16].DATAIN -sink_data[16] => src2_data[16].DATAIN -sink_data[16] => src3_data[16].DATAIN -sink_data[16] => src4_data[16].DATAIN -sink_data[16] => src5_data[16].DATAIN -sink_data[16] => src6_data[16].DATAIN -sink_data[16] => src7_data[16].DATAIN -sink_data[16] => src8_data[16].DATAIN -sink_data[16] => src9_data[16].DATAIN -sink_data[16] => src10_data[16].DATAIN -sink_data[16] => src11_data[16].DATAIN -sink_data[16] => src12_data[16].DATAIN -sink_data[16] => src13_data[16].DATAIN -sink_data[16] => src14_data[16].DATAIN -sink_data[16] => src15_data[16].DATAIN -sink_data[16] => src16_data[16].DATAIN -sink_data[17] => src17_data[17].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[17] => src1_data[17].DATAIN -sink_data[17] => src2_data[17].DATAIN -sink_data[17] => src3_data[17].DATAIN -sink_data[17] => src4_data[17].DATAIN -sink_data[17] => src5_data[17].DATAIN -sink_data[17] => src6_data[17].DATAIN -sink_data[17] => src7_data[17].DATAIN -sink_data[17] => src8_data[17].DATAIN -sink_data[17] => src9_data[17].DATAIN -sink_data[17] => src10_data[17].DATAIN -sink_data[17] => src11_data[17].DATAIN -sink_data[17] => src12_data[17].DATAIN -sink_data[17] => src13_data[17].DATAIN -sink_data[17] => src14_data[17].DATAIN -sink_data[17] => src15_data[17].DATAIN -sink_data[17] => src16_data[17].DATAIN -sink_data[18] => src17_data[18].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[18] => src1_data[18].DATAIN -sink_data[18] => src2_data[18].DATAIN -sink_data[18] => src3_data[18].DATAIN -sink_data[18] => src4_data[18].DATAIN -sink_data[18] => src5_data[18].DATAIN -sink_data[18] => src6_data[18].DATAIN -sink_data[18] => src7_data[18].DATAIN -sink_data[18] => src8_data[18].DATAIN -sink_data[18] => src9_data[18].DATAIN -sink_data[18] => src10_data[18].DATAIN -sink_data[18] => src11_data[18].DATAIN -sink_data[18] => src12_data[18].DATAIN -sink_data[18] => src13_data[18].DATAIN -sink_data[18] => src14_data[18].DATAIN -sink_data[18] => src15_data[18].DATAIN -sink_data[18] => src16_data[18].DATAIN -sink_data[19] => src17_data[19].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[19] => src1_data[19].DATAIN -sink_data[19] => src2_data[19].DATAIN -sink_data[19] => src3_data[19].DATAIN -sink_data[19] => src4_data[19].DATAIN -sink_data[19] => src5_data[19].DATAIN -sink_data[19] => src6_data[19].DATAIN -sink_data[19] => src7_data[19].DATAIN -sink_data[19] => src8_data[19].DATAIN -sink_data[19] => src9_data[19].DATAIN -sink_data[19] => src10_data[19].DATAIN -sink_data[19] => src11_data[19].DATAIN -sink_data[19] => src12_data[19].DATAIN -sink_data[19] => src13_data[19].DATAIN -sink_data[19] => src14_data[19].DATAIN -sink_data[19] => src15_data[19].DATAIN -sink_data[19] => src16_data[19].DATAIN -sink_data[20] => src17_data[20].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[20] => src1_data[20].DATAIN -sink_data[20] => src2_data[20].DATAIN -sink_data[20] => src3_data[20].DATAIN -sink_data[20] => src4_data[20].DATAIN -sink_data[20] => src5_data[20].DATAIN -sink_data[20] => src6_data[20].DATAIN -sink_data[20] => src7_data[20].DATAIN -sink_data[20] => src8_data[20].DATAIN -sink_data[20] => src9_data[20].DATAIN -sink_data[20] => src10_data[20].DATAIN -sink_data[20] => src11_data[20].DATAIN -sink_data[20] => src12_data[20].DATAIN -sink_data[20] => src13_data[20].DATAIN -sink_data[20] => src14_data[20].DATAIN -sink_data[20] => src15_data[20].DATAIN -sink_data[20] => src16_data[20].DATAIN -sink_data[21] => src17_data[21].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[21] => src1_data[21].DATAIN -sink_data[21] => src2_data[21].DATAIN -sink_data[21] => src3_data[21].DATAIN -sink_data[21] => src4_data[21].DATAIN -sink_data[21] => src5_data[21].DATAIN -sink_data[21] => src6_data[21].DATAIN -sink_data[21] => src7_data[21].DATAIN -sink_data[21] => src8_data[21].DATAIN -sink_data[21] => src9_data[21].DATAIN -sink_data[21] => src10_data[21].DATAIN -sink_data[21] => src11_data[21].DATAIN -sink_data[21] => src12_data[21].DATAIN -sink_data[21] => src13_data[21].DATAIN -sink_data[21] => src14_data[21].DATAIN -sink_data[21] => src15_data[21].DATAIN -sink_data[21] => src16_data[21].DATAIN -sink_data[22] => src17_data[22].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[22] => src1_data[22].DATAIN -sink_data[22] => src2_data[22].DATAIN -sink_data[22] => src3_data[22].DATAIN -sink_data[22] => src4_data[22].DATAIN -sink_data[22] => src5_data[22].DATAIN -sink_data[22] => src6_data[22].DATAIN -sink_data[22] => src7_data[22].DATAIN -sink_data[22] => src8_data[22].DATAIN -sink_data[22] => src9_data[22].DATAIN -sink_data[22] => src10_data[22].DATAIN -sink_data[22] => src11_data[22].DATAIN -sink_data[22] => src12_data[22].DATAIN -sink_data[22] => src13_data[22].DATAIN -sink_data[22] => src14_data[22].DATAIN -sink_data[22] => src15_data[22].DATAIN -sink_data[22] => src16_data[22].DATAIN -sink_data[23] => src17_data[23].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[23] => src1_data[23].DATAIN -sink_data[23] => src2_data[23].DATAIN -sink_data[23] => src3_data[23].DATAIN -sink_data[23] => src4_data[23].DATAIN -sink_data[23] => src5_data[23].DATAIN -sink_data[23] => src6_data[23].DATAIN -sink_data[23] => src7_data[23].DATAIN -sink_data[23] => src8_data[23].DATAIN -sink_data[23] => src9_data[23].DATAIN -sink_data[23] => src10_data[23].DATAIN -sink_data[23] => src11_data[23].DATAIN -sink_data[23] => src12_data[23].DATAIN -sink_data[23] => src13_data[23].DATAIN -sink_data[23] => src14_data[23].DATAIN -sink_data[23] => src15_data[23].DATAIN -sink_data[23] => src16_data[23].DATAIN -sink_data[24] => src17_data[24].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[24] => src1_data[24].DATAIN -sink_data[24] => src2_data[24].DATAIN -sink_data[24] => src3_data[24].DATAIN -sink_data[24] => src4_data[24].DATAIN -sink_data[24] => src5_data[24].DATAIN -sink_data[24] => src6_data[24].DATAIN -sink_data[24] => src7_data[24].DATAIN -sink_data[24] => src8_data[24].DATAIN -sink_data[24] => src9_data[24].DATAIN -sink_data[24] => src10_data[24].DATAIN -sink_data[24] => src11_data[24].DATAIN -sink_data[24] => src12_data[24].DATAIN -sink_data[24] => src13_data[24].DATAIN -sink_data[24] => src14_data[24].DATAIN -sink_data[24] => src15_data[24].DATAIN -sink_data[24] => src16_data[24].DATAIN -sink_data[25] => src17_data[25].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[25] => src1_data[25].DATAIN -sink_data[25] => src2_data[25].DATAIN -sink_data[25] => src3_data[25].DATAIN -sink_data[25] => src4_data[25].DATAIN -sink_data[25] => src5_data[25].DATAIN -sink_data[25] => src6_data[25].DATAIN -sink_data[25] => src7_data[25].DATAIN -sink_data[25] => src8_data[25].DATAIN -sink_data[25] => src9_data[25].DATAIN -sink_data[25] => src10_data[25].DATAIN -sink_data[25] => src11_data[25].DATAIN -sink_data[25] => src12_data[25].DATAIN -sink_data[25] => src13_data[25].DATAIN -sink_data[25] => src14_data[25].DATAIN -sink_data[25] => src15_data[25].DATAIN -sink_data[25] => src16_data[25].DATAIN -sink_data[26] => src17_data[26].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[26] => src1_data[26].DATAIN -sink_data[26] => src2_data[26].DATAIN -sink_data[26] => src3_data[26].DATAIN -sink_data[26] => src4_data[26].DATAIN -sink_data[26] => src5_data[26].DATAIN -sink_data[26] => src6_data[26].DATAIN -sink_data[26] => src7_data[26].DATAIN -sink_data[26] => src8_data[26].DATAIN -sink_data[26] => src9_data[26].DATAIN -sink_data[26] => src10_data[26].DATAIN -sink_data[26] => src11_data[26].DATAIN -sink_data[26] => src12_data[26].DATAIN -sink_data[26] => src13_data[26].DATAIN -sink_data[26] => src14_data[26].DATAIN -sink_data[26] => src15_data[26].DATAIN -sink_data[26] => src16_data[26].DATAIN -sink_data[27] => src17_data[27].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[27] => src1_data[27].DATAIN -sink_data[27] => src2_data[27].DATAIN -sink_data[27] => src3_data[27].DATAIN -sink_data[27] => src4_data[27].DATAIN -sink_data[27] => src5_data[27].DATAIN -sink_data[27] => src6_data[27].DATAIN -sink_data[27] => src7_data[27].DATAIN -sink_data[27] => src8_data[27].DATAIN -sink_data[27] => src9_data[27].DATAIN -sink_data[27] => src10_data[27].DATAIN -sink_data[27] => src11_data[27].DATAIN -sink_data[27] => src12_data[27].DATAIN -sink_data[27] => src13_data[27].DATAIN -sink_data[27] => src14_data[27].DATAIN -sink_data[27] => src15_data[27].DATAIN -sink_data[27] => src16_data[27].DATAIN -sink_data[28] => src17_data[28].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[28] => src1_data[28].DATAIN -sink_data[28] => src2_data[28].DATAIN -sink_data[28] => src3_data[28].DATAIN -sink_data[28] => src4_data[28].DATAIN -sink_data[28] => src5_data[28].DATAIN -sink_data[28] => src6_data[28].DATAIN -sink_data[28] => src7_data[28].DATAIN -sink_data[28] => src8_data[28].DATAIN -sink_data[28] => src9_data[28].DATAIN -sink_data[28] => src10_data[28].DATAIN -sink_data[28] => src11_data[28].DATAIN -sink_data[28] => src12_data[28].DATAIN -sink_data[28] => src13_data[28].DATAIN -sink_data[28] => src14_data[28].DATAIN -sink_data[28] => src15_data[28].DATAIN -sink_data[28] => src16_data[28].DATAIN -sink_data[29] => src17_data[29].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[29] => src1_data[29].DATAIN -sink_data[29] => src2_data[29].DATAIN -sink_data[29] => src3_data[29].DATAIN -sink_data[29] => src4_data[29].DATAIN -sink_data[29] => src5_data[29].DATAIN -sink_data[29] => src6_data[29].DATAIN -sink_data[29] => src7_data[29].DATAIN -sink_data[29] => src8_data[29].DATAIN -sink_data[29] => src9_data[29].DATAIN -sink_data[29] => src10_data[29].DATAIN -sink_data[29] => src11_data[29].DATAIN -sink_data[29] => src12_data[29].DATAIN -sink_data[29] => src13_data[29].DATAIN -sink_data[29] => src14_data[29].DATAIN -sink_data[29] => src15_data[29].DATAIN -sink_data[29] => src16_data[29].DATAIN -sink_data[30] => src17_data[30].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[30] => src1_data[30].DATAIN -sink_data[30] => src2_data[30].DATAIN -sink_data[30] => src3_data[30].DATAIN -sink_data[30] => src4_data[30].DATAIN -sink_data[30] => src5_data[30].DATAIN -sink_data[30] => src6_data[30].DATAIN -sink_data[30] => src7_data[30].DATAIN -sink_data[30] => src8_data[30].DATAIN -sink_data[30] => src9_data[30].DATAIN -sink_data[30] => src10_data[30].DATAIN -sink_data[30] => src11_data[30].DATAIN -sink_data[30] => src12_data[30].DATAIN -sink_data[30] => src13_data[30].DATAIN -sink_data[30] => src14_data[30].DATAIN -sink_data[30] => src15_data[30].DATAIN -sink_data[30] => src16_data[30].DATAIN -sink_data[31] => src17_data[31].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[31] => src1_data[31].DATAIN -sink_data[31] => src2_data[31].DATAIN -sink_data[31] => src3_data[31].DATAIN -sink_data[31] => src4_data[31].DATAIN -sink_data[31] => src5_data[31].DATAIN -sink_data[31] => src6_data[31].DATAIN -sink_data[31] => src7_data[31].DATAIN -sink_data[31] => src8_data[31].DATAIN -sink_data[31] => src9_data[31].DATAIN -sink_data[31] => src10_data[31].DATAIN -sink_data[31] => src11_data[31].DATAIN -sink_data[31] => src12_data[31].DATAIN -sink_data[31] => src13_data[31].DATAIN -sink_data[31] => src14_data[31].DATAIN -sink_data[31] => src15_data[31].DATAIN -sink_data[31] => src16_data[31].DATAIN -sink_data[32] => src17_data[32].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[32] => src1_data[32].DATAIN -sink_data[32] => src2_data[32].DATAIN -sink_data[32] => src3_data[32].DATAIN -sink_data[32] => src4_data[32].DATAIN -sink_data[32] => src5_data[32].DATAIN -sink_data[32] => src6_data[32].DATAIN -sink_data[32] => src7_data[32].DATAIN -sink_data[32] => src8_data[32].DATAIN -sink_data[32] => src9_data[32].DATAIN -sink_data[32] => src10_data[32].DATAIN -sink_data[32] => src11_data[32].DATAIN -sink_data[32] => src12_data[32].DATAIN -sink_data[32] => src13_data[32].DATAIN -sink_data[32] => src14_data[32].DATAIN -sink_data[32] => src15_data[32].DATAIN -sink_data[32] => src16_data[32].DATAIN -sink_data[33] => src17_data[33].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[33] => src1_data[33].DATAIN -sink_data[33] => src2_data[33].DATAIN -sink_data[33] => src3_data[33].DATAIN -sink_data[33] => src4_data[33].DATAIN -sink_data[33] => src5_data[33].DATAIN -sink_data[33] => src6_data[33].DATAIN -sink_data[33] => src7_data[33].DATAIN -sink_data[33] => src8_data[33].DATAIN -sink_data[33] => src9_data[33].DATAIN -sink_data[33] => src10_data[33].DATAIN -sink_data[33] => src11_data[33].DATAIN -sink_data[33] => src12_data[33].DATAIN -sink_data[33] => src13_data[33].DATAIN -sink_data[33] => src14_data[33].DATAIN -sink_data[33] => src15_data[33].DATAIN -sink_data[33] => src16_data[33].DATAIN -sink_data[34] => src17_data[34].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[34] => src1_data[34].DATAIN -sink_data[34] => src2_data[34].DATAIN -sink_data[34] => src3_data[34].DATAIN -sink_data[34] => src4_data[34].DATAIN -sink_data[34] => src5_data[34].DATAIN -sink_data[34] => src6_data[34].DATAIN -sink_data[34] => src7_data[34].DATAIN -sink_data[34] => src8_data[34].DATAIN -sink_data[34] => src9_data[34].DATAIN -sink_data[34] => src10_data[34].DATAIN -sink_data[34] => src11_data[34].DATAIN -sink_data[34] => src12_data[34].DATAIN -sink_data[34] => src13_data[34].DATAIN -sink_data[34] => src14_data[34].DATAIN -sink_data[34] => src15_data[34].DATAIN -sink_data[34] => src16_data[34].DATAIN -sink_data[35] => src17_data[35].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[35] => src1_data[35].DATAIN -sink_data[35] => src2_data[35].DATAIN -sink_data[35] => src3_data[35].DATAIN -sink_data[35] => src4_data[35].DATAIN -sink_data[35] => src5_data[35].DATAIN -sink_data[35] => src6_data[35].DATAIN -sink_data[35] => src7_data[35].DATAIN -sink_data[35] => src8_data[35].DATAIN -sink_data[35] => src9_data[35].DATAIN -sink_data[35] => src10_data[35].DATAIN -sink_data[35] => src11_data[35].DATAIN -sink_data[35] => src12_data[35].DATAIN -sink_data[35] => src13_data[35].DATAIN -sink_data[35] => src14_data[35].DATAIN -sink_data[35] => src15_data[35].DATAIN -sink_data[35] => src16_data[35].DATAIN -sink_data[36] => src17_data[36].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[36] => src1_data[36].DATAIN -sink_data[36] => src2_data[36].DATAIN -sink_data[36] => src3_data[36].DATAIN -sink_data[36] => src4_data[36].DATAIN -sink_data[36] => src5_data[36].DATAIN -sink_data[36] => src6_data[36].DATAIN -sink_data[36] => src7_data[36].DATAIN -sink_data[36] => src8_data[36].DATAIN -sink_data[36] => src9_data[36].DATAIN -sink_data[36] => src10_data[36].DATAIN -sink_data[36] => src11_data[36].DATAIN -sink_data[36] => src12_data[36].DATAIN -sink_data[36] => src13_data[36].DATAIN -sink_data[36] => src14_data[36].DATAIN -sink_data[36] => src15_data[36].DATAIN -sink_data[36] => src16_data[36].DATAIN -sink_data[37] => src17_data[37].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[37] => src1_data[37].DATAIN -sink_data[37] => src2_data[37].DATAIN -sink_data[37] => src3_data[37].DATAIN -sink_data[37] => src4_data[37].DATAIN -sink_data[37] => src5_data[37].DATAIN -sink_data[37] => src6_data[37].DATAIN -sink_data[37] => src7_data[37].DATAIN -sink_data[37] => src8_data[37].DATAIN -sink_data[37] => src9_data[37].DATAIN -sink_data[37] => src10_data[37].DATAIN -sink_data[37] => src11_data[37].DATAIN -sink_data[37] => src12_data[37].DATAIN -sink_data[37] => src13_data[37].DATAIN -sink_data[37] => src14_data[37].DATAIN -sink_data[37] => src15_data[37].DATAIN -sink_data[37] => src16_data[37].DATAIN -sink_data[38] => src17_data[38].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[38] => src1_data[38].DATAIN -sink_data[38] => src2_data[38].DATAIN -sink_data[38] => src3_data[38].DATAIN -sink_data[38] => src4_data[38].DATAIN -sink_data[38] => src5_data[38].DATAIN -sink_data[38] => src6_data[38].DATAIN -sink_data[38] => src7_data[38].DATAIN -sink_data[38] => src8_data[38].DATAIN -sink_data[38] => src9_data[38].DATAIN -sink_data[38] => src10_data[38].DATAIN -sink_data[38] => src11_data[38].DATAIN -sink_data[38] => src12_data[38].DATAIN -sink_data[38] => src13_data[38].DATAIN -sink_data[38] => src14_data[38].DATAIN -sink_data[38] => src15_data[38].DATAIN -sink_data[38] => src16_data[38].DATAIN -sink_data[39] => src17_data[39].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[39] => src1_data[39].DATAIN -sink_data[39] => src2_data[39].DATAIN -sink_data[39] => src3_data[39].DATAIN -sink_data[39] => src4_data[39].DATAIN -sink_data[39] => src5_data[39].DATAIN -sink_data[39] => src6_data[39].DATAIN -sink_data[39] => src7_data[39].DATAIN -sink_data[39] => src8_data[39].DATAIN -sink_data[39] => src9_data[39].DATAIN -sink_data[39] => src10_data[39].DATAIN -sink_data[39] => src11_data[39].DATAIN -sink_data[39] => src12_data[39].DATAIN -sink_data[39] => src13_data[39].DATAIN -sink_data[39] => src14_data[39].DATAIN -sink_data[39] => src15_data[39].DATAIN -sink_data[39] => src16_data[39].DATAIN -sink_data[40] => src17_data[40].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[40] => src1_data[40].DATAIN -sink_data[40] => src2_data[40].DATAIN -sink_data[40] => src3_data[40].DATAIN -sink_data[40] => src4_data[40].DATAIN -sink_data[40] => src5_data[40].DATAIN -sink_data[40] => src6_data[40].DATAIN -sink_data[40] => src7_data[40].DATAIN -sink_data[40] => src8_data[40].DATAIN -sink_data[40] => src9_data[40].DATAIN -sink_data[40] => src10_data[40].DATAIN -sink_data[40] => src11_data[40].DATAIN -sink_data[40] => src12_data[40].DATAIN -sink_data[40] => src13_data[40].DATAIN -sink_data[40] => src14_data[40].DATAIN -sink_data[40] => src15_data[40].DATAIN -sink_data[40] => src16_data[40].DATAIN -sink_data[41] => src17_data[41].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[41] => src1_data[41].DATAIN -sink_data[41] => src2_data[41].DATAIN -sink_data[41] => src3_data[41].DATAIN -sink_data[41] => src4_data[41].DATAIN -sink_data[41] => src5_data[41].DATAIN -sink_data[41] => src6_data[41].DATAIN -sink_data[41] => src7_data[41].DATAIN -sink_data[41] => src8_data[41].DATAIN -sink_data[41] => src9_data[41].DATAIN -sink_data[41] => src10_data[41].DATAIN -sink_data[41] => src11_data[41].DATAIN -sink_data[41] => src12_data[41].DATAIN -sink_data[41] => src13_data[41].DATAIN -sink_data[41] => src14_data[41].DATAIN -sink_data[41] => src15_data[41].DATAIN -sink_data[41] => src16_data[41].DATAIN -sink_data[42] => src17_data[42].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[42] => src1_data[42].DATAIN -sink_data[42] => src2_data[42].DATAIN -sink_data[42] => src3_data[42].DATAIN -sink_data[42] => src4_data[42].DATAIN -sink_data[42] => src5_data[42].DATAIN -sink_data[42] => src6_data[42].DATAIN -sink_data[42] => src7_data[42].DATAIN -sink_data[42] => src8_data[42].DATAIN -sink_data[42] => src9_data[42].DATAIN -sink_data[42] => src10_data[42].DATAIN -sink_data[42] => src11_data[42].DATAIN -sink_data[42] => src12_data[42].DATAIN -sink_data[42] => src13_data[42].DATAIN -sink_data[42] => src14_data[42].DATAIN -sink_data[42] => src15_data[42].DATAIN -sink_data[42] => src16_data[42].DATAIN -sink_data[43] => src17_data[43].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[43] => src1_data[43].DATAIN -sink_data[43] => src2_data[43].DATAIN -sink_data[43] => src3_data[43].DATAIN -sink_data[43] => src4_data[43].DATAIN -sink_data[43] => src5_data[43].DATAIN -sink_data[43] => src6_data[43].DATAIN -sink_data[43] => src7_data[43].DATAIN -sink_data[43] => src8_data[43].DATAIN -sink_data[43] => src9_data[43].DATAIN -sink_data[43] => src10_data[43].DATAIN -sink_data[43] => src11_data[43].DATAIN -sink_data[43] => src12_data[43].DATAIN -sink_data[43] => src13_data[43].DATAIN -sink_data[43] => src14_data[43].DATAIN -sink_data[43] => src15_data[43].DATAIN -sink_data[43] => src16_data[43].DATAIN -sink_data[44] => src17_data[44].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[44] => src1_data[44].DATAIN -sink_data[44] => src2_data[44].DATAIN -sink_data[44] => src3_data[44].DATAIN -sink_data[44] => src4_data[44].DATAIN -sink_data[44] => src5_data[44].DATAIN -sink_data[44] => src6_data[44].DATAIN -sink_data[44] => src7_data[44].DATAIN -sink_data[44] => src8_data[44].DATAIN -sink_data[44] => src9_data[44].DATAIN -sink_data[44] => src10_data[44].DATAIN -sink_data[44] => src11_data[44].DATAIN -sink_data[44] => src12_data[44].DATAIN -sink_data[44] => src13_data[44].DATAIN -sink_data[44] => src14_data[44].DATAIN -sink_data[44] => src15_data[44].DATAIN -sink_data[44] => src16_data[44].DATAIN -sink_data[45] => src17_data[45].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[45] => src1_data[45].DATAIN -sink_data[45] => src2_data[45].DATAIN -sink_data[45] => src3_data[45].DATAIN -sink_data[45] => src4_data[45].DATAIN -sink_data[45] => src5_data[45].DATAIN -sink_data[45] => src6_data[45].DATAIN -sink_data[45] => src7_data[45].DATAIN -sink_data[45] => src8_data[45].DATAIN -sink_data[45] => src9_data[45].DATAIN -sink_data[45] => src10_data[45].DATAIN -sink_data[45] => src11_data[45].DATAIN -sink_data[45] => src12_data[45].DATAIN -sink_data[45] => src13_data[45].DATAIN -sink_data[45] => src14_data[45].DATAIN -sink_data[45] => src15_data[45].DATAIN -sink_data[45] => src16_data[45].DATAIN -sink_data[46] => src17_data[46].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[46] => src1_data[46].DATAIN -sink_data[46] => src2_data[46].DATAIN -sink_data[46] => src3_data[46].DATAIN -sink_data[46] => src4_data[46].DATAIN -sink_data[46] => src5_data[46].DATAIN -sink_data[46] => src6_data[46].DATAIN -sink_data[46] => src7_data[46].DATAIN -sink_data[46] => src8_data[46].DATAIN -sink_data[46] => src9_data[46].DATAIN -sink_data[46] => src10_data[46].DATAIN -sink_data[46] => src11_data[46].DATAIN -sink_data[46] => src12_data[46].DATAIN -sink_data[46] => src13_data[46].DATAIN -sink_data[46] => src14_data[46].DATAIN -sink_data[46] => src15_data[46].DATAIN -sink_data[46] => src16_data[46].DATAIN -sink_data[47] => src17_data[47].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[47] => src1_data[47].DATAIN -sink_data[47] => src2_data[47].DATAIN -sink_data[47] => src3_data[47].DATAIN -sink_data[47] => src4_data[47].DATAIN -sink_data[47] => src5_data[47].DATAIN -sink_data[47] => src6_data[47].DATAIN -sink_data[47] => src7_data[47].DATAIN -sink_data[47] => src8_data[47].DATAIN -sink_data[47] => src9_data[47].DATAIN -sink_data[47] => src10_data[47].DATAIN -sink_data[47] => src11_data[47].DATAIN -sink_data[47] => src12_data[47].DATAIN -sink_data[47] => src13_data[47].DATAIN -sink_data[47] => src14_data[47].DATAIN -sink_data[47] => src15_data[47].DATAIN -sink_data[47] => src16_data[47].DATAIN -sink_data[48] => src17_data[48].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[48] => src1_data[48].DATAIN -sink_data[48] => src2_data[48].DATAIN -sink_data[48] => src3_data[48].DATAIN -sink_data[48] => src4_data[48].DATAIN -sink_data[48] => src5_data[48].DATAIN -sink_data[48] => src6_data[48].DATAIN -sink_data[48] => src7_data[48].DATAIN -sink_data[48] => src8_data[48].DATAIN -sink_data[48] => src9_data[48].DATAIN -sink_data[48] => src10_data[48].DATAIN -sink_data[48] => src11_data[48].DATAIN -sink_data[48] => src12_data[48].DATAIN -sink_data[48] => src13_data[48].DATAIN -sink_data[48] => src14_data[48].DATAIN -sink_data[48] => src15_data[48].DATAIN -sink_data[48] => src16_data[48].DATAIN -sink_data[49] => src17_data[49].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[49] => src1_data[49].DATAIN -sink_data[49] => src2_data[49].DATAIN -sink_data[49] => src3_data[49].DATAIN -sink_data[49] => src4_data[49].DATAIN -sink_data[49] => src5_data[49].DATAIN -sink_data[49] => src6_data[49].DATAIN -sink_data[49] => src7_data[49].DATAIN -sink_data[49] => src8_data[49].DATAIN -sink_data[49] => src9_data[49].DATAIN -sink_data[49] => src10_data[49].DATAIN -sink_data[49] => src11_data[49].DATAIN -sink_data[49] => src12_data[49].DATAIN -sink_data[49] => src13_data[49].DATAIN -sink_data[49] => src14_data[49].DATAIN -sink_data[49] => src15_data[49].DATAIN -sink_data[49] => src16_data[49].DATAIN -sink_data[50] => src17_data[50].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[50] => src1_data[50].DATAIN -sink_data[50] => src2_data[50].DATAIN -sink_data[50] => src3_data[50].DATAIN -sink_data[50] => src4_data[50].DATAIN -sink_data[50] => src5_data[50].DATAIN -sink_data[50] => src6_data[50].DATAIN -sink_data[50] => src7_data[50].DATAIN -sink_data[50] => src8_data[50].DATAIN -sink_data[50] => src9_data[50].DATAIN -sink_data[50] => src10_data[50].DATAIN -sink_data[50] => src11_data[50].DATAIN -sink_data[50] => src12_data[50].DATAIN -sink_data[50] => src13_data[50].DATAIN -sink_data[50] => src14_data[50].DATAIN -sink_data[50] => src15_data[50].DATAIN -sink_data[50] => src16_data[50].DATAIN -sink_data[51] => src17_data[51].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[51] => src1_data[51].DATAIN -sink_data[51] => src2_data[51].DATAIN -sink_data[51] => src3_data[51].DATAIN -sink_data[51] => src4_data[51].DATAIN -sink_data[51] => src5_data[51].DATAIN -sink_data[51] => src6_data[51].DATAIN -sink_data[51] => src7_data[51].DATAIN -sink_data[51] => src8_data[51].DATAIN -sink_data[51] => src9_data[51].DATAIN -sink_data[51] => src10_data[51].DATAIN -sink_data[51] => src11_data[51].DATAIN -sink_data[51] => src12_data[51].DATAIN -sink_data[51] => src13_data[51].DATAIN -sink_data[51] => src14_data[51].DATAIN -sink_data[51] => src15_data[51].DATAIN -sink_data[51] => src16_data[51].DATAIN -sink_data[52] => src17_data[52].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[52] => src1_data[52].DATAIN -sink_data[52] => src2_data[52].DATAIN -sink_data[52] => src3_data[52].DATAIN -sink_data[52] => src4_data[52].DATAIN -sink_data[52] => src5_data[52].DATAIN -sink_data[52] => src6_data[52].DATAIN -sink_data[52] => src7_data[52].DATAIN -sink_data[52] => src8_data[52].DATAIN -sink_data[52] => src9_data[52].DATAIN -sink_data[52] => src10_data[52].DATAIN -sink_data[52] => src11_data[52].DATAIN -sink_data[52] => src12_data[52].DATAIN -sink_data[52] => src13_data[52].DATAIN -sink_data[52] => src14_data[52].DATAIN -sink_data[52] => src15_data[52].DATAIN -sink_data[52] => src16_data[52].DATAIN -sink_data[53] => src17_data[53].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[53] => src1_data[53].DATAIN -sink_data[53] => src2_data[53].DATAIN -sink_data[53] => src3_data[53].DATAIN -sink_data[53] => src4_data[53].DATAIN -sink_data[53] => src5_data[53].DATAIN -sink_data[53] => src6_data[53].DATAIN -sink_data[53] => src7_data[53].DATAIN -sink_data[53] => src8_data[53].DATAIN -sink_data[53] => src9_data[53].DATAIN -sink_data[53] => src10_data[53].DATAIN -sink_data[53] => src11_data[53].DATAIN -sink_data[53] => src12_data[53].DATAIN -sink_data[53] => src13_data[53].DATAIN -sink_data[53] => src14_data[53].DATAIN -sink_data[53] => src15_data[53].DATAIN -sink_data[53] => src16_data[53].DATAIN -sink_data[54] => src17_data[54].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[54] => src1_data[54].DATAIN -sink_data[54] => src2_data[54].DATAIN -sink_data[54] => src3_data[54].DATAIN -sink_data[54] => src4_data[54].DATAIN -sink_data[54] => src5_data[54].DATAIN -sink_data[54] => src6_data[54].DATAIN -sink_data[54] => src7_data[54].DATAIN -sink_data[54] => src8_data[54].DATAIN -sink_data[54] => src9_data[54].DATAIN -sink_data[54] => src10_data[54].DATAIN -sink_data[54] => src11_data[54].DATAIN -sink_data[54] => src12_data[54].DATAIN -sink_data[54] => src13_data[54].DATAIN -sink_data[54] => src14_data[54].DATAIN -sink_data[54] => src15_data[54].DATAIN -sink_data[54] => src16_data[54].DATAIN -sink_data[55] => src17_data[55].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[55] => src1_data[55].DATAIN -sink_data[55] => src2_data[55].DATAIN -sink_data[55] => src3_data[55].DATAIN -sink_data[55] => src4_data[55].DATAIN -sink_data[55] => src5_data[55].DATAIN -sink_data[55] => src6_data[55].DATAIN -sink_data[55] => src7_data[55].DATAIN -sink_data[55] => src8_data[55].DATAIN -sink_data[55] => src9_data[55].DATAIN -sink_data[55] => src10_data[55].DATAIN -sink_data[55] => src11_data[55].DATAIN -sink_data[55] => src12_data[55].DATAIN -sink_data[55] => src13_data[55].DATAIN -sink_data[55] => src14_data[55].DATAIN -sink_data[55] => src15_data[55].DATAIN -sink_data[55] => src16_data[55].DATAIN -sink_data[56] => src17_data[56].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[56] => src1_data[56].DATAIN -sink_data[56] => src2_data[56].DATAIN -sink_data[56] => src3_data[56].DATAIN -sink_data[56] => src4_data[56].DATAIN -sink_data[56] => src5_data[56].DATAIN -sink_data[56] => src6_data[56].DATAIN -sink_data[56] => src7_data[56].DATAIN -sink_data[56] => src8_data[56].DATAIN -sink_data[56] => src9_data[56].DATAIN -sink_data[56] => src10_data[56].DATAIN -sink_data[56] => src11_data[56].DATAIN -sink_data[56] => src12_data[56].DATAIN -sink_data[56] => src13_data[56].DATAIN -sink_data[56] => src14_data[56].DATAIN -sink_data[56] => src15_data[56].DATAIN -sink_data[56] => src16_data[56].DATAIN -sink_data[57] => src17_data[57].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[57] => src1_data[57].DATAIN -sink_data[57] => src2_data[57].DATAIN -sink_data[57] => src3_data[57].DATAIN -sink_data[57] => src4_data[57].DATAIN -sink_data[57] => src5_data[57].DATAIN -sink_data[57] => src6_data[57].DATAIN -sink_data[57] => src7_data[57].DATAIN -sink_data[57] => src8_data[57].DATAIN -sink_data[57] => src9_data[57].DATAIN -sink_data[57] => src10_data[57].DATAIN -sink_data[57] => src11_data[57].DATAIN -sink_data[57] => src12_data[57].DATAIN -sink_data[57] => src13_data[57].DATAIN -sink_data[57] => src14_data[57].DATAIN -sink_data[57] => src15_data[57].DATAIN -sink_data[57] => src16_data[57].DATAIN -sink_data[58] => src17_data[58].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[58] => src1_data[58].DATAIN -sink_data[58] => src2_data[58].DATAIN -sink_data[58] => src3_data[58].DATAIN -sink_data[58] => src4_data[58].DATAIN -sink_data[58] => src5_data[58].DATAIN -sink_data[58] => src6_data[58].DATAIN -sink_data[58] => src7_data[58].DATAIN -sink_data[58] => src8_data[58].DATAIN -sink_data[58] => src9_data[58].DATAIN -sink_data[58] => src10_data[58].DATAIN -sink_data[58] => src11_data[58].DATAIN -sink_data[58] => src12_data[58].DATAIN -sink_data[58] => src13_data[58].DATAIN -sink_data[58] => src14_data[58].DATAIN -sink_data[58] => src15_data[58].DATAIN -sink_data[58] => src16_data[58].DATAIN -sink_data[59] => src17_data[59].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[59] => src1_data[59].DATAIN -sink_data[59] => src2_data[59].DATAIN -sink_data[59] => src3_data[59].DATAIN -sink_data[59] => src4_data[59].DATAIN -sink_data[59] => src5_data[59].DATAIN -sink_data[59] => src6_data[59].DATAIN -sink_data[59] => src7_data[59].DATAIN -sink_data[59] => src8_data[59].DATAIN -sink_data[59] => src9_data[59].DATAIN -sink_data[59] => src10_data[59].DATAIN -sink_data[59] => src11_data[59].DATAIN -sink_data[59] => src12_data[59].DATAIN -sink_data[59] => src13_data[59].DATAIN -sink_data[59] => src14_data[59].DATAIN -sink_data[59] => src15_data[59].DATAIN -sink_data[59] => src16_data[59].DATAIN -sink_data[60] => src17_data[60].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[60] => src1_data[60].DATAIN -sink_data[60] => src2_data[60].DATAIN -sink_data[60] => src3_data[60].DATAIN -sink_data[60] => src4_data[60].DATAIN -sink_data[60] => src5_data[60].DATAIN -sink_data[60] => src6_data[60].DATAIN -sink_data[60] => src7_data[60].DATAIN -sink_data[60] => src8_data[60].DATAIN -sink_data[60] => src9_data[60].DATAIN -sink_data[60] => src10_data[60].DATAIN -sink_data[60] => src11_data[60].DATAIN -sink_data[60] => src12_data[60].DATAIN -sink_data[60] => src13_data[60].DATAIN -sink_data[60] => src14_data[60].DATAIN -sink_data[60] => src15_data[60].DATAIN -sink_data[60] => src16_data[60].DATAIN -sink_data[61] => src17_data[61].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[61] => src1_data[61].DATAIN -sink_data[61] => src2_data[61].DATAIN -sink_data[61] => src3_data[61].DATAIN -sink_data[61] => src4_data[61].DATAIN -sink_data[61] => src5_data[61].DATAIN -sink_data[61] => src6_data[61].DATAIN -sink_data[61] => src7_data[61].DATAIN -sink_data[61] => src8_data[61].DATAIN -sink_data[61] => src9_data[61].DATAIN -sink_data[61] => src10_data[61].DATAIN -sink_data[61] => src11_data[61].DATAIN -sink_data[61] => src12_data[61].DATAIN -sink_data[61] => src13_data[61].DATAIN -sink_data[61] => src14_data[61].DATAIN -sink_data[61] => src15_data[61].DATAIN -sink_data[61] => src16_data[61].DATAIN -sink_data[62] => src17_data[62].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[62] => src1_data[62].DATAIN -sink_data[62] => src2_data[62].DATAIN -sink_data[62] => src3_data[62].DATAIN -sink_data[62] => src4_data[62].DATAIN -sink_data[62] => src5_data[62].DATAIN -sink_data[62] => src6_data[62].DATAIN -sink_data[62] => src7_data[62].DATAIN -sink_data[62] => src8_data[62].DATAIN -sink_data[62] => src9_data[62].DATAIN -sink_data[62] => src10_data[62].DATAIN -sink_data[62] => src11_data[62].DATAIN -sink_data[62] => src12_data[62].DATAIN -sink_data[62] => src13_data[62].DATAIN -sink_data[62] => src14_data[62].DATAIN -sink_data[62] => src15_data[62].DATAIN -sink_data[62] => src16_data[62].DATAIN -sink_data[63] => src17_data[63].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[63] => src1_data[63].DATAIN -sink_data[63] => src2_data[63].DATAIN -sink_data[63] => src3_data[63].DATAIN -sink_data[63] => src4_data[63].DATAIN -sink_data[63] => src5_data[63].DATAIN -sink_data[63] => src6_data[63].DATAIN -sink_data[63] => src7_data[63].DATAIN -sink_data[63] => src8_data[63].DATAIN -sink_data[63] => src9_data[63].DATAIN -sink_data[63] => src10_data[63].DATAIN -sink_data[63] => src11_data[63].DATAIN -sink_data[63] => src12_data[63].DATAIN -sink_data[63] => src13_data[63].DATAIN -sink_data[63] => src14_data[63].DATAIN -sink_data[63] => src15_data[63].DATAIN -sink_data[63] => src16_data[63].DATAIN -sink_data[64] => src17_data[64].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[64] => src1_data[64].DATAIN -sink_data[64] => src2_data[64].DATAIN -sink_data[64] => src3_data[64].DATAIN -sink_data[64] => src4_data[64].DATAIN -sink_data[64] => src5_data[64].DATAIN -sink_data[64] => src6_data[64].DATAIN -sink_data[64] => src7_data[64].DATAIN -sink_data[64] => src8_data[64].DATAIN -sink_data[64] => src9_data[64].DATAIN -sink_data[64] => src10_data[64].DATAIN -sink_data[64] => src11_data[64].DATAIN -sink_data[64] => src12_data[64].DATAIN -sink_data[64] => src13_data[64].DATAIN -sink_data[64] => src14_data[64].DATAIN -sink_data[64] => src15_data[64].DATAIN -sink_data[64] => src16_data[64].DATAIN -sink_data[65] => src17_data[65].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[65] => src1_data[65].DATAIN -sink_data[65] => src2_data[65].DATAIN -sink_data[65] => src3_data[65].DATAIN -sink_data[65] => src4_data[65].DATAIN -sink_data[65] => src5_data[65].DATAIN -sink_data[65] => src6_data[65].DATAIN -sink_data[65] => src7_data[65].DATAIN -sink_data[65] => src8_data[65].DATAIN -sink_data[65] => src9_data[65].DATAIN -sink_data[65] => src10_data[65].DATAIN -sink_data[65] => src11_data[65].DATAIN -sink_data[65] => src12_data[65].DATAIN -sink_data[65] => src13_data[65].DATAIN -sink_data[65] => src14_data[65].DATAIN -sink_data[65] => src15_data[65].DATAIN -sink_data[65] => src16_data[65].DATAIN -sink_data[66] => src17_data[66].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[66] => src1_data[66].DATAIN -sink_data[66] => src2_data[66].DATAIN -sink_data[66] => src3_data[66].DATAIN -sink_data[66] => src4_data[66].DATAIN -sink_data[66] => src5_data[66].DATAIN -sink_data[66] => src6_data[66].DATAIN -sink_data[66] => src7_data[66].DATAIN -sink_data[66] => src8_data[66].DATAIN -sink_data[66] => src9_data[66].DATAIN -sink_data[66] => src10_data[66].DATAIN -sink_data[66] => src11_data[66].DATAIN -sink_data[66] => src12_data[66].DATAIN -sink_data[66] => src13_data[66].DATAIN -sink_data[66] => src14_data[66].DATAIN -sink_data[66] => src15_data[66].DATAIN -sink_data[66] => src16_data[66].DATAIN -sink_data[67] => src17_data[67].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[67] => src1_data[67].DATAIN -sink_data[67] => src2_data[67].DATAIN -sink_data[67] => src3_data[67].DATAIN -sink_data[67] => src4_data[67].DATAIN -sink_data[67] => src5_data[67].DATAIN -sink_data[67] => src6_data[67].DATAIN -sink_data[67] => src7_data[67].DATAIN -sink_data[67] => src8_data[67].DATAIN -sink_data[67] => src9_data[67].DATAIN -sink_data[67] => src10_data[67].DATAIN -sink_data[67] => src11_data[67].DATAIN -sink_data[67] => src12_data[67].DATAIN -sink_data[67] => src13_data[67].DATAIN -sink_data[67] => src14_data[67].DATAIN -sink_data[67] => src15_data[67].DATAIN -sink_data[67] => src16_data[67].DATAIN -sink_data[68] => src17_data[68].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[68] => src1_data[68].DATAIN -sink_data[68] => src2_data[68].DATAIN -sink_data[68] => src3_data[68].DATAIN -sink_data[68] => src4_data[68].DATAIN -sink_data[68] => src5_data[68].DATAIN -sink_data[68] => src6_data[68].DATAIN -sink_data[68] => src7_data[68].DATAIN -sink_data[68] => src8_data[68].DATAIN -sink_data[68] => src9_data[68].DATAIN -sink_data[68] => src10_data[68].DATAIN -sink_data[68] => src11_data[68].DATAIN -sink_data[68] => src12_data[68].DATAIN -sink_data[68] => src13_data[68].DATAIN -sink_data[68] => src14_data[68].DATAIN -sink_data[68] => src15_data[68].DATAIN -sink_data[68] => src16_data[68].DATAIN -sink_data[69] => src17_data[69].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[69] => src1_data[69].DATAIN -sink_data[69] => src2_data[69].DATAIN -sink_data[69] => src3_data[69].DATAIN -sink_data[69] => src4_data[69].DATAIN -sink_data[69] => src5_data[69].DATAIN -sink_data[69] => src6_data[69].DATAIN -sink_data[69] => src7_data[69].DATAIN -sink_data[69] => src8_data[69].DATAIN -sink_data[69] => src9_data[69].DATAIN -sink_data[69] => src10_data[69].DATAIN -sink_data[69] => src11_data[69].DATAIN -sink_data[69] => src12_data[69].DATAIN -sink_data[69] => src13_data[69].DATAIN -sink_data[69] => src14_data[69].DATAIN -sink_data[69] => src15_data[69].DATAIN -sink_data[69] => src16_data[69].DATAIN -sink_data[70] => src17_data[70].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[70] => src1_data[70].DATAIN -sink_data[70] => src2_data[70].DATAIN -sink_data[70] => src3_data[70].DATAIN -sink_data[70] => src4_data[70].DATAIN -sink_data[70] => src5_data[70].DATAIN -sink_data[70] => src6_data[70].DATAIN -sink_data[70] => src7_data[70].DATAIN -sink_data[70] => src8_data[70].DATAIN -sink_data[70] => src9_data[70].DATAIN -sink_data[70] => src10_data[70].DATAIN -sink_data[70] => src11_data[70].DATAIN -sink_data[70] => src12_data[70].DATAIN -sink_data[70] => src13_data[70].DATAIN -sink_data[70] => src14_data[70].DATAIN -sink_data[70] => src15_data[70].DATAIN -sink_data[70] => src16_data[70].DATAIN -sink_data[71] => src17_data[71].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[71] => src1_data[71].DATAIN -sink_data[71] => src2_data[71].DATAIN -sink_data[71] => src3_data[71].DATAIN -sink_data[71] => src4_data[71].DATAIN -sink_data[71] => src5_data[71].DATAIN -sink_data[71] => src6_data[71].DATAIN -sink_data[71] => src7_data[71].DATAIN -sink_data[71] => src8_data[71].DATAIN -sink_data[71] => src9_data[71].DATAIN -sink_data[71] => src10_data[71].DATAIN -sink_data[71] => src11_data[71].DATAIN -sink_data[71] => src12_data[71].DATAIN -sink_data[71] => src13_data[71].DATAIN -sink_data[71] => src14_data[71].DATAIN -sink_data[71] => src15_data[71].DATAIN -sink_data[71] => src16_data[71].DATAIN -sink_data[72] => src17_data[72].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[72] => src1_data[72].DATAIN -sink_data[72] => src2_data[72].DATAIN -sink_data[72] => src3_data[72].DATAIN -sink_data[72] => src4_data[72].DATAIN -sink_data[72] => src5_data[72].DATAIN -sink_data[72] => src6_data[72].DATAIN -sink_data[72] => src7_data[72].DATAIN -sink_data[72] => src8_data[72].DATAIN -sink_data[72] => src9_data[72].DATAIN -sink_data[72] => src10_data[72].DATAIN -sink_data[72] => src11_data[72].DATAIN -sink_data[72] => src12_data[72].DATAIN -sink_data[72] => src13_data[72].DATAIN -sink_data[72] => src14_data[72].DATAIN -sink_data[72] => src15_data[72].DATAIN -sink_data[72] => src16_data[72].DATAIN -sink_data[73] => src17_data[73].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[73] => src1_data[73].DATAIN -sink_data[73] => src2_data[73].DATAIN -sink_data[73] => src3_data[73].DATAIN -sink_data[73] => src4_data[73].DATAIN -sink_data[73] => src5_data[73].DATAIN -sink_data[73] => src6_data[73].DATAIN -sink_data[73] => src7_data[73].DATAIN -sink_data[73] => src8_data[73].DATAIN -sink_data[73] => src9_data[73].DATAIN -sink_data[73] => src10_data[73].DATAIN -sink_data[73] => src11_data[73].DATAIN -sink_data[73] => src12_data[73].DATAIN -sink_data[73] => src13_data[73].DATAIN -sink_data[73] => src14_data[73].DATAIN -sink_data[73] => src15_data[73].DATAIN -sink_data[73] => src16_data[73].DATAIN -sink_data[74] => src17_data[74].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[74] => src1_data[74].DATAIN -sink_data[74] => src2_data[74].DATAIN -sink_data[74] => src3_data[74].DATAIN -sink_data[74] => src4_data[74].DATAIN -sink_data[74] => src5_data[74].DATAIN -sink_data[74] => src6_data[74].DATAIN -sink_data[74] => src7_data[74].DATAIN -sink_data[74] => src8_data[74].DATAIN -sink_data[74] => src9_data[74].DATAIN -sink_data[74] => src10_data[74].DATAIN -sink_data[74] => src11_data[74].DATAIN -sink_data[74] => src12_data[74].DATAIN -sink_data[74] => src13_data[74].DATAIN -sink_data[74] => src14_data[74].DATAIN -sink_data[74] => src15_data[74].DATAIN -sink_data[74] => src16_data[74].DATAIN -sink_data[75] => src17_data[75].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[75] => src1_data[75].DATAIN -sink_data[75] => src2_data[75].DATAIN -sink_data[75] => src3_data[75].DATAIN -sink_data[75] => src4_data[75].DATAIN -sink_data[75] => src5_data[75].DATAIN -sink_data[75] => src6_data[75].DATAIN -sink_data[75] => src7_data[75].DATAIN -sink_data[75] => src8_data[75].DATAIN -sink_data[75] => src9_data[75].DATAIN -sink_data[75] => src10_data[75].DATAIN -sink_data[75] => src11_data[75].DATAIN -sink_data[75] => src12_data[75].DATAIN -sink_data[75] => src13_data[75].DATAIN -sink_data[75] => src14_data[75].DATAIN -sink_data[75] => src15_data[75].DATAIN -sink_data[75] => src16_data[75].DATAIN -sink_data[76] => src17_data[76].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[76] => src1_data[76].DATAIN -sink_data[76] => src2_data[76].DATAIN -sink_data[76] => src3_data[76].DATAIN -sink_data[76] => src4_data[76].DATAIN -sink_data[76] => src5_data[76].DATAIN -sink_data[76] => src6_data[76].DATAIN -sink_data[76] => src7_data[76].DATAIN -sink_data[76] => src8_data[76].DATAIN -sink_data[76] => src9_data[76].DATAIN -sink_data[76] => src10_data[76].DATAIN -sink_data[76] => src11_data[76].DATAIN -sink_data[76] => src12_data[76].DATAIN -sink_data[76] => src13_data[76].DATAIN -sink_data[76] => src14_data[76].DATAIN -sink_data[76] => src15_data[76].DATAIN -sink_data[76] => src16_data[76].DATAIN -sink_data[77] => src17_data[77].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[77] => src1_data[77].DATAIN -sink_data[77] => src2_data[77].DATAIN -sink_data[77] => src3_data[77].DATAIN -sink_data[77] => src4_data[77].DATAIN -sink_data[77] => src5_data[77].DATAIN -sink_data[77] => src6_data[77].DATAIN -sink_data[77] => src7_data[77].DATAIN -sink_data[77] => src8_data[77].DATAIN -sink_data[77] => src9_data[77].DATAIN -sink_data[77] => src10_data[77].DATAIN -sink_data[77] => src11_data[77].DATAIN -sink_data[77] => src12_data[77].DATAIN -sink_data[77] => src13_data[77].DATAIN -sink_data[77] => src14_data[77].DATAIN -sink_data[77] => src15_data[77].DATAIN -sink_data[77] => src16_data[77].DATAIN -sink_data[78] => src17_data[78].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[78] => src1_data[78].DATAIN -sink_data[78] => src2_data[78].DATAIN -sink_data[78] => src3_data[78].DATAIN -sink_data[78] => src4_data[78].DATAIN -sink_data[78] => src5_data[78].DATAIN -sink_data[78] => src6_data[78].DATAIN -sink_data[78] => src7_data[78].DATAIN -sink_data[78] => src8_data[78].DATAIN -sink_data[78] => src9_data[78].DATAIN -sink_data[78] => src10_data[78].DATAIN -sink_data[78] => src11_data[78].DATAIN -sink_data[78] => src12_data[78].DATAIN -sink_data[78] => src13_data[78].DATAIN -sink_data[78] => src14_data[78].DATAIN -sink_data[78] => src15_data[78].DATAIN -sink_data[78] => src16_data[78].DATAIN -sink_data[79] => src17_data[79].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[79] => src1_data[79].DATAIN -sink_data[79] => src2_data[79].DATAIN -sink_data[79] => src3_data[79].DATAIN -sink_data[79] => src4_data[79].DATAIN -sink_data[79] => src5_data[79].DATAIN -sink_data[79] => src6_data[79].DATAIN -sink_data[79] => src7_data[79].DATAIN -sink_data[79] => src8_data[79].DATAIN -sink_data[79] => src9_data[79].DATAIN -sink_data[79] => src10_data[79].DATAIN -sink_data[79] => src11_data[79].DATAIN -sink_data[79] => src12_data[79].DATAIN -sink_data[79] => src13_data[79].DATAIN -sink_data[79] => src14_data[79].DATAIN -sink_data[79] => src15_data[79].DATAIN -sink_data[79] => src16_data[79].DATAIN -sink_data[80] => src17_data[80].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[80] => src1_data[80].DATAIN -sink_data[80] => src2_data[80].DATAIN -sink_data[80] => src3_data[80].DATAIN -sink_data[80] => src4_data[80].DATAIN -sink_data[80] => src5_data[80].DATAIN -sink_data[80] => src6_data[80].DATAIN -sink_data[80] => src7_data[80].DATAIN -sink_data[80] => src8_data[80].DATAIN -sink_data[80] => src9_data[80].DATAIN -sink_data[80] => src10_data[80].DATAIN -sink_data[80] => src11_data[80].DATAIN -sink_data[80] => src12_data[80].DATAIN -sink_data[80] => src13_data[80].DATAIN -sink_data[80] => src14_data[80].DATAIN -sink_data[80] => src15_data[80].DATAIN -sink_data[80] => src16_data[80].DATAIN -sink_data[81] => src17_data[81].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[81] => src1_data[81].DATAIN -sink_data[81] => src2_data[81].DATAIN -sink_data[81] => src3_data[81].DATAIN -sink_data[81] => src4_data[81].DATAIN -sink_data[81] => src5_data[81].DATAIN -sink_data[81] => src6_data[81].DATAIN -sink_data[81] => src7_data[81].DATAIN -sink_data[81] => src8_data[81].DATAIN -sink_data[81] => src9_data[81].DATAIN -sink_data[81] => src10_data[81].DATAIN -sink_data[81] => src11_data[81].DATAIN -sink_data[81] => src12_data[81].DATAIN -sink_data[81] => src13_data[81].DATAIN -sink_data[81] => src14_data[81].DATAIN -sink_data[81] => src15_data[81].DATAIN -sink_data[81] => src16_data[81].DATAIN -sink_data[82] => src17_data[82].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[82] => src1_data[82].DATAIN -sink_data[82] => src2_data[82].DATAIN -sink_data[82] => src3_data[82].DATAIN -sink_data[82] => src4_data[82].DATAIN -sink_data[82] => src5_data[82].DATAIN -sink_data[82] => src6_data[82].DATAIN -sink_data[82] => src7_data[82].DATAIN -sink_data[82] => src8_data[82].DATAIN -sink_data[82] => src9_data[82].DATAIN -sink_data[82] => src10_data[82].DATAIN -sink_data[82] => src11_data[82].DATAIN -sink_data[82] => src12_data[82].DATAIN -sink_data[82] => src13_data[82].DATAIN -sink_data[82] => src14_data[82].DATAIN -sink_data[82] => src15_data[82].DATAIN -sink_data[82] => src16_data[82].DATAIN -sink_data[83] => src17_data[83].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[83] => src1_data[83].DATAIN -sink_data[83] => src2_data[83].DATAIN -sink_data[83] => src3_data[83].DATAIN -sink_data[83] => src4_data[83].DATAIN -sink_data[83] => src5_data[83].DATAIN -sink_data[83] => src6_data[83].DATAIN -sink_data[83] => src7_data[83].DATAIN -sink_data[83] => src8_data[83].DATAIN -sink_data[83] => src9_data[83].DATAIN -sink_data[83] => src10_data[83].DATAIN -sink_data[83] => src11_data[83].DATAIN -sink_data[83] => src12_data[83].DATAIN -sink_data[83] => src13_data[83].DATAIN -sink_data[83] => src14_data[83].DATAIN -sink_data[83] => src15_data[83].DATAIN -sink_data[83] => src16_data[83].DATAIN -sink_data[84] => src17_data[84].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[84] => src1_data[84].DATAIN -sink_data[84] => src2_data[84].DATAIN -sink_data[84] => src3_data[84].DATAIN -sink_data[84] => src4_data[84].DATAIN -sink_data[84] => src5_data[84].DATAIN -sink_data[84] => src6_data[84].DATAIN -sink_data[84] => src7_data[84].DATAIN -sink_data[84] => src8_data[84].DATAIN -sink_data[84] => src9_data[84].DATAIN -sink_data[84] => src10_data[84].DATAIN -sink_data[84] => src11_data[84].DATAIN -sink_data[84] => src12_data[84].DATAIN -sink_data[84] => src13_data[84].DATAIN -sink_data[84] => src14_data[84].DATAIN -sink_data[84] => src15_data[84].DATAIN -sink_data[84] => src16_data[84].DATAIN -sink_data[85] => src17_data[85].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[85] => src1_data[85].DATAIN -sink_data[85] => src2_data[85].DATAIN -sink_data[85] => src3_data[85].DATAIN -sink_data[85] => src4_data[85].DATAIN -sink_data[85] => src5_data[85].DATAIN -sink_data[85] => src6_data[85].DATAIN -sink_data[85] => src7_data[85].DATAIN -sink_data[85] => src8_data[85].DATAIN -sink_data[85] => src9_data[85].DATAIN -sink_data[85] => src10_data[85].DATAIN -sink_data[85] => src11_data[85].DATAIN -sink_data[85] => src12_data[85].DATAIN -sink_data[85] => src13_data[85].DATAIN -sink_data[85] => src14_data[85].DATAIN -sink_data[85] => src15_data[85].DATAIN -sink_data[85] => src16_data[85].DATAIN -sink_data[86] => src17_data[86].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[86] => src1_data[86].DATAIN -sink_data[86] => src2_data[86].DATAIN -sink_data[86] => src3_data[86].DATAIN -sink_data[86] => src4_data[86].DATAIN -sink_data[86] => src5_data[86].DATAIN -sink_data[86] => src6_data[86].DATAIN -sink_data[86] => src7_data[86].DATAIN -sink_data[86] => src8_data[86].DATAIN -sink_data[86] => src9_data[86].DATAIN -sink_data[86] => src10_data[86].DATAIN -sink_data[86] => src11_data[86].DATAIN -sink_data[86] => src12_data[86].DATAIN -sink_data[86] => src13_data[86].DATAIN -sink_data[86] => src14_data[86].DATAIN -sink_data[86] => src15_data[86].DATAIN -sink_data[86] => src16_data[86].DATAIN -sink_data[87] => src17_data[87].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[87] => src1_data[87].DATAIN -sink_data[87] => src2_data[87].DATAIN -sink_data[87] => src3_data[87].DATAIN -sink_data[87] => src4_data[87].DATAIN -sink_data[87] => src5_data[87].DATAIN -sink_data[87] => src6_data[87].DATAIN -sink_data[87] => src7_data[87].DATAIN -sink_data[87] => src8_data[87].DATAIN -sink_data[87] => src9_data[87].DATAIN -sink_data[87] => src10_data[87].DATAIN -sink_data[87] => src11_data[87].DATAIN -sink_data[87] => src12_data[87].DATAIN -sink_data[87] => src13_data[87].DATAIN -sink_data[87] => src14_data[87].DATAIN -sink_data[87] => src15_data[87].DATAIN -sink_data[87] => src16_data[87].DATAIN -sink_data[88] => src17_data[88].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[88] => src1_data[88].DATAIN -sink_data[88] => src2_data[88].DATAIN -sink_data[88] => src3_data[88].DATAIN -sink_data[88] => src4_data[88].DATAIN -sink_data[88] => src5_data[88].DATAIN -sink_data[88] => src6_data[88].DATAIN -sink_data[88] => src7_data[88].DATAIN -sink_data[88] => src8_data[88].DATAIN -sink_data[88] => src9_data[88].DATAIN -sink_data[88] => src10_data[88].DATAIN -sink_data[88] => src11_data[88].DATAIN -sink_data[88] => src12_data[88].DATAIN -sink_data[88] => src13_data[88].DATAIN -sink_data[88] => src14_data[88].DATAIN -sink_data[88] => src15_data[88].DATAIN -sink_data[88] => src16_data[88].DATAIN -sink_data[89] => src17_data[89].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[89] => src1_data[89].DATAIN -sink_data[89] => src2_data[89].DATAIN -sink_data[89] => src3_data[89].DATAIN -sink_data[89] => src4_data[89].DATAIN -sink_data[89] => src5_data[89].DATAIN -sink_data[89] => src6_data[89].DATAIN -sink_data[89] => src7_data[89].DATAIN -sink_data[89] => src8_data[89].DATAIN -sink_data[89] => src9_data[89].DATAIN -sink_data[89] => src10_data[89].DATAIN -sink_data[89] => src11_data[89].DATAIN -sink_data[89] => src12_data[89].DATAIN -sink_data[89] => src13_data[89].DATAIN -sink_data[89] => src14_data[89].DATAIN -sink_data[89] => src15_data[89].DATAIN -sink_data[89] => src16_data[89].DATAIN -sink_data[90] => src17_data[90].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[90] => src1_data[90].DATAIN -sink_data[90] => src2_data[90].DATAIN -sink_data[90] => src3_data[90].DATAIN -sink_data[90] => src4_data[90].DATAIN -sink_data[90] => src5_data[90].DATAIN -sink_data[90] => src6_data[90].DATAIN -sink_data[90] => src7_data[90].DATAIN -sink_data[90] => src8_data[90].DATAIN -sink_data[90] => src9_data[90].DATAIN -sink_data[90] => src10_data[90].DATAIN -sink_data[90] => src11_data[90].DATAIN -sink_data[90] => src12_data[90].DATAIN -sink_data[90] => src13_data[90].DATAIN -sink_data[90] => src14_data[90].DATAIN -sink_data[90] => src15_data[90].DATAIN -sink_data[90] => src16_data[90].DATAIN -sink_data[91] => src17_data[91].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[91] => src1_data[91].DATAIN -sink_data[91] => src2_data[91].DATAIN -sink_data[91] => src3_data[91].DATAIN -sink_data[91] => src4_data[91].DATAIN -sink_data[91] => src5_data[91].DATAIN -sink_data[91] => src6_data[91].DATAIN -sink_data[91] => src7_data[91].DATAIN -sink_data[91] => src8_data[91].DATAIN -sink_data[91] => src9_data[91].DATAIN -sink_data[91] => src10_data[91].DATAIN -sink_data[91] => src11_data[91].DATAIN -sink_data[91] => src12_data[91].DATAIN -sink_data[91] => src13_data[91].DATAIN -sink_data[91] => src14_data[91].DATAIN -sink_data[91] => src15_data[91].DATAIN -sink_data[91] => src16_data[91].DATAIN -sink_data[92] => src17_data[92].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[92] => src1_data[92].DATAIN -sink_data[92] => src2_data[92].DATAIN -sink_data[92] => src3_data[92].DATAIN -sink_data[92] => src4_data[92].DATAIN -sink_data[92] => src5_data[92].DATAIN -sink_data[92] => src6_data[92].DATAIN -sink_data[92] => src7_data[92].DATAIN -sink_data[92] => src8_data[92].DATAIN -sink_data[92] => src9_data[92].DATAIN -sink_data[92] => src10_data[92].DATAIN -sink_data[92] => src11_data[92].DATAIN -sink_data[92] => src12_data[92].DATAIN -sink_data[92] => src13_data[92].DATAIN -sink_data[92] => src14_data[92].DATAIN -sink_data[92] => src15_data[92].DATAIN -sink_data[92] => src16_data[92].DATAIN -sink_data[93] => src17_data[93].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[93] => src1_data[93].DATAIN -sink_data[93] => src2_data[93].DATAIN -sink_data[93] => src3_data[93].DATAIN -sink_data[93] => src4_data[93].DATAIN -sink_data[93] => src5_data[93].DATAIN -sink_data[93] => src6_data[93].DATAIN -sink_data[93] => src7_data[93].DATAIN -sink_data[93] => src8_data[93].DATAIN -sink_data[93] => src9_data[93].DATAIN -sink_data[93] => src10_data[93].DATAIN -sink_data[93] => src11_data[93].DATAIN -sink_data[93] => src12_data[93].DATAIN -sink_data[93] => src13_data[93].DATAIN -sink_data[93] => src14_data[93].DATAIN -sink_data[93] => src15_data[93].DATAIN -sink_data[93] => src16_data[93].DATAIN -sink_data[94] => src17_data[94].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[94] => src1_data[94].DATAIN -sink_data[94] => src2_data[94].DATAIN -sink_data[94] => src3_data[94].DATAIN -sink_data[94] => src4_data[94].DATAIN -sink_data[94] => src5_data[94].DATAIN -sink_data[94] => src6_data[94].DATAIN -sink_data[94] => src7_data[94].DATAIN -sink_data[94] => src8_data[94].DATAIN -sink_data[94] => src9_data[94].DATAIN -sink_data[94] => src10_data[94].DATAIN -sink_data[94] => src11_data[94].DATAIN -sink_data[94] => src12_data[94].DATAIN -sink_data[94] => src13_data[94].DATAIN -sink_data[94] => src14_data[94].DATAIN -sink_data[94] => src15_data[94].DATAIN -sink_data[94] => src16_data[94].DATAIN -sink_data[95] => src17_data[95].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_data[95] => src1_data[95].DATAIN -sink_data[95] => src2_data[95].DATAIN -sink_data[95] => src3_data[95].DATAIN -sink_data[95] => src4_data[95].DATAIN -sink_data[95] => src5_data[95].DATAIN -sink_data[95] => src6_data[95].DATAIN -sink_data[95] => src7_data[95].DATAIN -sink_data[95] => src8_data[95].DATAIN -sink_data[95] => src9_data[95].DATAIN -sink_data[95] => src10_data[95].DATAIN -sink_data[95] => src11_data[95].DATAIN -sink_data[95] => src12_data[95].DATAIN -sink_data[95] => src13_data[95].DATAIN -sink_data[95] => src14_data[95].DATAIN -sink_data[95] => src15_data[95].DATAIN -sink_data[95] => src16_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src1_valid.IN1 -sink_channel[1] => sink_ready.IN0 -sink_channel[2] => src2_valid.IN1 -sink_channel[2] => sink_ready.IN0 -sink_channel[3] => src3_valid.IN1 -sink_channel[3] => sink_ready.IN0 -sink_channel[4] => src4_valid.IN1 -sink_channel[4] => sink_ready.IN0 -sink_channel[5] => src5_valid.IN1 -sink_channel[5] => sink_ready.IN0 -sink_channel[6] => src6_valid.IN1 -sink_channel[6] => sink_ready.IN0 -sink_channel[7] => src7_valid.IN1 -sink_channel[7] => sink_ready.IN0 -sink_channel[8] => src8_valid.IN1 -sink_channel[8] => sink_ready.IN0 -sink_channel[9] => src9_valid.IN1 -sink_channel[9] => sink_ready.IN0 -sink_channel[10] => src10_valid.IN1 -sink_channel[10] => sink_ready.IN0 -sink_channel[11] => src11_valid.IN1 -sink_channel[11] => sink_ready.IN0 -sink_channel[12] => src12_valid.IN1 -sink_channel[12] => sink_ready.IN0 -sink_channel[13] => src13_valid.IN1 -sink_channel[13] => sink_ready.IN0 -sink_channel[14] => src14_valid.IN1 -sink_channel[14] => sink_ready.IN0 -sink_channel[15] => src15_valid.IN1 -sink_channel[15] => sink_ready.IN0 -sink_channel[16] => src16_valid.IN1 -sink_channel[16] => sink_ready.IN0 -sink_channel[17] => src17_valid.IN1 -sink_channel[17] => sink_ready.IN0 -sink_startofpacket => src17_startofpacket.DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_startofpacket => src1_startofpacket.DATAIN -sink_startofpacket => src2_startofpacket.DATAIN -sink_startofpacket => src3_startofpacket.DATAIN -sink_startofpacket => src4_startofpacket.DATAIN -sink_startofpacket => src5_startofpacket.DATAIN -sink_startofpacket => src6_startofpacket.DATAIN -sink_startofpacket => src7_startofpacket.DATAIN -sink_startofpacket => src8_startofpacket.DATAIN -sink_startofpacket => src9_startofpacket.DATAIN -sink_startofpacket => src10_startofpacket.DATAIN -sink_startofpacket => src11_startofpacket.DATAIN -sink_startofpacket => src12_startofpacket.DATAIN -sink_startofpacket => src13_startofpacket.DATAIN -sink_startofpacket => src14_startofpacket.DATAIN -sink_startofpacket => src15_startofpacket.DATAIN -sink_startofpacket => src16_startofpacket.DATAIN -sink_endofpacket => src17_endofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_endofpacket => src1_endofpacket.DATAIN -sink_endofpacket => src2_endofpacket.DATAIN -sink_endofpacket => src3_endofpacket.DATAIN -sink_endofpacket => src4_endofpacket.DATAIN -sink_endofpacket => src5_endofpacket.DATAIN -sink_endofpacket => src6_endofpacket.DATAIN -sink_endofpacket => src7_endofpacket.DATAIN -sink_endofpacket => src8_endofpacket.DATAIN -sink_endofpacket => src9_endofpacket.DATAIN -sink_endofpacket => src10_endofpacket.DATAIN -sink_endofpacket => src11_endofpacket.DATAIN -sink_endofpacket => src12_endofpacket.DATAIN -sink_endofpacket => src13_endofpacket.DATAIN -sink_endofpacket => src14_endofpacket.DATAIN -sink_endofpacket => src15_endofpacket.DATAIN -sink_endofpacket => src16_endofpacket.DATAIN -sink_ready <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= -src0_channel[1] <= -src0_channel[2] <= -src0_channel[3] <= -src0_channel[4] <= -src0_channel[5] <= -src0_channel[6] <= -src0_channel[7] <= -src0_channel[8] <= -src0_channel[9] <= -src0_channel[10] <= -src0_channel[11] <= -src0_channel[12] <= -src0_channel[13] <= -src0_channel[14] <= -src0_channel[15] <= -src0_channel[16] <= -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -src1_valid <= src1_valid.DB_MAX_OUTPUT_PORT_TYPE -src1_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src1_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src1_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src1_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src1_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src1_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src1_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src1_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src1_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src1_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src1_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src1_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src1_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src1_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src1_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src1_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src1_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src1_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src1_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src1_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src1_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src1_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src1_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src1_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src1_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src1_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src1_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src1_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src1_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src1_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src1_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src1_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src1_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src1_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src1_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src1_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src1_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src1_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src1_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src1_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src1_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src1_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src1_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src1_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src1_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src1_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src1_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src1_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src1_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src1_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src1_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src1_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src1_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src1_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src1_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src1_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src1_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src1_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src1_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src1_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src1_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src1_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src1_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src1_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src1_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src1_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src1_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src1_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src1_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src1_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src1_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src1_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src1_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src1_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src1_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src1_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src1_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src1_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src1_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src1_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src1_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src1_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src1_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src1_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src1_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src1_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src1_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src1_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src1_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src1_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src1_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src1_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src1_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src1_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src1_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src1_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[0] <= -src1_channel[1] <= -src1_channel[2] <= -src1_channel[3] <= -src1_channel[4] <= -src1_channel[5] <= -src1_channel[6] <= -src1_channel[7] <= -src1_channel[8] <= -src1_channel[9] <= -src1_channel[10] <= -src1_channel[11] <= -src1_channel[12] <= -src1_channel[13] <= -src1_channel[14] <= -src1_channel[15] <= -src1_channel[16] <= -src1_channel[17] <= -src1_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src1_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src1_ready => sink_ready.IN1 -src2_valid <= src2_valid.DB_MAX_OUTPUT_PORT_TYPE -src2_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src2_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src2_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src2_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src2_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src2_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src2_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src2_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src2_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src2_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src2_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src2_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src2_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src2_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src2_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src2_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src2_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src2_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src2_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src2_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src2_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src2_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src2_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src2_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src2_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src2_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src2_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src2_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src2_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src2_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src2_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src2_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src2_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src2_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src2_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src2_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src2_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src2_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src2_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src2_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src2_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src2_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src2_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src2_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src2_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src2_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src2_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src2_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src2_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src2_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src2_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src2_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src2_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src2_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src2_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src2_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src2_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src2_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src2_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src2_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src2_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src2_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src2_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src2_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src2_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src2_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src2_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src2_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src2_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src2_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src2_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src2_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src2_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src2_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src2_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src2_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src2_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src2_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src2_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src2_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src2_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src2_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src2_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src2_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src2_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src2_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src2_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src2_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src2_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src2_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src2_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src2_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src2_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src2_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src2_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src2_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src2_channel[0] <= -src2_channel[1] <= -src2_channel[2] <= -src2_channel[3] <= -src2_channel[4] <= -src2_channel[5] <= -src2_channel[6] <= -src2_channel[7] <= -src2_channel[8] <= -src2_channel[9] <= -src2_channel[10] <= -src2_channel[11] <= -src2_channel[12] <= -src2_channel[13] <= -src2_channel[14] <= -src2_channel[15] <= -src2_channel[16] <= -src2_channel[17] <= -src2_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src2_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src2_ready => sink_ready.IN1 -src3_valid <= src3_valid.DB_MAX_OUTPUT_PORT_TYPE -src3_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src3_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src3_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src3_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src3_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src3_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src3_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src3_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src3_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src3_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src3_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src3_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src3_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src3_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src3_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src3_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src3_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src3_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src3_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src3_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src3_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src3_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src3_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src3_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src3_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src3_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src3_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src3_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src3_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src3_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src3_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src3_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src3_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src3_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src3_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src3_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src3_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src3_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src3_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src3_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src3_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src3_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src3_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src3_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src3_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src3_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src3_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src3_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src3_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src3_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src3_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src3_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src3_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src3_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src3_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src3_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src3_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src3_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src3_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src3_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src3_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src3_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src3_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src3_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src3_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src3_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src3_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src3_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src3_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src3_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src3_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src3_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src3_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src3_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src3_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src3_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src3_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src3_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src3_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src3_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src3_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src3_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src3_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src3_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src3_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src3_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src3_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src3_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src3_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src3_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src3_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src3_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src3_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src3_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src3_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src3_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src3_channel[0] <= -src3_channel[1] <= -src3_channel[2] <= -src3_channel[3] <= -src3_channel[4] <= -src3_channel[5] <= -src3_channel[6] <= -src3_channel[7] <= -src3_channel[8] <= -src3_channel[9] <= -src3_channel[10] <= -src3_channel[11] <= -src3_channel[12] <= -src3_channel[13] <= -src3_channel[14] <= -src3_channel[15] <= -src3_channel[16] <= -src3_channel[17] <= -src3_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src3_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src3_ready => sink_ready.IN1 -src4_valid <= src4_valid.DB_MAX_OUTPUT_PORT_TYPE -src4_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src4_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src4_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src4_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src4_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src4_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src4_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src4_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src4_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src4_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src4_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src4_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src4_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src4_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src4_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src4_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src4_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src4_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src4_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src4_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src4_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src4_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src4_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src4_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src4_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src4_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src4_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src4_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src4_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src4_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src4_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src4_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src4_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src4_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src4_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src4_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src4_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src4_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src4_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src4_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src4_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src4_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src4_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src4_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src4_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src4_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src4_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src4_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src4_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src4_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src4_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src4_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src4_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src4_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src4_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src4_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src4_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src4_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src4_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src4_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src4_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src4_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src4_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src4_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src4_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src4_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src4_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src4_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src4_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src4_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src4_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src4_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src4_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src4_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src4_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src4_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src4_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src4_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src4_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src4_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src4_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src4_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src4_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src4_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src4_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src4_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src4_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src4_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src4_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src4_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src4_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src4_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src4_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src4_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src4_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src4_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src4_channel[0] <= -src4_channel[1] <= -src4_channel[2] <= -src4_channel[3] <= -src4_channel[4] <= -src4_channel[5] <= -src4_channel[6] <= -src4_channel[7] <= -src4_channel[8] <= -src4_channel[9] <= -src4_channel[10] <= -src4_channel[11] <= -src4_channel[12] <= -src4_channel[13] <= -src4_channel[14] <= -src4_channel[15] <= -src4_channel[16] <= -src4_channel[17] <= -src4_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src4_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src4_ready => sink_ready.IN1 -src5_valid <= src5_valid.DB_MAX_OUTPUT_PORT_TYPE -src5_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src5_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src5_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src5_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src5_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src5_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src5_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src5_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src5_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src5_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src5_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src5_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src5_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src5_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src5_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src5_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src5_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src5_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src5_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src5_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src5_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src5_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src5_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src5_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src5_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src5_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src5_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src5_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src5_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src5_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src5_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src5_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src5_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src5_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src5_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src5_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src5_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src5_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src5_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src5_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src5_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src5_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src5_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src5_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src5_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src5_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src5_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src5_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src5_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src5_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src5_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src5_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src5_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src5_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src5_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src5_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src5_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src5_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src5_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src5_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src5_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src5_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src5_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src5_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src5_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src5_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src5_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src5_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src5_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src5_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src5_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src5_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src5_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src5_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src5_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src5_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src5_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src5_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src5_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src5_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src5_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src5_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src5_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src5_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src5_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src5_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src5_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src5_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src5_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src5_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src5_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src5_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src5_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src5_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src5_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src5_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src5_channel[0] <= -src5_channel[1] <= -src5_channel[2] <= -src5_channel[3] <= -src5_channel[4] <= -src5_channel[5] <= -src5_channel[6] <= -src5_channel[7] <= -src5_channel[8] <= -src5_channel[9] <= -src5_channel[10] <= -src5_channel[11] <= -src5_channel[12] <= -src5_channel[13] <= -src5_channel[14] <= -src5_channel[15] <= -src5_channel[16] <= -src5_channel[17] <= -src5_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src5_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src5_ready => sink_ready.IN1 -src6_valid <= src6_valid.DB_MAX_OUTPUT_PORT_TYPE -src6_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src6_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src6_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src6_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src6_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src6_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src6_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src6_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src6_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src6_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src6_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src6_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src6_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src6_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src6_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src6_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src6_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src6_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src6_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src6_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src6_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src6_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src6_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src6_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src6_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src6_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src6_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src6_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src6_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src6_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src6_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src6_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src6_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src6_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src6_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src6_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src6_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src6_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src6_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src6_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src6_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src6_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src6_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src6_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src6_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src6_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src6_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src6_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src6_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src6_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src6_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src6_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src6_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src6_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src6_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src6_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src6_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src6_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src6_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src6_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src6_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src6_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src6_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src6_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src6_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src6_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src6_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src6_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src6_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src6_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src6_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src6_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src6_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src6_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src6_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src6_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src6_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src6_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src6_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src6_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src6_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src6_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src6_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src6_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src6_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src6_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src6_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src6_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src6_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src6_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src6_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src6_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src6_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src6_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src6_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src6_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src6_channel[0] <= -src6_channel[1] <= -src6_channel[2] <= -src6_channel[3] <= -src6_channel[4] <= -src6_channel[5] <= -src6_channel[6] <= -src6_channel[7] <= -src6_channel[8] <= -src6_channel[9] <= -src6_channel[10] <= -src6_channel[11] <= -src6_channel[12] <= -src6_channel[13] <= -src6_channel[14] <= -src6_channel[15] <= -src6_channel[16] <= -src6_channel[17] <= -src6_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src6_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src6_ready => sink_ready.IN1 -src7_valid <= src7_valid.DB_MAX_OUTPUT_PORT_TYPE -src7_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src7_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src7_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src7_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src7_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src7_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src7_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src7_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src7_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src7_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src7_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src7_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src7_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src7_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src7_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src7_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src7_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src7_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src7_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src7_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src7_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src7_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src7_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src7_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src7_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src7_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src7_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src7_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src7_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src7_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src7_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src7_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src7_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src7_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src7_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src7_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src7_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src7_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src7_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src7_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src7_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src7_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src7_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src7_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src7_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src7_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src7_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src7_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src7_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src7_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src7_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src7_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src7_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src7_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src7_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src7_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src7_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src7_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src7_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src7_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src7_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src7_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src7_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src7_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src7_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src7_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src7_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src7_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src7_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src7_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src7_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src7_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src7_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src7_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src7_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src7_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src7_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src7_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src7_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src7_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src7_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src7_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src7_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src7_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src7_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src7_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src7_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src7_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src7_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src7_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src7_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src7_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src7_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src7_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src7_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src7_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src7_channel[0] <= -src7_channel[1] <= -src7_channel[2] <= -src7_channel[3] <= -src7_channel[4] <= -src7_channel[5] <= -src7_channel[6] <= -src7_channel[7] <= -src7_channel[8] <= -src7_channel[9] <= -src7_channel[10] <= -src7_channel[11] <= -src7_channel[12] <= -src7_channel[13] <= -src7_channel[14] <= -src7_channel[15] <= -src7_channel[16] <= -src7_channel[17] <= -src7_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src7_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src7_ready => sink_ready.IN1 -src8_valid <= src8_valid.DB_MAX_OUTPUT_PORT_TYPE -src8_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src8_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src8_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src8_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src8_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src8_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src8_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src8_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src8_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src8_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src8_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src8_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src8_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src8_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src8_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src8_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src8_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src8_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src8_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src8_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src8_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src8_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src8_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src8_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src8_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src8_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src8_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src8_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src8_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src8_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src8_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src8_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src8_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src8_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src8_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src8_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src8_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src8_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src8_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src8_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src8_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src8_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src8_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src8_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src8_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src8_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src8_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src8_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src8_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src8_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src8_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src8_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src8_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src8_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src8_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src8_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src8_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src8_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src8_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src8_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src8_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src8_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src8_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src8_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src8_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src8_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src8_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src8_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src8_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src8_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src8_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src8_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src8_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src8_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src8_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src8_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src8_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src8_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src8_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src8_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src8_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src8_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src8_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src8_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src8_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src8_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src8_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src8_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src8_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src8_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src8_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src8_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src8_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src8_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src8_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src8_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src8_channel[0] <= -src8_channel[1] <= -src8_channel[2] <= -src8_channel[3] <= -src8_channel[4] <= -src8_channel[5] <= -src8_channel[6] <= -src8_channel[7] <= -src8_channel[8] <= -src8_channel[9] <= -src8_channel[10] <= -src8_channel[11] <= -src8_channel[12] <= -src8_channel[13] <= -src8_channel[14] <= -src8_channel[15] <= -src8_channel[16] <= -src8_channel[17] <= -src8_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src8_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src8_ready => sink_ready.IN1 -src9_valid <= src9_valid.DB_MAX_OUTPUT_PORT_TYPE -src9_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src9_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src9_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src9_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src9_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src9_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src9_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src9_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src9_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src9_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src9_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src9_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src9_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src9_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src9_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src9_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src9_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src9_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src9_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src9_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src9_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src9_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src9_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src9_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src9_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src9_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src9_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src9_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src9_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src9_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src9_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src9_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src9_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src9_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src9_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src9_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src9_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src9_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src9_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src9_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src9_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src9_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src9_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src9_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src9_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src9_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src9_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src9_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src9_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src9_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src9_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src9_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src9_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src9_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src9_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src9_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src9_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src9_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src9_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src9_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src9_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src9_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src9_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src9_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src9_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src9_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src9_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src9_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src9_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src9_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src9_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src9_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src9_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src9_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src9_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src9_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src9_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src9_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src9_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src9_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src9_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src9_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src9_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src9_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src9_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src9_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src9_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src9_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src9_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src9_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src9_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src9_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src9_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src9_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src9_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src9_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src9_channel[0] <= -src9_channel[1] <= -src9_channel[2] <= -src9_channel[3] <= -src9_channel[4] <= -src9_channel[5] <= -src9_channel[6] <= -src9_channel[7] <= -src9_channel[8] <= -src9_channel[9] <= -src9_channel[10] <= -src9_channel[11] <= -src9_channel[12] <= -src9_channel[13] <= -src9_channel[14] <= -src9_channel[15] <= -src9_channel[16] <= -src9_channel[17] <= -src9_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src9_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src9_ready => sink_ready.IN1 -src10_valid <= src10_valid.DB_MAX_OUTPUT_PORT_TYPE -src10_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src10_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src10_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src10_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src10_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src10_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src10_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src10_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src10_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src10_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src10_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src10_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src10_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src10_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src10_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src10_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src10_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src10_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src10_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src10_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src10_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src10_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src10_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src10_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src10_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src10_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src10_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src10_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src10_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src10_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src10_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src10_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src10_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src10_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src10_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src10_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src10_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src10_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src10_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src10_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src10_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src10_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src10_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src10_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src10_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src10_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src10_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src10_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src10_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src10_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src10_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src10_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src10_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src10_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src10_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src10_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src10_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src10_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src10_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src10_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src10_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src10_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src10_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src10_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src10_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src10_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src10_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src10_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src10_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src10_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src10_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src10_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src10_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src10_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src10_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src10_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src10_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src10_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src10_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src10_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src10_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src10_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src10_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src10_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src10_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src10_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src10_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src10_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src10_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src10_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src10_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src10_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src10_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src10_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src10_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src10_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src10_channel[0] <= -src10_channel[1] <= -src10_channel[2] <= -src10_channel[3] <= -src10_channel[4] <= -src10_channel[5] <= -src10_channel[6] <= -src10_channel[7] <= -src10_channel[8] <= -src10_channel[9] <= -src10_channel[10] <= -src10_channel[11] <= -src10_channel[12] <= -src10_channel[13] <= -src10_channel[14] <= -src10_channel[15] <= -src10_channel[16] <= -src10_channel[17] <= -src10_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src10_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src10_ready => sink_ready.IN1 -src11_valid <= src11_valid.DB_MAX_OUTPUT_PORT_TYPE -src11_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src11_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src11_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src11_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src11_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src11_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src11_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src11_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src11_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src11_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src11_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src11_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src11_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src11_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src11_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src11_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src11_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src11_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src11_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src11_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src11_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src11_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src11_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src11_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src11_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src11_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src11_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src11_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src11_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src11_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src11_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src11_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src11_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src11_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src11_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src11_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src11_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src11_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src11_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src11_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src11_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src11_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src11_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src11_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src11_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src11_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src11_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src11_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src11_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src11_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src11_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src11_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src11_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src11_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src11_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src11_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src11_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src11_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src11_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src11_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src11_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src11_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src11_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src11_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src11_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src11_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src11_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src11_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src11_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src11_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src11_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src11_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src11_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src11_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src11_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src11_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src11_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src11_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src11_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src11_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src11_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src11_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src11_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src11_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src11_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src11_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src11_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src11_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src11_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src11_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src11_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src11_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src11_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src11_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src11_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src11_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src11_channel[0] <= -src11_channel[1] <= -src11_channel[2] <= -src11_channel[3] <= -src11_channel[4] <= -src11_channel[5] <= -src11_channel[6] <= -src11_channel[7] <= -src11_channel[8] <= -src11_channel[9] <= -src11_channel[10] <= -src11_channel[11] <= -src11_channel[12] <= -src11_channel[13] <= -src11_channel[14] <= -src11_channel[15] <= -src11_channel[16] <= -src11_channel[17] <= -src11_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src11_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src11_ready => sink_ready.IN1 -src12_valid <= src12_valid.DB_MAX_OUTPUT_PORT_TYPE -src12_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src12_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src12_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src12_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src12_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src12_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src12_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src12_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src12_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src12_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src12_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src12_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src12_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src12_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src12_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src12_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src12_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src12_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src12_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src12_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src12_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src12_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src12_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src12_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src12_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src12_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src12_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src12_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src12_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src12_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src12_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src12_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src12_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src12_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src12_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src12_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src12_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src12_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src12_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src12_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src12_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src12_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src12_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src12_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src12_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src12_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src12_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src12_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src12_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src12_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src12_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src12_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src12_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src12_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src12_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src12_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src12_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src12_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src12_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src12_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src12_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src12_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src12_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src12_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src12_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src12_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src12_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src12_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src12_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src12_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src12_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src12_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src12_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src12_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src12_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src12_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src12_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src12_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src12_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src12_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src12_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src12_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src12_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src12_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src12_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src12_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src12_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src12_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src12_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src12_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src12_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src12_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src12_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src12_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src12_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src12_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src12_channel[0] <= -src12_channel[1] <= -src12_channel[2] <= -src12_channel[3] <= -src12_channel[4] <= -src12_channel[5] <= -src12_channel[6] <= -src12_channel[7] <= -src12_channel[8] <= -src12_channel[9] <= -src12_channel[10] <= -src12_channel[11] <= -src12_channel[12] <= -src12_channel[13] <= -src12_channel[14] <= -src12_channel[15] <= -src12_channel[16] <= -src12_channel[17] <= -src12_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src12_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src12_ready => sink_ready.IN1 -src13_valid <= src13_valid.DB_MAX_OUTPUT_PORT_TYPE -src13_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src13_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src13_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src13_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src13_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src13_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src13_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src13_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src13_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src13_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src13_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src13_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src13_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src13_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src13_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src13_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src13_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src13_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src13_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src13_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src13_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src13_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src13_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src13_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src13_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src13_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src13_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src13_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src13_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src13_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src13_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src13_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src13_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src13_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src13_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src13_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src13_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src13_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src13_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src13_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src13_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src13_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src13_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src13_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src13_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src13_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src13_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src13_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src13_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src13_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src13_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src13_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src13_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src13_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src13_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src13_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src13_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src13_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src13_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src13_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src13_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src13_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src13_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src13_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src13_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src13_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src13_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src13_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src13_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src13_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src13_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src13_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src13_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src13_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src13_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src13_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src13_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src13_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src13_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src13_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src13_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src13_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src13_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src13_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src13_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src13_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src13_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src13_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src13_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src13_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src13_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src13_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src13_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src13_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src13_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src13_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src13_channel[0] <= -src13_channel[1] <= -src13_channel[2] <= -src13_channel[3] <= -src13_channel[4] <= -src13_channel[5] <= -src13_channel[6] <= -src13_channel[7] <= -src13_channel[8] <= -src13_channel[9] <= -src13_channel[10] <= -src13_channel[11] <= -src13_channel[12] <= -src13_channel[13] <= -src13_channel[14] <= -src13_channel[15] <= -src13_channel[16] <= -src13_channel[17] <= -src13_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src13_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src13_ready => sink_ready.IN1 -src14_valid <= src14_valid.DB_MAX_OUTPUT_PORT_TYPE -src14_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src14_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src14_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src14_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src14_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src14_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src14_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src14_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src14_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src14_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src14_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src14_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src14_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src14_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src14_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src14_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src14_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src14_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src14_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src14_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src14_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src14_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src14_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src14_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src14_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src14_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src14_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src14_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src14_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src14_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src14_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src14_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src14_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src14_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src14_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src14_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src14_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src14_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src14_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src14_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src14_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src14_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src14_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src14_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src14_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src14_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src14_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src14_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src14_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src14_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src14_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src14_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src14_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src14_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src14_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src14_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src14_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src14_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src14_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src14_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src14_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src14_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src14_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src14_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src14_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src14_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src14_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src14_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src14_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src14_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src14_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src14_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src14_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src14_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src14_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src14_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src14_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src14_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src14_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src14_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src14_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src14_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src14_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src14_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src14_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src14_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src14_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src14_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src14_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src14_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src14_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src14_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src14_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src14_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src14_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src14_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src14_channel[0] <= -src14_channel[1] <= -src14_channel[2] <= -src14_channel[3] <= -src14_channel[4] <= -src14_channel[5] <= -src14_channel[6] <= -src14_channel[7] <= -src14_channel[8] <= -src14_channel[9] <= -src14_channel[10] <= -src14_channel[11] <= -src14_channel[12] <= -src14_channel[13] <= -src14_channel[14] <= -src14_channel[15] <= -src14_channel[16] <= -src14_channel[17] <= -src14_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src14_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src14_ready => sink_ready.IN1 -src15_valid <= src15_valid.DB_MAX_OUTPUT_PORT_TYPE -src15_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src15_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src15_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src15_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src15_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src15_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src15_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src15_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src15_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src15_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src15_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src15_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src15_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src15_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src15_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src15_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src15_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src15_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src15_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src15_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src15_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src15_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src15_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src15_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src15_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src15_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src15_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src15_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src15_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src15_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src15_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src15_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src15_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src15_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src15_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src15_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src15_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src15_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src15_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src15_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src15_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src15_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src15_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src15_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src15_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src15_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src15_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src15_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src15_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src15_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src15_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src15_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src15_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src15_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src15_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src15_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src15_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src15_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src15_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src15_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src15_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src15_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src15_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src15_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src15_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src15_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src15_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src15_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src15_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src15_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src15_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src15_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src15_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src15_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src15_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src15_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src15_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src15_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src15_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src15_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src15_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src15_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src15_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src15_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src15_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src15_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src15_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src15_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src15_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src15_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src15_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src15_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src15_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src15_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src15_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src15_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src15_channel[0] <= -src15_channel[1] <= -src15_channel[2] <= -src15_channel[3] <= -src15_channel[4] <= -src15_channel[5] <= -src15_channel[6] <= -src15_channel[7] <= -src15_channel[8] <= -src15_channel[9] <= -src15_channel[10] <= -src15_channel[11] <= -src15_channel[12] <= -src15_channel[13] <= -src15_channel[14] <= -src15_channel[15] <= -src15_channel[16] <= -src15_channel[17] <= -src15_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src15_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src15_ready => sink_ready.IN1 -src16_valid <= src16_valid.DB_MAX_OUTPUT_PORT_TYPE -src16_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src16_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src16_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src16_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src16_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src16_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src16_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src16_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src16_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src16_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src16_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src16_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src16_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src16_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src16_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src16_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src16_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src16_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src16_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src16_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src16_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src16_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src16_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src16_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src16_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src16_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src16_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src16_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src16_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src16_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src16_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src16_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src16_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src16_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src16_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src16_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src16_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src16_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src16_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src16_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src16_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src16_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src16_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src16_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src16_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src16_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src16_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src16_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src16_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src16_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src16_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src16_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src16_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src16_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src16_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src16_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src16_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src16_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src16_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src16_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src16_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src16_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src16_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src16_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src16_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src16_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src16_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src16_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src16_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src16_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src16_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src16_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src16_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src16_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src16_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src16_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src16_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src16_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src16_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src16_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src16_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src16_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src16_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src16_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src16_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src16_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src16_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src16_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src16_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src16_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src16_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src16_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src16_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src16_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src16_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src16_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src16_channel[0] <= -src16_channel[1] <= -src16_channel[2] <= -src16_channel[3] <= -src16_channel[4] <= -src16_channel[5] <= -src16_channel[6] <= -src16_channel[7] <= -src16_channel[8] <= -src16_channel[9] <= -src16_channel[10] <= -src16_channel[11] <= -src16_channel[12] <= -src16_channel[13] <= -src16_channel[14] <= -src16_channel[15] <= -src16_channel[16] <= -src16_channel[17] <= -src16_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src16_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src16_ready => sink_ready.IN1 -src17_valid <= src17_valid.DB_MAX_OUTPUT_PORT_TYPE -src17_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src17_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src17_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src17_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src17_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src17_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src17_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src17_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src17_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src17_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src17_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src17_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src17_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src17_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src17_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src17_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src17_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src17_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src17_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src17_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src17_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src17_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src17_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src17_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src17_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src17_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src17_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src17_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src17_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src17_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src17_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src17_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src17_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src17_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src17_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src17_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src17_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src17_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src17_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src17_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src17_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src17_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src17_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src17_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src17_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src17_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src17_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src17_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src17_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src17_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src17_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src17_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src17_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src17_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src17_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src17_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src17_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src17_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src17_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src17_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src17_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src17_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src17_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src17_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src17_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src17_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src17_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src17_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src17_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src17_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src17_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src17_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src17_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src17_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src17_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src17_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src17_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src17_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src17_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src17_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src17_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src17_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src17_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src17_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src17_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src17_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src17_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src17_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src17_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src17_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src17_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src17_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src17_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src17_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src17_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src17_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src17_channel[0] <= -src17_channel[1] <= -src17_channel[2] <= -src17_channel[3] <= -src17_channel[4] <= -src17_channel[5] <= -src17_channel[6] <= -src17_channel[7] <= -src17_channel[8] <= -src17_channel[9] <= -src17_channel[10] <= -src17_channel[11] <= -src17_channel[12] <= -src17_channel[13] <= -src17_channel[14] <= -src17_channel[15] <= -src17_channel[16] <= -src17_channel[17] <= -src17_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src17_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src17_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux -sink0_valid => request.IN1 -sink0_valid => src_valid.IN1 -sink0_data[0] => src_payload.IN1 -sink0_data[1] => src_payload.IN1 -sink0_data[2] => src_payload.IN1 -sink0_data[3] => src_payload.IN1 -sink0_data[4] => src_payload.IN1 -sink0_data[5] => src_payload.IN1 -sink0_data[6] => src_payload.IN1 -sink0_data[7] => src_payload.IN1 -sink0_data[8] => src_payload.IN1 -sink0_data[9] => src_payload.IN1 -sink0_data[10] => src_payload.IN1 -sink0_data[11] => src_payload.IN1 -sink0_data[12] => src_payload.IN1 -sink0_data[13] => src_payload.IN1 -sink0_data[14] => src_payload.IN1 -sink0_data[15] => src_payload.IN1 -sink0_data[16] => src_payload.IN1 -sink0_data[17] => src_payload.IN1 -sink0_data[18] => src_payload.IN1 -sink0_data[19] => src_payload.IN1 -sink0_data[20] => src_payload.IN1 -sink0_data[21] => src_payload.IN1 -sink0_data[22] => src_payload.IN1 -sink0_data[23] => src_payload.IN1 -sink0_data[24] => src_payload.IN1 -sink0_data[25] => src_payload.IN1 -sink0_data[26] => src_payload.IN1 -sink0_data[27] => src_payload.IN1 -sink0_data[28] => src_payload.IN1 -sink0_data[29] => src_payload.IN1 -sink0_data[30] => src_payload.IN1 -sink0_data[31] => src_payload.IN1 -sink0_data[32] => src_payload.IN1 -sink0_data[33] => src_payload.IN1 -sink0_data[34] => src_payload.IN1 -sink0_data[35] => src_payload.IN1 -sink0_data[36] => src_payload.IN1 -sink0_data[37] => src_payload.IN1 -sink0_data[38] => src_payload.IN1 -sink0_data[39] => src_payload.IN1 -sink0_data[40] => src_payload.IN1 -sink0_data[41] => src_payload.IN1 -sink0_data[42] => src_payload.IN1 -sink0_data[43] => src_payload.IN1 -sink0_data[44] => src_payload.IN1 -sink0_data[45] => src_payload.IN1 -sink0_data[46] => src_payload.IN1 -sink0_data[47] => src_payload.IN1 -sink0_data[48] => src_payload.IN1 -sink0_data[49] => src_payload.IN1 -sink0_data[50] => src_payload.IN1 -sink0_data[51] => src_payload.IN1 -sink0_data[52] => src_payload.IN1 -sink0_data[53] => src_payload.IN1 -sink0_data[54] => src_payload.IN1 -sink0_data[55] => src_payload.IN1 -sink0_data[56] => src_payload.IN1 -sink0_data[57] => src_payload.IN1 -sink0_data[58] => src_payload.IN1 -sink0_data[59] => locked.IN1 -sink0_data[59] => src_payload.IN1 -sink0_data[60] => src_payload.IN1 -sink0_data[61] => src_payload.IN1 -sink0_data[62] => src_payload.IN1 -sink0_data[63] => src_payload.IN1 -sink0_data[64] => src_payload.IN1 -sink0_data[65] => src_payload.IN1 -sink0_data[66] => src_payload.IN1 -sink0_data[67] => src_payload.IN1 -sink0_data[68] => src_payload.IN1 -sink0_data[69] => src_payload.IN1 -sink0_data[70] => src_payload.IN1 -sink0_data[71] => src_payload.IN1 -sink0_data[72] => src_payload.IN1 -sink0_data[73] => src_payload.IN1 -sink0_data[74] => src_payload.IN1 -sink0_data[75] => src_payload.IN1 -sink0_data[76] => src_payload.IN1 -sink0_data[77] => src_payload.IN1 -sink0_data[78] => src_payload.IN1 -sink0_data[79] => src_payload.IN1 -sink0_data[80] => src_payload.IN1 -sink0_data[81] => src_payload.IN1 -sink0_data[82] => src_payload.IN1 -sink0_data[83] => src_payload.IN1 -sink0_data[84] => src_payload.IN1 -sink0_data[85] => src_payload.IN1 -sink0_data[86] => src_payload.IN1 -sink0_data[87] => src_payload.IN1 -sink0_data[88] => src_payload.IN1 -sink0_data[89] => src_payload.IN1 -sink0_data[90] => src_payload.IN1 -sink0_data[91] => src_payload.IN1 -sink0_data[92] => src_payload.IN1 -sink0_data[93] => src_payload.IN1 -sink0_data[94] => src_payload.IN1 -sink0_data[95] => src_payload.IN1 -sink0_channel[0] => src_payload.IN1 -sink0_channel[1] => src_payload.IN1 -sink0_channel[2] => src_payload.IN1 -sink0_channel[3] => src_payload.IN1 -sink0_channel[4] => src_payload.IN1 -sink0_channel[5] => src_payload.IN1 -sink0_channel[6] => src_payload.IN1 -sink0_channel[7] => src_payload.IN1 -sink0_channel[8] => src_payload.IN1 -sink0_channel[9] => src_payload.IN1 -sink0_channel[10] => src_payload.IN1 -sink0_channel[11] => src_payload.IN1 -sink0_channel[12] => src_payload.IN1 -sink0_channel[13] => src_payload.IN1 -sink0_channel[14] => src_payload.IN1 -sink0_channel[15] => src_payload.IN1 -sink0_channel[16] => src_payload.IN1 -sink0_channel[17] => src_payload.IN1 -sink0_startofpacket => src_payload.IN1 -sink0_endofpacket => src_payload.IN1 -sink0_ready <= sink0_ready.DB_MAX_OUTPUT_PORT_TYPE -sink1_valid => request.IN1 -sink1_valid => src_valid.IN1 -sink1_data[0] => src_payload.IN1 -sink1_data[1] => src_payload.IN1 -sink1_data[2] => src_payload.IN1 -sink1_data[3] => src_payload.IN1 -sink1_data[4] => src_payload.IN1 -sink1_data[5] => src_payload.IN1 -sink1_data[6] => src_payload.IN1 -sink1_data[7] => src_payload.IN1 -sink1_data[8] => src_payload.IN1 -sink1_data[9] => src_payload.IN1 -sink1_data[10] => src_payload.IN1 -sink1_data[11] => src_payload.IN1 -sink1_data[12] => src_payload.IN1 -sink1_data[13] => src_payload.IN1 -sink1_data[14] => src_payload.IN1 -sink1_data[15] => src_payload.IN1 -sink1_data[16] => src_payload.IN1 -sink1_data[17] => src_payload.IN1 -sink1_data[18] => src_payload.IN1 -sink1_data[19] => src_payload.IN1 -sink1_data[20] => src_payload.IN1 -sink1_data[21] => src_payload.IN1 -sink1_data[22] => src_payload.IN1 -sink1_data[23] => src_payload.IN1 -sink1_data[24] => src_payload.IN1 -sink1_data[25] => src_payload.IN1 -sink1_data[26] => src_payload.IN1 -sink1_data[27] => src_payload.IN1 -sink1_data[28] => src_payload.IN1 -sink1_data[29] => src_payload.IN1 -sink1_data[30] => src_payload.IN1 -sink1_data[31] => src_payload.IN1 -sink1_data[32] => src_payload.IN1 -sink1_data[33] => src_payload.IN1 -sink1_data[34] => src_payload.IN1 -sink1_data[35] => src_payload.IN1 -sink1_data[36] => src_payload.IN1 -sink1_data[37] => src_payload.IN1 -sink1_data[38] => src_payload.IN1 -sink1_data[39] => src_payload.IN1 -sink1_data[40] => src_payload.IN1 -sink1_data[41] => src_payload.IN1 -sink1_data[42] => src_payload.IN1 -sink1_data[43] => src_payload.IN1 -sink1_data[44] => src_payload.IN1 -sink1_data[45] => src_payload.IN1 -sink1_data[46] => src_payload.IN1 -sink1_data[47] => src_payload.IN1 -sink1_data[48] => src_payload.IN1 -sink1_data[49] => src_payload.IN1 -sink1_data[50] => src_payload.IN1 -sink1_data[51] => src_payload.IN1 -sink1_data[52] => src_payload.IN1 -sink1_data[53] => src_payload.IN1 -sink1_data[54] => src_payload.IN1 -sink1_data[55] => src_payload.IN1 -sink1_data[56] => src_payload.IN1 -sink1_data[57] => src_payload.IN1 -sink1_data[58] => src_payload.IN1 -sink1_data[59] => locked.IN1 -sink1_data[59] => src_payload.IN1 -sink1_data[60] => src_payload.IN1 -sink1_data[61] => src_payload.IN1 -sink1_data[62] => src_payload.IN1 -sink1_data[63] => src_payload.IN1 -sink1_data[64] => src_payload.IN1 -sink1_data[65] => src_payload.IN1 -sink1_data[66] => src_payload.IN1 -sink1_data[67] => src_payload.IN1 -sink1_data[68] => src_payload.IN1 -sink1_data[69] => src_payload.IN1 -sink1_data[70] => src_payload.IN1 -sink1_data[71] => src_payload.IN1 -sink1_data[72] => src_payload.IN1 -sink1_data[73] => src_payload.IN1 -sink1_data[74] => src_payload.IN1 -sink1_data[75] => src_payload.IN1 -sink1_data[76] => src_payload.IN1 -sink1_data[77] => src_payload.IN1 -sink1_data[78] => src_payload.IN1 -sink1_data[79] => src_payload.IN1 -sink1_data[80] => src_payload.IN1 -sink1_data[81] => src_payload.IN1 -sink1_data[82] => src_payload.IN1 -sink1_data[83] => src_payload.IN1 -sink1_data[84] => src_payload.IN1 -sink1_data[85] => src_payload.IN1 -sink1_data[86] => src_payload.IN1 -sink1_data[87] => src_payload.IN1 -sink1_data[88] => src_payload.IN1 -sink1_data[89] => src_payload.IN1 -sink1_data[90] => src_payload.IN1 -sink1_data[91] => src_payload.IN1 -sink1_data[92] => src_payload.IN1 -sink1_data[93] => src_payload.IN1 -sink1_data[94] => src_payload.IN1 -sink1_data[95] => src_payload.IN1 -sink1_channel[0] => src_payload.IN1 -sink1_channel[1] => src_payload.IN1 -sink1_channel[2] => src_payload.IN1 -sink1_channel[3] => src_payload.IN1 -sink1_channel[4] => src_payload.IN1 -sink1_channel[5] => src_payload.IN1 -sink1_channel[6] => src_payload.IN1 -sink1_channel[7] => src_payload.IN1 -sink1_channel[8] => src_payload.IN1 -sink1_channel[9] => src_payload.IN1 -sink1_channel[10] => src_payload.IN1 -sink1_channel[11] => src_payload.IN1 -sink1_channel[12] => src_payload.IN1 -sink1_channel[13] => src_payload.IN1 -sink1_channel[14] => src_payload.IN1 -sink1_channel[15] => src_payload.IN1 -sink1_channel[16] => src_payload.IN1 -sink1_channel[17] => src_payload.IN1 -sink1_startofpacket => src_payload.IN1 -sink1_endofpacket => src_payload.IN1 -sink1_ready <= sink1_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= src_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= src_payload[0].DB_MAX_OUTPUT_PORT_TYPE -src_ready => last_cycle.IN0 -src_ready => sink0_ready.IN1 -src_ready => sink1_ready.IN1 -clk => clk.IN1 -reset => reset.IN1 - - -|lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb -clk => top_priority_reg[0].CLK -clk => top_priority_reg[1].CLK -reset => top_priority_reg[0].PRESET -reset => top_priority_reg[1].ACLR -request[0] => grant_double_vector[0].IN1 -request[0] => grant_double_vector[2].IN1 -request[0] => WideOr0.IN0 -request[0] => _.IN1 -request[0] => _.IN1 -request[1] => grant_double_vector[1].IN1 -request[1] => grant_double_vector[3].IN1 -request[1] => WideOr0.IN1 -request[1] => _.IN1 -request[1] => _.IN1 -grant[0] <= grant.DB_MAX_OUTPUT_PORT_TYPE -grant[1] <= grant.DB_MAX_OUTPUT_PORT_TYPE -increment_top_priority => top_priority_reg.OUTPUTSELECT -increment_top_priority => top_priority_reg.OUTPUTSELECT -save_top_priority => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -a[0] => sum.IN0 -a[0] => full_adder.cout[0].IN0 -a[1] => cout.IN0 -a[1] => cout.IN0 -a[2] => cout.IN0 -a[2] => cout.IN0 -a[3] => sum.IN0 -b[0] => sum.IN1 -b[0] => full_adder.cout[0].IN1 -b[1] => cout.IN1 -b[1] => cout.IN1 -b[2] => cout.IN1 -b[2] => cout.IN1 -b[3] => sum.IN1 -sum[0] <= sum.DB_MAX_OUTPUT_PORT_TYPE -sum[1] <= sum.DB_MAX_OUTPUT_PORT_TYPE -sum[2] <= sum.DB_MAX_OUTPUT_PORT_TYPE -sum[3] <= sum.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001 -sink0_valid => request.IN1 -sink0_valid => src_valid.IN1 -sink0_data[0] => src_payload.IN1 -sink0_data[1] => src_payload.IN1 -sink0_data[2] => src_payload.IN1 -sink0_data[3] => src_payload.IN1 -sink0_data[4] => src_payload.IN1 -sink0_data[5] => src_payload.IN1 -sink0_data[6] => src_payload.IN1 -sink0_data[7] => src_payload.IN1 -sink0_data[8] => src_payload.IN1 -sink0_data[9] => src_payload.IN1 -sink0_data[10] => src_payload.IN1 -sink0_data[11] => src_payload.IN1 -sink0_data[12] => src_payload.IN1 -sink0_data[13] => src_payload.IN1 -sink0_data[14] => src_payload.IN1 -sink0_data[15] => src_payload.IN1 -sink0_data[16] => src_payload.IN1 -sink0_data[17] => src_payload.IN1 -sink0_data[18] => src_payload.IN1 -sink0_data[19] => src_payload.IN1 -sink0_data[20] => src_payload.IN1 -sink0_data[21] => src_payload.IN1 -sink0_data[22] => src_payload.IN1 -sink0_data[23] => src_payload.IN1 -sink0_data[24] => src_payload.IN1 -sink0_data[25] => src_payload.IN1 -sink0_data[26] => src_payload.IN1 -sink0_data[27] => src_payload.IN1 -sink0_data[28] => src_payload.IN1 -sink0_data[29] => src_payload.IN1 -sink0_data[30] => src_payload.IN1 -sink0_data[31] => src_payload.IN1 -sink0_data[32] => src_payload.IN1 -sink0_data[33] => src_payload.IN1 -sink0_data[34] => src_payload.IN1 -sink0_data[35] => src_payload.IN1 -sink0_data[36] => src_payload.IN1 -sink0_data[37] => src_payload.IN1 -sink0_data[38] => src_payload.IN1 -sink0_data[39] => src_payload.IN1 -sink0_data[40] => src_payload.IN1 -sink0_data[41] => src_payload.IN1 -sink0_data[42] => src_payload.IN1 -sink0_data[43] => src_payload.IN1 -sink0_data[44] => src_payload.IN1 -sink0_data[45] => src_payload.IN1 -sink0_data[46] => src_payload.IN1 -sink0_data[47] => src_payload.IN1 -sink0_data[48] => src_payload.IN1 -sink0_data[49] => src_payload.IN1 -sink0_data[50] => src_payload.IN1 -sink0_data[51] => src_payload.IN1 -sink0_data[52] => src_payload.IN1 -sink0_data[53] => src_payload.IN1 -sink0_data[54] => src_payload.IN1 -sink0_data[55] => src_payload.IN1 -sink0_data[56] => src_payload.IN1 -sink0_data[57] => src_payload.IN1 -sink0_data[58] => src_payload.IN1 -sink0_data[59] => locked.IN1 -sink0_data[59] => src_payload.IN1 -sink0_data[60] => src_payload.IN1 -sink0_data[61] => src_payload.IN1 -sink0_data[62] => src_payload.IN1 -sink0_data[63] => src_payload.IN1 -sink0_data[64] => src_payload.IN1 -sink0_data[65] => src_payload.IN1 -sink0_data[66] => src_payload.IN1 -sink0_data[67] => src_payload.IN1 -sink0_data[68] => src_payload.IN1 -sink0_data[69] => src_payload.IN1 -sink0_data[70] => src_payload.IN1 -sink0_data[71] => src_payload.IN1 -sink0_data[72] => src_payload.IN1 -sink0_data[73] => src_payload.IN1 -sink0_data[74] => src_payload.IN1 -sink0_data[75] => src_payload.IN1 -sink0_data[76] => src_payload.IN1 -sink0_data[77] => src_payload.IN1 -sink0_data[78] => src_payload.IN1 -sink0_data[79] => src_payload.IN1 -sink0_data[80] => src_payload.IN1 -sink0_data[81] => src_payload.IN1 -sink0_data[82] => src_payload.IN1 -sink0_data[83] => src_payload.IN1 -sink0_data[84] => src_payload.IN1 -sink0_data[85] => src_payload.IN1 -sink0_data[86] => src_payload.IN1 -sink0_data[87] => src_payload.IN1 -sink0_data[88] => src_payload.IN1 -sink0_data[89] => src_payload.IN1 -sink0_data[90] => src_payload.IN1 -sink0_data[91] => src_payload.IN1 -sink0_data[92] => src_payload.IN1 -sink0_data[93] => src_payload.IN1 -sink0_data[94] => src_payload.IN1 -sink0_data[95] => src_payload.IN1 -sink0_channel[0] => src_payload.IN1 -sink0_channel[1] => src_payload.IN1 -sink0_channel[2] => src_payload.IN1 -sink0_channel[3] => src_payload.IN1 -sink0_channel[4] => src_payload.IN1 -sink0_channel[5] => src_payload.IN1 -sink0_channel[6] => src_payload.IN1 -sink0_channel[7] => src_payload.IN1 -sink0_channel[8] => src_payload.IN1 -sink0_channel[9] => src_payload.IN1 -sink0_channel[10] => src_payload.IN1 -sink0_channel[11] => src_payload.IN1 -sink0_channel[12] => src_payload.IN1 -sink0_channel[13] => src_payload.IN1 -sink0_channel[14] => src_payload.IN1 -sink0_channel[15] => src_payload.IN1 -sink0_channel[16] => src_payload.IN1 -sink0_channel[17] => src_payload.IN1 -sink0_startofpacket => src_payload.IN1 -sink0_endofpacket => src_payload.IN1 -sink0_ready <= sink0_ready.DB_MAX_OUTPUT_PORT_TYPE -sink1_valid => request.IN1 -sink1_valid => src_valid.IN1 -sink1_data[0] => src_payload.IN1 -sink1_data[1] => src_payload.IN1 -sink1_data[2] => src_payload.IN1 -sink1_data[3] => src_payload.IN1 -sink1_data[4] => src_payload.IN1 -sink1_data[5] => src_payload.IN1 -sink1_data[6] => src_payload.IN1 -sink1_data[7] => src_payload.IN1 -sink1_data[8] => src_payload.IN1 -sink1_data[9] => src_payload.IN1 -sink1_data[10] => src_payload.IN1 -sink1_data[11] => src_payload.IN1 -sink1_data[12] => src_payload.IN1 -sink1_data[13] => src_payload.IN1 -sink1_data[14] => src_payload.IN1 -sink1_data[15] => src_payload.IN1 -sink1_data[16] => src_payload.IN1 -sink1_data[17] => src_payload.IN1 -sink1_data[18] => src_payload.IN1 -sink1_data[19] => src_payload.IN1 -sink1_data[20] => src_payload.IN1 -sink1_data[21] => src_payload.IN1 -sink1_data[22] => src_payload.IN1 -sink1_data[23] => src_payload.IN1 -sink1_data[24] => src_payload.IN1 -sink1_data[25] => src_payload.IN1 -sink1_data[26] => src_payload.IN1 -sink1_data[27] => src_payload.IN1 -sink1_data[28] => src_payload.IN1 -sink1_data[29] => src_payload.IN1 -sink1_data[30] => src_payload.IN1 -sink1_data[31] => src_payload.IN1 -sink1_data[32] => src_payload.IN1 -sink1_data[33] => src_payload.IN1 -sink1_data[34] => src_payload.IN1 -sink1_data[35] => src_payload.IN1 -sink1_data[36] => src_payload.IN1 -sink1_data[37] => src_payload.IN1 -sink1_data[38] => src_payload.IN1 -sink1_data[39] => src_payload.IN1 -sink1_data[40] => src_payload.IN1 -sink1_data[41] => src_payload.IN1 -sink1_data[42] => src_payload.IN1 -sink1_data[43] => src_payload.IN1 -sink1_data[44] => src_payload.IN1 -sink1_data[45] => src_payload.IN1 -sink1_data[46] => src_payload.IN1 -sink1_data[47] => src_payload.IN1 -sink1_data[48] => src_payload.IN1 -sink1_data[49] => src_payload.IN1 -sink1_data[50] => src_payload.IN1 -sink1_data[51] => src_payload.IN1 -sink1_data[52] => src_payload.IN1 -sink1_data[53] => src_payload.IN1 -sink1_data[54] => src_payload.IN1 -sink1_data[55] => src_payload.IN1 -sink1_data[56] => src_payload.IN1 -sink1_data[57] => src_payload.IN1 -sink1_data[58] => src_payload.IN1 -sink1_data[59] => locked.IN1 -sink1_data[59] => src_payload.IN1 -sink1_data[60] => src_payload.IN1 -sink1_data[61] => src_payload.IN1 -sink1_data[62] => src_payload.IN1 -sink1_data[63] => src_payload.IN1 -sink1_data[64] => src_payload.IN1 -sink1_data[65] => src_payload.IN1 -sink1_data[66] => src_payload.IN1 -sink1_data[67] => src_payload.IN1 -sink1_data[68] => src_payload.IN1 -sink1_data[69] => src_payload.IN1 -sink1_data[70] => src_payload.IN1 -sink1_data[71] => src_payload.IN1 -sink1_data[72] => src_payload.IN1 -sink1_data[73] => src_payload.IN1 -sink1_data[74] => src_payload.IN1 -sink1_data[75] => src_payload.IN1 -sink1_data[76] => src_payload.IN1 -sink1_data[77] => src_payload.IN1 -sink1_data[78] => src_payload.IN1 -sink1_data[79] => src_payload.IN1 -sink1_data[80] => src_payload.IN1 -sink1_data[81] => src_payload.IN1 -sink1_data[82] => src_payload.IN1 -sink1_data[83] => src_payload.IN1 -sink1_data[84] => src_payload.IN1 -sink1_data[85] => src_payload.IN1 -sink1_data[86] => src_payload.IN1 -sink1_data[87] => src_payload.IN1 -sink1_data[88] => src_payload.IN1 -sink1_data[89] => src_payload.IN1 -sink1_data[90] => src_payload.IN1 -sink1_data[91] => src_payload.IN1 -sink1_data[92] => src_payload.IN1 -sink1_data[93] => src_payload.IN1 -sink1_data[94] => src_payload.IN1 -sink1_data[95] => src_payload.IN1 -sink1_channel[0] => src_payload.IN1 -sink1_channel[1] => src_payload.IN1 -sink1_channel[2] => src_payload.IN1 -sink1_channel[3] => src_payload.IN1 -sink1_channel[4] => src_payload.IN1 -sink1_channel[5] => src_payload.IN1 -sink1_channel[6] => src_payload.IN1 -sink1_channel[7] => src_payload.IN1 -sink1_channel[8] => src_payload.IN1 -sink1_channel[9] => src_payload.IN1 -sink1_channel[10] => src_payload.IN1 -sink1_channel[11] => src_payload.IN1 -sink1_channel[12] => src_payload.IN1 -sink1_channel[13] => src_payload.IN1 -sink1_channel[14] => src_payload.IN1 -sink1_channel[15] => src_payload.IN1 -sink1_channel[16] => src_payload.IN1 -sink1_channel[17] => src_payload.IN1 -sink1_startofpacket => src_payload.IN1 -sink1_endofpacket => src_payload.IN1 -sink1_ready <= sink1_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= src_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= src_payload[0].DB_MAX_OUTPUT_PORT_TYPE -src_ready => last_cycle.IN0 -src_ready => sink0_ready.IN1 -src_ready => sink1_ready.IN1 -clk => clk.IN1 -reset => reset.IN1 - - -|lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb -clk => top_priority_reg[0].CLK -clk => top_priority_reg[1].CLK -reset => top_priority_reg[0].PRESET -reset => top_priority_reg[1].ACLR -request[0] => grant_double_vector[0].IN1 -request[0] => grant_double_vector[2].IN1 -request[0] => WideOr0.IN0 -request[0] => _.IN1 -request[0] => _.IN1 -request[1] => grant_double_vector[1].IN1 -request[1] => grant_double_vector[3].IN1 -request[1] => WideOr0.IN1 -request[1] => _.IN1 -request[1] => _.IN1 -grant[0] <= grant.DB_MAX_OUTPUT_PORT_TYPE -grant[1] <= grant.DB_MAX_OUTPUT_PORT_TYPE -increment_top_priority => top_priority_reg.OUTPUTSELECT -increment_top_priority => top_priority_reg.OUTPUTSELECT -save_top_priority => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -a[0] => sum.IN0 -a[0] => full_adder.cout[0].IN0 -a[1] => cout.IN0 -a[1] => cout.IN0 -a[2] => cout.IN0 -a[2] => cout.IN0 -a[3] => sum.IN0 -b[0] => sum.IN1 -b[0] => full_adder.cout[0].IN1 -b[1] => cout.IN1 -b[1] => cout.IN1 -b[2] => cout.IN1 -b[2] => cout.IN1 -b[3] => sum.IN1 -sum[0] <= sum.DB_MAX_OUTPUT_PORT_TYPE -sum[1] <= sum.DB_MAX_OUTPUT_PORT_TYPE -sum[2] <= sum.DB_MAX_OUTPUT_PORT_TYPE -sum[3] <= sum.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux -sink_valid[0] => src0_valid.IN0 -sink_valid[0] => src1_valid.IN0 -sink_data[0] => src1_data[0].DATAIN -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src1_data[1].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src1_data[2].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src1_data[3].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src1_data[4].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src1_data[5].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src1_data[6].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src1_data[7].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src1_data[8].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src1_data[9].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src1_data[10].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src1_data[11].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src1_data[12].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src1_data[13].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src1_data[14].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src1_data[15].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src1_data[16].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src1_data[17].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src1_data[18].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src1_data[19].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src1_data[20].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src1_data[21].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src1_data[22].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src1_data[23].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src1_data[24].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src1_data[25].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src1_data[26].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src1_data[27].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src1_data[28].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src1_data[29].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src1_data[30].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src1_data[31].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src1_data[32].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src1_data[33].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src1_data[34].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src1_data[35].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src1_data[36].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src1_data[37].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src1_data[38].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src1_data[39].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src1_data[40].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src1_data[41].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src1_data[42].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src1_data[43].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src1_data[44].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src1_data[45].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src1_data[46].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src1_data[47].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src1_data[48].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src1_data[49].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src1_data[50].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src1_data[51].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src1_data[52].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src1_data[53].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src1_data[54].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src1_data[55].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src1_data[56].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src1_data[57].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src1_data[58].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src1_data[59].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src1_data[60].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src1_data[61].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src1_data[62].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src1_data[63].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src1_data[64].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src1_data[65].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src1_data[66].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src1_data[67].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src1_data[68].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src1_data[69].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src1_data[70].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src1_data[71].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src1_data[72].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src1_data[73].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src1_data[74].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src1_data[75].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src1_data[76].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src1_data[77].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src1_data[78].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src1_data[79].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src1_data[80].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src1_data[81].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src1_data[82].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src1_data[83].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src1_data[84].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src1_data[85].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src1_data[86].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src1_data[87].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src1_data[88].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src1_data[89].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src1_data[90].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src1_data[91].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src1_data[92].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src1_data[93].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src1_data[94].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src1_data[95].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src1_valid.IN1 -sink_channel[1] => sink_ready.IN0 -sink_channel[2] => src1_channel[0].DATAIN -sink_channel[2] => src0_channel[0].DATAIN -sink_channel[3] => src1_channel[1].DATAIN -sink_channel[3] => src0_channel[1].DATAIN -sink_channel[4] => src1_channel[2].DATAIN -sink_channel[4] => src0_channel[2].DATAIN -sink_channel[5] => src1_channel[3].DATAIN -sink_channel[5] => src0_channel[3].DATAIN -sink_channel[6] => src1_channel[4].DATAIN -sink_channel[6] => src0_channel[4].DATAIN -sink_channel[7] => src1_channel[5].DATAIN -sink_channel[7] => src0_channel[5].DATAIN -sink_channel[8] => src1_channel[6].DATAIN -sink_channel[8] => src0_channel[6].DATAIN -sink_channel[9] => src1_channel[7].DATAIN -sink_channel[9] => src0_channel[7].DATAIN -sink_channel[10] => src1_channel[8].DATAIN -sink_channel[10] => src0_channel[8].DATAIN -sink_channel[11] => src1_channel[9].DATAIN -sink_channel[11] => src0_channel[9].DATAIN -sink_channel[12] => src1_channel[10].DATAIN -sink_channel[12] => src0_channel[10].DATAIN -sink_channel[13] => src1_channel[11].DATAIN -sink_channel[13] => src0_channel[11].DATAIN -sink_channel[14] => src1_channel[12].DATAIN -sink_channel[14] => src0_channel[12].DATAIN -sink_channel[15] => src1_channel[13].DATAIN -sink_channel[15] => src0_channel[13].DATAIN -sink_channel[16] => src1_channel[14].DATAIN -sink_channel[16] => src0_channel[14].DATAIN -sink_channel[17] => src1_channel[15].DATAIN -sink_channel[17] => src0_channel[15].DATAIN -sink_startofpacket => src1_startofpacket.DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src1_endofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -src1_valid <= src1_valid.DB_MAX_OUTPUT_PORT_TYPE -src1_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src1_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src1_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src1_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src1_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src1_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src1_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src1_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src1_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src1_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src1_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src1_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src1_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src1_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src1_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src1_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src1_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src1_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src1_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src1_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src1_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src1_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src1_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src1_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src1_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src1_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src1_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src1_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src1_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src1_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src1_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src1_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src1_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src1_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src1_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src1_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src1_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src1_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src1_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src1_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src1_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src1_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src1_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src1_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src1_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src1_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src1_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src1_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src1_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src1_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src1_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src1_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src1_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src1_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src1_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src1_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src1_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src1_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src1_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src1_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src1_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src1_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src1_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src1_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src1_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src1_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src1_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src1_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src1_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src1_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src1_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src1_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src1_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src1_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src1_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src1_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src1_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src1_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src1_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src1_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src1_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src1_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src1_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src1_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src1_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src1_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src1_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src1_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src1_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src1_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src1_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src1_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src1_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src1_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src1_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src1_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[0] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[1] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[2] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[3] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[4] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[5] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[6] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[7] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[8] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[9] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[10] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[11] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[12] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[13] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[14] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[15] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[16] <= -src1_channel[17] <= -src1_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src1_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src1_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux_001 -sink_valid[0] => src0_valid.IN0 -sink_valid[0] => src1_valid.IN0 -sink_data[0] => src1_data[0].DATAIN -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src1_data[1].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src1_data[2].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src1_data[3].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src1_data[4].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src1_data[5].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src1_data[6].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src1_data[7].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src1_data[8].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src1_data[9].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src1_data[10].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src1_data[11].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src1_data[12].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src1_data[13].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src1_data[14].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src1_data[15].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src1_data[16].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src1_data[17].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src1_data[18].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src1_data[19].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src1_data[20].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src1_data[21].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src1_data[22].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src1_data[23].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src1_data[24].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src1_data[25].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src1_data[26].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src1_data[27].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src1_data[28].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src1_data[29].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src1_data[30].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src1_data[31].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src1_data[32].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src1_data[33].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src1_data[34].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src1_data[35].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src1_data[36].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src1_data[37].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src1_data[38].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src1_data[39].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src1_data[40].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src1_data[41].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src1_data[42].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src1_data[43].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src1_data[44].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src1_data[45].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src1_data[46].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src1_data[47].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src1_data[48].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src1_data[49].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src1_data[50].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src1_data[51].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src1_data[52].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src1_data[53].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src1_data[54].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src1_data[55].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src1_data[56].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src1_data[57].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src1_data[58].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src1_data[59].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src1_data[60].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src1_data[61].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src1_data[62].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src1_data[63].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src1_data[64].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src1_data[65].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src1_data[66].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src1_data[67].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src1_data[68].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src1_data[69].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src1_data[70].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src1_data[71].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src1_data[72].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src1_data[73].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src1_data[74].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src1_data[75].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src1_data[76].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src1_data[77].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src1_data[78].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src1_data[79].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src1_data[80].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src1_data[81].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src1_data[82].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src1_data[83].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src1_data[84].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src1_data[85].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src1_data[86].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src1_data[87].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src1_data[88].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src1_data[89].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src1_data[90].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src1_data[91].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src1_data[92].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src1_data[93].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src1_data[94].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src1_data[95].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src1_valid.IN1 -sink_channel[1] => sink_ready.IN0 -sink_channel[2] => src1_channel[0].DATAIN -sink_channel[2] => src0_channel[0].DATAIN -sink_channel[3] => src1_channel[1].DATAIN -sink_channel[3] => src0_channel[1].DATAIN -sink_channel[4] => src1_channel[2].DATAIN -sink_channel[4] => src0_channel[2].DATAIN -sink_channel[5] => src1_channel[3].DATAIN -sink_channel[5] => src0_channel[3].DATAIN -sink_channel[6] => src1_channel[4].DATAIN -sink_channel[6] => src0_channel[4].DATAIN -sink_channel[7] => src1_channel[5].DATAIN -sink_channel[7] => src0_channel[5].DATAIN -sink_channel[8] => src1_channel[6].DATAIN -sink_channel[8] => src0_channel[6].DATAIN -sink_channel[9] => src1_channel[7].DATAIN -sink_channel[9] => src0_channel[7].DATAIN -sink_channel[10] => src1_channel[8].DATAIN -sink_channel[10] => src0_channel[8].DATAIN -sink_channel[11] => src1_channel[9].DATAIN -sink_channel[11] => src0_channel[9].DATAIN -sink_channel[12] => src1_channel[10].DATAIN -sink_channel[12] => src0_channel[10].DATAIN -sink_channel[13] => src1_channel[11].DATAIN -sink_channel[13] => src0_channel[11].DATAIN -sink_channel[14] => src1_channel[12].DATAIN -sink_channel[14] => src0_channel[12].DATAIN -sink_channel[15] => src1_channel[13].DATAIN -sink_channel[15] => src0_channel[13].DATAIN -sink_channel[16] => src1_channel[14].DATAIN -sink_channel[16] => src0_channel[14].DATAIN -sink_channel[17] => src1_channel[15].DATAIN -sink_channel[17] => src0_channel[15].DATAIN -sink_startofpacket => src1_startofpacket.DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src1_endofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -src1_valid <= src1_valid.DB_MAX_OUTPUT_PORT_TYPE -src1_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src1_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src1_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src1_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src1_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src1_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src1_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src1_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src1_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src1_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src1_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src1_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src1_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src1_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src1_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src1_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src1_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src1_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src1_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src1_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src1_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src1_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src1_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src1_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src1_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src1_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src1_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src1_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src1_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src1_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src1_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src1_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src1_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src1_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src1_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src1_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src1_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src1_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src1_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src1_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src1_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src1_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src1_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src1_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src1_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src1_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src1_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src1_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src1_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src1_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src1_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src1_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src1_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src1_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src1_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src1_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src1_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src1_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src1_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src1_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src1_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src1_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src1_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src1_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src1_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src1_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src1_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src1_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src1_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src1_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src1_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src1_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src1_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src1_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src1_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src1_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src1_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src1_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src1_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src1_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src1_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src1_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src1_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src1_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src1_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src1_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src1_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src1_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src1_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src1_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src1_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src1_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src1_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src1_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src1_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src1_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[0] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[1] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[2] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[3] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[4] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[5] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[6] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[7] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[8] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[9] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[10] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[11] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[12] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[13] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[14] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[15] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[16] <= -src1_channel[17] <= -src1_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src1_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src1_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_002 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_003 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_004 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_005 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_006 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_007 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_008 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_009 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_010 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_011 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_012 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_013 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_014 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_015 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_016 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_017 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux -sink0_valid => request[0].IN1 -sink0_data[0] => src_payload.IN1 -sink0_data[1] => src_payload.IN1 -sink0_data[2] => src_payload.IN1 -sink0_data[3] => src_payload.IN1 -sink0_data[4] => src_payload.IN1 -sink0_data[5] => src_payload.IN1 -sink0_data[6] => src_payload.IN1 -sink0_data[7] => src_payload.IN1 -sink0_data[8] => src_payload.IN1 -sink0_data[9] => src_payload.IN1 -sink0_data[10] => src_payload.IN1 -sink0_data[11] => src_payload.IN1 -sink0_data[12] => src_payload.IN1 -sink0_data[13] => src_payload.IN1 -sink0_data[14] => src_payload.IN1 -sink0_data[15] => src_payload.IN1 -sink0_data[16] => src_payload.IN1 -sink0_data[17] => src_payload.IN1 -sink0_data[18] => src_payload.IN1 -sink0_data[19] => src_payload.IN1 -sink0_data[20] => src_payload.IN1 -sink0_data[21] => src_payload.IN1 -sink0_data[22] => src_payload.IN1 -sink0_data[23] => src_payload.IN1 -sink0_data[24] => src_payload.IN1 -sink0_data[25] => src_payload.IN1 -sink0_data[26] => src_payload.IN1 -sink0_data[27] => src_payload.IN1 -sink0_data[28] => src_payload.IN1 -sink0_data[29] => src_payload.IN1 -sink0_data[30] => src_payload.IN1 -sink0_data[31] => src_payload.IN1 -sink0_data[32] => src_payload.IN1 -sink0_data[33] => src_payload.IN1 -sink0_data[34] => src_payload.IN1 -sink0_data[35] => src_payload.IN1 -sink0_data[36] => src_payload.IN1 -sink0_data[37] => src_payload.IN1 -sink0_data[38] => src_payload.IN1 -sink0_data[39] => src_payload.IN1 -sink0_data[40] => src_payload.IN1 -sink0_data[41] => src_payload.IN1 -sink0_data[42] => src_payload.IN1 -sink0_data[43] => src_payload.IN1 -sink0_data[44] => src_payload.IN1 -sink0_data[45] => src_payload.IN1 -sink0_data[46] => src_payload.IN1 -sink0_data[47] => src_payload.IN1 -sink0_data[48] => src_payload.IN1 -sink0_data[49] => src_payload.IN1 -sink0_data[50] => src_payload.IN1 -sink0_data[51] => src_payload.IN1 -sink0_data[52] => src_payload.IN1 -sink0_data[53] => src_payload.IN1 -sink0_data[54] => src_payload.IN1 -sink0_data[55] => src_payload.IN1 -sink0_data[56] => src_payload.IN1 -sink0_data[57] => src_payload.IN1 -sink0_data[58] => src_payload.IN1 -sink0_data[59] => src_payload.IN1 -sink0_data[59] => last_cycle.IN1 -sink0_data[60] => src_payload.IN1 -sink0_data[61] => src_payload.IN1 -sink0_data[62] => src_payload.IN1 -sink0_data[63] => src_payload.IN1 -sink0_data[64] => src_payload.IN1 -sink0_data[65] => src_payload.IN1 -sink0_data[66] => src_payload.IN1 -sink0_data[67] => src_payload.IN1 -sink0_data[68] => src_payload.IN1 -sink0_data[69] => src_payload.IN1 -sink0_data[70] => src_payload.IN1 -sink0_data[71] => src_payload.IN1 -sink0_data[72] => src_payload.IN1 -sink0_data[73] => src_payload.IN1 -sink0_data[74] => src_payload.IN1 -sink0_data[75] => src_payload.IN1 -sink0_data[76] => src_payload.IN1 -sink0_data[77] => src_payload.IN1 -sink0_data[78] => src_payload.IN1 -sink0_data[79] => src_payload.IN1 -sink0_data[80] => src_payload.IN1 -sink0_data[81] => src_payload.IN1 -sink0_data[82] => src_payload.IN1 -sink0_data[83] => src_payload.IN1 -sink0_data[84] => src_payload.IN1 -sink0_data[85] => src_payload.IN1 -sink0_data[86] => src_payload.IN1 -sink0_data[87] => src_payload.IN1 -sink0_data[88] => src_payload.IN1 -sink0_data[89] => src_payload.IN1 -sink0_data[90] => src_payload.IN1 -sink0_data[91] => src_payload.IN1 -sink0_data[92] => src_payload.IN1 -sink0_data[93] => src_payload.IN1 -sink0_data[94] => src_payload.IN1 -sink0_data[95] => src_payload.IN1 -sink0_channel[0] => src_payload.IN1 -sink0_channel[1] => src_payload.IN1 -sink0_channel[2] => src_payload.IN1 -sink0_channel[3] => src_payload.IN1 -sink0_channel[4] => src_payload.IN1 -sink0_channel[5] => src_payload.IN1 -sink0_channel[6] => src_payload.IN1 -sink0_channel[7] => src_payload.IN1 -sink0_channel[8] => src_payload.IN1 -sink0_channel[9] => src_payload.IN1 -sink0_channel[10] => src_payload.IN1 -sink0_channel[11] => src_payload.IN1 -sink0_channel[12] => src_payload.IN1 -sink0_channel[13] => src_payload.IN1 -sink0_channel[14] => src_payload.IN1 -sink0_channel[15] => src_payload.IN1 -sink0_channel[16] => src_payload.IN1 -sink0_channel[17] => src_payload.IN1 -sink0_startofpacket => src_payload.IN1 -sink0_endofpacket => src_payload.IN1 -sink0_ready <= sink0_ready.DB_MAX_OUTPUT_PORT_TYPE -sink1_valid => request[1].IN1 -sink1_data[0] => src_payload.IN1 -sink1_data[1] => src_payload.IN1 -sink1_data[2] => src_payload.IN1 -sink1_data[3] => src_payload.IN1 -sink1_data[4] => src_payload.IN1 -sink1_data[5] => src_payload.IN1 -sink1_data[6] => src_payload.IN1 -sink1_data[7] => src_payload.IN1 -sink1_data[8] => src_payload.IN1 -sink1_data[9] => src_payload.IN1 -sink1_data[10] => src_payload.IN1 -sink1_data[11] => src_payload.IN1 -sink1_data[12] => src_payload.IN1 -sink1_data[13] => src_payload.IN1 -sink1_data[14] => src_payload.IN1 -sink1_data[15] => src_payload.IN1 -sink1_data[16] => src_payload.IN1 -sink1_data[17] => src_payload.IN1 -sink1_data[18] => src_payload.IN1 -sink1_data[19] => src_payload.IN1 -sink1_data[20] => src_payload.IN1 -sink1_data[21] => src_payload.IN1 -sink1_data[22] => src_payload.IN1 -sink1_data[23] => src_payload.IN1 -sink1_data[24] => src_payload.IN1 -sink1_data[25] => src_payload.IN1 -sink1_data[26] => src_payload.IN1 -sink1_data[27] => src_payload.IN1 -sink1_data[28] => src_payload.IN1 -sink1_data[29] => src_payload.IN1 -sink1_data[30] => src_payload.IN1 -sink1_data[31] => src_payload.IN1 -sink1_data[32] => src_payload.IN1 -sink1_data[33] => src_payload.IN1 -sink1_data[34] => src_payload.IN1 -sink1_data[35] => src_payload.IN1 -sink1_data[36] => src_payload.IN1 -sink1_data[37] => src_payload.IN1 -sink1_data[38] => src_payload.IN1 -sink1_data[39] => src_payload.IN1 -sink1_data[40] => src_payload.IN1 -sink1_data[41] => src_payload.IN1 -sink1_data[42] => src_payload.IN1 -sink1_data[43] => src_payload.IN1 -sink1_data[44] => src_payload.IN1 -sink1_data[45] => src_payload.IN1 -sink1_data[46] => src_payload.IN1 -sink1_data[47] => src_payload.IN1 -sink1_data[48] => src_payload.IN1 -sink1_data[49] => src_payload.IN1 -sink1_data[50] => src_payload.IN1 -sink1_data[51] => src_payload.IN1 -sink1_data[52] => src_payload.IN1 -sink1_data[53] => src_payload.IN1 -sink1_data[54] => src_payload.IN1 -sink1_data[55] => src_payload.IN1 -sink1_data[56] => src_payload.IN1 -sink1_data[57] => src_payload.IN1 -sink1_data[58] => src_payload.IN1 -sink1_data[59] => src_payload.IN1 -sink1_data[59] => last_cycle.IN1 -sink1_data[60] => src_payload.IN1 -sink1_data[61] => src_payload.IN1 -sink1_data[62] => src_payload.IN1 -sink1_data[63] => src_payload.IN1 -sink1_data[64] => src_payload.IN1 -sink1_data[65] => src_payload.IN1 -sink1_data[66] => src_payload.IN1 -sink1_data[67] => src_payload.IN1 -sink1_data[68] => src_payload.IN1 -sink1_data[69] => src_payload.IN1 -sink1_data[70] => src_payload.IN1 -sink1_data[71] => src_payload.IN1 -sink1_data[72] => src_payload.IN1 -sink1_data[73] => src_payload.IN1 -sink1_data[74] => src_payload.IN1 -sink1_data[75] => src_payload.IN1 -sink1_data[76] => src_payload.IN1 -sink1_data[77] => src_payload.IN1 -sink1_data[78] => src_payload.IN1 -sink1_data[79] => src_payload.IN1 -sink1_data[80] => src_payload.IN1 -sink1_data[81] => src_payload.IN1 -sink1_data[82] => src_payload.IN1 -sink1_data[83] => src_payload.IN1 -sink1_data[84] => src_payload.IN1 -sink1_data[85] => src_payload.IN1 -sink1_data[86] => src_payload.IN1 -sink1_data[87] => src_payload.IN1 -sink1_data[88] => src_payload.IN1 -sink1_data[89] => src_payload.IN1 -sink1_data[90] => src_payload.IN1 -sink1_data[91] => src_payload.IN1 -sink1_data[92] => src_payload.IN1 -sink1_data[93] => src_payload.IN1 -sink1_data[94] => src_payload.IN1 -sink1_data[95] => src_payload.IN1 -sink1_channel[0] => src_payload.IN1 -sink1_channel[1] => src_payload.IN1 -sink1_channel[2] => src_payload.IN1 -sink1_channel[3] => src_payload.IN1 -sink1_channel[4] => src_payload.IN1 -sink1_channel[5] => src_payload.IN1 -sink1_channel[6] => src_payload.IN1 -sink1_channel[7] => src_payload.IN1 -sink1_channel[8] => src_payload.IN1 -sink1_channel[9] => src_payload.IN1 -sink1_channel[10] => src_payload.IN1 -sink1_channel[11] => src_payload.IN1 -sink1_channel[12] => src_payload.IN1 -sink1_channel[13] => src_payload.IN1 -sink1_channel[14] => src_payload.IN1 -sink1_channel[15] => src_payload.IN1 -sink1_channel[16] => src_payload.IN1 -sink1_channel[17] => src_payload.IN1 -sink1_startofpacket => src_payload.IN1 -sink1_endofpacket => src_payload.IN1 -sink1_ready <= sink1_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= src_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= src_payload[0].DB_MAX_OUTPUT_PORT_TYPE -src_ready => last_cycle.IN0 -src_ready => sink0_ready.IN1 -src_ready => sink1_ready.IN1 -clk => clk.IN1 -reset => reset.IN1 - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -request[0] => grant[0].DATAIN -request[0] => _.IN1 -request[0] => _.IN1 -request[1] => grant[1].DATAIN -request[1] => _.IN1 -request[1] => _.IN1 -grant[0] <= request[0].DB_MAX_OUTPUT_PORT_TYPE -grant[1] <= request[1].DB_MAX_OUTPUT_PORT_TYPE -increment_top_priority => ~NO_FANOUT~ -save_top_priority => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -a[0] => sum.IN0 -a[0] => full_adder.cout[0].IN0 -a[1] => cout.IN0 -a[1] => cout.IN0 -a[2] => cout.IN0 -a[2] => cout.IN0 -a[3] => sum.IN0 -b[0] => sum.IN1 -b[0] => full_adder.cout[0].IN1 -b[1] => cout.IN1 -b[1] => cout.IN1 -b[2] => cout.IN1 -b[2] => cout.IN1 -b[3] => sum.IN1 -sum[0] <= sum.DB_MAX_OUTPUT_PORT_TYPE -sum[1] <= sum.DB_MAX_OUTPUT_PORT_TYPE -sum[2] <= sum.DB_MAX_OUTPUT_PORT_TYPE -sum[3] <= sum.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001 -sink0_valid => request[0].IN1 -sink0_data[0] => src_payload.IN1 -sink0_data[1] => src_payload.IN1 -sink0_data[2] => src_payload.IN1 -sink0_data[3] => src_payload.IN1 -sink0_data[4] => src_payload.IN1 -sink0_data[5] => src_payload.IN1 -sink0_data[6] => src_payload.IN1 -sink0_data[7] => src_payload.IN1 -sink0_data[8] => src_payload.IN1 -sink0_data[9] => src_payload.IN1 -sink0_data[10] => src_payload.IN1 -sink0_data[11] => src_payload.IN1 -sink0_data[12] => src_payload.IN1 -sink0_data[13] => src_payload.IN1 -sink0_data[14] => src_payload.IN1 -sink0_data[15] => src_payload.IN1 -sink0_data[16] => src_payload.IN1 -sink0_data[17] => src_payload.IN1 -sink0_data[18] => src_payload.IN1 -sink0_data[19] => src_payload.IN1 -sink0_data[20] => src_payload.IN1 -sink0_data[21] => src_payload.IN1 -sink0_data[22] => src_payload.IN1 -sink0_data[23] => src_payload.IN1 -sink0_data[24] => src_payload.IN1 -sink0_data[25] => src_payload.IN1 -sink0_data[26] => src_payload.IN1 -sink0_data[27] => src_payload.IN1 -sink0_data[28] => src_payload.IN1 -sink0_data[29] => src_payload.IN1 -sink0_data[30] => src_payload.IN1 -sink0_data[31] => src_payload.IN1 -sink0_data[32] => src_payload.IN1 -sink0_data[33] => src_payload.IN1 -sink0_data[34] => src_payload.IN1 -sink0_data[35] => src_payload.IN1 -sink0_data[36] => src_payload.IN1 -sink0_data[37] => src_payload.IN1 -sink0_data[38] => src_payload.IN1 -sink0_data[39] => src_payload.IN1 -sink0_data[40] => src_payload.IN1 -sink0_data[41] => src_payload.IN1 -sink0_data[42] => src_payload.IN1 -sink0_data[43] => src_payload.IN1 -sink0_data[44] => src_payload.IN1 -sink0_data[45] => src_payload.IN1 -sink0_data[46] => src_payload.IN1 -sink0_data[47] => src_payload.IN1 -sink0_data[48] => src_payload.IN1 -sink0_data[49] => src_payload.IN1 -sink0_data[50] => src_payload.IN1 -sink0_data[51] => src_payload.IN1 -sink0_data[52] => src_payload.IN1 -sink0_data[53] => src_payload.IN1 -sink0_data[54] => src_payload.IN1 -sink0_data[55] => src_payload.IN1 -sink0_data[56] => src_payload.IN1 -sink0_data[57] => src_payload.IN1 -sink0_data[58] => src_payload.IN1 -sink0_data[59] => src_payload.IN1 -sink0_data[59] => last_cycle.IN1 -sink0_data[60] => src_payload.IN1 -sink0_data[61] => src_payload.IN1 -sink0_data[62] => src_payload.IN1 -sink0_data[63] => src_payload.IN1 -sink0_data[64] => src_payload.IN1 -sink0_data[65] => src_payload.IN1 -sink0_data[66] => src_payload.IN1 -sink0_data[67] => src_payload.IN1 -sink0_data[68] => src_payload.IN1 -sink0_data[69] => src_payload.IN1 -sink0_data[70] => src_payload.IN1 -sink0_data[71] => src_payload.IN1 -sink0_data[72] => src_payload.IN1 -sink0_data[73] => src_payload.IN1 -sink0_data[74] => src_payload.IN1 -sink0_data[75] => src_payload.IN1 -sink0_data[76] => src_payload.IN1 -sink0_data[77] => src_payload.IN1 -sink0_data[78] => src_payload.IN1 -sink0_data[79] => src_payload.IN1 -sink0_data[80] => src_payload.IN1 -sink0_data[81] => src_payload.IN1 -sink0_data[82] => src_payload.IN1 -sink0_data[83] => src_payload.IN1 -sink0_data[84] => src_payload.IN1 -sink0_data[85] => src_payload.IN1 -sink0_data[86] => src_payload.IN1 -sink0_data[87] => src_payload.IN1 -sink0_data[88] => src_payload.IN1 -sink0_data[89] => src_payload.IN1 -sink0_data[90] => src_payload.IN1 -sink0_data[91] => src_payload.IN1 -sink0_data[92] => src_payload.IN1 -sink0_data[93] => src_payload.IN1 -sink0_data[94] => src_payload.IN1 -sink0_data[95] => src_payload.IN1 -sink0_channel[0] => src_payload.IN1 -sink0_channel[1] => src_payload.IN1 -sink0_channel[2] => src_payload.IN1 -sink0_channel[3] => src_payload.IN1 -sink0_channel[4] => src_payload.IN1 -sink0_channel[5] => src_payload.IN1 -sink0_channel[6] => src_payload.IN1 -sink0_channel[7] => src_payload.IN1 -sink0_channel[8] => src_payload.IN1 -sink0_channel[9] => src_payload.IN1 -sink0_channel[10] => src_payload.IN1 -sink0_channel[11] => src_payload.IN1 -sink0_channel[12] => src_payload.IN1 -sink0_channel[13] => src_payload.IN1 -sink0_channel[14] => src_payload.IN1 -sink0_channel[15] => src_payload.IN1 -sink0_channel[16] => src_payload.IN1 -sink0_channel[17] => src_payload.IN1 -sink0_startofpacket => src_payload.IN1 -sink0_endofpacket => src_payload.IN1 -sink0_ready <= sink0_ready.DB_MAX_OUTPUT_PORT_TYPE -sink1_valid => request[1].IN1 -sink1_data[0] => src_payload.IN1 -sink1_data[1] => src_payload.IN1 -sink1_data[2] => src_payload.IN1 -sink1_data[3] => src_payload.IN1 -sink1_data[4] => src_payload.IN1 -sink1_data[5] => src_payload.IN1 -sink1_data[6] => src_payload.IN1 -sink1_data[7] => src_payload.IN1 -sink1_data[8] => src_payload.IN1 -sink1_data[9] => src_payload.IN1 -sink1_data[10] => src_payload.IN1 -sink1_data[11] => src_payload.IN1 -sink1_data[12] => src_payload.IN1 -sink1_data[13] => src_payload.IN1 -sink1_data[14] => src_payload.IN1 -sink1_data[15] => src_payload.IN1 -sink1_data[16] => src_payload.IN1 -sink1_data[17] => src_payload.IN1 -sink1_data[18] => src_payload.IN1 -sink1_data[19] => src_payload.IN1 -sink1_data[20] => src_payload.IN1 -sink1_data[21] => src_payload.IN1 -sink1_data[22] => src_payload.IN1 -sink1_data[23] => src_payload.IN1 -sink1_data[24] => src_payload.IN1 -sink1_data[25] => src_payload.IN1 -sink1_data[26] => src_payload.IN1 -sink1_data[27] => src_payload.IN1 -sink1_data[28] => src_payload.IN1 -sink1_data[29] => src_payload.IN1 -sink1_data[30] => src_payload.IN1 -sink1_data[31] => src_payload.IN1 -sink1_data[32] => src_payload.IN1 -sink1_data[33] => src_payload.IN1 -sink1_data[34] => src_payload.IN1 -sink1_data[35] => src_payload.IN1 -sink1_data[36] => src_payload.IN1 -sink1_data[37] => src_payload.IN1 -sink1_data[38] => src_payload.IN1 -sink1_data[39] => src_payload.IN1 -sink1_data[40] => src_payload.IN1 -sink1_data[41] => src_payload.IN1 -sink1_data[42] => src_payload.IN1 -sink1_data[43] => src_payload.IN1 -sink1_data[44] => src_payload.IN1 -sink1_data[45] => src_payload.IN1 -sink1_data[46] => src_payload.IN1 -sink1_data[47] => src_payload.IN1 -sink1_data[48] => src_payload.IN1 -sink1_data[49] => src_payload.IN1 -sink1_data[50] => src_payload.IN1 -sink1_data[51] => src_payload.IN1 -sink1_data[52] => src_payload.IN1 -sink1_data[53] => src_payload.IN1 -sink1_data[54] => src_payload.IN1 -sink1_data[55] => src_payload.IN1 -sink1_data[56] => src_payload.IN1 -sink1_data[57] => src_payload.IN1 -sink1_data[58] => src_payload.IN1 -sink1_data[59] => src_payload.IN1 -sink1_data[59] => last_cycle.IN1 -sink1_data[60] => src_payload.IN1 -sink1_data[61] => src_payload.IN1 -sink1_data[62] => src_payload.IN1 -sink1_data[63] => src_payload.IN1 -sink1_data[64] => src_payload.IN1 -sink1_data[65] => src_payload.IN1 -sink1_data[66] => src_payload.IN1 -sink1_data[67] => src_payload.IN1 -sink1_data[68] => src_payload.IN1 -sink1_data[69] => src_payload.IN1 -sink1_data[70] => src_payload.IN1 -sink1_data[71] => src_payload.IN1 -sink1_data[72] => src_payload.IN1 -sink1_data[73] => src_payload.IN1 -sink1_data[74] => src_payload.IN1 -sink1_data[75] => src_payload.IN1 -sink1_data[76] => src_payload.IN1 -sink1_data[77] => src_payload.IN1 -sink1_data[78] => src_payload.IN1 -sink1_data[79] => src_payload.IN1 -sink1_data[80] => src_payload.IN1 -sink1_data[81] => src_payload.IN1 -sink1_data[82] => src_payload.IN1 -sink1_data[83] => src_payload.IN1 -sink1_data[84] => src_payload.IN1 -sink1_data[85] => src_payload.IN1 -sink1_data[86] => src_payload.IN1 -sink1_data[87] => src_payload.IN1 -sink1_data[88] => src_payload.IN1 -sink1_data[89] => src_payload.IN1 -sink1_data[90] => src_payload.IN1 -sink1_data[91] => src_payload.IN1 -sink1_data[92] => src_payload.IN1 -sink1_data[93] => src_payload.IN1 -sink1_data[94] => src_payload.IN1 -sink1_data[95] => src_payload.IN1 -sink1_channel[0] => src_payload.IN1 -sink1_channel[1] => src_payload.IN1 -sink1_channel[2] => src_payload.IN1 -sink1_channel[3] => src_payload.IN1 -sink1_channel[4] => src_payload.IN1 -sink1_channel[5] => src_payload.IN1 -sink1_channel[6] => src_payload.IN1 -sink1_channel[7] => src_payload.IN1 -sink1_channel[8] => src_payload.IN1 -sink1_channel[9] => src_payload.IN1 -sink1_channel[10] => src_payload.IN1 -sink1_channel[11] => src_payload.IN1 -sink1_channel[12] => src_payload.IN1 -sink1_channel[13] => src_payload.IN1 -sink1_channel[14] => src_payload.IN1 -sink1_channel[15] => src_payload.IN1 -sink1_channel[16] => src_payload.IN1 -sink1_channel[17] => src_payload.IN1 -sink1_startofpacket => src_payload.IN1 -sink1_endofpacket => src_payload.IN1 -sink1_ready <= sink1_ready.DB_MAX_OUTPUT_PORT_TYPE -sink2_valid => request[2].IN1 -sink2_data[0] => src_payload.IN1 -sink2_data[1] => src_payload.IN1 -sink2_data[2] => src_payload.IN1 -sink2_data[3] => src_payload.IN1 -sink2_data[4] => src_payload.IN1 -sink2_data[5] => src_payload.IN1 -sink2_data[6] => src_payload.IN1 -sink2_data[7] => src_payload.IN1 -sink2_data[8] => src_payload.IN1 -sink2_data[9] => src_payload.IN1 -sink2_data[10] => src_payload.IN1 -sink2_data[11] => src_payload.IN1 -sink2_data[12] => src_payload.IN1 -sink2_data[13] => src_payload.IN1 -sink2_data[14] => src_payload.IN1 -sink2_data[15] => src_payload.IN1 -sink2_data[16] => src_payload.IN1 -sink2_data[17] => src_payload.IN1 -sink2_data[18] => src_payload.IN1 -sink2_data[19] => src_payload.IN1 -sink2_data[20] => src_payload.IN1 -sink2_data[21] => src_payload.IN1 -sink2_data[22] => src_payload.IN1 -sink2_data[23] => src_payload.IN1 -sink2_data[24] => src_payload.IN1 -sink2_data[25] => src_payload.IN1 -sink2_data[26] => src_payload.IN1 -sink2_data[27] => src_payload.IN1 -sink2_data[28] => src_payload.IN1 -sink2_data[29] => src_payload.IN1 -sink2_data[30] => src_payload.IN1 -sink2_data[31] => src_payload.IN1 -sink2_data[32] => src_payload.IN1 -sink2_data[33] => src_payload.IN1 -sink2_data[34] => src_payload.IN1 -sink2_data[35] => src_payload.IN1 -sink2_data[36] => src_payload.IN1 -sink2_data[37] => src_payload.IN1 -sink2_data[38] => src_payload.IN1 -sink2_data[39] => src_payload.IN1 -sink2_data[40] => src_payload.IN1 -sink2_data[41] => src_payload.IN1 -sink2_data[42] => src_payload.IN1 -sink2_data[43] => src_payload.IN1 -sink2_data[44] => src_payload.IN1 -sink2_data[45] => src_payload.IN1 -sink2_data[46] => src_payload.IN1 -sink2_data[47] => src_payload.IN1 -sink2_data[48] => src_payload.IN1 -sink2_data[49] => src_payload.IN1 -sink2_data[50] => src_payload.IN1 -sink2_data[51] => src_payload.IN1 -sink2_data[52] => src_payload.IN1 -sink2_data[53] => src_payload.IN1 -sink2_data[54] => src_payload.IN1 -sink2_data[55] => src_payload.IN1 -sink2_data[56] => src_payload.IN1 -sink2_data[57] => src_payload.IN1 -sink2_data[58] => src_payload.IN1 -sink2_data[59] => src_payload.IN1 -sink2_data[59] => last_cycle.IN1 -sink2_data[60] => src_payload.IN1 -sink2_data[61] => src_payload.IN1 -sink2_data[62] => src_payload.IN1 -sink2_data[63] => src_payload.IN1 -sink2_data[64] => src_payload.IN1 -sink2_data[65] => src_payload.IN1 -sink2_data[66] => src_payload.IN1 -sink2_data[67] => src_payload.IN1 -sink2_data[68] => src_payload.IN1 -sink2_data[69] => src_payload.IN1 -sink2_data[70] => src_payload.IN1 -sink2_data[71] => src_payload.IN1 -sink2_data[72] => src_payload.IN1 -sink2_data[73] => src_payload.IN1 -sink2_data[74] => src_payload.IN1 -sink2_data[75] => src_payload.IN1 -sink2_data[76] => src_payload.IN1 -sink2_data[77] => src_payload.IN1 -sink2_data[78] => src_payload.IN1 -sink2_data[79] => src_payload.IN1 -sink2_data[80] => src_payload.IN1 -sink2_data[81] => src_payload.IN1 -sink2_data[82] => src_payload.IN1 -sink2_data[83] => src_payload.IN1 -sink2_data[84] => src_payload.IN1 -sink2_data[85] => src_payload.IN1 -sink2_data[86] => src_payload.IN1 -sink2_data[87] => src_payload.IN1 -sink2_data[88] => src_payload.IN1 -sink2_data[89] => src_payload.IN1 -sink2_data[90] => src_payload.IN1 -sink2_data[91] => src_payload.IN1 -sink2_data[92] => src_payload.IN1 -sink2_data[93] => src_payload.IN1 -sink2_data[94] => src_payload.IN1 -sink2_data[95] => src_payload.IN1 -sink2_channel[0] => src_payload.IN1 -sink2_channel[1] => src_payload.IN1 -sink2_channel[2] => src_payload.IN1 -sink2_channel[3] => src_payload.IN1 -sink2_channel[4] => src_payload.IN1 -sink2_channel[5] => src_payload.IN1 -sink2_channel[6] => src_payload.IN1 -sink2_channel[7] => src_payload.IN1 -sink2_channel[8] => src_payload.IN1 -sink2_channel[9] => src_payload.IN1 -sink2_channel[10] => src_payload.IN1 -sink2_channel[11] => src_payload.IN1 -sink2_channel[12] => src_payload.IN1 -sink2_channel[13] => src_payload.IN1 -sink2_channel[14] => src_payload.IN1 -sink2_channel[15] => src_payload.IN1 -sink2_channel[16] => src_payload.IN1 -sink2_channel[17] => src_payload.IN1 -sink2_startofpacket => src_payload.IN1 -sink2_endofpacket => src_payload.IN1 -sink2_ready <= sink2_ready.DB_MAX_OUTPUT_PORT_TYPE -sink3_valid => request[3].IN1 -sink3_data[0] => src_payload.IN1 -sink3_data[1] => src_payload.IN1 -sink3_data[2] => src_payload.IN1 -sink3_data[3] => src_payload.IN1 -sink3_data[4] => src_payload.IN1 -sink3_data[5] => src_payload.IN1 -sink3_data[6] => src_payload.IN1 -sink3_data[7] => src_payload.IN1 -sink3_data[8] => src_payload.IN1 -sink3_data[9] => src_payload.IN1 -sink3_data[10] => src_payload.IN1 -sink3_data[11] => src_payload.IN1 -sink3_data[12] => src_payload.IN1 -sink3_data[13] => src_payload.IN1 -sink3_data[14] => src_payload.IN1 -sink3_data[15] => src_payload.IN1 -sink3_data[16] => src_payload.IN1 -sink3_data[17] => src_payload.IN1 -sink3_data[18] => src_payload.IN1 -sink3_data[19] => src_payload.IN1 -sink3_data[20] => src_payload.IN1 -sink3_data[21] => src_payload.IN1 -sink3_data[22] => src_payload.IN1 -sink3_data[23] => src_payload.IN1 -sink3_data[24] => src_payload.IN1 -sink3_data[25] => src_payload.IN1 -sink3_data[26] => src_payload.IN1 -sink3_data[27] => src_payload.IN1 -sink3_data[28] => src_payload.IN1 -sink3_data[29] => src_payload.IN1 -sink3_data[30] => src_payload.IN1 -sink3_data[31] => src_payload.IN1 -sink3_data[32] => src_payload.IN1 -sink3_data[33] => src_payload.IN1 -sink3_data[34] => src_payload.IN1 -sink3_data[35] => src_payload.IN1 -sink3_data[36] => src_payload.IN1 -sink3_data[37] => src_payload.IN1 -sink3_data[38] => src_payload.IN1 -sink3_data[39] => src_payload.IN1 -sink3_data[40] => src_payload.IN1 -sink3_data[41] => src_payload.IN1 -sink3_data[42] => src_payload.IN1 -sink3_data[43] => src_payload.IN1 -sink3_data[44] => src_payload.IN1 -sink3_data[45] => src_payload.IN1 -sink3_data[46] => src_payload.IN1 -sink3_data[47] => src_payload.IN1 -sink3_data[48] => src_payload.IN1 -sink3_data[49] => src_payload.IN1 -sink3_data[50] => src_payload.IN1 -sink3_data[51] => src_payload.IN1 -sink3_data[52] => src_payload.IN1 -sink3_data[53] => src_payload.IN1 -sink3_data[54] => src_payload.IN1 -sink3_data[55] => src_payload.IN1 -sink3_data[56] => src_payload.IN1 -sink3_data[57] => src_payload.IN1 -sink3_data[58] => src_payload.IN1 -sink3_data[59] => src_payload.IN1 -sink3_data[59] => last_cycle.IN1 -sink3_data[60] => src_payload.IN1 -sink3_data[61] => src_payload.IN1 -sink3_data[62] => src_payload.IN1 -sink3_data[63] => src_payload.IN1 -sink3_data[64] => src_payload.IN1 -sink3_data[65] => src_payload.IN1 -sink3_data[66] => src_payload.IN1 -sink3_data[67] => src_payload.IN1 -sink3_data[68] => src_payload.IN1 -sink3_data[69] => src_payload.IN1 -sink3_data[70] => src_payload.IN1 -sink3_data[71] => src_payload.IN1 -sink3_data[72] => src_payload.IN1 -sink3_data[73] => src_payload.IN1 -sink3_data[74] => src_payload.IN1 -sink3_data[75] => src_payload.IN1 -sink3_data[76] => src_payload.IN1 -sink3_data[77] => src_payload.IN1 -sink3_data[78] => src_payload.IN1 -sink3_data[79] => src_payload.IN1 -sink3_data[80] => src_payload.IN1 -sink3_data[81] => src_payload.IN1 -sink3_data[82] => src_payload.IN1 -sink3_data[83] => src_payload.IN1 -sink3_data[84] => src_payload.IN1 -sink3_data[85] => src_payload.IN1 -sink3_data[86] => src_payload.IN1 -sink3_data[87] => src_payload.IN1 -sink3_data[88] => src_payload.IN1 -sink3_data[89] => src_payload.IN1 -sink3_data[90] => src_payload.IN1 -sink3_data[91] => src_payload.IN1 -sink3_data[92] => src_payload.IN1 -sink3_data[93] => src_payload.IN1 -sink3_data[94] => src_payload.IN1 -sink3_data[95] => src_payload.IN1 -sink3_channel[0] => src_payload.IN1 -sink3_channel[1] => src_payload.IN1 -sink3_channel[2] => src_payload.IN1 -sink3_channel[3] => src_payload.IN1 -sink3_channel[4] => src_payload.IN1 -sink3_channel[5] => src_payload.IN1 -sink3_channel[6] => src_payload.IN1 -sink3_channel[7] => src_payload.IN1 -sink3_channel[8] => src_payload.IN1 -sink3_channel[9] => src_payload.IN1 -sink3_channel[10] => src_payload.IN1 -sink3_channel[11] => src_payload.IN1 -sink3_channel[12] => src_payload.IN1 -sink3_channel[13] => src_payload.IN1 -sink3_channel[14] => src_payload.IN1 -sink3_channel[15] => src_payload.IN1 -sink3_channel[16] => src_payload.IN1 -sink3_channel[17] => src_payload.IN1 -sink3_startofpacket => src_payload.IN1 -sink3_endofpacket => src_payload.IN1 -sink3_ready <= sink3_ready.DB_MAX_OUTPUT_PORT_TYPE -sink4_valid => request[4].IN1 -sink4_data[0] => src_payload.IN1 -sink4_data[1] => src_payload.IN1 -sink4_data[2] => src_payload.IN1 -sink4_data[3] => src_payload.IN1 -sink4_data[4] => src_payload.IN1 -sink4_data[5] => src_payload.IN1 -sink4_data[6] => src_payload.IN1 -sink4_data[7] => src_payload.IN1 -sink4_data[8] => src_payload.IN1 -sink4_data[9] => src_payload.IN1 -sink4_data[10] => src_payload.IN1 -sink4_data[11] => src_payload.IN1 -sink4_data[12] => src_payload.IN1 -sink4_data[13] => src_payload.IN1 -sink4_data[14] => src_payload.IN1 -sink4_data[15] => src_payload.IN1 -sink4_data[16] => src_payload.IN1 -sink4_data[17] => src_payload.IN1 -sink4_data[18] => src_payload.IN1 -sink4_data[19] => src_payload.IN1 -sink4_data[20] => src_payload.IN1 -sink4_data[21] => src_payload.IN1 -sink4_data[22] => src_payload.IN1 -sink4_data[23] => src_payload.IN1 -sink4_data[24] => src_payload.IN1 -sink4_data[25] => src_payload.IN1 -sink4_data[26] => src_payload.IN1 -sink4_data[27] => src_payload.IN1 -sink4_data[28] => src_payload.IN1 -sink4_data[29] => src_payload.IN1 -sink4_data[30] => src_payload.IN1 -sink4_data[31] => src_payload.IN1 -sink4_data[32] => src_payload.IN1 -sink4_data[33] => src_payload.IN1 -sink4_data[34] => src_payload.IN1 -sink4_data[35] => src_payload.IN1 -sink4_data[36] => src_payload.IN1 -sink4_data[37] => src_payload.IN1 -sink4_data[38] => src_payload.IN1 -sink4_data[39] => src_payload.IN1 -sink4_data[40] => src_payload.IN1 -sink4_data[41] => src_payload.IN1 -sink4_data[42] => src_payload.IN1 -sink4_data[43] => src_payload.IN1 -sink4_data[44] => src_payload.IN1 -sink4_data[45] => src_payload.IN1 -sink4_data[46] => src_payload.IN1 -sink4_data[47] => src_payload.IN1 -sink4_data[48] => src_payload.IN1 -sink4_data[49] => src_payload.IN1 -sink4_data[50] => src_payload.IN1 -sink4_data[51] => src_payload.IN1 -sink4_data[52] => src_payload.IN1 -sink4_data[53] => src_payload.IN1 -sink4_data[54] => src_payload.IN1 -sink4_data[55] => src_payload.IN1 -sink4_data[56] => src_payload.IN1 -sink4_data[57] => src_payload.IN1 -sink4_data[58] => src_payload.IN1 -sink4_data[59] => src_payload.IN1 -sink4_data[59] => last_cycle.IN1 -sink4_data[60] => src_payload.IN1 -sink4_data[61] => src_payload.IN1 -sink4_data[62] => src_payload.IN1 -sink4_data[63] => src_payload.IN1 -sink4_data[64] => src_payload.IN1 -sink4_data[65] => src_payload.IN1 -sink4_data[66] => src_payload.IN1 -sink4_data[67] => src_payload.IN1 -sink4_data[68] => src_payload.IN1 -sink4_data[69] => src_payload.IN1 -sink4_data[70] => src_payload.IN1 -sink4_data[71] => src_payload.IN1 -sink4_data[72] => src_payload.IN1 -sink4_data[73] => src_payload.IN1 -sink4_data[74] => src_payload.IN1 -sink4_data[75] => src_payload.IN1 -sink4_data[76] => src_payload.IN1 -sink4_data[77] => src_payload.IN1 -sink4_data[78] => src_payload.IN1 -sink4_data[79] => src_payload.IN1 -sink4_data[80] => src_payload.IN1 -sink4_data[81] => src_payload.IN1 -sink4_data[82] => src_payload.IN1 -sink4_data[83] => src_payload.IN1 -sink4_data[84] => src_payload.IN1 -sink4_data[85] => src_payload.IN1 -sink4_data[86] => src_payload.IN1 -sink4_data[87] => src_payload.IN1 -sink4_data[88] => src_payload.IN1 -sink4_data[89] => src_payload.IN1 -sink4_data[90] => src_payload.IN1 -sink4_data[91] => src_payload.IN1 -sink4_data[92] => src_payload.IN1 -sink4_data[93] => src_payload.IN1 -sink4_data[94] => src_payload.IN1 -sink4_data[95] => src_payload.IN1 -sink4_channel[0] => src_payload.IN1 -sink4_channel[1] => src_payload.IN1 -sink4_channel[2] => src_payload.IN1 -sink4_channel[3] => src_payload.IN1 -sink4_channel[4] => src_payload.IN1 -sink4_channel[5] => src_payload.IN1 -sink4_channel[6] => src_payload.IN1 -sink4_channel[7] => src_payload.IN1 -sink4_channel[8] => src_payload.IN1 -sink4_channel[9] => src_payload.IN1 -sink4_channel[10] => src_payload.IN1 -sink4_channel[11] => src_payload.IN1 -sink4_channel[12] => src_payload.IN1 -sink4_channel[13] => src_payload.IN1 -sink4_channel[14] => src_payload.IN1 -sink4_channel[15] => src_payload.IN1 -sink4_channel[16] => src_payload.IN1 -sink4_channel[17] => src_payload.IN1 -sink4_startofpacket => src_payload.IN1 -sink4_endofpacket => src_payload.IN1 -sink4_ready <= sink4_ready.DB_MAX_OUTPUT_PORT_TYPE -sink5_valid => request[5].IN1 -sink5_data[0] => src_payload.IN1 -sink5_data[1] => src_payload.IN1 -sink5_data[2] => src_payload.IN1 -sink5_data[3] => src_payload.IN1 -sink5_data[4] => src_payload.IN1 -sink5_data[5] => src_payload.IN1 -sink5_data[6] => src_payload.IN1 -sink5_data[7] => src_payload.IN1 -sink5_data[8] => src_payload.IN1 -sink5_data[9] => src_payload.IN1 -sink5_data[10] => src_payload.IN1 -sink5_data[11] => src_payload.IN1 -sink5_data[12] => src_payload.IN1 -sink5_data[13] => src_payload.IN1 -sink5_data[14] => src_payload.IN1 -sink5_data[15] => src_payload.IN1 -sink5_data[16] => src_payload.IN1 -sink5_data[17] => src_payload.IN1 -sink5_data[18] => src_payload.IN1 -sink5_data[19] => src_payload.IN1 -sink5_data[20] => src_payload.IN1 -sink5_data[21] => src_payload.IN1 -sink5_data[22] => src_payload.IN1 -sink5_data[23] => src_payload.IN1 -sink5_data[24] => src_payload.IN1 -sink5_data[25] => src_payload.IN1 -sink5_data[26] => src_payload.IN1 -sink5_data[27] => src_payload.IN1 -sink5_data[28] => src_payload.IN1 -sink5_data[29] => src_payload.IN1 -sink5_data[30] => src_payload.IN1 -sink5_data[31] => src_payload.IN1 -sink5_data[32] => src_payload.IN1 -sink5_data[33] => src_payload.IN1 -sink5_data[34] => src_payload.IN1 -sink5_data[35] => src_payload.IN1 -sink5_data[36] => src_payload.IN1 -sink5_data[37] => src_payload.IN1 -sink5_data[38] => src_payload.IN1 -sink5_data[39] => src_payload.IN1 -sink5_data[40] => src_payload.IN1 -sink5_data[41] => src_payload.IN1 -sink5_data[42] => src_payload.IN1 -sink5_data[43] => src_payload.IN1 -sink5_data[44] => src_payload.IN1 -sink5_data[45] => src_payload.IN1 -sink5_data[46] => src_payload.IN1 -sink5_data[47] => src_payload.IN1 -sink5_data[48] => src_payload.IN1 -sink5_data[49] => src_payload.IN1 -sink5_data[50] => src_payload.IN1 -sink5_data[51] => src_payload.IN1 -sink5_data[52] => src_payload.IN1 -sink5_data[53] => src_payload.IN1 -sink5_data[54] => src_payload.IN1 -sink5_data[55] => src_payload.IN1 -sink5_data[56] => src_payload.IN1 -sink5_data[57] => src_payload.IN1 -sink5_data[58] => src_payload.IN1 -sink5_data[59] => src_payload.IN1 -sink5_data[59] => last_cycle.IN1 -sink5_data[60] => src_payload.IN1 -sink5_data[61] => src_payload.IN1 -sink5_data[62] => src_payload.IN1 -sink5_data[63] => src_payload.IN1 -sink5_data[64] => src_payload.IN1 -sink5_data[65] => src_payload.IN1 -sink5_data[66] => src_payload.IN1 -sink5_data[67] => src_payload.IN1 -sink5_data[68] => src_payload.IN1 -sink5_data[69] => src_payload.IN1 -sink5_data[70] => src_payload.IN1 -sink5_data[71] => src_payload.IN1 -sink5_data[72] => src_payload.IN1 -sink5_data[73] => src_payload.IN1 -sink5_data[74] => src_payload.IN1 -sink5_data[75] => src_payload.IN1 -sink5_data[76] => src_payload.IN1 -sink5_data[77] => src_payload.IN1 -sink5_data[78] => src_payload.IN1 -sink5_data[79] => src_payload.IN1 -sink5_data[80] => src_payload.IN1 -sink5_data[81] => src_payload.IN1 -sink5_data[82] => src_payload.IN1 -sink5_data[83] => src_payload.IN1 -sink5_data[84] => src_payload.IN1 -sink5_data[85] => src_payload.IN1 -sink5_data[86] => src_payload.IN1 -sink5_data[87] => src_payload.IN1 -sink5_data[88] => src_payload.IN1 -sink5_data[89] => src_payload.IN1 -sink5_data[90] => src_payload.IN1 -sink5_data[91] => src_payload.IN1 -sink5_data[92] => src_payload.IN1 -sink5_data[93] => src_payload.IN1 -sink5_data[94] => src_payload.IN1 -sink5_data[95] => src_payload.IN1 -sink5_channel[0] => src_payload.IN1 -sink5_channel[1] => src_payload.IN1 -sink5_channel[2] => src_payload.IN1 -sink5_channel[3] => src_payload.IN1 -sink5_channel[4] => src_payload.IN1 -sink5_channel[5] => src_payload.IN1 -sink5_channel[6] => src_payload.IN1 -sink5_channel[7] => src_payload.IN1 -sink5_channel[8] => src_payload.IN1 -sink5_channel[9] => src_payload.IN1 -sink5_channel[10] => src_payload.IN1 -sink5_channel[11] => src_payload.IN1 -sink5_channel[12] => src_payload.IN1 -sink5_channel[13] => src_payload.IN1 -sink5_channel[14] => src_payload.IN1 -sink5_channel[15] => src_payload.IN1 -sink5_channel[16] => src_payload.IN1 -sink5_channel[17] => src_payload.IN1 -sink5_startofpacket => src_payload.IN1 -sink5_endofpacket => src_payload.IN1 -sink5_ready <= sink5_ready.DB_MAX_OUTPUT_PORT_TYPE -sink6_valid => request[6].IN1 -sink6_data[0] => src_payload.IN1 -sink6_data[1] => src_payload.IN1 -sink6_data[2] => src_payload.IN1 -sink6_data[3] => src_payload.IN1 -sink6_data[4] => src_payload.IN1 -sink6_data[5] => src_payload.IN1 -sink6_data[6] => src_payload.IN1 -sink6_data[7] => src_payload.IN1 -sink6_data[8] => src_payload.IN1 -sink6_data[9] => src_payload.IN1 -sink6_data[10] => src_payload.IN1 -sink6_data[11] => src_payload.IN1 -sink6_data[12] => src_payload.IN1 -sink6_data[13] => src_payload.IN1 -sink6_data[14] => src_payload.IN1 -sink6_data[15] => src_payload.IN1 -sink6_data[16] => src_payload.IN1 -sink6_data[17] => src_payload.IN1 -sink6_data[18] => src_payload.IN1 -sink6_data[19] => src_payload.IN1 -sink6_data[20] => src_payload.IN1 -sink6_data[21] => src_payload.IN1 -sink6_data[22] => src_payload.IN1 -sink6_data[23] => src_payload.IN1 -sink6_data[24] => src_payload.IN1 -sink6_data[25] => src_payload.IN1 -sink6_data[26] => src_payload.IN1 -sink6_data[27] => src_payload.IN1 -sink6_data[28] => src_payload.IN1 -sink6_data[29] => src_payload.IN1 -sink6_data[30] => src_payload.IN1 -sink6_data[31] => src_payload.IN1 -sink6_data[32] => src_payload.IN1 -sink6_data[33] => src_payload.IN1 -sink6_data[34] => src_payload.IN1 -sink6_data[35] => src_payload.IN1 -sink6_data[36] => src_payload.IN1 -sink6_data[37] => src_payload.IN1 -sink6_data[38] => src_payload.IN1 -sink6_data[39] => src_payload.IN1 -sink6_data[40] => src_payload.IN1 -sink6_data[41] => src_payload.IN1 -sink6_data[42] => src_payload.IN1 -sink6_data[43] => src_payload.IN1 -sink6_data[44] => src_payload.IN1 -sink6_data[45] => src_payload.IN1 -sink6_data[46] => src_payload.IN1 -sink6_data[47] => src_payload.IN1 -sink6_data[48] => src_payload.IN1 -sink6_data[49] => src_payload.IN1 -sink6_data[50] => src_payload.IN1 -sink6_data[51] => src_payload.IN1 -sink6_data[52] => src_payload.IN1 -sink6_data[53] => src_payload.IN1 -sink6_data[54] => src_payload.IN1 -sink6_data[55] => src_payload.IN1 -sink6_data[56] => src_payload.IN1 -sink6_data[57] => src_payload.IN1 -sink6_data[58] => src_payload.IN1 -sink6_data[59] => src_payload.IN1 -sink6_data[59] => last_cycle.IN1 -sink6_data[60] => src_payload.IN1 -sink6_data[61] => src_payload.IN1 -sink6_data[62] => src_payload.IN1 -sink6_data[63] => src_payload.IN1 -sink6_data[64] => src_payload.IN1 -sink6_data[65] => src_payload.IN1 -sink6_data[66] => src_payload.IN1 -sink6_data[67] => src_payload.IN1 -sink6_data[68] => src_payload.IN1 -sink6_data[69] => src_payload.IN1 -sink6_data[70] => src_payload.IN1 -sink6_data[71] => src_payload.IN1 -sink6_data[72] => src_payload.IN1 -sink6_data[73] => src_payload.IN1 -sink6_data[74] => src_payload.IN1 -sink6_data[75] => src_payload.IN1 -sink6_data[76] => src_payload.IN1 -sink6_data[77] => src_payload.IN1 -sink6_data[78] => src_payload.IN1 -sink6_data[79] => src_payload.IN1 -sink6_data[80] => src_payload.IN1 -sink6_data[81] => src_payload.IN1 -sink6_data[82] => src_payload.IN1 -sink6_data[83] => src_payload.IN1 -sink6_data[84] => src_payload.IN1 -sink6_data[85] => src_payload.IN1 -sink6_data[86] => src_payload.IN1 -sink6_data[87] => src_payload.IN1 -sink6_data[88] => src_payload.IN1 -sink6_data[89] => src_payload.IN1 -sink6_data[90] => src_payload.IN1 -sink6_data[91] => src_payload.IN1 -sink6_data[92] => src_payload.IN1 -sink6_data[93] => src_payload.IN1 -sink6_data[94] => src_payload.IN1 -sink6_data[95] => src_payload.IN1 -sink6_channel[0] => src_payload.IN1 -sink6_channel[1] => src_payload.IN1 -sink6_channel[2] => src_payload.IN1 -sink6_channel[3] => src_payload.IN1 -sink6_channel[4] => src_payload.IN1 -sink6_channel[5] => src_payload.IN1 -sink6_channel[6] => src_payload.IN1 -sink6_channel[7] => src_payload.IN1 -sink6_channel[8] => src_payload.IN1 -sink6_channel[9] => src_payload.IN1 -sink6_channel[10] => src_payload.IN1 -sink6_channel[11] => src_payload.IN1 -sink6_channel[12] => src_payload.IN1 -sink6_channel[13] => src_payload.IN1 -sink6_channel[14] => src_payload.IN1 -sink6_channel[15] => src_payload.IN1 -sink6_channel[16] => src_payload.IN1 -sink6_channel[17] => src_payload.IN1 -sink6_startofpacket => src_payload.IN1 -sink6_endofpacket => src_payload.IN1 -sink6_ready <= sink6_ready.DB_MAX_OUTPUT_PORT_TYPE -sink7_valid => request[7].IN1 -sink7_data[0] => src_payload.IN1 -sink7_data[1] => src_payload.IN1 -sink7_data[2] => src_payload.IN1 -sink7_data[3] => src_payload.IN1 -sink7_data[4] => src_payload.IN1 -sink7_data[5] => src_payload.IN1 -sink7_data[6] => src_payload.IN1 -sink7_data[7] => src_payload.IN1 -sink7_data[8] => src_payload.IN1 -sink7_data[9] => src_payload.IN1 -sink7_data[10] => src_payload.IN1 -sink7_data[11] => src_payload.IN1 -sink7_data[12] => src_payload.IN1 -sink7_data[13] => src_payload.IN1 -sink7_data[14] => src_payload.IN1 -sink7_data[15] => src_payload.IN1 -sink7_data[16] => src_payload.IN1 -sink7_data[17] => src_payload.IN1 -sink7_data[18] => src_payload.IN1 -sink7_data[19] => src_payload.IN1 -sink7_data[20] => src_payload.IN1 -sink7_data[21] => src_payload.IN1 -sink7_data[22] => src_payload.IN1 -sink7_data[23] => src_payload.IN1 -sink7_data[24] => src_payload.IN1 -sink7_data[25] => src_payload.IN1 -sink7_data[26] => src_payload.IN1 -sink7_data[27] => src_payload.IN1 -sink7_data[28] => src_payload.IN1 -sink7_data[29] => src_payload.IN1 -sink7_data[30] => src_payload.IN1 -sink7_data[31] => src_payload.IN1 -sink7_data[32] => src_payload.IN1 -sink7_data[33] => src_payload.IN1 -sink7_data[34] => src_payload.IN1 -sink7_data[35] => src_payload.IN1 -sink7_data[36] => src_payload.IN1 -sink7_data[37] => src_payload.IN1 -sink7_data[38] => src_payload.IN1 -sink7_data[39] => src_payload.IN1 -sink7_data[40] => src_payload.IN1 -sink7_data[41] => src_payload.IN1 -sink7_data[42] => src_payload.IN1 -sink7_data[43] => src_payload.IN1 -sink7_data[44] => src_payload.IN1 -sink7_data[45] => src_payload.IN1 -sink7_data[46] => src_payload.IN1 -sink7_data[47] => src_payload.IN1 -sink7_data[48] => src_payload.IN1 -sink7_data[49] => src_payload.IN1 -sink7_data[50] => src_payload.IN1 -sink7_data[51] => src_payload.IN1 -sink7_data[52] => src_payload.IN1 -sink7_data[53] => src_payload.IN1 -sink7_data[54] => src_payload.IN1 -sink7_data[55] => src_payload.IN1 -sink7_data[56] => src_payload.IN1 -sink7_data[57] => src_payload.IN1 -sink7_data[58] => src_payload.IN1 -sink7_data[59] => src_payload.IN1 -sink7_data[59] => last_cycle.IN1 -sink7_data[60] => src_payload.IN1 -sink7_data[61] => src_payload.IN1 -sink7_data[62] => src_payload.IN1 -sink7_data[63] => src_payload.IN1 -sink7_data[64] => src_payload.IN1 -sink7_data[65] => src_payload.IN1 -sink7_data[66] => src_payload.IN1 -sink7_data[67] => src_payload.IN1 -sink7_data[68] => src_payload.IN1 -sink7_data[69] => src_payload.IN1 -sink7_data[70] => src_payload.IN1 -sink7_data[71] => src_payload.IN1 -sink7_data[72] => src_payload.IN1 -sink7_data[73] => src_payload.IN1 -sink7_data[74] => src_payload.IN1 -sink7_data[75] => src_payload.IN1 -sink7_data[76] => src_payload.IN1 -sink7_data[77] => src_payload.IN1 -sink7_data[78] => src_payload.IN1 -sink7_data[79] => src_payload.IN1 -sink7_data[80] => src_payload.IN1 -sink7_data[81] => src_payload.IN1 -sink7_data[82] => src_payload.IN1 -sink7_data[83] => src_payload.IN1 -sink7_data[84] => src_payload.IN1 -sink7_data[85] => src_payload.IN1 -sink7_data[86] => src_payload.IN1 -sink7_data[87] => src_payload.IN1 -sink7_data[88] => src_payload.IN1 -sink7_data[89] => src_payload.IN1 -sink7_data[90] => src_payload.IN1 -sink7_data[91] => src_payload.IN1 -sink7_data[92] => src_payload.IN1 -sink7_data[93] => src_payload.IN1 -sink7_data[94] => src_payload.IN1 -sink7_data[95] => src_payload.IN1 -sink7_channel[0] => src_payload.IN1 -sink7_channel[1] => src_payload.IN1 -sink7_channel[2] => src_payload.IN1 -sink7_channel[3] => src_payload.IN1 -sink7_channel[4] => src_payload.IN1 -sink7_channel[5] => src_payload.IN1 -sink7_channel[6] => src_payload.IN1 -sink7_channel[7] => src_payload.IN1 -sink7_channel[8] => src_payload.IN1 -sink7_channel[9] => src_payload.IN1 -sink7_channel[10] => src_payload.IN1 -sink7_channel[11] => src_payload.IN1 -sink7_channel[12] => src_payload.IN1 -sink7_channel[13] => src_payload.IN1 -sink7_channel[14] => src_payload.IN1 -sink7_channel[15] => src_payload.IN1 -sink7_channel[16] => src_payload.IN1 -sink7_channel[17] => src_payload.IN1 -sink7_startofpacket => src_payload.IN1 -sink7_endofpacket => src_payload.IN1 -sink7_ready <= sink7_ready.DB_MAX_OUTPUT_PORT_TYPE -sink8_valid => request[8].IN1 -sink8_data[0] => src_payload.IN1 -sink8_data[1] => src_payload.IN1 -sink8_data[2] => src_payload.IN1 -sink8_data[3] => src_payload.IN1 -sink8_data[4] => src_payload.IN1 -sink8_data[5] => src_payload.IN1 -sink8_data[6] => src_payload.IN1 -sink8_data[7] => src_payload.IN1 -sink8_data[8] => src_payload.IN1 -sink8_data[9] => src_payload.IN1 -sink8_data[10] => src_payload.IN1 -sink8_data[11] => src_payload.IN1 -sink8_data[12] => src_payload.IN1 -sink8_data[13] => src_payload.IN1 -sink8_data[14] => src_payload.IN1 -sink8_data[15] => src_payload.IN1 -sink8_data[16] => src_payload.IN1 -sink8_data[17] => src_payload.IN1 -sink8_data[18] => src_payload.IN1 -sink8_data[19] => src_payload.IN1 -sink8_data[20] => src_payload.IN1 -sink8_data[21] => src_payload.IN1 -sink8_data[22] => src_payload.IN1 -sink8_data[23] => src_payload.IN1 -sink8_data[24] => src_payload.IN1 -sink8_data[25] => src_payload.IN1 -sink8_data[26] => src_payload.IN1 -sink8_data[27] => src_payload.IN1 -sink8_data[28] => src_payload.IN1 -sink8_data[29] => src_payload.IN1 -sink8_data[30] => src_payload.IN1 -sink8_data[31] => src_payload.IN1 -sink8_data[32] => src_payload.IN1 -sink8_data[33] => src_payload.IN1 -sink8_data[34] => src_payload.IN1 -sink8_data[35] => src_payload.IN1 -sink8_data[36] => src_payload.IN1 -sink8_data[37] => src_payload.IN1 -sink8_data[38] => src_payload.IN1 -sink8_data[39] => src_payload.IN1 -sink8_data[40] => src_payload.IN1 -sink8_data[41] => src_payload.IN1 -sink8_data[42] => src_payload.IN1 -sink8_data[43] => src_payload.IN1 -sink8_data[44] => src_payload.IN1 -sink8_data[45] => src_payload.IN1 -sink8_data[46] => src_payload.IN1 -sink8_data[47] => src_payload.IN1 -sink8_data[48] => src_payload.IN1 -sink8_data[49] => src_payload.IN1 -sink8_data[50] => src_payload.IN1 -sink8_data[51] => src_payload.IN1 -sink8_data[52] => src_payload.IN1 -sink8_data[53] => src_payload.IN1 -sink8_data[54] => src_payload.IN1 -sink8_data[55] => src_payload.IN1 -sink8_data[56] => src_payload.IN1 -sink8_data[57] => src_payload.IN1 -sink8_data[58] => src_payload.IN1 -sink8_data[59] => src_payload.IN1 -sink8_data[59] => last_cycle.IN1 -sink8_data[60] => src_payload.IN1 -sink8_data[61] => src_payload.IN1 -sink8_data[62] => src_payload.IN1 -sink8_data[63] => src_payload.IN1 -sink8_data[64] => src_payload.IN1 -sink8_data[65] => src_payload.IN1 -sink8_data[66] => src_payload.IN1 -sink8_data[67] => src_payload.IN1 -sink8_data[68] => src_payload.IN1 -sink8_data[69] => src_payload.IN1 -sink8_data[70] => src_payload.IN1 -sink8_data[71] => src_payload.IN1 -sink8_data[72] => src_payload.IN1 -sink8_data[73] => src_payload.IN1 -sink8_data[74] => src_payload.IN1 -sink8_data[75] => src_payload.IN1 -sink8_data[76] => src_payload.IN1 -sink8_data[77] => src_payload.IN1 -sink8_data[78] => src_payload.IN1 -sink8_data[79] => src_payload.IN1 -sink8_data[80] => src_payload.IN1 -sink8_data[81] => src_payload.IN1 -sink8_data[82] => src_payload.IN1 -sink8_data[83] => src_payload.IN1 -sink8_data[84] => src_payload.IN1 -sink8_data[85] => src_payload.IN1 -sink8_data[86] => src_payload.IN1 -sink8_data[87] => src_payload.IN1 -sink8_data[88] => src_payload.IN1 -sink8_data[89] => src_payload.IN1 -sink8_data[90] => src_payload.IN1 -sink8_data[91] => src_payload.IN1 -sink8_data[92] => src_payload.IN1 -sink8_data[93] => src_payload.IN1 -sink8_data[94] => src_payload.IN1 -sink8_data[95] => src_payload.IN1 -sink8_channel[0] => src_payload.IN1 -sink8_channel[1] => src_payload.IN1 -sink8_channel[2] => src_payload.IN1 -sink8_channel[3] => src_payload.IN1 -sink8_channel[4] => src_payload.IN1 -sink8_channel[5] => src_payload.IN1 -sink8_channel[6] => src_payload.IN1 -sink8_channel[7] => src_payload.IN1 -sink8_channel[8] => src_payload.IN1 -sink8_channel[9] => src_payload.IN1 -sink8_channel[10] => src_payload.IN1 -sink8_channel[11] => src_payload.IN1 -sink8_channel[12] => src_payload.IN1 -sink8_channel[13] => src_payload.IN1 -sink8_channel[14] => src_payload.IN1 -sink8_channel[15] => src_payload.IN1 -sink8_channel[16] => src_payload.IN1 -sink8_channel[17] => src_payload.IN1 -sink8_startofpacket => src_payload.IN1 -sink8_endofpacket => src_payload.IN1 -sink8_ready <= sink8_ready.DB_MAX_OUTPUT_PORT_TYPE -sink9_valid => request[9].IN1 -sink9_data[0] => src_payload.IN1 -sink9_data[1] => src_payload.IN1 -sink9_data[2] => src_payload.IN1 -sink9_data[3] => src_payload.IN1 -sink9_data[4] => src_payload.IN1 -sink9_data[5] => src_payload.IN1 -sink9_data[6] => src_payload.IN1 -sink9_data[7] => src_payload.IN1 -sink9_data[8] => src_payload.IN1 -sink9_data[9] => src_payload.IN1 -sink9_data[10] => src_payload.IN1 -sink9_data[11] => src_payload.IN1 -sink9_data[12] => src_payload.IN1 -sink9_data[13] => src_payload.IN1 -sink9_data[14] => src_payload.IN1 -sink9_data[15] => src_payload.IN1 -sink9_data[16] => src_payload.IN1 -sink9_data[17] => src_payload.IN1 -sink9_data[18] => src_payload.IN1 -sink9_data[19] => src_payload.IN1 -sink9_data[20] => src_payload.IN1 -sink9_data[21] => src_payload.IN1 -sink9_data[22] => src_payload.IN1 -sink9_data[23] => src_payload.IN1 -sink9_data[24] => src_payload.IN1 -sink9_data[25] => src_payload.IN1 -sink9_data[26] => src_payload.IN1 -sink9_data[27] => src_payload.IN1 -sink9_data[28] => src_payload.IN1 -sink9_data[29] => src_payload.IN1 -sink9_data[30] => src_payload.IN1 -sink9_data[31] => src_payload.IN1 -sink9_data[32] => src_payload.IN1 -sink9_data[33] => src_payload.IN1 -sink9_data[34] => src_payload.IN1 -sink9_data[35] => src_payload.IN1 -sink9_data[36] => src_payload.IN1 -sink9_data[37] => src_payload.IN1 -sink9_data[38] => src_payload.IN1 -sink9_data[39] => src_payload.IN1 -sink9_data[40] => src_payload.IN1 -sink9_data[41] => src_payload.IN1 -sink9_data[42] => src_payload.IN1 -sink9_data[43] => src_payload.IN1 -sink9_data[44] => src_payload.IN1 -sink9_data[45] => src_payload.IN1 -sink9_data[46] => src_payload.IN1 -sink9_data[47] => src_payload.IN1 -sink9_data[48] => src_payload.IN1 -sink9_data[49] => src_payload.IN1 -sink9_data[50] => src_payload.IN1 -sink9_data[51] => src_payload.IN1 -sink9_data[52] => src_payload.IN1 -sink9_data[53] => src_payload.IN1 -sink9_data[54] => src_payload.IN1 -sink9_data[55] => src_payload.IN1 -sink9_data[56] => src_payload.IN1 -sink9_data[57] => src_payload.IN1 -sink9_data[58] => src_payload.IN1 -sink9_data[59] => src_payload.IN1 -sink9_data[59] => last_cycle.IN1 -sink9_data[60] => src_payload.IN1 -sink9_data[61] => src_payload.IN1 -sink9_data[62] => src_payload.IN1 -sink9_data[63] => src_payload.IN1 -sink9_data[64] => src_payload.IN1 -sink9_data[65] => src_payload.IN1 -sink9_data[66] => src_payload.IN1 -sink9_data[67] => src_payload.IN1 -sink9_data[68] => src_payload.IN1 -sink9_data[69] => src_payload.IN1 -sink9_data[70] => src_payload.IN1 -sink9_data[71] => src_payload.IN1 -sink9_data[72] => src_payload.IN1 -sink9_data[73] => src_payload.IN1 -sink9_data[74] => src_payload.IN1 -sink9_data[75] => src_payload.IN1 -sink9_data[76] => src_payload.IN1 -sink9_data[77] => src_payload.IN1 -sink9_data[78] => src_payload.IN1 -sink9_data[79] => src_payload.IN1 -sink9_data[80] => src_payload.IN1 -sink9_data[81] => src_payload.IN1 -sink9_data[82] => src_payload.IN1 -sink9_data[83] => src_payload.IN1 -sink9_data[84] => src_payload.IN1 -sink9_data[85] => src_payload.IN1 -sink9_data[86] => src_payload.IN1 -sink9_data[87] => src_payload.IN1 -sink9_data[88] => src_payload.IN1 -sink9_data[89] => src_payload.IN1 -sink9_data[90] => src_payload.IN1 -sink9_data[91] => src_payload.IN1 -sink9_data[92] => src_payload.IN1 -sink9_data[93] => src_payload.IN1 -sink9_data[94] => src_payload.IN1 -sink9_data[95] => src_payload.IN1 -sink9_channel[0] => src_payload.IN1 -sink9_channel[1] => src_payload.IN1 -sink9_channel[2] => src_payload.IN1 -sink9_channel[3] => src_payload.IN1 -sink9_channel[4] => src_payload.IN1 -sink9_channel[5] => src_payload.IN1 -sink9_channel[6] => src_payload.IN1 -sink9_channel[7] => src_payload.IN1 -sink9_channel[8] => src_payload.IN1 -sink9_channel[9] => src_payload.IN1 -sink9_channel[10] => src_payload.IN1 -sink9_channel[11] => src_payload.IN1 -sink9_channel[12] => src_payload.IN1 -sink9_channel[13] => src_payload.IN1 -sink9_channel[14] => src_payload.IN1 -sink9_channel[15] => src_payload.IN1 -sink9_channel[16] => src_payload.IN1 -sink9_channel[17] => src_payload.IN1 -sink9_startofpacket => src_payload.IN1 -sink9_endofpacket => src_payload.IN1 -sink9_ready <= sink9_ready.DB_MAX_OUTPUT_PORT_TYPE -sink10_valid => request[10].IN1 -sink10_data[0] => src_payload.IN1 -sink10_data[1] => src_payload.IN1 -sink10_data[2] => src_payload.IN1 -sink10_data[3] => src_payload.IN1 -sink10_data[4] => src_payload.IN1 -sink10_data[5] => src_payload.IN1 -sink10_data[6] => src_payload.IN1 -sink10_data[7] => src_payload.IN1 -sink10_data[8] => src_payload.IN1 -sink10_data[9] => src_payload.IN1 -sink10_data[10] => src_payload.IN1 -sink10_data[11] => src_payload.IN1 -sink10_data[12] => src_payload.IN1 -sink10_data[13] => src_payload.IN1 -sink10_data[14] => src_payload.IN1 -sink10_data[15] => src_payload.IN1 -sink10_data[16] => src_payload.IN1 -sink10_data[17] => src_payload.IN1 -sink10_data[18] => src_payload.IN1 -sink10_data[19] => src_payload.IN1 -sink10_data[20] => src_payload.IN1 -sink10_data[21] => src_payload.IN1 -sink10_data[22] => src_payload.IN1 -sink10_data[23] => src_payload.IN1 -sink10_data[24] => src_payload.IN1 -sink10_data[25] => src_payload.IN1 -sink10_data[26] => src_payload.IN1 -sink10_data[27] => src_payload.IN1 -sink10_data[28] => src_payload.IN1 -sink10_data[29] => src_payload.IN1 -sink10_data[30] => src_payload.IN1 -sink10_data[31] => src_payload.IN1 -sink10_data[32] => src_payload.IN1 -sink10_data[33] => src_payload.IN1 -sink10_data[34] => src_payload.IN1 -sink10_data[35] => src_payload.IN1 -sink10_data[36] => src_payload.IN1 -sink10_data[37] => src_payload.IN1 -sink10_data[38] => src_payload.IN1 -sink10_data[39] => src_payload.IN1 -sink10_data[40] => src_payload.IN1 -sink10_data[41] => src_payload.IN1 -sink10_data[42] => src_payload.IN1 -sink10_data[43] => src_payload.IN1 -sink10_data[44] => src_payload.IN1 -sink10_data[45] => src_payload.IN1 -sink10_data[46] => src_payload.IN1 -sink10_data[47] => src_payload.IN1 -sink10_data[48] => src_payload.IN1 -sink10_data[49] => src_payload.IN1 -sink10_data[50] => src_payload.IN1 -sink10_data[51] => src_payload.IN1 -sink10_data[52] => src_payload.IN1 -sink10_data[53] => src_payload.IN1 -sink10_data[54] => src_payload.IN1 -sink10_data[55] => src_payload.IN1 -sink10_data[56] => src_payload.IN1 -sink10_data[57] => src_payload.IN1 -sink10_data[58] => src_payload.IN1 -sink10_data[59] => src_payload.IN1 -sink10_data[59] => last_cycle.IN1 -sink10_data[60] => src_payload.IN1 -sink10_data[61] => src_payload.IN1 -sink10_data[62] => src_payload.IN1 -sink10_data[63] => src_payload.IN1 -sink10_data[64] => src_payload.IN1 -sink10_data[65] => src_payload.IN1 -sink10_data[66] => src_payload.IN1 -sink10_data[67] => src_payload.IN1 -sink10_data[68] => src_payload.IN1 -sink10_data[69] => src_payload.IN1 -sink10_data[70] => src_payload.IN1 -sink10_data[71] => src_payload.IN1 -sink10_data[72] => src_payload.IN1 -sink10_data[73] => src_payload.IN1 -sink10_data[74] => src_payload.IN1 -sink10_data[75] => src_payload.IN1 -sink10_data[76] => src_payload.IN1 -sink10_data[77] => src_payload.IN1 -sink10_data[78] => src_payload.IN1 -sink10_data[79] => src_payload.IN1 -sink10_data[80] => src_payload.IN1 -sink10_data[81] => src_payload.IN1 -sink10_data[82] => src_payload.IN1 -sink10_data[83] => src_payload.IN1 -sink10_data[84] => src_payload.IN1 -sink10_data[85] => src_payload.IN1 -sink10_data[86] => src_payload.IN1 -sink10_data[87] => src_payload.IN1 -sink10_data[88] => src_payload.IN1 -sink10_data[89] => src_payload.IN1 -sink10_data[90] => src_payload.IN1 -sink10_data[91] => src_payload.IN1 -sink10_data[92] => src_payload.IN1 -sink10_data[93] => src_payload.IN1 -sink10_data[94] => src_payload.IN1 -sink10_data[95] => src_payload.IN1 -sink10_channel[0] => src_payload.IN1 -sink10_channel[1] => src_payload.IN1 -sink10_channel[2] => src_payload.IN1 -sink10_channel[3] => src_payload.IN1 -sink10_channel[4] => src_payload.IN1 -sink10_channel[5] => src_payload.IN1 -sink10_channel[6] => src_payload.IN1 -sink10_channel[7] => src_payload.IN1 -sink10_channel[8] => src_payload.IN1 -sink10_channel[9] => src_payload.IN1 -sink10_channel[10] => src_payload.IN1 -sink10_channel[11] => src_payload.IN1 -sink10_channel[12] => src_payload.IN1 -sink10_channel[13] => src_payload.IN1 -sink10_channel[14] => src_payload.IN1 -sink10_channel[15] => src_payload.IN1 -sink10_channel[16] => src_payload.IN1 -sink10_channel[17] => src_payload.IN1 -sink10_startofpacket => src_payload.IN1 -sink10_endofpacket => src_payload.IN1 -sink10_ready <= sink10_ready.DB_MAX_OUTPUT_PORT_TYPE -sink11_valid => request[11].IN1 -sink11_data[0] => src_payload.IN1 -sink11_data[1] => src_payload.IN1 -sink11_data[2] => src_payload.IN1 -sink11_data[3] => src_payload.IN1 -sink11_data[4] => src_payload.IN1 -sink11_data[5] => src_payload.IN1 -sink11_data[6] => src_payload.IN1 -sink11_data[7] => src_payload.IN1 -sink11_data[8] => src_payload.IN1 -sink11_data[9] => src_payload.IN1 -sink11_data[10] => src_payload.IN1 -sink11_data[11] => src_payload.IN1 -sink11_data[12] => src_payload.IN1 -sink11_data[13] => src_payload.IN1 -sink11_data[14] => src_payload.IN1 -sink11_data[15] => src_payload.IN1 -sink11_data[16] => src_payload.IN1 -sink11_data[17] => src_payload.IN1 -sink11_data[18] => src_payload.IN1 -sink11_data[19] => src_payload.IN1 -sink11_data[20] => src_payload.IN1 -sink11_data[21] => src_payload.IN1 -sink11_data[22] => src_payload.IN1 -sink11_data[23] => src_payload.IN1 -sink11_data[24] => src_payload.IN1 -sink11_data[25] => src_payload.IN1 -sink11_data[26] => src_payload.IN1 -sink11_data[27] => src_payload.IN1 -sink11_data[28] => src_payload.IN1 -sink11_data[29] => src_payload.IN1 -sink11_data[30] => src_payload.IN1 -sink11_data[31] => src_payload.IN1 -sink11_data[32] => src_payload.IN1 -sink11_data[33] => src_payload.IN1 -sink11_data[34] => src_payload.IN1 -sink11_data[35] => src_payload.IN1 -sink11_data[36] => src_payload.IN1 -sink11_data[37] => src_payload.IN1 -sink11_data[38] => src_payload.IN1 -sink11_data[39] => src_payload.IN1 -sink11_data[40] => src_payload.IN1 -sink11_data[41] => src_payload.IN1 -sink11_data[42] => src_payload.IN1 -sink11_data[43] => src_payload.IN1 -sink11_data[44] => src_payload.IN1 -sink11_data[45] => src_payload.IN1 -sink11_data[46] => src_payload.IN1 -sink11_data[47] => src_payload.IN1 -sink11_data[48] => src_payload.IN1 -sink11_data[49] => src_payload.IN1 -sink11_data[50] => src_payload.IN1 -sink11_data[51] => src_payload.IN1 -sink11_data[52] => src_payload.IN1 -sink11_data[53] => src_payload.IN1 -sink11_data[54] => src_payload.IN1 -sink11_data[55] => src_payload.IN1 -sink11_data[56] => src_payload.IN1 -sink11_data[57] => src_payload.IN1 -sink11_data[58] => src_payload.IN1 -sink11_data[59] => src_payload.IN1 -sink11_data[59] => last_cycle.IN1 -sink11_data[60] => src_payload.IN1 -sink11_data[61] => src_payload.IN1 -sink11_data[62] => src_payload.IN1 -sink11_data[63] => src_payload.IN1 -sink11_data[64] => src_payload.IN1 -sink11_data[65] => src_payload.IN1 -sink11_data[66] => src_payload.IN1 -sink11_data[67] => src_payload.IN1 -sink11_data[68] => src_payload.IN1 -sink11_data[69] => src_payload.IN1 -sink11_data[70] => src_payload.IN1 -sink11_data[71] => src_payload.IN1 -sink11_data[72] => src_payload.IN1 -sink11_data[73] => src_payload.IN1 -sink11_data[74] => src_payload.IN1 -sink11_data[75] => src_payload.IN1 -sink11_data[76] => src_payload.IN1 -sink11_data[77] => src_payload.IN1 -sink11_data[78] => src_payload.IN1 -sink11_data[79] => src_payload.IN1 -sink11_data[80] => src_payload.IN1 -sink11_data[81] => src_payload.IN1 -sink11_data[82] => src_payload.IN1 -sink11_data[83] => src_payload.IN1 -sink11_data[84] => src_payload.IN1 -sink11_data[85] => src_payload.IN1 -sink11_data[86] => src_payload.IN1 -sink11_data[87] => src_payload.IN1 -sink11_data[88] => src_payload.IN1 -sink11_data[89] => src_payload.IN1 -sink11_data[90] => src_payload.IN1 -sink11_data[91] => src_payload.IN1 -sink11_data[92] => src_payload.IN1 -sink11_data[93] => src_payload.IN1 -sink11_data[94] => src_payload.IN1 -sink11_data[95] => src_payload.IN1 -sink11_channel[0] => src_payload.IN1 -sink11_channel[1] => src_payload.IN1 -sink11_channel[2] => src_payload.IN1 -sink11_channel[3] => src_payload.IN1 -sink11_channel[4] => src_payload.IN1 -sink11_channel[5] => src_payload.IN1 -sink11_channel[6] => src_payload.IN1 -sink11_channel[7] => src_payload.IN1 -sink11_channel[8] => src_payload.IN1 -sink11_channel[9] => src_payload.IN1 -sink11_channel[10] => src_payload.IN1 -sink11_channel[11] => src_payload.IN1 -sink11_channel[12] => src_payload.IN1 -sink11_channel[13] => src_payload.IN1 -sink11_channel[14] => src_payload.IN1 -sink11_channel[15] => src_payload.IN1 -sink11_channel[16] => src_payload.IN1 -sink11_channel[17] => src_payload.IN1 -sink11_startofpacket => src_payload.IN1 -sink11_endofpacket => src_payload.IN1 -sink11_ready <= sink11_ready.DB_MAX_OUTPUT_PORT_TYPE -sink12_valid => request[12].IN1 -sink12_data[0] => src_payload.IN1 -sink12_data[1] => src_payload.IN1 -sink12_data[2] => src_payload.IN1 -sink12_data[3] => src_payload.IN1 -sink12_data[4] => src_payload.IN1 -sink12_data[5] => src_payload.IN1 -sink12_data[6] => src_payload.IN1 -sink12_data[7] => src_payload.IN1 -sink12_data[8] => src_payload.IN1 -sink12_data[9] => src_payload.IN1 -sink12_data[10] => src_payload.IN1 -sink12_data[11] => src_payload.IN1 -sink12_data[12] => src_payload.IN1 -sink12_data[13] => src_payload.IN1 -sink12_data[14] => src_payload.IN1 -sink12_data[15] => src_payload.IN1 -sink12_data[16] => src_payload.IN1 -sink12_data[17] => src_payload.IN1 -sink12_data[18] => src_payload.IN1 -sink12_data[19] => src_payload.IN1 -sink12_data[20] => src_payload.IN1 -sink12_data[21] => src_payload.IN1 -sink12_data[22] => src_payload.IN1 -sink12_data[23] => src_payload.IN1 -sink12_data[24] => src_payload.IN1 -sink12_data[25] => src_payload.IN1 -sink12_data[26] => src_payload.IN1 -sink12_data[27] => src_payload.IN1 -sink12_data[28] => src_payload.IN1 -sink12_data[29] => src_payload.IN1 -sink12_data[30] => src_payload.IN1 -sink12_data[31] => src_payload.IN1 -sink12_data[32] => src_payload.IN1 -sink12_data[33] => src_payload.IN1 -sink12_data[34] => src_payload.IN1 -sink12_data[35] => src_payload.IN1 -sink12_data[36] => src_payload.IN1 -sink12_data[37] => src_payload.IN1 -sink12_data[38] => src_payload.IN1 -sink12_data[39] => src_payload.IN1 -sink12_data[40] => src_payload.IN1 -sink12_data[41] => src_payload.IN1 -sink12_data[42] => src_payload.IN1 -sink12_data[43] => src_payload.IN1 -sink12_data[44] => src_payload.IN1 -sink12_data[45] => src_payload.IN1 -sink12_data[46] => src_payload.IN1 -sink12_data[47] => src_payload.IN1 -sink12_data[48] => src_payload.IN1 -sink12_data[49] => src_payload.IN1 -sink12_data[50] => src_payload.IN1 -sink12_data[51] => src_payload.IN1 -sink12_data[52] => src_payload.IN1 -sink12_data[53] => src_payload.IN1 -sink12_data[54] => src_payload.IN1 -sink12_data[55] => src_payload.IN1 -sink12_data[56] => src_payload.IN1 -sink12_data[57] => src_payload.IN1 -sink12_data[58] => src_payload.IN1 -sink12_data[59] => src_payload.IN1 -sink12_data[59] => last_cycle.IN1 -sink12_data[60] => src_payload.IN1 -sink12_data[61] => src_payload.IN1 -sink12_data[62] => src_payload.IN1 -sink12_data[63] => src_payload.IN1 -sink12_data[64] => src_payload.IN1 -sink12_data[65] => src_payload.IN1 -sink12_data[66] => src_payload.IN1 -sink12_data[67] => src_payload.IN1 -sink12_data[68] => src_payload.IN1 -sink12_data[69] => src_payload.IN1 -sink12_data[70] => src_payload.IN1 -sink12_data[71] => src_payload.IN1 -sink12_data[72] => src_payload.IN1 -sink12_data[73] => src_payload.IN1 -sink12_data[74] => src_payload.IN1 -sink12_data[75] => src_payload.IN1 -sink12_data[76] => src_payload.IN1 -sink12_data[77] => src_payload.IN1 -sink12_data[78] => src_payload.IN1 -sink12_data[79] => src_payload.IN1 -sink12_data[80] => src_payload.IN1 -sink12_data[81] => src_payload.IN1 -sink12_data[82] => src_payload.IN1 -sink12_data[83] => src_payload.IN1 -sink12_data[84] => src_payload.IN1 -sink12_data[85] => src_payload.IN1 -sink12_data[86] => src_payload.IN1 -sink12_data[87] => src_payload.IN1 -sink12_data[88] => src_payload.IN1 -sink12_data[89] => src_payload.IN1 -sink12_data[90] => src_payload.IN1 -sink12_data[91] => src_payload.IN1 -sink12_data[92] => src_payload.IN1 -sink12_data[93] => src_payload.IN1 -sink12_data[94] => src_payload.IN1 -sink12_data[95] => src_payload.IN1 -sink12_channel[0] => src_payload.IN1 -sink12_channel[1] => src_payload.IN1 -sink12_channel[2] => src_payload.IN1 -sink12_channel[3] => src_payload.IN1 -sink12_channel[4] => src_payload.IN1 -sink12_channel[5] => src_payload.IN1 -sink12_channel[6] => src_payload.IN1 -sink12_channel[7] => src_payload.IN1 -sink12_channel[8] => src_payload.IN1 -sink12_channel[9] => src_payload.IN1 -sink12_channel[10] => src_payload.IN1 -sink12_channel[11] => src_payload.IN1 -sink12_channel[12] => src_payload.IN1 -sink12_channel[13] => src_payload.IN1 -sink12_channel[14] => src_payload.IN1 -sink12_channel[15] => src_payload.IN1 -sink12_channel[16] => src_payload.IN1 -sink12_channel[17] => src_payload.IN1 -sink12_startofpacket => src_payload.IN1 -sink12_endofpacket => src_payload.IN1 -sink12_ready <= sink12_ready.DB_MAX_OUTPUT_PORT_TYPE -sink13_valid => request[13].IN1 -sink13_data[0] => src_payload.IN1 -sink13_data[1] => src_payload.IN1 -sink13_data[2] => src_payload.IN1 -sink13_data[3] => src_payload.IN1 -sink13_data[4] => src_payload.IN1 -sink13_data[5] => src_payload.IN1 -sink13_data[6] => src_payload.IN1 -sink13_data[7] => src_payload.IN1 -sink13_data[8] => src_payload.IN1 -sink13_data[9] => src_payload.IN1 -sink13_data[10] => src_payload.IN1 -sink13_data[11] => src_payload.IN1 -sink13_data[12] => src_payload.IN1 -sink13_data[13] => src_payload.IN1 -sink13_data[14] => src_payload.IN1 -sink13_data[15] => src_payload.IN1 -sink13_data[16] => src_payload.IN1 -sink13_data[17] => src_payload.IN1 -sink13_data[18] => src_payload.IN1 -sink13_data[19] => src_payload.IN1 -sink13_data[20] => src_payload.IN1 -sink13_data[21] => src_payload.IN1 -sink13_data[22] => src_payload.IN1 -sink13_data[23] => src_payload.IN1 -sink13_data[24] => src_payload.IN1 -sink13_data[25] => src_payload.IN1 -sink13_data[26] => src_payload.IN1 -sink13_data[27] => src_payload.IN1 -sink13_data[28] => src_payload.IN1 -sink13_data[29] => src_payload.IN1 -sink13_data[30] => src_payload.IN1 -sink13_data[31] => src_payload.IN1 -sink13_data[32] => src_payload.IN1 -sink13_data[33] => src_payload.IN1 -sink13_data[34] => src_payload.IN1 -sink13_data[35] => src_payload.IN1 -sink13_data[36] => src_payload.IN1 -sink13_data[37] => src_payload.IN1 -sink13_data[38] => src_payload.IN1 -sink13_data[39] => src_payload.IN1 -sink13_data[40] => src_payload.IN1 -sink13_data[41] => src_payload.IN1 -sink13_data[42] => src_payload.IN1 -sink13_data[43] => src_payload.IN1 -sink13_data[44] => src_payload.IN1 -sink13_data[45] => src_payload.IN1 -sink13_data[46] => src_payload.IN1 -sink13_data[47] => src_payload.IN1 -sink13_data[48] => src_payload.IN1 -sink13_data[49] => src_payload.IN1 -sink13_data[50] => src_payload.IN1 -sink13_data[51] => src_payload.IN1 -sink13_data[52] => src_payload.IN1 -sink13_data[53] => src_payload.IN1 -sink13_data[54] => src_payload.IN1 -sink13_data[55] => src_payload.IN1 -sink13_data[56] => src_payload.IN1 -sink13_data[57] => src_payload.IN1 -sink13_data[58] => src_payload.IN1 -sink13_data[59] => src_payload.IN1 -sink13_data[59] => last_cycle.IN1 -sink13_data[60] => src_payload.IN1 -sink13_data[61] => src_payload.IN1 -sink13_data[62] => src_payload.IN1 -sink13_data[63] => src_payload.IN1 -sink13_data[64] => src_payload.IN1 -sink13_data[65] => src_payload.IN1 -sink13_data[66] => src_payload.IN1 -sink13_data[67] => src_payload.IN1 -sink13_data[68] => src_payload.IN1 -sink13_data[69] => src_payload.IN1 -sink13_data[70] => src_payload.IN1 -sink13_data[71] => src_payload.IN1 -sink13_data[72] => src_payload.IN1 -sink13_data[73] => src_payload.IN1 -sink13_data[74] => src_payload.IN1 -sink13_data[75] => src_payload.IN1 -sink13_data[76] => src_payload.IN1 -sink13_data[77] => src_payload.IN1 -sink13_data[78] => src_payload.IN1 -sink13_data[79] => src_payload.IN1 -sink13_data[80] => src_payload.IN1 -sink13_data[81] => src_payload.IN1 -sink13_data[82] => src_payload.IN1 -sink13_data[83] => src_payload.IN1 -sink13_data[84] => src_payload.IN1 -sink13_data[85] => src_payload.IN1 -sink13_data[86] => src_payload.IN1 -sink13_data[87] => src_payload.IN1 -sink13_data[88] => src_payload.IN1 -sink13_data[89] => src_payload.IN1 -sink13_data[90] => src_payload.IN1 -sink13_data[91] => src_payload.IN1 -sink13_data[92] => src_payload.IN1 -sink13_data[93] => src_payload.IN1 -sink13_data[94] => src_payload.IN1 -sink13_data[95] => src_payload.IN1 -sink13_channel[0] => src_payload.IN1 -sink13_channel[1] => src_payload.IN1 -sink13_channel[2] => src_payload.IN1 -sink13_channel[3] => src_payload.IN1 -sink13_channel[4] => src_payload.IN1 -sink13_channel[5] => src_payload.IN1 -sink13_channel[6] => src_payload.IN1 -sink13_channel[7] => src_payload.IN1 -sink13_channel[8] => src_payload.IN1 -sink13_channel[9] => src_payload.IN1 -sink13_channel[10] => src_payload.IN1 -sink13_channel[11] => src_payload.IN1 -sink13_channel[12] => src_payload.IN1 -sink13_channel[13] => src_payload.IN1 -sink13_channel[14] => src_payload.IN1 -sink13_channel[15] => src_payload.IN1 -sink13_channel[16] => src_payload.IN1 -sink13_channel[17] => src_payload.IN1 -sink13_startofpacket => src_payload.IN1 -sink13_endofpacket => src_payload.IN1 -sink13_ready <= sink13_ready.DB_MAX_OUTPUT_PORT_TYPE -sink14_valid => request[14].IN1 -sink14_data[0] => src_payload.IN1 -sink14_data[1] => src_payload.IN1 -sink14_data[2] => src_payload.IN1 -sink14_data[3] => src_payload.IN1 -sink14_data[4] => src_payload.IN1 -sink14_data[5] => src_payload.IN1 -sink14_data[6] => src_payload.IN1 -sink14_data[7] => src_payload.IN1 -sink14_data[8] => src_payload.IN1 -sink14_data[9] => src_payload.IN1 -sink14_data[10] => src_payload.IN1 -sink14_data[11] => src_payload.IN1 -sink14_data[12] => src_payload.IN1 -sink14_data[13] => src_payload.IN1 -sink14_data[14] => src_payload.IN1 -sink14_data[15] => src_payload.IN1 -sink14_data[16] => src_payload.IN1 -sink14_data[17] => src_payload.IN1 -sink14_data[18] => src_payload.IN1 -sink14_data[19] => src_payload.IN1 -sink14_data[20] => src_payload.IN1 -sink14_data[21] => src_payload.IN1 -sink14_data[22] => src_payload.IN1 -sink14_data[23] => src_payload.IN1 -sink14_data[24] => src_payload.IN1 -sink14_data[25] => src_payload.IN1 -sink14_data[26] => src_payload.IN1 -sink14_data[27] => src_payload.IN1 -sink14_data[28] => src_payload.IN1 -sink14_data[29] => src_payload.IN1 -sink14_data[30] => src_payload.IN1 -sink14_data[31] => src_payload.IN1 -sink14_data[32] => src_payload.IN1 -sink14_data[33] => src_payload.IN1 -sink14_data[34] => src_payload.IN1 -sink14_data[35] => src_payload.IN1 -sink14_data[36] => src_payload.IN1 -sink14_data[37] => src_payload.IN1 -sink14_data[38] => src_payload.IN1 -sink14_data[39] => src_payload.IN1 -sink14_data[40] => src_payload.IN1 -sink14_data[41] => src_payload.IN1 -sink14_data[42] => src_payload.IN1 -sink14_data[43] => src_payload.IN1 -sink14_data[44] => src_payload.IN1 -sink14_data[45] => src_payload.IN1 -sink14_data[46] => src_payload.IN1 -sink14_data[47] => src_payload.IN1 -sink14_data[48] => src_payload.IN1 -sink14_data[49] => src_payload.IN1 -sink14_data[50] => src_payload.IN1 -sink14_data[51] => src_payload.IN1 -sink14_data[52] => src_payload.IN1 -sink14_data[53] => src_payload.IN1 -sink14_data[54] => src_payload.IN1 -sink14_data[55] => src_payload.IN1 -sink14_data[56] => src_payload.IN1 -sink14_data[57] => src_payload.IN1 -sink14_data[58] => src_payload.IN1 -sink14_data[59] => src_payload.IN1 -sink14_data[59] => last_cycle.IN1 -sink14_data[60] => src_payload.IN1 -sink14_data[61] => src_payload.IN1 -sink14_data[62] => src_payload.IN1 -sink14_data[63] => src_payload.IN1 -sink14_data[64] => src_payload.IN1 -sink14_data[65] => src_payload.IN1 -sink14_data[66] => src_payload.IN1 -sink14_data[67] => src_payload.IN1 -sink14_data[68] => src_payload.IN1 -sink14_data[69] => src_payload.IN1 -sink14_data[70] => src_payload.IN1 -sink14_data[71] => src_payload.IN1 -sink14_data[72] => src_payload.IN1 -sink14_data[73] => src_payload.IN1 -sink14_data[74] => src_payload.IN1 -sink14_data[75] => src_payload.IN1 -sink14_data[76] => src_payload.IN1 -sink14_data[77] => src_payload.IN1 -sink14_data[78] => src_payload.IN1 -sink14_data[79] => src_payload.IN1 -sink14_data[80] => src_payload.IN1 -sink14_data[81] => src_payload.IN1 -sink14_data[82] => src_payload.IN1 -sink14_data[83] => src_payload.IN1 -sink14_data[84] => src_payload.IN1 -sink14_data[85] => src_payload.IN1 -sink14_data[86] => src_payload.IN1 -sink14_data[87] => src_payload.IN1 -sink14_data[88] => src_payload.IN1 -sink14_data[89] => src_payload.IN1 -sink14_data[90] => src_payload.IN1 -sink14_data[91] => src_payload.IN1 -sink14_data[92] => src_payload.IN1 -sink14_data[93] => src_payload.IN1 -sink14_data[94] => src_payload.IN1 -sink14_data[95] => src_payload.IN1 -sink14_channel[0] => src_payload.IN1 -sink14_channel[1] => src_payload.IN1 -sink14_channel[2] => src_payload.IN1 -sink14_channel[3] => src_payload.IN1 -sink14_channel[4] => src_payload.IN1 -sink14_channel[5] => src_payload.IN1 -sink14_channel[6] => src_payload.IN1 -sink14_channel[7] => src_payload.IN1 -sink14_channel[8] => src_payload.IN1 -sink14_channel[9] => src_payload.IN1 -sink14_channel[10] => src_payload.IN1 -sink14_channel[11] => src_payload.IN1 -sink14_channel[12] => src_payload.IN1 -sink14_channel[13] => src_payload.IN1 -sink14_channel[14] => src_payload.IN1 -sink14_channel[15] => src_payload.IN1 -sink14_channel[16] => src_payload.IN1 -sink14_channel[17] => src_payload.IN1 -sink14_startofpacket => src_payload.IN1 -sink14_endofpacket => src_payload.IN1 -sink14_ready <= sink14_ready.DB_MAX_OUTPUT_PORT_TYPE -sink15_valid => request[15].IN1 -sink15_data[0] => src_payload.IN1 -sink15_data[1] => src_payload.IN1 -sink15_data[2] => src_payload.IN1 -sink15_data[3] => src_payload.IN1 -sink15_data[4] => src_payload.IN1 -sink15_data[5] => src_payload.IN1 -sink15_data[6] => src_payload.IN1 -sink15_data[7] => src_payload.IN1 -sink15_data[8] => src_payload.IN1 -sink15_data[9] => src_payload.IN1 -sink15_data[10] => src_payload.IN1 -sink15_data[11] => src_payload.IN1 -sink15_data[12] => src_payload.IN1 -sink15_data[13] => src_payload.IN1 -sink15_data[14] => src_payload.IN1 -sink15_data[15] => src_payload.IN1 -sink15_data[16] => src_payload.IN1 -sink15_data[17] => src_payload.IN1 -sink15_data[18] => src_payload.IN1 -sink15_data[19] => src_payload.IN1 -sink15_data[20] => src_payload.IN1 -sink15_data[21] => src_payload.IN1 -sink15_data[22] => src_payload.IN1 -sink15_data[23] => src_payload.IN1 -sink15_data[24] => src_payload.IN1 -sink15_data[25] => src_payload.IN1 -sink15_data[26] => src_payload.IN1 -sink15_data[27] => src_payload.IN1 -sink15_data[28] => src_payload.IN1 -sink15_data[29] => src_payload.IN1 -sink15_data[30] => src_payload.IN1 -sink15_data[31] => src_payload.IN1 -sink15_data[32] => src_payload.IN1 -sink15_data[33] => src_payload.IN1 -sink15_data[34] => src_payload.IN1 -sink15_data[35] => src_payload.IN1 -sink15_data[36] => src_payload.IN1 -sink15_data[37] => src_payload.IN1 -sink15_data[38] => src_payload.IN1 -sink15_data[39] => src_payload.IN1 -sink15_data[40] => src_payload.IN1 -sink15_data[41] => src_payload.IN1 -sink15_data[42] => src_payload.IN1 -sink15_data[43] => src_payload.IN1 -sink15_data[44] => src_payload.IN1 -sink15_data[45] => src_payload.IN1 -sink15_data[46] => src_payload.IN1 -sink15_data[47] => src_payload.IN1 -sink15_data[48] => src_payload.IN1 -sink15_data[49] => src_payload.IN1 -sink15_data[50] => src_payload.IN1 -sink15_data[51] => src_payload.IN1 -sink15_data[52] => src_payload.IN1 -sink15_data[53] => src_payload.IN1 -sink15_data[54] => src_payload.IN1 -sink15_data[55] => src_payload.IN1 -sink15_data[56] => src_payload.IN1 -sink15_data[57] => src_payload.IN1 -sink15_data[58] => src_payload.IN1 -sink15_data[59] => src_payload.IN1 -sink15_data[59] => last_cycle.IN1 -sink15_data[60] => src_payload.IN1 -sink15_data[61] => src_payload.IN1 -sink15_data[62] => src_payload.IN1 -sink15_data[63] => src_payload.IN1 -sink15_data[64] => src_payload.IN1 -sink15_data[65] => src_payload.IN1 -sink15_data[66] => src_payload.IN1 -sink15_data[67] => src_payload.IN1 -sink15_data[68] => src_payload.IN1 -sink15_data[69] => src_payload.IN1 -sink15_data[70] => src_payload.IN1 -sink15_data[71] => src_payload.IN1 -sink15_data[72] => src_payload.IN1 -sink15_data[73] => src_payload.IN1 -sink15_data[74] => src_payload.IN1 -sink15_data[75] => src_payload.IN1 -sink15_data[76] => src_payload.IN1 -sink15_data[77] => src_payload.IN1 -sink15_data[78] => src_payload.IN1 -sink15_data[79] => src_payload.IN1 -sink15_data[80] => src_payload.IN1 -sink15_data[81] => src_payload.IN1 -sink15_data[82] => src_payload.IN1 -sink15_data[83] => src_payload.IN1 -sink15_data[84] => src_payload.IN1 -sink15_data[85] => src_payload.IN1 -sink15_data[86] => src_payload.IN1 -sink15_data[87] => src_payload.IN1 -sink15_data[88] => src_payload.IN1 -sink15_data[89] => src_payload.IN1 -sink15_data[90] => src_payload.IN1 -sink15_data[91] => src_payload.IN1 -sink15_data[92] => src_payload.IN1 -sink15_data[93] => src_payload.IN1 -sink15_data[94] => src_payload.IN1 -sink15_data[95] => src_payload.IN1 -sink15_channel[0] => src_payload.IN1 -sink15_channel[1] => src_payload.IN1 -sink15_channel[2] => src_payload.IN1 -sink15_channel[3] => src_payload.IN1 -sink15_channel[4] => src_payload.IN1 -sink15_channel[5] => src_payload.IN1 -sink15_channel[6] => src_payload.IN1 -sink15_channel[7] => src_payload.IN1 -sink15_channel[8] => src_payload.IN1 -sink15_channel[9] => src_payload.IN1 -sink15_channel[10] => src_payload.IN1 -sink15_channel[11] => src_payload.IN1 -sink15_channel[12] => src_payload.IN1 -sink15_channel[13] => src_payload.IN1 -sink15_channel[14] => src_payload.IN1 -sink15_channel[15] => src_payload.IN1 -sink15_channel[16] => src_payload.IN1 -sink15_channel[17] => src_payload.IN1 -sink15_startofpacket => src_payload.IN1 -sink15_endofpacket => src_payload.IN1 -sink15_ready <= sink15_ready.DB_MAX_OUTPUT_PORT_TYPE -sink16_valid => request[16].IN1 -sink16_data[0] => src_payload.IN1 -sink16_data[1] => src_payload.IN1 -sink16_data[2] => src_payload.IN1 -sink16_data[3] => src_payload.IN1 -sink16_data[4] => src_payload.IN1 -sink16_data[5] => src_payload.IN1 -sink16_data[6] => src_payload.IN1 -sink16_data[7] => src_payload.IN1 -sink16_data[8] => src_payload.IN1 -sink16_data[9] => src_payload.IN1 -sink16_data[10] => src_payload.IN1 -sink16_data[11] => src_payload.IN1 -sink16_data[12] => src_payload.IN1 -sink16_data[13] => src_payload.IN1 -sink16_data[14] => src_payload.IN1 -sink16_data[15] => src_payload.IN1 -sink16_data[16] => src_payload.IN1 -sink16_data[17] => src_payload.IN1 -sink16_data[18] => src_payload.IN1 -sink16_data[19] => src_payload.IN1 -sink16_data[20] => src_payload.IN1 -sink16_data[21] => src_payload.IN1 -sink16_data[22] => src_payload.IN1 -sink16_data[23] => src_payload.IN1 -sink16_data[24] => src_payload.IN1 -sink16_data[25] => src_payload.IN1 -sink16_data[26] => src_payload.IN1 -sink16_data[27] => src_payload.IN1 -sink16_data[28] => src_payload.IN1 -sink16_data[29] => src_payload.IN1 -sink16_data[30] => src_payload.IN1 -sink16_data[31] => src_payload.IN1 -sink16_data[32] => src_payload.IN1 -sink16_data[33] => src_payload.IN1 -sink16_data[34] => src_payload.IN1 -sink16_data[35] => src_payload.IN1 -sink16_data[36] => src_payload.IN1 -sink16_data[37] => src_payload.IN1 -sink16_data[38] => src_payload.IN1 -sink16_data[39] => src_payload.IN1 -sink16_data[40] => src_payload.IN1 -sink16_data[41] => src_payload.IN1 -sink16_data[42] => src_payload.IN1 -sink16_data[43] => src_payload.IN1 -sink16_data[44] => src_payload.IN1 -sink16_data[45] => src_payload.IN1 -sink16_data[46] => src_payload.IN1 -sink16_data[47] => src_payload.IN1 -sink16_data[48] => src_payload.IN1 -sink16_data[49] => src_payload.IN1 -sink16_data[50] => src_payload.IN1 -sink16_data[51] => src_payload.IN1 -sink16_data[52] => src_payload.IN1 -sink16_data[53] => src_payload.IN1 -sink16_data[54] => src_payload.IN1 -sink16_data[55] => src_payload.IN1 -sink16_data[56] => src_payload.IN1 -sink16_data[57] => src_payload.IN1 -sink16_data[58] => src_payload.IN1 -sink16_data[59] => src_payload.IN1 -sink16_data[59] => last_cycle.IN1 -sink16_data[60] => src_payload.IN1 -sink16_data[61] => src_payload.IN1 -sink16_data[62] => src_payload.IN1 -sink16_data[63] => src_payload.IN1 -sink16_data[64] => src_payload.IN1 -sink16_data[65] => src_payload.IN1 -sink16_data[66] => src_payload.IN1 -sink16_data[67] => src_payload.IN1 -sink16_data[68] => src_payload.IN1 -sink16_data[69] => src_payload.IN1 -sink16_data[70] => src_payload.IN1 -sink16_data[71] => src_payload.IN1 -sink16_data[72] => src_payload.IN1 -sink16_data[73] => src_payload.IN1 -sink16_data[74] => src_payload.IN1 -sink16_data[75] => src_payload.IN1 -sink16_data[76] => src_payload.IN1 -sink16_data[77] => src_payload.IN1 -sink16_data[78] => src_payload.IN1 -sink16_data[79] => src_payload.IN1 -sink16_data[80] => src_payload.IN1 -sink16_data[81] => src_payload.IN1 -sink16_data[82] => src_payload.IN1 -sink16_data[83] => src_payload.IN1 -sink16_data[84] => src_payload.IN1 -sink16_data[85] => src_payload.IN1 -sink16_data[86] => src_payload.IN1 -sink16_data[87] => src_payload.IN1 -sink16_data[88] => src_payload.IN1 -sink16_data[89] => src_payload.IN1 -sink16_data[90] => src_payload.IN1 -sink16_data[91] => src_payload.IN1 -sink16_data[92] => src_payload.IN1 -sink16_data[93] => src_payload.IN1 -sink16_data[94] => src_payload.IN1 -sink16_data[95] => src_payload.IN1 -sink16_channel[0] => src_payload.IN1 -sink16_channel[1] => src_payload.IN1 -sink16_channel[2] => src_payload.IN1 -sink16_channel[3] => src_payload.IN1 -sink16_channel[4] => src_payload.IN1 -sink16_channel[5] => src_payload.IN1 -sink16_channel[6] => src_payload.IN1 -sink16_channel[7] => src_payload.IN1 -sink16_channel[8] => src_payload.IN1 -sink16_channel[9] => src_payload.IN1 -sink16_channel[10] => src_payload.IN1 -sink16_channel[11] => src_payload.IN1 -sink16_channel[12] => src_payload.IN1 -sink16_channel[13] => src_payload.IN1 -sink16_channel[14] => src_payload.IN1 -sink16_channel[15] => src_payload.IN1 -sink16_channel[16] => src_payload.IN1 -sink16_channel[17] => src_payload.IN1 -sink16_startofpacket => src_payload.IN1 -sink16_endofpacket => src_payload.IN1 -sink16_ready <= sink16_ready.DB_MAX_OUTPUT_PORT_TYPE -sink17_valid => request[17].IN1 -sink17_data[0] => src_payload.IN1 -sink17_data[1] => src_payload.IN1 -sink17_data[2] => src_payload.IN1 -sink17_data[3] => src_payload.IN1 -sink17_data[4] => src_payload.IN1 -sink17_data[5] => src_payload.IN1 -sink17_data[6] => src_payload.IN1 -sink17_data[7] => src_payload.IN1 -sink17_data[8] => src_payload.IN1 -sink17_data[9] => src_payload.IN1 -sink17_data[10] => src_payload.IN1 -sink17_data[11] => src_payload.IN1 -sink17_data[12] => src_payload.IN1 -sink17_data[13] => src_payload.IN1 -sink17_data[14] => src_payload.IN1 -sink17_data[15] => src_payload.IN1 -sink17_data[16] => src_payload.IN1 -sink17_data[17] => src_payload.IN1 -sink17_data[18] => src_payload.IN1 -sink17_data[19] => src_payload.IN1 -sink17_data[20] => src_payload.IN1 -sink17_data[21] => src_payload.IN1 -sink17_data[22] => src_payload.IN1 -sink17_data[23] => src_payload.IN1 -sink17_data[24] => src_payload.IN1 -sink17_data[25] => src_payload.IN1 -sink17_data[26] => src_payload.IN1 -sink17_data[27] => src_payload.IN1 -sink17_data[28] => src_payload.IN1 -sink17_data[29] => src_payload.IN1 -sink17_data[30] => src_payload.IN1 -sink17_data[31] => src_payload.IN1 -sink17_data[32] => src_payload.IN1 -sink17_data[33] => src_payload.IN1 -sink17_data[34] => src_payload.IN1 -sink17_data[35] => src_payload.IN1 -sink17_data[36] => src_payload.IN1 -sink17_data[37] => src_payload.IN1 -sink17_data[38] => src_payload.IN1 -sink17_data[39] => src_payload.IN1 -sink17_data[40] => src_payload.IN1 -sink17_data[41] => src_payload.IN1 -sink17_data[42] => src_payload.IN1 -sink17_data[43] => src_payload.IN1 -sink17_data[44] => src_payload.IN1 -sink17_data[45] => src_payload.IN1 -sink17_data[46] => src_payload.IN1 -sink17_data[47] => src_payload.IN1 -sink17_data[48] => src_payload.IN1 -sink17_data[49] => src_payload.IN1 -sink17_data[50] => src_payload.IN1 -sink17_data[51] => src_payload.IN1 -sink17_data[52] => src_payload.IN1 -sink17_data[53] => src_payload.IN1 -sink17_data[54] => src_payload.IN1 -sink17_data[55] => src_payload.IN1 -sink17_data[56] => src_payload.IN1 -sink17_data[57] => src_payload.IN1 -sink17_data[58] => src_payload.IN1 -sink17_data[59] => src_payload.IN1 -sink17_data[59] => last_cycle.IN1 -sink17_data[60] => src_payload.IN1 -sink17_data[61] => src_payload.IN1 -sink17_data[62] => src_payload.IN1 -sink17_data[63] => src_payload.IN1 -sink17_data[64] => src_payload.IN1 -sink17_data[65] => src_payload.IN1 -sink17_data[66] => src_payload.IN1 -sink17_data[67] => src_payload.IN1 -sink17_data[68] => src_payload.IN1 -sink17_data[69] => src_payload.IN1 -sink17_data[70] => src_payload.IN1 -sink17_data[71] => src_payload.IN1 -sink17_data[72] => src_payload.IN1 -sink17_data[73] => src_payload.IN1 -sink17_data[74] => src_payload.IN1 -sink17_data[75] => src_payload.IN1 -sink17_data[76] => src_payload.IN1 -sink17_data[77] => src_payload.IN1 -sink17_data[78] => src_payload.IN1 -sink17_data[79] => src_payload.IN1 -sink17_data[80] => src_payload.IN1 -sink17_data[81] => src_payload.IN1 -sink17_data[82] => src_payload.IN1 -sink17_data[83] => src_payload.IN1 -sink17_data[84] => src_payload.IN1 -sink17_data[85] => src_payload.IN1 -sink17_data[86] => src_payload.IN1 -sink17_data[87] => src_payload.IN1 -sink17_data[88] => src_payload.IN1 -sink17_data[89] => src_payload.IN1 -sink17_data[90] => src_payload.IN1 -sink17_data[91] => src_payload.IN1 -sink17_data[92] => src_payload.IN1 -sink17_data[93] => src_payload.IN1 -sink17_data[94] => src_payload.IN1 -sink17_data[95] => src_payload.IN1 -sink17_channel[0] => src_payload.IN1 -sink17_channel[1] => src_payload.IN1 -sink17_channel[2] => src_payload.IN1 -sink17_channel[3] => src_payload.IN1 -sink17_channel[4] => src_payload.IN1 -sink17_channel[5] => src_payload.IN1 -sink17_channel[6] => src_payload.IN1 -sink17_channel[7] => src_payload.IN1 -sink17_channel[8] => src_payload.IN1 -sink17_channel[9] => src_payload.IN1 -sink17_channel[10] => src_payload.IN1 -sink17_channel[11] => src_payload.IN1 -sink17_channel[12] => src_payload.IN1 -sink17_channel[13] => src_payload.IN1 -sink17_channel[14] => src_payload.IN1 -sink17_channel[15] => src_payload.IN1 -sink17_channel[16] => src_payload.IN1 -sink17_channel[17] => src_payload.IN1 -sink17_startofpacket => src_payload.IN1 -sink17_endofpacket => src_payload.IN1 -sink17_ready <= sink17_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= src_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= src_payload[0].DB_MAX_OUTPUT_PORT_TYPE -src_ready => last_cycle.IN0 -src_ready => sink0_ready.IN1 -src_ready => sink1_ready.IN1 -src_ready => sink2_ready.IN1 -src_ready => sink3_ready.IN1 -src_ready => sink4_ready.IN1 -src_ready => sink5_ready.IN1 -src_ready => sink6_ready.IN1 -src_ready => sink7_ready.IN1 -src_ready => sink8_ready.IN1 -src_ready => sink9_ready.IN1 -src_ready => sink10_ready.IN1 -src_ready => sink11_ready.IN1 -src_ready => sink12_ready.IN1 -src_ready => sink13_ready.IN1 -src_ready => sink14_ready.IN1 -src_ready => sink15_ready.IN1 -src_ready => sink16_ready.IN1 -src_ready => sink17_ready.IN1 -clk => clk.IN1 -reset => reset.IN1 - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -request[0] => grant[0].DATAIN -request[0] => _.IN1 -request[0] => _.IN1 -request[1] => grant[1].DATAIN -request[1] => _.IN1 -request[1] => _.IN1 -request[2] => grant[2].DATAIN -request[2] => _.IN1 -request[2] => _.IN1 -request[3] => grant[3].DATAIN -request[3] => _.IN1 -request[3] => _.IN1 -request[4] => grant[4].DATAIN -request[4] => _.IN1 -request[4] => _.IN1 -request[5] => grant[5].DATAIN -request[5] => _.IN1 -request[5] => _.IN1 -request[6] => grant[6].DATAIN -request[6] => _.IN1 -request[6] => _.IN1 -request[7] => grant[7].DATAIN -request[7] => _.IN1 -request[7] => _.IN1 -request[8] => grant[8].DATAIN -request[8] => _.IN1 -request[8] => _.IN1 -request[9] => grant[9].DATAIN -request[9] => _.IN1 -request[9] => _.IN1 -request[10] => grant[10].DATAIN -request[10] => _.IN1 -request[10] => _.IN1 -request[11] => grant[11].DATAIN -request[11] => _.IN1 -request[11] => _.IN1 -request[12] => grant[12].DATAIN -request[12] => _.IN1 -request[12] => _.IN1 -request[13] => grant[13].DATAIN -request[13] => _.IN1 -request[13] => _.IN1 -request[14] => grant[14].DATAIN -request[14] => _.IN1 -request[14] => _.IN1 -request[15] => grant[15].DATAIN -request[15] => _.IN1 -request[15] => _.IN1 -request[16] => grant[16].DATAIN -request[16] => _.IN1 -request[16] => _.IN1 -request[17] => grant[17].DATAIN -request[17] => _.IN1 -request[17] => _.IN1 -grant[0] <= request[0].DB_MAX_OUTPUT_PORT_TYPE -grant[1] <= request[1].DB_MAX_OUTPUT_PORT_TYPE -grant[2] <= request[2].DB_MAX_OUTPUT_PORT_TYPE -grant[3] <= request[3].DB_MAX_OUTPUT_PORT_TYPE -grant[4] <= request[4].DB_MAX_OUTPUT_PORT_TYPE -grant[5] <= request[5].DB_MAX_OUTPUT_PORT_TYPE -grant[6] <= request[6].DB_MAX_OUTPUT_PORT_TYPE -grant[7] <= request[7].DB_MAX_OUTPUT_PORT_TYPE -grant[8] <= request[8].DB_MAX_OUTPUT_PORT_TYPE -grant[9] <= request[9].DB_MAX_OUTPUT_PORT_TYPE -grant[10] <= request[10].DB_MAX_OUTPUT_PORT_TYPE -grant[11] <= request[11].DB_MAX_OUTPUT_PORT_TYPE -grant[12] <= request[12].DB_MAX_OUTPUT_PORT_TYPE -grant[13] <= request[13].DB_MAX_OUTPUT_PORT_TYPE -grant[14] <= request[14].DB_MAX_OUTPUT_PORT_TYPE -grant[15] <= request[15].DB_MAX_OUTPUT_PORT_TYPE -grant[16] <= request[16].DB_MAX_OUTPUT_PORT_TYPE -grant[17] <= request[17].DB_MAX_OUTPUT_PORT_TYPE -increment_top_priority => ~NO_FANOUT~ -save_top_priority => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -a[0] => Add0.IN36 -a[1] => Add0.IN35 -a[2] => Add0.IN34 -a[3] => Add0.IN33 -a[4] => Add0.IN32 -a[5] => Add0.IN31 -a[6] => Add0.IN30 -a[7] => Add0.IN29 -a[8] => Add0.IN28 -a[9] => Add0.IN27 -a[10] => Add0.IN26 -a[11] => Add0.IN25 -a[12] => Add0.IN24 -a[13] => Add0.IN23 -a[14] => Add0.IN22 -a[15] => Add0.IN21 -a[16] => Add0.IN20 -a[17] => Add0.IN19 -a[18] => Add0.IN18 -a[19] => Add0.IN17 -a[20] => Add0.IN16 -a[21] => Add0.IN15 -a[22] => Add0.IN14 -a[23] => Add0.IN13 -a[24] => Add0.IN12 -a[25] => Add0.IN11 -a[26] => Add0.IN10 -a[27] => Add0.IN9 -a[28] => Add0.IN8 -a[29] => Add0.IN7 -a[30] => Add0.IN6 -a[31] => Add0.IN5 -a[32] => Add0.IN4 -a[33] => Add0.IN3 -a[34] => Add0.IN2 -a[35] => Add0.IN1 -b[0] => Add0.IN72 -b[1] => Add0.IN71 -b[2] => Add0.IN70 -b[3] => Add0.IN69 -b[4] => Add0.IN68 -b[5] => Add0.IN67 -b[6] => Add0.IN66 -b[7] => Add0.IN65 -b[8] => Add0.IN64 -b[9] => Add0.IN63 -b[10] => Add0.IN62 -b[11] => Add0.IN61 -b[12] => Add0.IN60 -b[13] => Add0.IN59 -b[14] => Add0.IN58 -b[15] => Add0.IN57 -b[16] => Add0.IN56 -b[17] => Add0.IN55 -b[18] => Add0.IN54 -b[19] => Add0.IN53 -b[20] => Add0.IN52 -b[21] => Add0.IN51 -b[22] => Add0.IN50 -b[23] => Add0.IN49 -b[24] => Add0.IN48 -b[25] => Add0.IN47 -b[26] => Add0.IN46 -b[27] => Add0.IN45 -b[28] => Add0.IN44 -b[29] => Add0.IN43 -b[30] => Add0.IN42 -b[31] => Add0.IN41 -b[32] => Add0.IN40 -b[33] => Add0.IN39 -b[34] => Add0.IN38 -b[35] => Add0.IN37 -sum[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[8] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[9] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[10] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[11] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[12] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[13] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[14] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[15] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[16] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[17] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[18] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[19] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[20] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[21] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[22] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[23] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[24] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[25] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[26] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[27] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[28] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[29] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[30] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[31] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[32] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[33] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[34] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[35] <= Add0.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_irq_mapper:irq_mapper -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -receiver0_irq => sender_irq[5].DATAIN -sender_irq[0] <= -sender_irq[1] <= -sender_irq[2] <= -sender_irq[3] <= -sender_irq[4] <= -sender_irq[5] <= receiver0_irq.DB_MAX_OUTPUT_PORT_TYPE -sender_irq[6] <= -sender_irq[7] <= -sender_irq[8] <= -sender_irq[9] <= -sender_irq[10] <= -sender_irq[11] <= -sender_irq[12] <= -sender_irq[13] <= -sender_irq[14] <= -sender_irq[15] <= -sender_irq[16] <= -sender_irq[17] <= -sender_irq[18] <= -sender_irq[19] <= -sender_irq[20] <= -sender_irq[21] <= -sender_irq[22] <= -sender_irq[23] <= -sender_irq[24] <= -sender_irq[25] <= -sender_irq[26] <= -sender_irq[27] <= -sender_irq[28] <= -sender_irq[29] <= -sender_irq[30] <= -sender_irq[31] <= - - diff --git a/db/lights.hif b/db/lights.hif deleted file mode 100644 index 15bfca1..0000000 --- a/db/lights.hif +++ /dev/null Binary files differ diff --git a/db/lights.ipinfo b/db/lights.ipinfo deleted file mode 100644 index fa2304d..0000000 --- a/db/lights.ipinfo +++ /dev/null Binary files differ diff --git a/db/lights.lpc.html b/db/lights.lpc.html deleted file mode 100644 index 2d33dba..0000000 --- a/db/lights.lpc.html +++ /dev/null @@ -1,3506 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
NiosII|irq_mapper3312313231313100000
NiosII|rsp_xbar_mux_001|arb|adder72360363636363600000
NiosII|rsp_xbar_mux_001|arb220401800000000
NiosII|rsp_xbar_mux_001210900013500000000
NiosII|rsp_xbar_mux|arb|adder8404444400000
NiosII|rsp_xbar_mux|arb6040200000000
NiosII|rsp_xbar_mux23700011900000000
NiosII|rsp_xbar_demux_01712012111811100000
NiosII|rsp_xbar_demux_01612012111811100000
NiosII|rsp_xbar_demux_01512012111811100000
NiosII|rsp_xbar_demux_01412012111811100000
NiosII|rsp_xbar_demux_01312012111811100000
NiosII|rsp_xbar_demux_01212012111811100000
NiosII|rsp_xbar_demux_01112012111811100000
NiosII|rsp_xbar_demux_01012012111811100000
NiosII|rsp_xbar_demux_00912012111811100000
NiosII|rsp_xbar_demux_00812012111811100000
NiosII|rsp_xbar_demux_00712012111811100000
NiosII|rsp_xbar_demux_00612012111811100000
NiosII|rsp_xbar_demux_00512012111811100000
NiosII|rsp_xbar_demux_00412012111811100000
NiosII|rsp_xbar_demux_00312012111811100000
NiosII|rsp_xbar_demux_00212012111811100000
NiosII|rsp_xbar_demux_00112142423544400000
NiosII|rsp_xbar_demux12142423544400000
NiosII|cmd_xbar_mux_001|arb|adder8202422200000
NiosII|cmd_xbar_mux_001|arb6010200000000
NiosII|cmd_xbar_mux_00123700011900000000
NiosII|cmd_xbar_mux|arb|adder8202422200000
NiosII|cmd_xbar_mux|arb6010200000000
NiosII|cmd_xbar_mux23700011900000000
NiosII|cmd_xbar_demux_0011373242324210732432432400000
NiosII|cmd_xbar_demux12142423544400000
NiosII|rst_controller|alt_rst_sync_uq12000100000000
NiosII|rst_controller1714014214141400000
NiosII|id_router_017|the_default_decode0230232323232300000
NiosII|id_router_01710202011800000000
NiosII|id_router_016|the_default_decode0230232323232300000
NiosII|id_router_01610202011800000000
NiosII|id_router_015|the_default_decode0230232323232300000
NiosII|id_router_01510202011800000000
NiosII|id_router_014|the_default_decode0230232323232300000
NiosII|id_router_01410202011800000000
NiosII|id_router_013|the_default_decode0230232323232300000
NiosII|id_router_01310202011800000000
NiosII|id_router_012|the_default_decode0230232323232300000
NiosII|id_router_01210202011800000000
NiosII|id_router_011|the_default_decode0230232323232300000
NiosII|id_router_01110202011800000000
NiosII|id_router_010|the_default_decode0230232323232300000
NiosII|id_router_01010202011800000000
NiosII|id_router_009|the_default_decode0230232323232300000
NiosII|id_router_00910202011800000000
NiosII|id_router_008|the_default_decode0230232323232300000
NiosII|id_router_00810202011800000000
NiosII|id_router_007|the_default_decode0230232323232300000
NiosII|id_router_00710202011800000000
NiosII|id_router_006|the_default_decode0230232323232300000
NiosII|id_router_00610202011800000000
NiosII|id_router_005|the_default_decode0230232323232300000
NiosII|id_router_00510202011800000000
NiosII|id_router_004|the_default_decode0230232323232300000
NiosII|id_router_00410202011800000000
NiosII|id_router_003|the_default_decode0230232323232300000
NiosII|id_router_00310202011800000000
NiosII|id_router_002|the_default_decode0230232323232300000
NiosII|id_router_00210202011800000000
NiosII|id_router_001|the_default_decode0230232323232300000
NiosII|id_router_00110202011800000000
NiosII|id_router|the_default_decode0230232323232300000
NiosII|id_router10202011800000000
NiosII|addr_router_001|the_default_decode0230232323232300000
NiosII|addr_router_00110207011800000000
NiosII|addr_router|the_default_decode0230232323232300000
NiosII|addr_router10207011800000000
NiosII|lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|lcd_blon_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|lcd_blon_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|lcd_on_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|lcd_on_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|hex7_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|hex7_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|hex6_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|hex6_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|hex5_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|hex5_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|hex4_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|hex4_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|hex3_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|hex3_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|hex2_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|hex2_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|hex1_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|hex1_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|hex0_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|hex0_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|push_switches_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|push_switches_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|switches_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|switches_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|ledrs_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|ledrs_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|leds_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|leds_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|onchip_memory_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|onchip_memory_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|nios2_processor_data_master_translator_avalon_universal_master_0_agent18339853913439393900000
NiosII|nios2_processor_instruction_master_translator_avalon_universal_master_0_agent18339853913439393900000
NiosII|lcd_blon_s1_translator10372077077700000
NiosII|lcd_on_s1_translator10372077077700000
NiosII|lcd_16207_0_control_slave_translator793144314731313100000
NiosII|hex7_s1_translator10372077077700000
NiosII|hex6_s1_translator10372077077700000
NiosII|hex5_s1_translator10372077077700000
NiosII|hex4_s1_translator10372077077700000
NiosII|hex3_s1_translator10372077077700000
NiosII|hex2_s1_translator10372077077700000
NiosII|hex1_s1_translator10372077077700000
NiosII|hex0_s1_translator10372077077700000
NiosII|push_switches_s1_translator10372073677700000
NiosII|switches_s1_translator10372073677700000
NiosII|ledrs_s1_translator10372077077700000
NiosII|jtag_uart_avalon_jtag_slave_translator10362167066600000
NiosII|leds_s1_translator10372077077700000
NiosII|onchip_memory_s1_translator1038388988800000
NiosII|nios2_processor_jtag_debug_module_translator10361068266600000
NiosII|nios2_processor_data_master_translator104130139513131300000
NiosII|nios2_processor_instruction_master_translator104520529552525200000
NiosII|lcd_blon383131313331313100000
NiosII|lcd_on383131313331313100000
NiosII|lcd_16207_0150301100080000
NiosII|hex7382525253925252500000
NiosII|hex6382525253925252500000
NiosII|hex5382525253925252500000
NiosII|hex4382525253925252500000
NiosII|hex3382525253925252500000
NiosII|hex2382525253925252500000
NiosII|hex1382525253925252500000
NiosII|hex0382525253925252500000
NiosII|push_switches70003200000000
NiosII|switches220003200000000
NiosII|ledrs381414145014141400000
NiosII|leds382424244024242400000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr4000600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count4000600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram|altsyncram124000800000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram24000800000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw5000600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state5000800000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo130001600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated120001600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r130101600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr4000600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count4000600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram|altsyncram124000800000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram24000800000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw5000600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state5000800000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo130001600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated120001600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w120001600000000
NiosII|jtag_uart381023103410101000000
NiosII|onchip_memory|the_altsyncram|auto_generated|mux22270003200000000
NiosII|onchip_memory|the_altsyncram|auto_generated|decode34000700000000
NiosII|onchip_memory|the_altsyncram|auto_generated550003200000000
NiosII|onchip_memory580103200000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_jtag_debug_module_wrapper|the_nios_system_nios2_processor_jtag_debug_module_sysclk430005100000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_jtag_debug_module_wrapper|the_nios_system_nios2_processor_jtag_debug_module_tck1300104300000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_jtag_debug_module_wrapper1230005300000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_im973693364836363600000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_pib392038201920202000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo|the_nios_system_nios2_processor_oci_test_bench360360000000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount5000500000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp4202422200000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count3000200000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo15106503600000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_dtrace|nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode9060400000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_dtrace10409307200000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_itrace251723178717171700000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_dbrk890009300000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_xbrk555525655500000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_break52366367136363600000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_avalon_reg4802806800000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram|the_altsyncram|auto_generated460003200000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram460003200000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_ocimem910606500000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_debug501301711100000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci1590006900000000
NiosII|nios2_processor|nios_system_nios2_processor_register_bank_b|the_altsyncram|auto_generated440003200000000
NiosII|nios2_processor|nios_system_nios2_processor_register_bank_b440003200000000
NiosII|nios2_processor|nios_system_nios2_processor_register_bank_a|the_altsyncram|auto_generated440003200000000
NiosII|nios2_processor|nios_system_nios2_processor_register_bank_a440003200000000
NiosII|nios2_processor|the_nios_system_nios2_processor_test_bench275323833433300000
NiosII|nios2_processor148031011200000000
NiosII230008700080008
diff --git a/db/lights.lpc.rdb b/db/lights.lpc.rdb deleted file mode 100644 index a39c035..0000000 --- a/db/lights.lpc.rdb +++ /dev/null Binary files differ diff --git a/db/lights.lpc.txt b/db/lights.lpc.txt deleted file mode 100644 index 751930a..0000000 --- a/db/lights.lpc.txt +++ /dev/null @@ -1,224 +0,0 @@ -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Legal Partition Candidates ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ -; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ -; NiosII|irq_mapper ; 3 ; 31 ; 2 ; 31 ; 32 ; 31 ; 31 ; 31 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_mux_001|arb|adder ; 72 ; 36 ; 0 ; 36 ; 36 ; 36 ; 36 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_mux_001|arb ; 22 ; 0 ; 4 ; 0 ; 18 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_mux_001 ; 2109 ; 0 ; 0 ; 0 ; 135 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_mux|arb|adder ; 8 ; 4 ; 0 ; 4 ; 4 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_mux|arb ; 6 ; 0 ; 4 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_mux ; 237 ; 0 ; 0 ; 0 ; 119 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_017 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_016 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_015 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_014 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_013 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_012 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_011 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_010 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_009 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_008 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_007 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_006 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_005 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_004 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_003 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_002 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_001 ; 121 ; 4 ; 2 ; 4 ; 235 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux ; 121 ; 4 ; 2 ; 4 ; 235 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|cmd_xbar_mux_001|arb|adder ; 8 ; 2 ; 0 ; 2 ; 4 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|cmd_xbar_mux_001|arb ; 6 ; 0 ; 1 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|cmd_xbar_mux_001 ; 237 ; 0 ; 0 ; 0 ; 119 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|cmd_xbar_mux|arb|adder ; 8 ; 2 ; 0 ; 2 ; 4 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|cmd_xbar_mux|arb ; 6 ; 0 ; 1 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|cmd_xbar_mux ; 237 ; 0 ; 0 ; 0 ; 119 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|cmd_xbar_demux_001 ; 137 ; 324 ; 2 ; 324 ; 2107 ; 324 ; 324 ; 324 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|cmd_xbar_demux ; 121 ; 4 ; 2 ; 4 ; 235 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rst_controller|alt_rst_sync_uq1 ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rst_controller ; 17 ; 14 ; 0 ; 14 ; 2 ; 14 ; 14 ; 14 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_017|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_017 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_016|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_016 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_015|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_015 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_014|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_014 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_013|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_013 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_012|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_012 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_011|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_011 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_010|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_010 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_009|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_009 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_008|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_008 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_007|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_007 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_006|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_006 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_005|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_005 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_004|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_004 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_003|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_003 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_002|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_002 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_001|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_001 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|addr_router_001|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|addr_router_001 ; 102 ; 0 ; 7 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|addr_router|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|addr_router ; 102 ; 0 ; 7 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_blon_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_blon_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_on_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_on_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex7_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex7_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex6_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex6_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex5_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex5_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex4_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex4_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex3_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex3_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex2_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex2_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex1_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex1_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex0_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex0_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|push_switches_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|push_switches_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|switches_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|switches_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|ledrs_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|ledrs_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|leds_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|leds_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|onchip_memory_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|onchip_memory_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor_data_master_translator_avalon_universal_master_0_agent ; 183 ; 39 ; 85 ; 39 ; 134 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor_instruction_master_translator_avalon_universal_master_0_agent ; 183 ; 39 ; 85 ; 39 ; 134 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_blon_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_on_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_16207_0_control_slave_translator ; 79 ; 31 ; 44 ; 31 ; 47 ; 31 ; 31 ; 31 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex7_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex6_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex5_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex4_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex3_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex2_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex1_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex0_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|push_switches_s1_translator ; 103 ; 7 ; 20 ; 7 ; 36 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|switches_s1_translator ; 103 ; 7 ; 20 ; 7 ; 36 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|ledrs_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart_avalon_jtag_slave_translator ; 103 ; 6 ; 21 ; 6 ; 70 ; 6 ; 6 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|leds_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|onchip_memory_s1_translator ; 103 ; 8 ; 3 ; 8 ; 89 ; 8 ; 8 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor_jtag_debug_module_translator ; 103 ; 6 ; 10 ; 6 ; 82 ; 6 ; 6 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor_data_master_translator ; 104 ; 13 ; 0 ; 13 ; 95 ; 13 ; 13 ; 13 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor_instruction_master_translator ; 104 ; 52 ; 0 ; 52 ; 95 ; 52 ; 52 ; 52 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_blon ; 38 ; 31 ; 31 ; 31 ; 33 ; 31 ; 31 ; 31 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_on ; 38 ; 31 ; 31 ; 31 ; 33 ; 31 ; 31 ; 31 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_16207_0 ; 15 ; 0 ; 3 ; 0 ; 11 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex7 ; 38 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex6 ; 38 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex5 ; 38 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex4 ; 38 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex3 ; 38 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex2 ; 38 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex1 ; 38 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex0 ; 38 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|push_switches ; 7 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|switches ; 22 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|ledrs ; 38 ; 14 ; 14 ; 14 ; 50 ; 14 ; 14 ; 14 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|leds ; 38 ; 24 ; 24 ; 24 ; 40 ; 24 ; 24 ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr ; 4 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count ; 4 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram|altsyncram1 ; 24 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram ; 24 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw ; 5 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state ; 5 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo ; 13 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated ; 12 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r ; 13 ; 0 ; 1 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr ; 4 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count ; 4 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram|altsyncram1 ; 24 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram ; 24 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw ; 5 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state ; 5 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo ; 13 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated ; 12 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w ; 12 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart ; 38 ; 10 ; 23 ; 10 ; 34 ; 10 ; 10 ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|onchip_memory|the_altsyncram|auto_generated|mux2 ; 227 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|onchip_memory|the_altsyncram|auto_generated|decode3 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|onchip_memory|the_altsyncram|auto_generated ; 55 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|onchip_memory ; 58 ; 0 ; 1 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_jtag_debug_module_wrapper|the_nios_system_nios2_processor_jtag_debug_module_sysclk ; 43 ; 0 ; 0 ; 0 ; 51 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_jtag_debug_module_wrapper|the_nios_system_nios2_processor_jtag_debug_module_tck ; 130 ; 0 ; 1 ; 0 ; 43 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_jtag_debug_module_wrapper ; 123 ; 0 ; 0 ; 0 ; 53 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_im ; 97 ; 36 ; 93 ; 36 ; 48 ; 36 ; 36 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_pib ; 39 ; 20 ; 38 ; 20 ; 19 ; 20 ; 20 ; 20 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo|the_nios_system_nios2_processor_oci_test_bench ; 36 ; 0 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount ; 5 ; 0 ; 0 ; 0 ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp ; 4 ; 2 ; 0 ; 2 ; 4 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo ; 151 ; 0 ; 65 ; 0 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_dtrace|nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode ; 9 ; 0 ; 6 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_dtrace ; 104 ; 0 ; 93 ; 0 ; 72 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_itrace ; 25 ; 17 ; 23 ; 17 ; 87 ; 17 ; 17 ; 17 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_dbrk ; 89 ; 0 ; 0 ; 0 ; 93 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_xbrk ; 55 ; 5 ; 52 ; 5 ; 6 ; 5 ; 5 ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_break ; 52 ; 36 ; 6 ; 36 ; 71 ; 36 ; 36 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_avalon_reg ; 48 ; 0 ; 28 ; 0 ; 68 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram|the_altsyncram|auto_generated ; 46 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram ; 46 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_ocimem ; 91 ; 0 ; 6 ; 0 ; 65 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_debug ; 50 ; 1 ; 30 ; 1 ; 7 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci ; 159 ; 0 ; 0 ; 0 ; 69 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|nios_system_nios2_processor_register_bank_b|the_altsyncram|auto_generated ; 44 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|nios_system_nios2_processor_register_bank_b ; 44 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|nios_system_nios2_processor_register_bank_a|the_altsyncram|auto_generated ; 44 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|nios_system_nios2_processor_register_bank_a ; 44 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_test_bench ; 275 ; 3 ; 238 ; 3 ; 34 ; 3 ; 3 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor ; 148 ; 0 ; 31 ; 0 ; 112 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII ; 23 ; 0 ; 0 ; 0 ; 87 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 8 ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/db/lights.map.ammdb b/db/lights.map.ammdb deleted file mode 100644 index a3faede..0000000 --- a/db/lights.map.ammdb +++ /dev/null Binary files differ diff --git a/db/lights.map.bpm b/db/lights.map.bpm deleted file mode 100644 index 47b5b67..0000000 --- a/db/lights.map.bpm +++ /dev/null Binary files differ diff --git a/db/lights.map.cdb b/db/lights.map.cdb deleted file mode 100644 index 7a6133a..0000000 --- a/db/lights.map.cdb +++ /dev/null Binary files differ diff --git a/db/lights.map.hdb b/db/lights.map.hdb deleted file mode 100644 index 5e9211f..0000000 --- a/db/lights.map.hdb +++ /dev/null Binary files differ diff --git a/db/lights.map.kpt b/db/lights.map.kpt deleted file mode 100644 index 141e6b7..0000000 --- a/db/lights.map.kpt +++ /dev/null Binary files differ diff --git a/db/lights.map.logdb b/db/lights.map.logdb deleted file mode 100644 index d45424f..0000000 --- a/db/lights.map.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/db/lights.map.qmsg b/db/lights.map.qmsg deleted file mode 100644 index 48de8e6..0000000 --- a/db/lights.map.qmsg +++ /dev/null @@ -1,459 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1482368833579 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1482368833579 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 22 10:07:13 2016 " "Processing started: Thu Dec 22 10:07:13 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1482368833579 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1482368833579 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lights -c lights " "Command: quartus_map --read_settings_files=on --write_settings_files=off lights -c lights" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1482368833579 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1482368833940 ""} -{ "Info" "ISGN_START_ELABORATION_QSYS" "nios_system.qsys " "Elaborating Qsys system entity \"nios_system.qsys\"" { } { } 0 12248 "Elaborating Qsys system entity \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368833977 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:14 Progress: Loading qsys_tutorial/nios_system.qsys " "2016.12.22.10:07:14 Progress: Loading qsys_tutorial/nios_system.qsys" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368834703 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:14 Progress: Reading input file " "2016.12.22.10:07:14 Progress: Reading input file" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368834888 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:14 Progress: Adding clk_0 \[clock_source 13.0\] " "2016.12.22.10:07:14 Progress: Adding clk_0 \[clock_source 13.0\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368834935 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module clk_0 " "2016.12.22.10:07:15 Progress: Parameterizing module clk_0" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835119 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding nios2_processor \[altera_nios2_qsys 13.0\] " "2016.12.22.10:07:15 Progress: Adding nios2_processor \[altera_nios2_qsys 13.0\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835119 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module nios2_processor " "2016.12.22.10:07:15 Progress: Parameterizing module nios2_processor" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835819 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding onchip_memory \[altera_avalon_onchip_memory2 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding onchip_memory \[altera_avalon_onchip_memory2 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835819 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module onchip_memory " "2016.12.22.10:07:15 Progress: Parameterizing module onchip_memory" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835888 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding jtag_uart \[altera_avalon_jtag_uart 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding jtag_uart \[altera_avalon_jtag_uart 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835888 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module jtag_uart " "2016.12.22.10:07:15 Progress: Parameterizing module jtag_uart" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835935 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding LEDs \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding LEDs \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835935 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module LEDs " "2016.12.22.10:07:15 Progress: Parameterizing module LEDs" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835972 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding LEDRs \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding LEDRs \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835972 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module LEDRs " "2016.12.22.10:07:15 Progress: Parameterizing module LEDRs" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835972 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding switches \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding switches \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835972 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module switches " "2016.12.22.10:07:15 Progress: Parameterizing module switches" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding push_switches \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding push_switches \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module push_switches " "2016.12.22.10:07:15 Progress: Parameterizing module push_switches" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding hex0 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding hex0 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module hex0 " "2016.12.22.10:07:15 Progress: Parameterizing module hex0" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding hex1 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding hex1 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module hex1 " "2016.12.22.10:07:15 Progress: Parameterizing module hex1" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding hex2 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding hex2 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module hex2 " "2016.12.22.10:07:15 Progress: Parameterizing module hex2" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding hex3 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding hex3 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module hex3 " "2016.12.22.10:07:15 Progress: Parameterizing module hex3" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding hex4 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding hex4 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module hex4 " "2016.12.22.10:07:15 Progress: Parameterizing module hex4" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding hex5 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding hex5 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module hex5 " "2016.12.22.10:07:15 Progress: Parameterizing module hex5" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding hex6 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding hex6 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Parameterizing module hex6 " "2016.12.22.10:07:16 Progress: Parameterizing module hex6" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836003 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Adding hex7 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:16 Progress: Adding hex7 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836003 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Parameterizing module hex7 " "2016.12.22.10:07:16 Progress: Parameterizing module hex7" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836003 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Adding lcd_16207_0 \[altera_avalon_lcd_16207 13.0.1.99.2\] " "2016.12.22.10:07:16 Progress: Adding lcd_16207_0 \[altera_avalon_lcd_16207 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836003 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Parameterizing module lcd_16207_0 " "2016.12.22.10:07:16 Progress: Parameterizing module lcd_16207_0" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836019 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Adding lcd_on \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:16 Progress: Adding lcd_on \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836019 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Parameterizing module lcd_on " "2016.12.22.10:07:16 Progress: Parameterizing module lcd_on" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836019 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Adding lcd_blon \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:16 Progress: Adding lcd_blon \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836019 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Parameterizing module lcd_blon " "2016.12.22.10:07:16 Progress: Parameterizing module lcd_blon" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836019 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Building connections " "2016.12.22.10:07:16 Progress: Building connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836019 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Parameterizing connections " "2016.12.22.10:07:16 Progress: Parameterizing connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836335 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Validating " "2016.12.22.10:07:16 Progress: Validating" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836335 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Done reading input file " "2016.12.22.10:07:16 Progress: Done reading input file" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836974 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. " "Nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368837290 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. " "Nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368837290 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios_system: Generating nios_system \"nios_system\" for QUARTUS_SYNTH " "Nios_system: Generating nios_system \"nios_system\" for QUARTUS_SYNTH" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368838207 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Pipeline_bridge_swap_transform: After transform: 19 modules, 75 connections " "Pipeline_bridge_swap_transform: After transform: 19 modules, 75 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368838438 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "No custom instruction connections, skipping transform " "No custom instruction connections, skipping transform " { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368838446 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_translator_transform: After transform: 39 modules, 155 connections " "Merlin_translator_transform: After transform: 39 modules, 155 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368839130 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_domain_transform: After transform: 78 modules, 423 connections " "Merlin_domain_transform: After transform: 78 modules, 423 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368840233 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_router_transform: After transform: 98 modules, 503 connections " "Merlin_router_transform: After transform: 98 modules, 503 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368840668 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Reset_adaptation_transform: After transform: 99 modules, 390 connections " "Reset_adaptation_transform: After transform: 99 modules, 390 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368840752 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_network_to_switch_transform: After transform: 138 modules, 470 connections " "Merlin_network_to_switch_transform: After transform: 138 modules, 470 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368840984 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_mm_transform: After transform: 138 modules, 470 connections " "Merlin_mm_transform: After transform: 138 modules, 470 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368841081 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_interrupt_mapper_transform: After transform: 139 modules, 473 connections " "Merlin_interrupt_mapper_transform: After transform: 139 modules, 473 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368841112 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 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"Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842239 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842239 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842239 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842239 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842239 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842239 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842239 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842239 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842239 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842239 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842239 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842239 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' " "Nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842677 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: Generation command is \[exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus \] " "Nios2_processor: Generation command is \[exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842677 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.22 10:07:23 (*) Starting Nios II generation " "Nios2_processor: # 2016.12.22 10:07:23 (*) Starting Nios II generation" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.22 10:07:23 (*) Checking for plaintext license. " "Nios2_processor: # 2016.12.22 10:07:23 (*) Checking for plaintext license." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.22 10:07:23 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus " "Nios2_processor: # 2016.12.22 10:07:23 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.22 10:07:23 (*) Defaulting to contents of LM_LICENSE_FILE environment variable " "Nios2_processor: # 2016.12.22 10:07:23 (*) Defaulting to contents of LM_LICENSE_FILE environment variable" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.22 10:07:23 (*) LM_LICENSE_FILE environment variable is empty " "Nios2_processor: # 2016.12.22 10:07:23 (*) LM_LICENSE_FILE environment variable is empty" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.22 10:07:23 (*) Plaintext license not found. " "Nios2_processor: # 2016.12.22 10:07:23 (*) Plaintext license not found." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.22 10:07:23 (*) No license required to generate encrypted Nios II/e. " "Nios2_processor: # 2016.12.22 10:07:23 (*) No license required to generate encrypted Nios II/e." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.22 10:07:23 (*) Elaborating CPU configuration settings " "Nios2_processor: # 2016.12.22 10:07:23 (*) Elaborating CPU configuration settings" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.22 10:07:23 (*) Creating all objects for CPU " "Nios2_processor: # 2016.12.22 10:07:23 (*) Creating all objects for CPU" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.22 10:07:24 (*) Generating RTL from CPU objects " "Nios2_processor: # 2016.12.22 10:07:24 (*) Generating RTL from CPU objects" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.22 10:07:24 (*) Creating plain-text RTL " "Nios2_processor: # 2016.12.22 10:07:24 (*) Creating plain-text RTL" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.22 10:07:26 (*) Done Nios II generation " "Nios2_processor: # 2016.12.22 10:07:26 (*) Done Nios II generation" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' " "Nios2_processor: Done RTL generation for module 'nios_system_nios2_processor'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: \"nios_system\" instantiated altera_nios2_qsys \"nios2_processor\" " "Nios2_processor: \"nios_system\" instantiated altera_nios2_qsys \"nios2_processor\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846840 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' " "Onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846877 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Onchip_memory: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 \] " "Onchip_memory: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846877 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' " "Onchip_memory: Done RTL generation for module 'nios_system_onchip_memory'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368847896 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Onchip_memory: \"nios_system\" instantiated altera_avalon_onchip_memory2 \"onchip_memory\" " "Onchip_memory: \"nios_system\" instantiated altera_avalon_onchip_memory2 \"onchip_memory\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368847911 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' " "Jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368847927 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Jtag_uart: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 \] " "Jtag_uart: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368847927 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' " "Jtag_uart: Done RTL generation for module 'nios_system_jtag_uart'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848212 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Jtag_uart: \"nios_system\" instantiated altera_avalon_jtag_uart \"jtag_uart\" " "Jtag_uart: \"nios_system\" instantiated altera_avalon_jtag_uart \"jtag_uart\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848212 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDs: Starting RTL generation for module 'nios_system_LEDs' " "LEDs: Starting RTL generation for module 'nios_system_LEDs'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848227 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDs: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 \] " "LEDs: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848243 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDs: Done RTL generation for module 'nios_system_LEDs' " "LEDs: Done RTL generation for module 'nios_system_LEDs'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848412 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDs: \"nios_system\" instantiated altera_avalon_pio \"LEDs\" " "LEDs: \"nios_system\" instantiated altera_avalon_pio \"LEDs\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848412 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDRs: Starting RTL generation for module 'nios_system_LEDRs' " "LEDRs: Starting RTL generation for module 'nios_system_LEDRs'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848428 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDRs: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 \] " "LEDRs: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848428 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDRs: Done RTL generation for module 'nios_system_LEDRs' " "LEDRs: Done RTL generation for module 'nios_system_LEDRs'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848612 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDRs: \"nios_system\" instantiated altera_avalon_pio \"LEDRs\" " "LEDRs: \"nios_system\" instantiated altera_avalon_pio \"LEDRs\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848612 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Switches: Starting RTL generation for module 'nios_system_switches' " "Switches: Starting RTL generation for module 'nios_system_switches'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848643 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Switches: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 \] " "Switches: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848643 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Switches: Done RTL generation for module 'nios_system_switches' " "Switches: Done RTL generation for module 'nios_system_switches'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848812 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Switches: \"nios_system\" instantiated altera_avalon_pio \"switches\" " "Switches: \"nios_system\" instantiated altera_avalon_pio \"switches\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848812 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Push_switches: Starting RTL generation for module 'nios_system_push_switches' " "Push_switches: Starting RTL generation for module 'nios_system_push_switches'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848828 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Push_switches: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 \] " "Push_switches: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848828 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Push_switches: Done RTL generation for module 'nios_system_push_switches' " "Push_switches: Done RTL generation for module 'nios_system_push_switches'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848997 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Push_switches: \"nios_system\" instantiated altera_avalon_pio \"push_switches\" " "Push_switches: \"nios_system\" instantiated altera_avalon_pio \"push_switches\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848997 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Hex0: Starting RTL generation for module 'nios_system_hex0' " "Hex0: Starting RTL generation for module 'nios_system_hex0'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849013 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Hex0: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 \] " "Hex0: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849013 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Hex0: Done RTL generation for module 'nios_system_hex0' " "Hex0: Done RTL generation for module 'nios_system_hex0'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849198 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Hex0: \"nios_system\" instantiated altera_avalon_pio \"hex0\" " "Hex0: \"nios_system\" instantiated altera_avalon_pio \"hex0\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849198 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_16207_0: Starting RTL generation for module 'nios_system_lcd_16207_0' " "Lcd_16207_0: Starting RTL generation for module 'nios_system_lcd_16207_0'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849214 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_16207_0: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 \] " "Lcd_16207_0: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849214 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_16207_0: Done RTL generation for module 'nios_system_lcd_16207_0' " "Lcd_16207_0: Done RTL generation for module 'nios_system_lcd_16207_0'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849382 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_16207_0: \"nios_system\" instantiated altera_avalon_lcd_16207 \"lcd_16207_0\" " "Lcd_16207_0: \"nios_system\" instantiated altera_avalon_lcd_16207 \"lcd_16207_0\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849382 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_on: Starting RTL generation for module 'nios_system_lcd_on' " "Lcd_on: Starting RTL generation for module 'nios_system_lcd_on'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849398 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_on: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 \] " "Lcd_on: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849398 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_on: Done RTL generation for module 'nios_system_lcd_on' " "Lcd_on: Done RTL generation for module 'nios_system_lcd_on'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849582 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_on: \"nios_system\" instantiated altera_avalon_pio \"lcd_on\" " "Lcd_on: \"nios_system\" instantiated altera_avalon_pio \"lcd_on\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849582 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_instruction_master_translator: \"nios_system\" instantiated altera_merlin_master_translator \"nios2_processor_instruction_master_translator\" " "Nios2_processor_instruction_master_translator: \"nios_system\" instantiated altera_merlin_master_translator \"nios2_processor_instruction_master_translator\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849582 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_jtag_debug_module_translator: \"nios_system\" instantiated altera_merlin_slave_translator \"nios2_processor_jtag_debug_module_translator\" " "Nios2_processor_jtag_debug_module_translator: \"nios_system\" instantiated altera_merlin_slave_translator \"nios2_processor_jtag_debug_module_translator\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849598 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: \"nios_system\" instantiated altera_merlin_master_agent \"nios2_processor_instruction_master_translator_avalon_universal_master_0_agent\" " "Nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: \"nios_system\" instantiated altera_merlin_master_agent \"nios2_processor_instruction_master_translator_avalon_universal_master_0_agent\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849614 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: \"nios_system\" instantiated altera_merlin_slave_agent \"nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\" " "Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: \"nios_system\" instantiated altera_merlin_slave_agent \"nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849614 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: \"nios_system\" instantiated altera_avalon_sc_fifo \"nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo\" " "Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: \"nios_system\" instantiated altera_avalon_sc_fifo \"nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849629 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Addr_router: \"nios_system\" instantiated altera_merlin_router \"addr_router\" " "Addr_router: \"nios_system\" instantiated altera_merlin_router \"addr_router\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849645 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Addr_router_001: \"nios_system\" instantiated altera_merlin_router \"addr_router_001\" " "Addr_router_001: \"nios_system\" instantiated altera_merlin_router \"addr_router_001\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849676 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Id_router: \"nios_system\" instantiated altera_merlin_router \"id_router\" " "Id_router: \"nios_system\" instantiated altera_merlin_router \"id_router\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849683 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Id_router_002: \"nios_system\" instantiated altera_merlin_router \"id_router_002\" " "Id_router_002: \"nios_system\" instantiated altera_merlin_router \"id_router_002\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849698 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rst_controller: \"nios_system\" instantiated altera_reset_controller \"rst_controller\" " "Rst_controller: \"nios_system\" instantiated altera_reset_controller \"rst_controller\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849698 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Cmd_xbar_demux: \"nios_system\" instantiated altera_merlin_demultiplexer \"cmd_xbar_demux\" " "Cmd_xbar_demux: \"nios_system\" instantiated altera_merlin_demultiplexer \"cmd_xbar_demux\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849714 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Cmd_xbar_demux_001: \"nios_system\" instantiated altera_merlin_demultiplexer \"cmd_xbar_demux_001\" " "Cmd_xbar_demux_001: \"nios_system\" instantiated altera_merlin_demultiplexer \"cmd_xbar_demux_001\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849761 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Cmd_xbar_mux: \"nios_system\" instantiated altera_merlin_multiplexer \"cmd_xbar_mux\" " "Cmd_xbar_mux: \"nios_system\" instantiated altera_merlin_multiplexer \"cmd_xbar_mux\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849798 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rsp_xbar_demux_002: \"nios_system\" instantiated altera_merlin_demultiplexer \"rsp_xbar_demux_002\" " "Rsp_xbar_demux_002: \"nios_system\" instantiated altera_merlin_demultiplexer \"rsp_xbar_demux_002\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849829 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rsp_xbar_mux: \"nios_system\" instantiated altera_merlin_multiplexer \"rsp_xbar_mux\" " "Rsp_xbar_mux: \"nios_system\" instantiated altera_merlin_multiplexer \"rsp_xbar_mux\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849861 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv " "Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849861 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rsp_xbar_mux_001: \"nios_system\" instantiated altera_merlin_multiplexer \"rsp_xbar_mux_001\" " "Rsp_xbar_mux_001: \"nios_system\" instantiated altera_merlin_multiplexer \"rsp_xbar_mux_001\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849929 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv " "Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849929 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Irq_mapper: \"nios_system\" instantiated altera_irq_mapper \"irq_mapper\" " "Irq_mapper: \"nios_system\" instantiated altera_irq_mapper \"irq_mapper\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849945 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios_system: Done nios_system\" with 28 modules, 155 files, 4086283 bytes " "Nios_system: Done nios_system\" with 28 modules, 155 files, 4086283 bytes" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849945 ""} -{ "Info" "ISGN_END_ELABORATION_QSYS" "nios_system.qsys " "Finished elaborating Qsys system entity \"nios_system.qsys\"" { } { } 0 12249 "Finished elaborating Qsys system entity \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368850903 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lights.vhd 2 1 " "Found 2 design units, including 1 entities, in source file lights.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lights-lights_rtl " "Found design unit 1: lights-lights_rtl" { } { { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 27 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851319 ""} { "Info" "ISGN_ENTITY_NAME" "1 lights " "Found entity 1: lights" { } { { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851319 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851319 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_system/synthesis/nios_system.v 1 1 " "Found 1 design units, including 1 entities, in source file nios_system/synthesis/nios_system.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system " "Found entity 1: nios_system" { } { { "nios_system/synthesis/nios_system.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851335 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851335 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/nios_system.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/nios_system.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system " "Found entity 1: nios_system" { } { { "db/ip/nios_system/nios_system.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/nios_system.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851366 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851366 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" { } { { "db/ip/nios_system/submodules/altera_avalon_sc_fifo.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_avalon_sc_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851366 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851366 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_arbitrator " "Found entity 1: altera_merlin_arbitrator" { } { { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 103 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851366 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_arb_adder " "Found entity 2: altera_merlin_arb_adder" { } { { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 228 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851366 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851366 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_uncompressor " "Found entity 1: altera_merlin_burst_uncompressor" { } { { "db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851366 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851366 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_master_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_master_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_agent " "Found entity 1: altera_merlin_master_agent" { } { { "db/ip/nios_system/submodules/altera_merlin_master_agent.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_agent.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851366 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851366 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_master_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_master_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_translator " "Found entity 1: altera_merlin_master_translator" { } { { "db/ip/nios_system/submodules/altera_merlin_master_translator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_translator.sv" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851384 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851384 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_slave_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_agent " "Found entity 1: altera_merlin_slave_agent" { } { { "db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851388 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851388 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_slave_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_slave_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_translator " "Found entity 1: altera_merlin_slave_translator" { } { { "db/ip/nios_system/submodules/altera_merlin_slave_translator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_translator.sv" 35 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851388 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851388 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_reset_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_reset_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_controller " "Found entity 1: altera_reset_controller" { } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851388 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851388 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_synchronizer " "Found entity 1: altera_reset_synchronizer" { } { { "db/ip/nios_system/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_synchronizer.v" 24 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851388 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851388 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_ledrs.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_ledrs.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_LEDRs " "Found entity 1: nios_system_LEDRs" { } { { "db/ip/nios_system/submodules/nios_system_LEDRs.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_LEDRs.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851388 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851388 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_leds.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_leds.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_LEDs " "Found entity 1: nios_system_LEDs" { } { { "db/ip/nios_system/submodules/nios_system_LEDs.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_LEDs.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851388 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851388 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel nios_system_addr_router.sv(48) " "Verilog HDL Declaration information at nios_system_addr_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1482368851404 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel nios_system_addr_router.sv(49) " "Verilog HDL Declaration information at nios_system_addr_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1482368851404 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_addr_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_addr_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_addr_router_default_decode " "Found entity 1: nios_system_addr_router_default_decode" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851404 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_addr_router " "Found entity 2: nios_system_addr_router" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851404 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851404 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel nios_system_addr_router_001.sv(48) " "Verilog HDL Declaration information at nios_system_addr_router_001.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1482368851404 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel nios_system_addr_router_001.sv(49) " "Verilog HDL Declaration information at nios_system_addr_router_001.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1482368851404 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_addr_router_001.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_addr_router_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_addr_router_001_default_decode " "Found entity 1: nios_system_addr_router_001_default_decode" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851404 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_addr_router_001 " "Found entity 2: nios_system_addr_router_001" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851404 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851404 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_cmd_xbar_demux " "Found entity 1: nios_system_cmd_xbar_demux" { } { { "db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851404 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851404 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_cmd_xbar_demux_001 " "Found entity 1: nios_system_cmd_xbar_demux_001" { } { { "db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851420 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851420 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_cmd_xbar_mux " "Found entity 1: nios_system_cmd_xbar_mux" { } { { "db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851420 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851420 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_hex0.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_hex0.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_hex0 " "Found entity 1: nios_system_hex0" { } { { "db/ip/nios_system/submodules/nios_system_hex0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_hex0.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851420 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851420 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel nios_system_id_router.sv(48) " "Verilog HDL Declaration information at nios_system_id_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1482368851420 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel nios_system_id_router.sv(49) " "Verilog HDL Declaration information at nios_system_id_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1482368851420 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_id_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_id_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_id_router_default_decode " "Found entity 1: nios_system_id_router_default_decode" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851420 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_id_router " "Found entity 2: nios_system_id_router" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851420 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851420 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel nios_system_id_router_002.sv(48) " "Verilog HDL Declaration information at nios_system_id_router_002.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1482368851420 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel nios_system_id_router_002.sv(49) " "Verilog HDL Declaration information at nios_system_id_router_002.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1482368851420 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_id_router_002.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_id_router_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_id_router_002_default_decode " "Found entity 1: nios_system_id_router_002_default_decode" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851420 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_id_router_002 " "Found entity 2: nios_system_id_router_002" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851420 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851420 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_irq_mapper.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_irq_mapper.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_irq_mapper " "Found entity 1: nios_system_irq_mapper" { } { { "db/ip/nios_system/submodules/nios_system_irq_mapper.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_irq_mapper.sv" 31 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851435 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851435 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_jtag_uart.v 5 5 " "Found 5 design units, including 5 entities, in source file db/ip/nios_system/submodules/nios_system_jtag_uart.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_jtag_uart_sim_scfifo_w " "Found entity 1: nios_system_jtag_uart_sim_scfifo_w" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851435 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_jtag_uart_scfifo_w " "Found entity 2: nios_system_jtag_uart_scfifo_w" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 77 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851435 ""} { "Info" "ISGN_ENTITY_NAME" "3 nios_system_jtag_uart_sim_scfifo_r " "Found entity 3: nios_system_jtag_uart_sim_scfifo_r" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 162 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851435 ""} { "Info" "ISGN_ENTITY_NAME" "4 nios_system_jtag_uart_scfifo_r " "Found entity 4: nios_system_jtag_uart_scfifo_r" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 240 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851435 ""} { "Info" "ISGN_ENTITY_NAME" "5 nios_system_jtag_uart " "Found entity 5: nios_system_jtag_uart" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 327 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851435 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851435 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_lcd_16207_0 " "Found entity 1: nios_system_lcd_16207_0" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851435 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851435 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_lcd_on.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_lcd_on.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_lcd_on " "Found entity 1: nios_system_lcd_on" { } { { "db/ip/nios_system/submodules/nios_system_lcd_on.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_on.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851435 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851435 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor.v 21 21 " "Found 21 design units, including 21 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_register_bank_a_module " "Found entity 1: nios_system_nios2_processor_register_bank_a_module" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_nios2_processor_register_bank_b_module " "Found entity 2: nios_system_nios2_processor_register_bank_b_module" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 84 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "3 nios_system_nios2_processor_nios2_oci_debug " "Found entity 3: nios_system_nios2_processor_nios2_oci_debug" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 147 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "4 nios_system_nios2_processor_ociram_sp_ram_module " "Found entity 4: nios_system_nios2_processor_ociram_sp_ram_module" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 288 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "5 nios_system_nios2_processor_nios2_ocimem " "Found entity 5: nios_system_nios2_processor_nios2_ocimem" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 346 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "6 nios_system_nios2_processor_nios2_avalon_reg " "Found entity 6: nios_system_nios2_processor_nios2_avalon_reg" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 524 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "7 nios_system_nios2_processor_nios2_oci_break " "Found entity 7: nios_system_nios2_processor_nios2_oci_break" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 616 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "8 nios_system_nios2_processor_nios2_oci_xbrk " "Found entity 8: nios_system_nios2_processor_nios2_oci_xbrk" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 910 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "9 nios_system_nios2_processor_nios2_oci_dbrk " "Found entity 9: nios_system_nios2_processor_nios2_oci_dbrk" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1116 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "10 nios_system_nios2_processor_nios2_oci_itrace " "Found entity 10: nios_system_nios2_processor_nios2_oci_itrace" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1302 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "11 nios_system_nios2_processor_nios2_oci_td_mode " "Found entity 11: nios_system_nios2_processor_nios2_oci_td_mode" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1599 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "12 nios_system_nios2_processor_nios2_oci_dtrace " "Found entity 12: nios_system_nios2_processor_nios2_oci_dtrace" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1666 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "13 nios_system_nios2_processor_nios2_oci_compute_tm_count " "Found entity 13: nios_system_nios2_processor_nios2_oci_compute_tm_count" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1760 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "14 nios_system_nios2_processor_nios2_oci_fifowp_inc " "Found entity 14: nios_system_nios2_processor_nios2_oci_fifowp_inc" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1831 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "15 nios_system_nios2_processor_nios2_oci_fifocount_inc " "Found entity 15: nios_system_nios2_processor_nios2_oci_fifocount_inc" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1873 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "16 nios_system_nios2_processor_nios2_oci_fifo " "Found entity 16: nios_system_nios2_processor_nios2_oci_fifo" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1919 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "17 nios_system_nios2_processor_nios2_oci_pib " "Found entity 17: nios_system_nios2_processor_nios2_oci_pib" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2424 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "18 nios_system_nios2_processor_nios2_oci_im " "Found entity 18: nios_system_nios2_processor_nios2_oci_im" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2492 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "19 nios_system_nios2_processor_nios2_performance_monitors " "Found entity 19: nios_system_nios2_processor_nios2_performance_monitors" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2608 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "20 nios_system_nios2_processor_nios2_oci " "Found entity 20: nios_system_nios2_processor_nios2_oci" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2624 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "21 nios_system_nios2_processor " "Found entity 21: nios_system_nios2_processor" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3129 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_jtag_debug_module_sysclk " "Found entity 1: nios_system_nios2_processor_jtag_debug_module_sysclk" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_jtag_debug_module_tck " "Found entity 1: nios_system_nios2_processor_jtag_debug_module_tck" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_jtag_debug_module_wrapper " "Found entity 1: nios_system_nios2_processor_jtag_debug_module_wrapper" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_oci_test_bench " "Found entity 1: nios_system_nios2_processor_oci_test_bench" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851483 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851483 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_test_bench " "Found entity 1: nios_system_nios2_processor_test_bench" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851487 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851487 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_onchip_memory.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_onchip_memory.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_onchip_memory " "Found entity 1: nios_system_onchip_memory" { } { { "db/ip/nios_system/submodules/nios_system_onchip_memory.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851488 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851488 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_push_switches.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_push_switches.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_push_switches " "Found entity 1: nios_system_push_switches" { } { { "db/ip/nios_system/submodules/nios_system_push_switches.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_push_switches.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851488 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851488 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_rsp_xbar_demux_002 " "Found entity 1: nios_system_rsp_xbar_demux_002" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851488 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851488 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_rsp_xbar_mux " "Found entity 1: nios_system_rsp_xbar_mux" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851488 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851488 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_rsp_xbar_mux_001 " "Found entity 1: nios_system_rsp_xbar_mux_001" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851488 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851488 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_switches.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_switches.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_switches " "Found entity 1: nios_system_switches" { } { { "db/ip/nios_system/submodules/nios_system_switches.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_switches.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851504 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851504 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "nios_system_nios2_processor.v(1567) " "Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1567): conditional expression evaluates to a constant" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1567 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "Quartus II" 0 -1 1482368851520 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "nios_system_nios2_processor.v(1569) " "Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1569): conditional expression evaluates to a constant" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1569 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "Quartus II" 0 -1 1482368851520 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "nios_system_nios2_processor.v(1725) " "Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1725): conditional expression evaluates to a constant" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1725 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "Quartus II" 0 -1 1482368851520 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "nios_system_nios2_processor.v(2553) " "Verilog HDL or VHDL warning at nios_system_nios2_processor.v(2553): conditional expression evaluates to a constant" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2553 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "Quartus II" 0 -1 1482368851520 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "lights " "Elaborating entity \"lights\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1482368851689 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system nios_system:NiosII " "Elaborating entity \"nios_system\" for hierarchy \"nios_system:NiosII\"" { } { { "lights.vhd" "NiosII" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 53 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368851689 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor nios_system:NiosII\|nios_system_nios2_processor:nios2_processor " "Elaborating entity \"nios_system_nios2_processor\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1103 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852468 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_test_bench nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench " "Elaborating entity \"nios_system_nios2_processor_test_bench\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_test_bench" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3794 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852638 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_register_bank_a_module nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a " "Elaborating entity \"nios_system_nios2_processor_register_bank_a_module\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_register_bank_a" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 4279 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852691 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_altsyncram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 55 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852785 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 55 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368852787 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nios_system_nios2_processor_rf_ram_a.mif " "Parameter \"init_file\" = \"nios_system_nios2_processor_rf_ram_a.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 55 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1482368852788 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_0rh1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_0rh1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_0rh1 " "Found entity 1: altsyncram_0rh1" { } { { "db/altsyncram_0rh1.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_0rh1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368852854 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368852854 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_0rh1 nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_0rh1:auto_generated " "Elaborating entity \"altsyncram_0rh1\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_0rh1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852854 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_register_bank_b_module nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b " "Elaborating entity \"nios_system_nios2_processor_register_bank_b_module\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_register_bank_b" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 4300 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852891 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_altsyncram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 118 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 118 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nios_system_nios2_processor_rf_ram_b.mif " "Parameter \"init_file\" = \"nios_system_nios2_processor_rf_ram_b.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 118 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1482368852923 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_1rh1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_1rh1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_1rh1 " "Found entity 1: altsyncram_1rh1" { } { { "db/altsyncram_1rh1.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_1rh1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368852992 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368852992 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_1rh1 nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_1rh1:auto_generated " "Elaborating entity \"altsyncram_1rh1\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_1rh1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852992 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci " "Elaborating entity \"nios_system_nios2_processor_nios2_oci\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 4758 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853023 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_debug nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_debug\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_debug" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2802 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853070 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborating entity \"altera_std_synchronizer\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_altera_std_synchronizer" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 213 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853092 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 213 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368853092 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "depth 2 " "Parameter \"depth\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853092 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 213 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1482368853092 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_ocimem nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem " "Elaborating entity \"nios_system_nios2_processor_nios2_ocimem\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_ocimem" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2821 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853107 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_ociram_sp_ram_module nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram " "Elaborating entity \"nios_system_nios2_processor_ociram_sp_ram_module\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_ociram_sp_ram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 491 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853170 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_altsyncram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 322 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853192 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 322 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368853192 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nios_system_nios2_processor_ociram_default_contents.mif " "Parameter \"init_file\" = \"nios_system_nios2_processor_ociram_default_contents.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853192 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853192 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853192 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853192 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853192 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853192 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853192 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853192 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853192 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 322 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1482368853192 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4891.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_4891.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4891 " "Found entity 1: altsyncram_4891" { } { { "db/altsyncram_4891.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4891.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368853255 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368853255 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_4891 nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\|altsyncram_4891:auto_generated " "Elaborating entity \"altsyncram_4891\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\|altsyncram_4891:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853255 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_avalon_reg nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg " "Elaborating entity \"nios_system_nios2_processor_nios2_avalon_reg\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_avalon_reg" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2840 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853292 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_break nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_break\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_break" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2871 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853308 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_xbrk nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_xbrk\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_xbrk" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2892 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853339 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_dbrk nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_dbrk\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_dbrk" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2918 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853355 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_itrace nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_itrace:the_nios_system_nios2_processor_nios2_oci_itrace " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_itrace\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_itrace:the_nios_system_nios2_processor_nios2_oci_itrace\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_itrace" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2937 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853370 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_dtrace nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_dtrace\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_dtrace" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2952 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853393 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_td_mode nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace\|nios_system_nios2_processor_nios2_oci_td_mode:nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_td_mode\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace\|nios_system_nios2_processor_nios2_oci_td_mode:nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1714 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853424 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_fifo nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_fifo\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_fifo" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2971 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853439 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_compute_tm_count nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_compute_tm_count:nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_compute_tm_count\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_compute_tm_count:nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2046 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853488 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_fifowp_inc nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_fifowp_inc:nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_fifowp_inc\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_fifowp_inc:nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2056 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853493 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_fifocount_inc nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_fifocount_inc:nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_fifocount_inc\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_fifocount_inc:nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2066 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853540 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_oci_test_bench nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_oci_test_bench:the_nios_system_nios2_processor_oci_test_bench " "Elaborating entity \"nios_system_nios2_processor_oci_test_bench\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_oci_test_bench:the_nios_system_nios2_processor_oci_test_bench\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_oci_test_bench" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2075 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853571 ""} -{ "Warning" "WSGN_EMPTY_SHELL" "nios_system_nios2_processor_oci_test_bench " "Entity \"nios_system_nios2_processor_oci_test_bench\" contains only dangling pins" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_oci_test_bench" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2075 0 0 } } } 0 12158 "Entity \"%1!s!\" contains only dangling pins" 0 0 "Quartus II" 0 -1 1482368853571 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_pib nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_pib:the_nios_system_nios2_processor_nios2_oci_pib " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_pib\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_pib:the_nios_system_nios2_processor_nios2_oci_pib\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_pib" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2981 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853588 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_im nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_im:the_nios_system_nios2_processor_nios2_oci_im " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_im\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_im:the_nios_system_nios2_processor_nios2_oci_im\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_im" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3002 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853593 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_jtag_debug_module_wrapper nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper " "Elaborating entity \"nios_system_nios2_processor_jtag_debug_module_wrapper\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_jtag_debug_module_wrapper" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3107 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853609 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_jtag_debug_module_tck nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck " "Elaborating entity \"nios_system_nios2_processor_jtag_debug_module_tck\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "the_nios_system_nios2_processor_jtag_debug_module_tck" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 165 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853640 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_jtag_debug_module_sysclk nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk " "Elaborating entity \"nios_system_nios2_processor_jtag_debug_module_sysclk\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "the_nios_system_nios2_processor_jtag_debug_module_sysclk" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 188 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853671 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_basic nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy " "Elaborating entity \"sld_virtual_jtag_basic\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "nios_system_nios2_processor_jtag_debug_module_phy" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_auto_instance_index YES " "Parameter \"sld_auto_instance_index\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_instance_index 0 " "Parameter \"sld_instance_index\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_ir_width 2 " "Parameter \"sld_ir_width\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_mfg_id 70 " "Parameter \"sld_mfg_id\" = \"70\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_action " "Parameter \"sld_sim_action\" = \"\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_n_scan 0 " "Parameter \"sld_sim_n_scan\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_total_length 0 " "Parameter \"sld_sim_total_length\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_type_id 34 " "Parameter \"sld_type_id\" = \"34\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_version 3 " "Parameter \"sld_version\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1482368853709 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_impl nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst " "Elaborating entity \"sld_virtual_jtag_impl\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\"" { } { { "sld_virtual_jtag_basic.v" "sld_virtual_jtag_impl_inst" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\", which is child of megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\"" { } { { "sld_virtual_jtag_basic.v" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_onchip_memory nios_system:NiosII\|nios_system_onchip_memory:onchip_memory " "Elaborating entity \"nios_system_onchip_memory\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\"" { } { { "nios_system/synthesis/nios_system.v" "onchip_memory" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_onchip_memory.v" "the_altsyncram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v" 66 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853724 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_onchip_memory.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v" 66 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram " "Instantiated megafunction \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "byte_size 8 " "Parameter \"byte_size\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nios_system_onchip_memory.hex " "Parameter \"init_file\" = \"nios_system_onchip_memory.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 51200 " "Parameter \"maximum_depth\" = \"51200\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 51200 " "Parameter \"numwords_a\" = \"51200\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 16 " "Parameter \"widthad_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} } { { "db/ip/nios_system/submodules/nios_system_onchip_memory.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v" 66 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1482368853740 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4ed1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_4ed1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4ed1 " "Found entity 1: altsyncram_4ed1" { } { { "db/altsyncram_4ed1.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4ed1.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368853824 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368853824 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_4ed1 nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated " "Elaborating entity \"altsyncram_4ed1\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853840 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_qsa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_qsa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_qsa " "Found entity 1: decode_qsa" { } { { "db/decode_qsa.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/decode_qsa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368853893 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368853893 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_qsa nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\|decode_qsa:decode3 " "Elaborating entity \"decode_qsa\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\|decode_qsa:decode3\"" { } { { "db/altsyncram_4ed1.tdf" "decode3" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4ed1.tdf" 43 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853893 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_nob.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_nob.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_nob " "Found entity 1: mux_nob" { } { { "db/mux_nob.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/mux_nob.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368853971 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368853971 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_nob nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\|mux_nob:mux2 " "Elaborating entity \"mux_nob\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\|mux_nob:mux2\"" { } { { "db/altsyncram_4ed1.tdf" "mux2" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4ed1.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853971 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_jtag_uart nios_system:NiosII\|nios_system_jtag_uart:jtag_uart " "Elaborating entity \"nios_system_jtag_uart\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\"" { } { { "nios_system/synthesis/nios_system.v" "jtag_uart" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1129 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854272 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_jtag_uart_scfifo_w nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w " "Elaborating entity \"nios_system_jtag_uart_scfifo_w\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "the_nios_system_jtag_uart_scfifo_w" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 415 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854294 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo " "Elaborating entity \"scfifo\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "wfifo" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 137 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854372 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 137 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368854372 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo " "Instantiated megafunction \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint RAM_BLOCK_TYPE=AUTO " "Parameter \"lpm_hint\" = \"RAM_BLOCK_TYPE=AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 64 " "Parameter \"lpm_numwords\" = \"64\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Parameter \"lpm_width\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 6 " "Parameter \"lpm_widthu\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Parameter \"overflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Parameter \"underflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854372 ""} } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 137 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1482368854372 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_jr21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_jr21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_jr21 " "Found entity 1: scfifo_jr21" { } { { "db/scfifo_jr21.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/scfifo_jr21.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368854441 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368854441 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_jr21 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated " "Elaborating entity \"scfifo_jr21\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854441 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_q131.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_q131.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_q131 " "Found entity 1: a_dpfifo_q131" { } { { "db/a_dpfifo_q131.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368854457 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368854457 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_q131 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo " "Elaborating entity \"a_dpfifo_q131\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\"" { } { { "db/scfifo_jr21.tdf" "dpfifo" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/scfifo_jr21.tdf" 37 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854457 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_7cf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_7cf " "Found entity 1: a_fefifo_7cf" { } { { "db/a_fefifo_7cf.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_fefifo_7cf.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368854473 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368854473 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_fefifo_7cf nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state " "Elaborating entity \"a_fefifo_7cf\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\"" { } { { "db/a_dpfifo_q131.tdf" "fifo_state" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf" 42 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854489 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_do7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_do7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_do7 " "Found entity 1: cntr_do7" { } { { "db/cntr_do7.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/cntr_do7.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368854573 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368854573 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_do7 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw " "Elaborating entity \"cntr_do7\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw\"" { } { { "db/a_fefifo_7cf.tdf" "count_usedw" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_fefifo_7cf.tdf" 38 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854573 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_nl21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dpram_nl21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_nl21 " "Found entity 1: dpram_nl21" { } { { "db/dpram_nl21.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/dpram_nl21.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368854673 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368854673 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpram_nl21 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram " "Elaborating entity \"dpram_nl21\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\"" { } { { "db/a_dpfifo_q131.tdf" "FIFOram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf" 43 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854673 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_r1m1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_r1m1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_r1m1 " "Found entity 1: altsyncram_r1m1" { } { { "db/altsyncram_r1m1.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_r1m1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368854825 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368854825 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_r1m1 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1 " "Elaborating entity \"altsyncram_r1m1\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1\"" { } { { "db/dpram_nl21.tdf" "altsyncram1" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/dpram_nl21.tdf" 36 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854826 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_1ob.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_1ob.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_1ob " "Found entity 1: cntr_1ob" { } { { "db/cntr_1ob.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/cntr_1ob.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368854889 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368854889 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_1ob nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count " "Elaborating entity \"cntr_1ob\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count\"" { } { { "db/a_dpfifo_q131.tdf" "rd_ptr_count" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854889 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_jtag_uart_scfifo_r nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r " "Elaborating entity \"nios_system_jtag_uart_scfifo_r\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "the_nios_system_jtag_uart_scfifo_r" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 429 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854904 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_jtag_atlantic nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic " "Elaborating entity \"alt_jtag_atlantic\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "nios_system_jtag_uart_alt_jtag_atlantic" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 564 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855073 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 564 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368855089 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic " "Instantiated megafunction \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "INSTANCE_ID 0 " "Parameter \"INSTANCE_ID\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855089 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_RXFIFO_DEPTH 6 " "Parameter \"LOG2_RXFIFO_DEPTH\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855089 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_TXFIFO_DEPTH 6 " "Parameter \"LOG2_TXFIFO_DEPTH\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855089 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_AUTO_INSTANCE_INDEX YES " "Parameter \"SLD_AUTO_INSTANCE_INDEX\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855089 ""} } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 564 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1482368855089 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_LEDs nios_system:NiosII\|nios_system_LEDs:leds " "Elaborating entity \"nios_system_LEDs\" for hierarchy \"nios_system:NiosII\|nios_system_LEDs:leds\"" { } { { "nios_system/synthesis/nios_system.v" "leds" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1140 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855089 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_LEDRs nios_system:NiosII\|nios_system_LEDRs:ledrs " "Elaborating entity \"nios_system_LEDRs\" for hierarchy \"nios_system:NiosII\|nios_system_LEDRs:ledrs\"" { } { { "nios_system/synthesis/nios_system.v" "ledrs" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1151 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855104 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_switches nios_system:NiosII\|nios_system_switches:switches " "Elaborating entity \"nios_system_switches\" for hierarchy \"nios_system:NiosII\|nios_system_switches:switches\"" { } { { "nios_system/synthesis/nios_system.v" "switches" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1159 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855126 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_push_switches nios_system:NiosII\|nios_system_push_switches:push_switches " "Elaborating entity \"nios_system_push_switches\" for hierarchy \"nios_system:NiosII\|nios_system_push_switches:push_switches\"" { } { { "nios_system/synthesis/nios_system.v" "push_switches" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1167 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855142 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_hex0 nios_system:NiosII\|nios_system_hex0:hex0 " "Elaborating entity \"nios_system_hex0\" for hierarchy \"nios_system:NiosII\|nios_system_hex0:hex0\"" { } { { "nios_system/synthesis/nios_system.v" "hex0" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1178 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855158 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_lcd_16207_0 nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0 " "Elaborating entity \"nios_system_lcd_16207_0\" for hierarchy \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\"" { } { { "nios_system/synthesis/nios_system.v" "lcd_16207_0" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1270 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855189 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_lcd_on nios_system:NiosII\|nios_system_lcd_on:lcd_on " "Elaborating entity \"nios_system_lcd_on\" for hierarchy \"nios_system:NiosII\|nios_system_lcd_on:lcd_on\"" { } { { "nios_system/synthesis/nios_system.v" "lcd_on" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1281 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855204 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator nios_system:NiosII\|altera_merlin_master_translator:nios2_processor_instruction_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_master_translator:nios2_processor_instruction_master_translator\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_instruction_master_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1354 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855227 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator nios_system:NiosII\|altera_merlin_master_translator:nios2_processor_data_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_master_translator:nios2_processor_data_master_translator\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_data_master_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1416 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855324 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_jtag_debug_module_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1482 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855342 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:onchip_memory_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:onchip_memory_s1_translator\"" { } { { "nios_system/synthesis/nios_system.v" "onchip_memory_s1_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1548 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855374 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:leds_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:leds_s1_translator\"" { } { { "nios_system/synthesis/nios_system.v" "leds_s1_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1614 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855405 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator\"" { } { { "nios_system/synthesis/nios_system.v" "jtag_uart_avalon_jtag_slave_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1680 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855443 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\"" { } { { "nios_system/synthesis/nios_system.v" "lcd_16207_0_control_slave_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2472 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855505 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent nios_system:NiosII\|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"nios_system:NiosII\|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2684 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855559 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent nios_system:NiosII\|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"nios_system:NiosII\|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_data_master_translator_avalon_universal_master_0_agent" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2764 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855590 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent nios_system:NiosII\|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2845 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855627 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor nios_system:NiosII\|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor\"" { } { { "db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" "uncompressor" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" 574 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855659 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo nios_system:NiosII\|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"nios_system:NiosII\|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2886 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855690 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_addr_router nios_system:NiosII\|nios_system_addr_router:addr_router " "Elaborating entity \"nios_system_addr_router\" for hierarchy \"nios_system:NiosII\|nios_system_addr_router:addr_router\"" { } { { "nios_system/synthesis/nios_system.v" "addr_router" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 4976 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855928 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_addr_router_default_decode nios_system:NiosII\|nios_system_addr_router:addr_router\|nios_system_addr_router_default_decode:the_default_decode " "Elaborating entity \"nios_system_addr_router_default_decode\" for hierarchy \"nios_system:NiosII\|nios_system_addr_router:addr_router\|nios_system_addr_router_default_decode:the_default_decode\"" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "the_default_decode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 177 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855960 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_addr_router_001 nios_system:NiosII\|nios_system_addr_router_001:addr_router_001 " "Elaborating entity \"nios_system_addr_router_001\" for hierarchy \"nios_system:NiosII\|nios_system_addr_router_001:addr_router_001\"" { } { { "nios_system/synthesis/nios_system.v" "addr_router_001" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 4992 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855975 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_addr_router_001_default_decode nios_system:NiosII\|nios_system_addr_router_001:addr_router_001\|nios_system_addr_router_001_default_decode:the_default_decode " "Elaborating entity \"nios_system_addr_router_001_default_decode\" for hierarchy \"nios_system:NiosII\|nios_system_addr_router_001:addr_router_001\|nios_system_addr_router_001_default_decode:the_default_decode\"" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "the_default_decode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 193 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856029 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_id_router nios_system:NiosII\|nios_system_id_router:id_router " "Elaborating entity \"nios_system_id_router\" for hierarchy \"nios_system:NiosII\|nios_system_id_router:id_router\"" { } { { "nios_system/synthesis/nios_system.v" "id_router" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5008 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856044 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_id_router_default_decode nios_system:NiosII\|nios_system_id_router:id_router\|nios_system_id_router_default_decode:the_default_decode " "Elaborating entity \"nios_system_id_router_default_decode\" for hierarchy \"nios_system:NiosII\|nios_system_id_router:id_router\|nios_system_id_router_default_decode:the_default_decode\"" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "the_default_decode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 175 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856076 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_id_router_002 nios_system:NiosII\|nios_system_id_router_002:id_router_002 " "Elaborating entity \"nios_system_id_router_002\" for hierarchy \"nios_system:NiosII\|nios_system_id_router_002:id_router_002\"" { } { { "nios_system/synthesis/nios_system.v" "id_router_002" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5040 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856091 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_id_router_002_default_decode nios_system:NiosII\|nios_system_id_router_002:id_router_002\|nios_system_id_router_002_default_decode:the_default_decode " "Elaborating entity \"nios_system_id_router_002_default_decode\" for hierarchy \"nios_system:NiosII\|nios_system_id_router_002:id_router_002\|nios_system_id_router_002_default_decode:the_default_decode\"" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "the_default_decode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 175 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856107 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_controller nios_system:NiosII\|altera_reset_controller:rst_controller " "Elaborating entity \"altera_reset_controller\" for hierarchy \"nios_system:NiosII\|altera_reset_controller:rst_controller\"" { } { { "nios_system/synthesis/nios_system.v" "rst_controller" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5307 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856608 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer nios_system:NiosII\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"nios_system:NiosII\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\"" { } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "alt_rst_sync_uq1" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 120 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856629 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_cmd_xbar_demux nios_system:NiosII\|nios_system_cmd_xbar_demux:cmd_xbar_demux " "Elaborating entity \"nios_system_cmd_xbar_demux\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_demux:cmd_xbar_demux\"" { } { { "nios_system/synthesis/nios_system.v" "cmd_xbar_demux" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5330 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856630 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_cmd_xbar_demux_001 nios_system:NiosII\|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001 " "Elaborating entity \"nios_system_cmd_xbar_demux_001\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001\"" { } { { "nios_system/synthesis/nios_system.v" "cmd_xbar_demux_001" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5449 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856661 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_cmd_xbar_mux nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux " "Elaborating entity \"nios_system_cmd_xbar_mux\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\"" { } { { "nios_system/synthesis/nios_system.v" "cmd_xbar_mux" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5472 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856730 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\"" { } { { "db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" "arb" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" 273 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856777 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856793 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_rsp_xbar_demux_002 nios_system:NiosII\|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_002 " "Elaborating entity \"nios_system_rsp_xbar_demux_002\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_002\"" { } { { "nios_system/synthesis/nios_system.v" "rsp_xbar_demux_002" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5558 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856830 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_rsp_xbar_mux nios_system:NiosII\|nios_system_rsp_xbar_mux:rsp_xbar_mux " "Elaborating entity \"nios_system_rsp_xbar_mux\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux:rsp_xbar_mux\"" { } { { "nios_system/synthesis/nios_system.v" "rsp_xbar_mux" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5836 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856893 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator nios_system:NiosII\|nios_system_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb\"" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" "arb" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" 296 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856930 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_rsp_xbar_mux_001 nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001 " "Elaborating entity \"nios_system_rsp_xbar_mux_001\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\"" { } { { "nios_system/synthesis/nios_system.v" "rsp_xbar_mux_001" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5955 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856962 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\"" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" "arb" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" 552 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368857128 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368857147 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_irq_mapper nios_system:NiosII\|nios_system_irq_mapper:irq_mapper " "Elaborating entity \"nios_system_irq_mapper\" for hierarchy \"nios_system:NiosII\|nios_system_irq_mapper:irq_mapper\"" { } { { "nios_system/synthesis/nios_system.v" "irq_mapper" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5962 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368857162 ""} -{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "5 " "5 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1482368866226 ""} -{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[0\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[0\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[0\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[0\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1482368866410 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[1\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[1\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[1\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[1\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1482368866410 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[2\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[2\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[2\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[2\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1482368866410 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[3\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[3\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[3\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[3\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1482368866410 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[4\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[4\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[4\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[4\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1482368866410 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[5\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[5\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[5\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[5\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1482368866410 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[6\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[6\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[6\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[6\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1482368866410 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[7\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[7\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[7\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[7\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1482368866410 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1482368866410 ""} -{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "db/ip/nios_system/submodules/altera_merlin_master_agent.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_agent.sv" 276 -1 0 } } { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 348 -1 0 } } { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3167 -1 0 } } { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 203 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 291 -1 0 } } { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3740 -1 0 } } { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 393 -1 0 } } { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 599 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 224 -1 0 } } { "db/ip/nios_system/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_synchronizer.v" 62 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1482368866448 ""} -{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1482368866448 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368868229 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "166 " "166 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1482368870827 ""} -{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 384 -1 0 } } { "sld_jtag_hub.vhd" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 521 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1482368870965 ""} -{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1482368870965 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "sld_hub:auto_hub\|receive\[0\]\[0\] GND " "Pin \"sld_hub:auto_hub\|receive\[0\]\[0\]\" is stuck at GND" { } { { "sld_hub.vhd" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_hub.vhd" 181 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1482368871065 "|lights|sld_hub:auto_hub|receive[0][0]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1482368871065 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "sld_hub:auto_hub " "Timing-Driven Synthesis is running on partition \"sld_hub:auto_hub\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368871212 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.map.smsg " "Generated suppressed messages file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1482368871813 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1482368872784 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368872784 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "2878 " "Implemented 2878 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "26 " "Implemented 26 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1482368873216 ""} { "Info" "ICUT_CUT_TM_OPINS" "96 " "Implemented 96 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1482368873216 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2419 " "Implemented 2419 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1482368873216 ""} { "Info" "ICUT_CUT_TM_RAMS" "336 " "Implemented 336 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1482368873216 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1482368873216 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 150 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 150 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "657 " "Peak virtual memory: 657 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1482368873385 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 22 10:07:53 2016 " "Processing ended: Thu Dec 22 10:07:53 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1482368873385 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:40 " "Elapsed time: 00:00:40" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1482368873385 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:36 " "Total CPU time (on all processors): 00:00:36" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1482368873385 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1482368873385 ""} diff --git a/db/lights.map.rdb b/db/lights.map.rdb deleted file mode 100644 index f9de163..0000000 --- a/db/lights.map.rdb +++ /dev/null Binary files differ diff --git a/db/lights.map_bb.cdb b/db/lights.map_bb.cdb deleted file mode 100644 index 1e47766..0000000 --- a/db/lights.map_bb.cdb +++ /dev/null Binary files differ diff --git a/db/lights.map_bb.hdb b/db/lights.map_bb.hdb deleted file mode 100644 index f876e14..0000000 --- a/db/lights.map_bb.hdb +++ /dev/null Binary files differ diff --git a/db/lights.map_bb.logdb b/db/lights.map_bb.logdb deleted file mode 100644 index d45424f..0000000 --- a/db/lights.map_bb.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/db/lights.pre_map.hdb b/db/lights.pre_map.hdb deleted file mode 100644 index d1c0f30..0000000 --- a/db/lights.pre_map.hdb +++ /dev/null Binary files differ diff --git a/db/lights.pti_db_list.ddb b/db/lights.pti_db_list.ddb deleted file mode 100644 index 89aa9b4..0000000 --- a/db/lights.pti_db_list.ddb +++ /dev/null Binary files differ diff --git a/db/lights.root_partition.map.reg_db.cdb b/db/lights.root_partition.map.reg_db.cdb deleted file mode 100644 index 6482524..0000000 --- a/db/lights.root_partition.map.reg_db.cdb +++ /dev/null Binary files differ diff --git a/db/lights.routing.rdb b/db/lights.routing.rdb deleted file mode 100644 index de01a9e..0000000 --- a/db/lights.routing.rdb +++ /dev/null Binary files differ diff --git a/db/lights.rtlv.hdb b/db/lights.rtlv.hdb deleted file mode 100644 index e72b35f..0000000 --- a/db/lights.rtlv.hdb +++ /dev/null Binary files differ diff --git a/db/lights.rtlv_sg.cdb b/db/lights.rtlv_sg.cdb deleted file mode 100644 index dd838f2..0000000 --- a/db/lights.rtlv_sg.cdb +++ /dev/null Binary files differ diff --git a/db/lights.rtlv_sg_swap.cdb b/db/lights.rtlv_sg_swap.cdb deleted file mode 100644 index 203d12c..0000000 --- a/db/lights.rtlv_sg_swap.cdb +++ /dev/null Binary files differ diff --git a/db/lights.sgdiff.cdb b/db/lights.sgdiff.cdb deleted file mode 100644 index 3e4e6ed..0000000 --- a/db/lights.sgdiff.cdb +++ /dev/null Binary files differ diff --git a/db/lights.sgdiff.hdb b/db/lights.sgdiff.hdb deleted file mode 100644 index 9620e6c..0000000 --- a/db/lights.sgdiff.hdb +++ /dev/null Binary files differ diff --git a/db/lights.sld_design_entry.sci b/db/lights.sld_design_entry.sci deleted file mode 100644 index 1d6d60f..0000000 --- a/db/lights.sld_design_entry.sci +++ /dev/null Binary files differ diff --git a/db/lights.sld_design_entry_dsc.sci b/db/lights.sld_design_entry_dsc.sci deleted file mode 100644 index 74164de..0000000 --- a/db/lights.sld_design_entry_dsc.sci +++ /dev/null Binary files differ diff --git a/db/lights.smart_action.txt b/db/lights.smart_action.txt deleted file mode 100644 index 437a63e..0000000 --- a/db/lights.smart_action.txt +++ /dev/null @@ -1 +0,0 @@ -DONE diff --git a/db/lights.smp_dump.txt b/db/lights.smp_dump.txt deleted file mode 100644 index bed5286..0000000 --- a/db/lights.smp_dump.txt +++ /dev/null @@ -1,9 +0,0 @@ - -State Machine - |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize -Name DRsize.101 DRsize.100 DRsize.011 DRsize.010 DRsize.001 DRsize.000 -DRsize.000 0 0 0 0 0 0 -DRsize.001 0 0 0 0 1 1 -DRsize.010 0 0 0 1 0 1 -DRsize.011 0 0 1 0 0 1 -DRsize.100 0 1 0 0 0 1 -DRsize.101 1 0 0 0 0 1 diff --git a/db/lights.sta.qmsg b/db/lights.sta.qmsg deleted file mode 100644 index a097636..0000000 --- a/db/lights.sta.qmsg +++ /dev/null @@ -1,43 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1482368922934 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1482368922934 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 22 10:08:42 2016 " "Processing started: Thu Dec 22 10:08:42 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1482368922934 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1482368922934 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta lights -c lights " "Command: quartus_sta lights -c lights" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1482368922934 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1482368923013 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1482368923350 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1482368923350 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1482368923435 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1482368923435 ""} -{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\] " "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Quartus II" 0 -1 1482368924166 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "lights.sdc " "Synopsys Design Constraints File file not found: 'lights.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1482368924198 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1482368924213 "|lights|CLOCK_50"} -{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1482368924736 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1482368924736 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1482368924736 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1482368924736 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1482368924736 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1482368924783 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup 46.656 " "Worst-case setup slack is 46.656" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924814 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924814 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 46.656 0.000 altera_reserved_tck " " 46.656 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924814 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368924814 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.401 " "Worst-case hold slack is 0.401" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924834 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924834 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.401 0.000 altera_reserved_tck " " 0.401 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924834 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368924834 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 47.591 " "Worst-case recovery slack is 47.591" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 47.591 0.000 altera_reserved_tck " " 47.591 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924836 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368924836 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.180 " "Worst-case removal slack is 1.180" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.180 0.000 altera_reserved_tck " " 1.180 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924836 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368924836 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.555 " "Worst-case minimum pulse width slack is 49.555" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924852 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924852 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.555 0.000 altera_reserved_tck " " 49.555 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924852 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368924852 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924967 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924967 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924967 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924967 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 197.069 ns " "Worst Case Available Settling Time: 197.069 ns" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924967 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924967 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924967 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924967 ""} } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924967 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1482368924983 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1482368925014 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1482368926251 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1482368926652 "|lights|CLOCK_50"} -{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1482368926667 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1482368926667 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1482368926667 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1482368926667 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup 47.042 " "Worst-case setup slack is 47.042" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926699 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926699 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 47.042 0.000 altera_reserved_tck " " 47.042 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926699 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368926699 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.353 " "Worst-case hold slack is 0.353" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926714 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926714 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.353 0.000 altera_reserved_tck " " 0.353 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926714 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368926714 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 47.930 " "Worst-case recovery slack is 47.930" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926730 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926730 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 47.930 0.000 altera_reserved_tck " " 47.930 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926730 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368926730 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.082 " "Worst-case removal slack is 1.082" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.082 0.000 altera_reserved_tck " " 1.082 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926736 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368926736 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.489 " "Worst-case minimum pulse width slack is 49.489" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.489 0.000 altera_reserved_tck " " 49.489 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926736 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368926736 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926952 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926952 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926952 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926952 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 197.362 ns " "Worst Case Available Settling Time: 197.362 ns" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926952 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926952 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926952 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926952 ""} } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926952 ""} -{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1482368926967 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1482368927452 "|lights|CLOCK_50"} -{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1482368927467 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1482368927467 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1482368927467 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1482368927467 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup 48.710 " "Worst-case setup slack is 48.710" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927483 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927483 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 48.710 0.000 altera_reserved_tck " " 48.710 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927483 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368927483 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.178 " "Worst-case hold slack is 0.178" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927483 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927483 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.178 0.000 altera_reserved_tck " " 0.178 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927483 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368927483 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 49.091 " "Worst-case recovery slack is 49.091" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927499 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927499 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.091 0.000 altera_reserved_tck " " 49.091 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927499 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368927499 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.560 " "Worst-case removal slack is 0.560" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927514 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927514 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.560 0.000 altera_reserved_tck " " 0.560 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927514 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368927514 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.301 " "Worst-case minimum pulse width slack is 49.301" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927531 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927531 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.301 0.000 altera_reserved_tck " " 49.301 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927531 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368927531 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927668 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927668 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927668 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927668 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 198.608 ns " "Worst Case Available Settling Time: 198.608 ns" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927668 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927668 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927668 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927668 ""} } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927668 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1482368928485 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1482368928485 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 17 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "605 " "Peak virtual memory: 605 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1482368928785 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 22 10:08:48 2016 " "Processing ended: Thu Dec 22 10:08:48 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1482368928785 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1482368928785 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1482368928785 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1482368928785 ""} diff --git a/db/lights.sta.rdb b/db/lights.sta.rdb deleted file mode 100644 index 465b5e9..0000000 --- a/db/lights.sta.rdb +++ /dev/null Binary files differ diff --git a/db/lights.sta_cmp.7_slow_1200mv_85c.tdb b/db/lights.sta_cmp.7_slow_1200mv_85c.tdb deleted file mode 100644 index b34b9e3..0000000 --- a/db/lights.sta_cmp.7_slow_1200mv_85c.tdb +++ /dev/null Binary files differ diff --git a/db/lights.syn_hier_info b/db/lights.syn_hier_info deleted file mode 100644 index e69de29..0000000 --- a/db/lights.syn_hier_info +++ /dev/null diff --git a/db/lights.tis_db_list.ddb b/db/lights.tis_db_list.ddb deleted file mode 100644 index f36f273..0000000 --- a/db/lights.tis_db_list.ddb +++ /dev/null Binary files differ diff --git a/db/lights.tiscmp.fast_1200mv_0c.ddb b/db/lights.tiscmp.fast_1200mv_0c.ddb deleted file mode 100644 index c611c18..0000000 --- a/db/lights.tiscmp.fast_1200mv_0c.ddb +++ /dev/null Binary files differ diff --git a/db/lights.tiscmp.slow_1200mv_0c.ddb b/db/lights.tiscmp.slow_1200mv_0c.ddb deleted file mode 100644 index 985b273..0000000 --- a/db/lights.tiscmp.slow_1200mv_0c.ddb +++ /dev/null Binary files differ diff --git a/db/lights.tiscmp.slow_1200mv_85c.ddb b/db/lights.tiscmp.slow_1200mv_85c.ddb deleted file mode 100644 index 091992f..0000000 --- a/db/lights.tiscmp.slow_1200mv_85c.ddb +++ /dev/null Binary files differ diff --git a/db/lights.tmw_info b/db/lights.tmw_info deleted file mode 100644 index 00bcc65..0000000 --- a/db/lights.tmw_info +++ /dev/null @@ -1,6 +0,0 @@ -start_full_compilation:s:00:01:36 -start_analysis_synthesis:s:00:00:41-start_full_compilation -start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:40-start_full_compilation -start_assembler:s:00:00:08-start_full_compilation -start_timing_analyzer:s:00:00:07-start_full_compilation diff --git a/db/lights.vpr.ammdb b/db/lights.vpr.ammdb deleted file mode 100644 index c5824e4..0000000 --- a/db/lights.vpr.ammdb +++ /dev/null Binary files differ diff --git a/db/logic_util_heursitic.dat b/db/logic_util_heursitic.dat deleted file mode 100644 index 43cd21a..0000000 --- a/db/logic_util_heursitic.dat +++ /dev/null Binary files differ diff --git a/db/mux_nob.tdf b/db/mux_nob.tdf deleted file mode 100644 index f31664f..0000000 --- a/db/mux_nob.tdf +++ /dev/null @@ -1,295 +0,0 @@ ---lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_SIZE=7 LPM_WIDTH=32 LPM_WIDTHS=3 data result sel ---VERSION_BEGIN 13.0 cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - - ---synthesis_resources = lut 160 -SUBDESIGN mux_nob -( - data[223..0] : input; - result[31..0] : output; - sel[2..0] : input; -) -VARIABLE - result_node[31..0] : WIRE; - sel_ffs_wire[2..0] : WIRE; - sel_node[2..0] : WIRE; - w_data1945w[7..0] : WIRE; - w_data1967w[3..0] : WIRE; - w_data1968w[3..0] : WIRE; - w_data2016w[7..0] : WIRE; - w_data2038w[3..0] : WIRE; - w_data2039w[3..0] : WIRE; - w_data2085w[7..0] : WIRE; - w_data2107w[3..0] : WIRE; - w_data2108w[3..0] : WIRE; - w_data2154w[7..0] : WIRE; - w_data2176w[3..0] : WIRE; - w_data2177w[3..0] : WIRE; - w_data2223w[7..0] : WIRE; - w_data2245w[3..0] : WIRE; - w_data2246w[3..0] : WIRE; - w_data2292w[7..0] : WIRE; - w_data2314w[3..0] : WIRE; - w_data2315w[3..0] : WIRE; - w_data2361w[7..0] : WIRE; - w_data2383w[3..0] : WIRE; - w_data2384w[3..0] : WIRE; - w_data2430w[7..0] : WIRE; - w_data2452w[3..0] : WIRE; - w_data2453w[3..0] : WIRE; - w_data2499w[7..0] : WIRE; - w_data2521w[3..0] : WIRE; - w_data2522w[3..0] : WIRE; - w_data2568w[7..0] : WIRE; - w_data2590w[3..0] : WIRE; - w_data2591w[3..0] : WIRE; - w_data2637w[7..0] : WIRE; - w_data2659w[3..0] : WIRE; - w_data2660w[3..0] : WIRE; - w_data2706w[7..0] : WIRE; - w_data2728w[3..0] : WIRE; - w_data2729w[3..0] : WIRE; - w_data2775w[7..0] : WIRE; - w_data2797w[3..0] : WIRE; - w_data2798w[3..0] : WIRE; - w_data2844w[7..0] : WIRE; - w_data2866w[3..0] : WIRE; - w_data2867w[3..0] : WIRE; - w_data2913w[7..0] : WIRE; - w_data2935w[3..0] : WIRE; - w_data2936w[3..0] : WIRE; - w_data2982w[7..0] : WIRE; - w_data3004w[3..0] : WIRE; - w_data3005w[3..0] : WIRE; - w_data3051w[7..0] : WIRE; - w_data3073w[3..0] : WIRE; - w_data3074w[3..0] : WIRE; - w_data3120w[7..0] : WIRE; - w_data3142w[3..0] : WIRE; - w_data3143w[3..0] : WIRE; - w_data3189w[7..0] : WIRE; - w_data3211w[3..0] : WIRE; - w_data3212w[3..0] : WIRE; - w_data3258w[7..0] : WIRE; - w_data3280w[3..0] : WIRE; - w_data3281w[3..0] : WIRE; - w_data3327w[7..0] : WIRE; - w_data3349w[3..0] : WIRE; - w_data3350w[3..0] : WIRE; - w_data3396w[7..0] : WIRE; - w_data3418w[3..0] : WIRE; - w_data3419w[3..0] : WIRE; - w_data3465w[7..0] : WIRE; - w_data3487w[3..0] : WIRE; - w_data3488w[3..0] : WIRE; - w_data3534w[7..0] : WIRE; - w_data3556w[3..0] : WIRE; - w_data3557w[3..0] : WIRE; - w_data3603w[7..0] : WIRE; - w_data3625w[3..0] : WIRE; - w_data3626w[3..0] : WIRE; - w_data3672w[7..0] : WIRE; - w_data3694w[3..0] : WIRE; - w_data3695w[3..0] : WIRE; - w_data3741w[7..0] : WIRE; - w_data3763w[3..0] : WIRE; - w_data3764w[3..0] : WIRE; - w_data3810w[7..0] : WIRE; - w_data3832w[3..0] : WIRE; - w_data3833w[3..0] : WIRE; - w_data3879w[7..0] : WIRE; - w_data3901w[3..0] : WIRE; - w_data3902w[3..0] : WIRE; - w_data3948w[7..0] : WIRE; - w_data3970w[3..0] : WIRE; - w_data3971w[3..0] : WIRE; - w_data4017w[7..0] : WIRE; - w_data4039w[3..0] : WIRE; - w_data4040w[3..0] : WIRE; - w_data4086w[7..0] : WIRE; - w_data4108w[3..0] : WIRE; - w_data4109w[3..0] : WIRE; - w_sel1969w[1..0] : WIRE; - w_sel2040w[1..0] : WIRE; - w_sel2109w[1..0] : WIRE; - w_sel2178w[1..0] : WIRE; - w_sel2247w[1..0] : WIRE; - w_sel2316w[1..0] : WIRE; - w_sel2385w[1..0] : WIRE; - w_sel2454w[1..0] : WIRE; - w_sel2523w[1..0] : WIRE; - w_sel2592w[1..0] : WIRE; - w_sel2661w[1..0] : WIRE; - w_sel2730w[1..0] : WIRE; - w_sel2799w[1..0] : WIRE; - w_sel2868w[1..0] : WIRE; - w_sel2937w[1..0] : WIRE; - w_sel3006w[1..0] : WIRE; - w_sel3075w[1..0] : WIRE; - w_sel3144w[1..0] : WIRE; - w_sel3213w[1..0] : WIRE; - w_sel3282w[1..0] : WIRE; - w_sel3351w[1..0] : WIRE; - w_sel3420w[1..0] : WIRE; - w_sel3489w[1..0] : WIRE; - w_sel3558w[1..0] : WIRE; - w_sel3627w[1..0] : WIRE; - w_sel3696w[1..0] : WIRE; - w_sel3765w[1..0] : WIRE; - w_sel3834w[1..0] : WIRE; - w_sel3903w[1..0] : WIRE; - w_sel3972w[1..0] : WIRE; - w_sel4041w[1..0] : WIRE; - w_sel4110w[1..0] : WIRE; - -BEGIN - result[] = result_node[]; - result_node[] = ( ((sel_node[2..2] & (((w_data4109w[1..1] & w_sel4110w[0..0]) & (! (((w_data4109w[0..0] & (! w_sel4110w[1..1])) & (! w_sel4110w[0..0])) # (w_sel4110w[1..1] & (w_sel4110w[0..0] # w_data4109w[2..2]))))) # ((((w_data4109w[0..0] & (! w_sel4110w[1..1])) & (! w_sel4110w[0..0])) # (w_sel4110w[1..1] & (w_sel4110w[0..0] # w_data4109w[2..2]))) & (w_data4109w[3..3] # (! w_sel4110w[0..0]))))) # ((! sel_node[2..2]) & (((w_data4108w[1..1] & w_sel4110w[0..0]) & (! (((w_data4108w[0..0] & (! w_sel4110w[1..1])) & (! w_sel4110w[0..0])) # (w_sel4110w[1..1] & (w_sel4110w[0..0] # w_data4108w[2..2]))))) # ((((w_data4108w[0..0] & (! w_sel4110w[1..1])) & (! w_sel4110w[0..0])) # (w_sel4110w[1..1] & (w_sel4110w[0..0] # w_data4108w[2..2]))) & (w_data4108w[3..3] # (! w_sel4110w[0..0])))))), ((sel_node[2..2] & (((w_data4040w[1..1] & w_sel4041w[0..0]) & (! (((w_data4040w[0..0] & (! w_sel4041w[1..1])) & (! w_sel4041w[0..0])) # (w_sel4041w[1..1] & (w_sel4041w[0..0] # w_data4040w[2..2]))))) # ((((w_data4040w[0..0] & (! w_sel4041w[1..1])) & (! w_sel4041w[0..0])) # (w_sel4041w[1..1] & (w_sel4041w[0..0] # w_data4040w[2..2]))) & (w_data4040w[3..3] # (! w_sel4041w[0..0]))))) # ((! sel_node[2..2]) & (((w_data4039w[1..1] & w_sel4041w[0..0]) & (! (((w_data4039w[0..0] & (! w_sel4041w[1..1])) & (! w_sel4041w[0..0])) # (w_sel4041w[1..1] & (w_sel4041w[0..0] # w_data4039w[2..2]))))) # ((((w_data4039w[0..0] & (! w_sel4041w[1..1])) & (! w_sel4041w[0..0])) # (w_sel4041w[1..1] & (w_sel4041w[0..0] # w_data4039w[2..2]))) & (w_data4039w[3..3] # (! w_sel4041w[0..0])))))), ((sel_node[2..2] & (((w_data3971w[1..1] & w_sel3972w[0..0]) & (! (((w_data3971w[0..0] & (! w_sel3972w[1..1])) & (! w_sel3972w[0..0])) # (w_sel3972w[1..1] & (w_sel3972w[0..0] # w_data3971w[2..2]))))) # ((((w_data3971w[0..0] & (! w_sel3972w[1..1])) & (! w_sel3972w[0..0])) # (w_sel3972w[1..1] & (w_sel3972w[0..0] # w_data3971w[2..2]))) & (w_data3971w[3..3] # (! w_sel3972w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3970w[1..1] & w_sel3972w[0..0]) & (! (((w_data3970w[0..0] & (! w_sel3972w[1..1])) & (! w_sel3972w[0..0])) # (w_sel3972w[1..1] & (w_sel3972w[0..0] # w_data3970w[2..2]))))) # ((((w_data3970w[0..0] & (! w_sel3972w[1..1])) & (! w_sel3972w[0..0])) # (w_sel3972w[1..1] & (w_sel3972w[0..0] # w_data3970w[2..2]))) & (w_data3970w[3..3] # (! w_sel3972w[0..0])))))), ((sel_node[2..2] & (((w_data3902w[1..1] & w_sel3903w[0..0]) & (! (((w_data3902w[0..0] & (! w_sel3903w[1..1])) & (! w_sel3903w[0..0])) # (w_sel3903w[1..1] & (w_sel3903w[0..0] # w_data3902w[2..2]))))) # ((((w_data3902w[0..0] & (! w_sel3903w[1..1])) & (! w_sel3903w[0..0])) # (w_sel3903w[1..1] & (w_sel3903w[0..0] # w_data3902w[2..2]))) & (w_data3902w[3..3] # (! w_sel3903w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3901w[1..1] & w_sel3903w[0..0]) & (! (((w_data3901w[0..0] & (! w_sel3903w[1..1])) & (! w_sel3903w[0..0])) # (w_sel3903w[1..1] & (w_sel3903w[0..0] # w_data3901w[2..2]))))) # ((((w_data3901w[0..0] & (! w_sel3903w[1..1])) & (! w_sel3903w[0..0])) # (w_sel3903w[1..1] & (w_sel3903w[0..0] # w_data3901w[2..2]))) & (w_data3901w[3..3] # (! w_sel3903w[0..0])))))), ((sel_node[2..2] & (((w_data3833w[1..1] & w_sel3834w[0..0]) & (! (((w_data3833w[0..0] & (! w_sel3834w[1..1])) & (! w_sel3834w[0..0])) # (w_sel3834w[1..1] & (w_sel3834w[0..0] # w_data3833w[2..2]))))) # ((((w_data3833w[0..0] & (! w_sel3834w[1..1])) & (! w_sel3834w[0..0])) # (w_sel3834w[1..1] & (w_sel3834w[0..0] # w_data3833w[2..2]))) & (w_data3833w[3..3] # (! w_sel3834w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3832w[1..1] & w_sel3834w[0..0]) & (! (((w_data3832w[0..0] & (! w_sel3834w[1..1])) & (! w_sel3834w[0..0])) # (w_sel3834w[1..1] & (w_sel3834w[0..0] # w_data3832w[2..2]))))) # ((((w_data3832w[0..0] & (! w_sel3834w[1..1])) & (! w_sel3834w[0..0])) # (w_sel3834w[1..1] & (w_sel3834w[0..0] # w_data3832w[2..2]))) & (w_data3832w[3..3] # (! w_sel3834w[0..0])))))), ((sel_node[2..2] & (((w_data3764w[1..1] & w_sel3765w[0..0]) & (! (((w_data3764w[0..0] & (! w_sel3765w[1..1])) & (! w_sel3765w[0..0])) # (w_sel3765w[1..1] & (w_sel3765w[0..0] # w_data3764w[2..2]))))) # ((((w_data3764w[0..0] & (! w_sel3765w[1..1])) & (! w_sel3765w[0..0])) # (w_sel3765w[1..1] & (w_sel3765w[0..0] # w_data3764w[2..2]))) & (w_data3764w[3..3] # (! w_sel3765w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3763w[1..1] & w_sel3765w[0..0]) & (! (((w_data3763w[0..0] & (! w_sel3765w[1..1])) & (! w_sel3765w[0..0])) # (w_sel3765w[1..1] & (w_sel3765w[0..0] # w_data3763w[2..2]))))) # ((((w_data3763w[0..0] & (! w_sel3765w[1..1])) & (! w_sel3765w[0..0])) # (w_sel3765w[1..1] & (w_sel3765w[0..0] # w_data3763w[2..2]))) & (w_data3763w[3..3] # (! w_sel3765w[0..0])))))), ((sel_node[2..2] & (((w_data3695w[1..1] & w_sel3696w[0..0]) & (! (((w_data3695w[0..0] & (! w_sel3696w[1..1])) & (! w_sel3696w[0..0])) # (w_sel3696w[1..1] & (w_sel3696w[0..0] # w_data3695w[2..2]))))) # ((((w_data3695w[0..0] & (! w_sel3696w[1..1])) & (! w_sel3696w[0..0])) # (w_sel3696w[1..1] & (w_sel3696w[0..0] # w_data3695w[2..2]))) & (w_data3695w[3..3] # (! w_sel3696w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3694w[1..1] & w_sel3696w[0..0]) & (! (((w_data3694w[0..0] & (! w_sel3696w[1..1])) & (! w_sel3696w[0..0])) # (w_sel3696w[1..1] & (w_sel3696w[0..0] # w_data3694w[2..2]))))) # ((((w_data3694w[0..0] & (! w_sel3696w[1..1])) & (! w_sel3696w[0..0])) # (w_sel3696w[1..1] & (w_sel3696w[0..0] # w_data3694w[2..2]))) & (w_data3694w[3..3] # (! w_sel3696w[0..0])))))), ((sel_node[2..2] & (((w_data3626w[1..1] & w_sel3627w[0..0]) & (! (((w_data3626w[0..0] & (! w_sel3627w[1..1])) & (! w_sel3627w[0..0])) # (w_sel3627w[1..1] & (w_sel3627w[0..0] # w_data3626w[2..2]))))) # ((((w_data3626w[0..0] & (! w_sel3627w[1..1])) & (! w_sel3627w[0..0])) # (w_sel3627w[1..1] & (w_sel3627w[0..0] # w_data3626w[2..2]))) & (w_data3626w[3..3] # (! w_sel3627w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3625w[1..1] & w_sel3627w[0..0]) & (! (((w_data3625w[0..0] & (! w_sel3627w[1..1])) & (! w_sel3627w[0..0])) # (w_sel3627w[1..1] & (w_sel3627w[0..0] # w_data3625w[2..2]))))) # ((((w_data3625w[0..0] & (! w_sel3627w[1..1])) & (! w_sel3627w[0..0])) # (w_sel3627w[1..1] & (w_sel3627w[0..0] # w_data3625w[2..2]))) & (w_data3625w[3..3] # (! w_sel3627w[0..0])))))), ((sel_node[2..2] & (((w_data3557w[1..1] & w_sel3558w[0..0]) & (! (((w_data3557w[0..0] & (! w_sel3558w[1..1])) & (! w_sel3558w[0..0])) # (w_sel3558w[1..1] & (w_sel3558w[0..0] # w_data3557w[2..2]))))) # ((((w_data3557w[0..0] & (! w_sel3558w[1..1])) & (! w_sel3558w[0..0])) # (w_sel3558w[1..1] & (w_sel3558w[0..0] # w_data3557w[2..2]))) & (w_data3557w[3..3] # (! w_sel3558w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3556w[1..1] & w_sel3558w[0..0]) & (! (((w_data3556w[0..0] & (! w_sel3558w[1..1])) & (! w_sel3558w[0..0])) # (w_sel3558w[1..1] & (w_sel3558w[0..0] # w_data3556w[2..2]))))) # ((((w_data3556w[0..0] & (! w_sel3558w[1..1])) & (! w_sel3558w[0..0])) # (w_sel3558w[1..1] & (w_sel3558w[0..0] # w_data3556w[2..2]))) & (w_data3556w[3..3] # (! w_sel3558w[0..0])))))), ((sel_node[2..2] & (((w_data3488w[1..1] & w_sel3489w[0..0]) & (! (((w_data3488w[0..0] & (! w_sel3489w[1..1])) & (! w_sel3489w[0..0])) # (w_sel3489w[1..1] & (w_sel3489w[0..0] # w_data3488w[2..2]))))) # ((((w_data3488w[0..0] & (! w_sel3489w[1..1])) & (! w_sel3489w[0..0])) # (w_sel3489w[1..1] & (w_sel3489w[0..0] # w_data3488w[2..2]))) & (w_data3488w[3..3] # (! w_sel3489w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3487w[1..1] & w_sel3489w[0..0]) & (! (((w_data3487w[0..0] & (! w_sel3489w[1..1])) & (! w_sel3489w[0..0])) # (w_sel3489w[1..1] & (w_sel3489w[0..0] # w_data3487w[2..2]))))) # ((((w_data3487w[0..0] & (! w_sel3489w[1..1])) & (! w_sel3489w[0..0])) # (w_sel3489w[1..1] & (w_sel3489w[0..0] # w_data3487w[2..2]))) & (w_data3487w[3..3] # (! w_sel3489w[0..0])))))), ((sel_node[2..2] & (((w_data3419w[1..1] & w_sel3420w[0..0]) & (! (((w_data3419w[0..0] & (! w_sel3420w[1..1])) & (! w_sel3420w[0..0])) # (w_sel3420w[1..1] & (w_sel3420w[0..0] # w_data3419w[2..2]))))) # ((((w_data3419w[0..0] & (! w_sel3420w[1..1])) & (! w_sel3420w[0..0])) # (w_sel3420w[1..1] & (w_sel3420w[0..0] # w_data3419w[2..2]))) & (w_data3419w[3..3] # (! w_sel3420w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3418w[1..1] & w_sel3420w[0..0]) & (! (((w_data3418w[0..0] & (! w_sel3420w[1..1])) & (! w_sel3420w[0..0])) # (w_sel3420w[1..1] & (w_sel3420w[0..0] # w_data3418w[2..2]))))) # ((((w_data3418w[0..0] & (! w_sel3420w[1..1])) & (! w_sel3420w[0..0])) # (w_sel3420w[1..1] & (w_sel3420w[0..0] # w_data3418w[2..2]))) & (w_data3418w[3..3] # (! w_sel3420w[0..0])))))), ((sel_node[2..2] & (((w_data3350w[1..1] & w_sel3351w[0..0]) & (! (((w_data3350w[0..0] & (! w_sel3351w[1..1])) & (! w_sel3351w[0..0])) # (w_sel3351w[1..1] & (w_sel3351w[0..0] # w_data3350w[2..2]))))) # ((((w_data3350w[0..0] & (! w_sel3351w[1..1])) & (! w_sel3351w[0..0])) # (w_sel3351w[1..1] & (w_sel3351w[0..0] # w_data3350w[2..2]))) & (w_data3350w[3..3] # (! w_sel3351w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3349w[1..1] & w_sel3351w[0..0]) & (! (((w_data3349w[0..0] & (! w_sel3351w[1..1])) & (! w_sel3351w[0..0])) # (w_sel3351w[1..1] & (w_sel3351w[0..0] # w_data3349w[2..2]))))) # ((((w_data3349w[0..0] & (! w_sel3351w[1..1])) & (! w_sel3351w[0..0])) # (w_sel3351w[1..1] & (w_sel3351w[0..0] # w_data3349w[2..2]))) & (w_data3349w[3..3] # (! w_sel3351w[0..0])))))), ((sel_node[2..2] & (((w_data3281w[1..1] & w_sel3282w[0..0]) & (! (((w_data3281w[0..0] & (! w_sel3282w[1..1])) & (! w_sel3282w[0..0])) # (w_sel3282w[1..1] & (w_sel3282w[0..0] # w_data3281w[2..2]))))) # ((((w_data3281w[0..0] & (! w_sel3282w[1..1])) & (! w_sel3282w[0..0])) # (w_sel3282w[1..1] & (w_sel3282w[0..0] # w_data3281w[2..2]))) & (w_data3281w[3..3] # (! w_sel3282w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3280w[1..1] & w_sel3282w[0..0]) & (! (((w_data3280w[0..0] & (! w_sel3282w[1..1])) & (! w_sel3282w[0..0])) # (w_sel3282w[1..1] & (w_sel3282w[0..0] # w_data3280w[2..2]))))) # ((((w_data3280w[0..0] & (! w_sel3282w[1..1])) & (! w_sel3282w[0..0])) # (w_sel3282w[1..1] & (w_sel3282w[0..0] # w_data3280w[2..2]))) & (w_data3280w[3..3] # (! w_sel3282w[0..0])))))), ((sel_node[2..2] & (((w_data3212w[1..1] & w_sel3213w[0..0]) & (! (((w_data3212w[0..0] & (! w_sel3213w[1..1])) & (! w_sel3213w[0..0])) # (w_sel3213w[1..1] & (w_sel3213w[0..0] # w_data3212w[2..2]))))) # ((((w_data3212w[0..0] & (! w_sel3213w[1..1])) & (! w_sel3213w[0..0])) # (w_sel3213w[1..1] & (w_sel3213w[0..0] # w_data3212w[2..2]))) & (w_data3212w[3..3] # (! w_sel3213w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3211w[1..1] & w_sel3213w[0..0]) & (! (((w_data3211w[0..0] & (! w_sel3213w[1..1])) & (! w_sel3213w[0..0])) # (w_sel3213w[1..1] & (w_sel3213w[0..0] # w_data3211w[2..2]))))) # ((((w_data3211w[0..0] & (! w_sel3213w[1..1])) & (! w_sel3213w[0..0])) # (w_sel3213w[1..1] & (w_sel3213w[0..0] # w_data3211w[2..2]))) & (w_data3211w[3..3] # (! w_sel3213w[0..0])))))), ((sel_node[2..2] & (((w_data3143w[1..1] & w_sel3144w[0..0]) & (! (((w_data3143w[0..0] & (! w_sel3144w[1..1])) & (! w_sel3144w[0..0])) # (w_sel3144w[1..1] & (w_sel3144w[0..0] # w_data3143w[2..2]))))) # ((((w_data3143w[0..0] & (! w_sel3144w[1..1])) & (! w_sel3144w[0..0])) # (w_sel3144w[1..1] & (w_sel3144w[0..0] # w_data3143w[2..2]))) & (w_data3143w[3..3] # (! w_sel3144w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3142w[1..1] & w_sel3144w[0..0]) & (! (((w_data3142w[0..0] & (! w_sel3144w[1..1])) & (! w_sel3144w[0..0])) # (w_sel3144w[1..1] & (w_sel3144w[0..0] # w_data3142w[2..2]))))) # ((((w_data3142w[0..0] & (! w_sel3144w[1..1])) & (! w_sel3144w[0..0])) # (w_sel3144w[1..1] & (w_sel3144w[0..0] # w_data3142w[2..2]))) & (w_data3142w[3..3] # (! w_sel3144w[0..0])))))), ((sel_node[2..2] & (((w_data3074w[1..1] & w_sel3075w[0..0]) & (! (((w_data3074w[0..0] & (! w_sel3075w[1..1])) & (! w_sel3075w[0..0])) # (w_sel3075w[1..1] & (w_sel3075w[0..0] # w_data3074w[2..2]))))) # ((((w_data3074w[0..0] & (! w_sel3075w[1..1])) & (! w_sel3075w[0..0])) # (w_sel3075w[1..1] & (w_sel3075w[0..0] # w_data3074w[2..2]))) & (w_data3074w[3..3] # (! w_sel3075w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3073w[1..1] & w_sel3075w[0..0]) & (! (((w_data3073w[0..0] & (! w_sel3075w[1..1])) & (! w_sel3075w[0..0])) # (w_sel3075w[1..1] & (w_sel3075w[0..0] # w_data3073w[2..2]))))) # ((((w_data3073w[0..0] & (! w_sel3075w[1..1])) & (! w_sel3075w[0..0])) # (w_sel3075w[1..1] & (w_sel3075w[0..0] # w_data3073w[2..2]))) & (w_data3073w[3..3] # (! w_sel3075w[0..0])))))), ((sel_node[2..2] & (((w_data3005w[1..1] & w_sel3006w[0..0]) & (! (((w_data3005w[0..0] & (! w_sel3006w[1..1])) & (! w_sel3006w[0..0])) # (w_sel3006w[1..1] & (w_sel3006w[0..0] # w_data3005w[2..2]))))) # ((((w_data3005w[0..0] & (! w_sel3006w[1..1])) & (! w_sel3006w[0..0])) # (w_sel3006w[1..1] & (w_sel3006w[0..0] # w_data3005w[2..2]))) & (w_data3005w[3..3] # (! w_sel3006w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3004w[1..1] & w_sel3006w[0..0]) & (! (((w_data3004w[0..0] & (! w_sel3006w[1..1])) & (! w_sel3006w[0..0])) # (w_sel3006w[1..1] & (w_sel3006w[0..0] # w_data3004w[2..2]))))) # ((((w_data3004w[0..0] & (! w_sel3006w[1..1])) & (! w_sel3006w[0..0])) # (w_sel3006w[1..1] & (w_sel3006w[0..0] # w_data3004w[2..2]))) & (w_data3004w[3..3] # (! w_sel3006w[0..0])))))), ((sel_node[2..2] & (((w_data2936w[1..1] & w_sel2937w[0..0]) & (! (((w_data2936w[0..0] & (! w_sel2937w[1..1])) & (! w_sel2937w[0..0])) # (w_sel2937w[1..1] & (w_sel2937w[0..0] # w_data2936w[2..2]))))) # ((((w_data2936w[0..0] & (! w_sel2937w[1..1])) & (! w_sel2937w[0..0])) # (w_sel2937w[1..1] & (w_sel2937w[0..0] # w_data2936w[2..2]))) & (w_data2936w[3..3] # (! w_sel2937w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2935w[1..1] & w_sel2937w[0..0]) & (! (((w_data2935w[0..0] & (! w_sel2937w[1..1])) & (! w_sel2937w[0..0])) # (w_sel2937w[1..1] & (w_sel2937w[0..0] # w_data2935w[2..2]))))) # ((((w_data2935w[0..0] & (! w_sel2937w[1..1])) & (! w_sel2937w[0..0])) # (w_sel2937w[1..1] & (w_sel2937w[0..0] # w_data2935w[2..2]))) & (w_data2935w[3..3] # (! w_sel2937w[0..0])))))), ((sel_node[2..2] & (((w_data2867w[1..1] & w_sel2868w[0..0]) & (! (((w_data2867w[0..0] & (! w_sel2868w[1..1])) & (! w_sel2868w[0..0])) # (w_sel2868w[1..1] & (w_sel2868w[0..0] # w_data2867w[2..2]))))) # ((((w_data2867w[0..0] & (! w_sel2868w[1..1])) & (! w_sel2868w[0..0])) # (w_sel2868w[1..1] & (w_sel2868w[0..0] # w_data2867w[2..2]))) & (w_data2867w[3..3] # (! w_sel2868w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2866w[1..1] & w_sel2868w[0..0]) & (! (((w_data2866w[0..0] & (! w_sel2868w[1..1])) & (! w_sel2868w[0..0])) # (w_sel2868w[1..1] & (w_sel2868w[0..0] # w_data2866w[2..2]))))) # ((((w_data2866w[0..0] & (! w_sel2868w[1..1])) & (! w_sel2868w[0..0])) # (w_sel2868w[1..1] & (w_sel2868w[0..0] # w_data2866w[2..2]))) & (w_data2866w[3..3] # (! w_sel2868w[0..0])))))), ((sel_node[2..2] & (((w_data2798w[1..1] & w_sel2799w[0..0]) & (! (((w_data2798w[0..0] & (! w_sel2799w[1..1])) & (! w_sel2799w[0..0])) # (w_sel2799w[1..1] & (w_sel2799w[0..0] # w_data2798w[2..2]))))) # ((((w_data2798w[0..0] & (! w_sel2799w[1..1])) & (! w_sel2799w[0..0])) # (w_sel2799w[1..1] & (w_sel2799w[0..0] # w_data2798w[2..2]))) & (w_data2798w[3..3] # (! w_sel2799w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2797w[1..1] & w_sel2799w[0..0]) & (! (((w_data2797w[0..0] & (! w_sel2799w[1..1])) & (! w_sel2799w[0..0])) # (w_sel2799w[1..1] & (w_sel2799w[0..0] # w_data2797w[2..2]))))) # ((((w_data2797w[0..0] & (! w_sel2799w[1..1])) & (! w_sel2799w[0..0])) # (w_sel2799w[1..1] & (w_sel2799w[0..0] # w_data2797w[2..2]))) & (w_data2797w[3..3] # (! w_sel2799w[0..0])))))), ((sel_node[2..2] & (((w_data2729w[1..1] & w_sel2730w[0..0]) & (! (((w_data2729w[0..0] & (! w_sel2730w[1..1])) & (! w_sel2730w[0..0])) # (w_sel2730w[1..1] & (w_sel2730w[0..0] # w_data2729w[2..2]))))) # ((((w_data2729w[0..0] & (! w_sel2730w[1..1])) & (! w_sel2730w[0..0])) # (w_sel2730w[1..1] & (w_sel2730w[0..0] # w_data2729w[2..2]))) & (w_data2729w[3..3] # (! w_sel2730w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2728w[1..1] & w_sel2730w[0..0]) & (! (((w_data2728w[0..0] & (! w_sel2730w[1..1])) & (! w_sel2730w[0..0])) # (w_sel2730w[1..1] & (w_sel2730w[0..0] # w_data2728w[2..2]))))) # ((((w_data2728w[0..0] & (! w_sel2730w[1..1])) & (! w_sel2730w[0..0])) # (w_sel2730w[1..1] & (w_sel2730w[0..0] # w_data2728w[2..2]))) & (w_data2728w[3..3] # (! w_sel2730w[0..0])))))), ((sel_node[2..2] & (((w_data2660w[1..1] & w_sel2661w[0..0]) & (! (((w_data2660w[0..0] & (! w_sel2661w[1..1])) & (! w_sel2661w[0..0])) # (w_sel2661w[1..1] & (w_sel2661w[0..0] # w_data2660w[2..2]))))) # ((((w_data2660w[0..0] & (! w_sel2661w[1..1])) & (! w_sel2661w[0..0])) # (w_sel2661w[1..1] & (w_sel2661w[0..0] # w_data2660w[2..2]))) & (w_data2660w[3..3] # (! w_sel2661w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2659w[1..1] & w_sel2661w[0..0]) & (! (((w_data2659w[0..0] & (! w_sel2661w[1..1])) & (! w_sel2661w[0..0])) # (w_sel2661w[1..1] & (w_sel2661w[0..0] # w_data2659w[2..2]))))) # ((((w_data2659w[0..0] & (! w_sel2661w[1..1])) & (! w_sel2661w[0..0])) # (w_sel2661w[1..1] & (w_sel2661w[0..0] # w_data2659w[2..2]))) & (w_data2659w[3..3] # (! w_sel2661w[0..0])))))), ((sel_node[2..2] & (((w_data2591w[1..1] & w_sel2592w[0..0]) & (! (((w_data2591w[0..0] & (! w_sel2592w[1..1])) & (! w_sel2592w[0..0])) # (w_sel2592w[1..1] & (w_sel2592w[0..0] # w_data2591w[2..2]))))) # ((((w_data2591w[0..0] & (! w_sel2592w[1..1])) & (! w_sel2592w[0..0])) # (w_sel2592w[1..1] & (w_sel2592w[0..0] # w_data2591w[2..2]))) & (w_data2591w[3..3] # (! w_sel2592w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2590w[1..1] & w_sel2592w[0..0]) & (! (((w_data2590w[0..0] & (! w_sel2592w[1..1])) & (! w_sel2592w[0..0])) # (w_sel2592w[1..1] & (w_sel2592w[0..0] # w_data2590w[2..2]))))) # ((((w_data2590w[0..0] & (! w_sel2592w[1..1])) & (! w_sel2592w[0..0])) # (w_sel2592w[1..1] & (w_sel2592w[0..0] # w_data2590w[2..2]))) & (w_data2590w[3..3] # (! w_sel2592w[0..0])))))), ((sel_node[2..2] & (((w_data2522w[1..1] & w_sel2523w[0..0]) & (! (((w_data2522w[0..0] & (! w_sel2523w[1..1])) & (! w_sel2523w[0..0])) # (w_sel2523w[1..1] & (w_sel2523w[0..0] # w_data2522w[2..2]))))) # ((((w_data2522w[0..0] & (! w_sel2523w[1..1])) & (! w_sel2523w[0..0])) # (w_sel2523w[1..1] & (w_sel2523w[0..0] # w_data2522w[2..2]))) & (w_data2522w[3..3] # (! w_sel2523w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2521w[1..1] & w_sel2523w[0..0]) & (! (((w_data2521w[0..0] & (! w_sel2523w[1..1])) & (! w_sel2523w[0..0])) # (w_sel2523w[1..1] & (w_sel2523w[0..0] # w_data2521w[2..2]))))) # ((((w_data2521w[0..0] & (! w_sel2523w[1..1])) & (! w_sel2523w[0..0])) # (w_sel2523w[1..1] & (w_sel2523w[0..0] # w_data2521w[2..2]))) & (w_data2521w[3..3] # (! w_sel2523w[0..0])))))), ((sel_node[2..2] & (((w_data2453w[1..1] & w_sel2454w[0..0]) & (! (((w_data2453w[0..0] & (! w_sel2454w[1..1])) & (! w_sel2454w[0..0])) # (w_sel2454w[1..1] & (w_sel2454w[0..0] # w_data2453w[2..2]))))) # ((((w_data2453w[0..0] & (! w_sel2454w[1..1])) & (! w_sel2454w[0..0])) # (w_sel2454w[1..1] & (w_sel2454w[0..0] # w_data2453w[2..2]))) & (w_data2453w[3..3] # (! w_sel2454w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2452w[1..1] & w_sel2454w[0..0]) & (! (((w_data2452w[0..0] & (! w_sel2454w[1..1])) & (! w_sel2454w[0..0])) # (w_sel2454w[1..1] & (w_sel2454w[0..0] # w_data2452w[2..2]))))) # ((((w_data2452w[0..0] & (! w_sel2454w[1..1])) & (! w_sel2454w[0..0])) # (w_sel2454w[1..1] & (w_sel2454w[0..0] # w_data2452w[2..2]))) & (w_data2452w[3..3] # (! w_sel2454w[0..0])))))), ((sel_node[2..2] & (((w_data2384w[1..1] & w_sel2385w[0..0]) & (! (((w_data2384w[0..0] & (! w_sel2385w[1..1])) & (! w_sel2385w[0..0])) # (w_sel2385w[1..1] & (w_sel2385w[0..0] # w_data2384w[2..2]))))) # ((((w_data2384w[0..0] & (! w_sel2385w[1..1])) & (! w_sel2385w[0..0])) # (w_sel2385w[1..1] & (w_sel2385w[0..0] # w_data2384w[2..2]))) & (w_data2384w[3..3] # (! w_sel2385w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2383w[1..1] & w_sel2385w[0..0]) & (! (((w_data2383w[0..0] & (! w_sel2385w[1..1])) & (! w_sel2385w[0..0])) # (w_sel2385w[1..1] & (w_sel2385w[0..0] # w_data2383w[2..2]))))) # ((((w_data2383w[0..0] & (! w_sel2385w[1..1])) & (! w_sel2385w[0..0])) # (w_sel2385w[1..1] & (w_sel2385w[0..0] # w_data2383w[2..2]))) & (w_data2383w[3..3] # (! w_sel2385w[0..0])))))), ((sel_node[2..2] & (((w_data2315w[1..1] & w_sel2316w[0..0]) & (! (((w_data2315w[0..0] & (! w_sel2316w[1..1])) & (! w_sel2316w[0..0])) # (w_sel2316w[1..1] & (w_sel2316w[0..0] # w_data2315w[2..2]))))) # ((((w_data2315w[0..0] & (! w_sel2316w[1..1])) & (! w_sel2316w[0..0])) # (w_sel2316w[1..1] & (w_sel2316w[0..0] # w_data2315w[2..2]))) & (w_data2315w[3..3] # (! w_sel2316w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2314w[1..1] & w_sel2316w[0..0]) & (! (((w_data2314w[0..0] & (! w_sel2316w[1..1])) & (! w_sel2316w[0..0])) # (w_sel2316w[1..1] & (w_sel2316w[0..0] # w_data2314w[2..2]))))) # ((((w_data2314w[0..0] & (! w_sel2316w[1..1])) & (! w_sel2316w[0..0])) # (w_sel2316w[1..1] & (w_sel2316w[0..0] # w_data2314w[2..2]))) & (w_data2314w[3..3] # (! w_sel2316w[0..0])))))), ((sel_node[2..2] & (((w_data2246w[1..1] & w_sel2247w[0..0]) & (! (((w_data2246w[0..0] & (! w_sel2247w[1..1])) & (! w_sel2247w[0..0])) # (w_sel2247w[1..1] & (w_sel2247w[0..0] # w_data2246w[2..2]))))) # ((((w_data2246w[0..0] & (! w_sel2247w[1..1])) & (! w_sel2247w[0..0])) # (w_sel2247w[1..1] & (w_sel2247w[0..0] # w_data2246w[2..2]))) & (w_data2246w[3..3] # (! w_sel2247w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2245w[1..1] & w_sel2247w[0..0]) & (! (((w_data2245w[0..0] & (! w_sel2247w[1..1])) & (! w_sel2247w[0..0])) # (w_sel2247w[1..1] & (w_sel2247w[0..0] # w_data2245w[2..2]))))) # ((((w_data2245w[0..0] & (! w_sel2247w[1..1])) & (! w_sel2247w[0..0])) # (w_sel2247w[1..1] & (w_sel2247w[0..0] # w_data2245w[2..2]))) & (w_data2245w[3..3] # (! w_sel2247w[0..0])))))), ((sel_node[2..2] & (((w_data2177w[1..1] & w_sel2178w[0..0]) & (! (((w_data2177w[0..0] & (! w_sel2178w[1..1])) & (! w_sel2178w[0..0])) # (w_sel2178w[1..1] & (w_sel2178w[0..0] # w_data2177w[2..2]))))) # ((((w_data2177w[0..0] & (! w_sel2178w[1..1])) & (! w_sel2178w[0..0])) # (w_sel2178w[1..1] & (w_sel2178w[0..0] # w_data2177w[2..2]))) & (w_data2177w[3..3] # (! w_sel2178w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2176w[1..1] & w_sel2178w[0..0]) & (! (((w_data2176w[0..0] & (! w_sel2178w[1..1])) & (! w_sel2178w[0..0])) # (w_sel2178w[1..1] & (w_sel2178w[0..0] # w_data2176w[2..2]))))) # ((((w_data2176w[0..0] & (! w_sel2178w[1..1])) & (! w_sel2178w[0..0])) # (w_sel2178w[1..1] & (w_sel2178w[0..0] # w_data2176w[2..2]))) & (w_data2176w[3..3] # (! w_sel2178w[0..0])))))), ((sel_node[2..2] & (((w_data2108w[1..1] & w_sel2109w[0..0]) & (! (((w_data2108w[0..0] & (! w_sel2109w[1..1])) & (! w_sel2109w[0..0])) # (w_sel2109w[1..1] & (w_sel2109w[0..0] # w_data2108w[2..2]))))) # ((((w_data2108w[0..0] & (! w_sel2109w[1..1])) & (! w_sel2109w[0..0])) # (w_sel2109w[1..1] & (w_sel2109w[0..0] # w_data2108w[2..2]))) & (w_data2108w[3..3] # (! w_sel2109w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2107w[1..1] & w_sel2109w[0..0]) & (! (((w_data2107w[0..0] & (! w_sel2109w[1..1])) & (! w_sel2109w[0..0])) # (w_sel2109w[1..1] & (w_sel2109w[0..0] # w_data2107w[2..2]))))) # ((((w_data2107w[0..0] & (! w_sel2109w[1..1])) & (! w_sel2109w[0..0])) # (w_sel2109w[1..1] & (w_sel2109w[0..0] # w_data2107w[2..2]))) & (w_data2107w[3..3] # (! w_sel2109w[0..0])))))), ((sel_node[2..2] & (((w_data2039w[1..1] & w_sel2040w[0..0]) & (! (((w_data2039w[0..0] & (! w_sel2040w[1..1])) & (! w_sel2040w[0..0])) # (w_sel2040w[1..1] & (w_sel2040w[0..0] # w_data2039w[2..2]))))) # ((((w_data2039w[0..0] & (! w_sel2040w[1..1])) & (! w_sel2040w[0..0])) # (w_sel2040w[1..1] & (w_sel2040w[0..0] # w_data2039w[2..2]))) & (w_data2039w[3..3] # (! w_sel2040w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2038w[1..1] & w_sel2040w[0..0]) & (! (((w_data2038w[0..0] & (! w_sel2040w[1..1])) & (! w_sel2040w[0..0])) # (w_sel2040w[1..1] & (w_sel2040w[0..0] # w_data2038w[2..2]))))) # ((((w_data2038w[0..0] & (! w_sel2040w[1..1])) & (! w_sel2040w[0..0])) # (w_sel2040w[1..1] & (w_sel2040w[0..0] # w_data2038w[2..2]))) & (w_data2038w[3..3] # (! w_sel2040w[0..0])))))), ((sel_node[2..2] & (((w_data1968w[1..1] & w_sel1969w[0..0]) & (! (((w_data1968w[0..0] & (! w_sel1969w[1..1])) & (! w_sel1969w[0..0])) # (w_sel1969w[1..1] & (w_sel1969w[0..0] # w_data1968w[2..2]))))) # ((((w_data1968w[0..0] & (! w_sel1969w[1..1])) & (! w_sel1969w[0..0])) # (w_sel1969w[1..1] & (w_sel1969w[0..0] # w_data1968w[2..2]))) & (w_data1968w[3..3] # (! w_sel1969w[0..0]))))) # ((! sel_node[2..2]) & (((w_data1967w[1..1] & w_sel1969w[0..0]) & (! (((w_data1967w[0..0] & (! w_sel1969w[1..1])) & (! w_sel1969w[0..0])) # (w_sel1969w[1..1] & (w_sel1969w[0..0] # w_data1967w[2..2]))))) # ((((w_data1967w[0..0] & (! w_sel1969w[1..1])) & (! w_sel1969w[0..0])) # (w_sel1969w[1..1] & (w_sel1969w[0..0] # w_data1967w[2..2]))) & (w_data1967w[3..3] # (! w_sel1969w[0..0]))))))); - sel_ffs_wire[] = ( sel[2..0]); - sel_node[] = ( sel_ffs_wire[2..2], sel[1..0]); - w_data1945w[] = ( B"0", data[192..192], data[160..160], data[128..128], data[96..96], data[64..64], data[32..32], data[0..0]); - w_data1967w[3..0] = w_data1945w[3..0]; - w_data1968w[3..0] = w_data1945w[7..4]; - w_data2016w[] = ( B"0", data[193..193], data[161..161], data[129..129], data[97..97], data[65..65], data[33..33], data[1..1]); - w_data2038w[3..0] = w_data2016w[3..0]; - w_data2039w[3..0] = w_data2016w[7..4]; - w_data2085w[] = ( B"0", data[194..194], data[162..162], data[130..130], data[98..98], data[66..66], data[34..34], data[2..2]); - w_data2107w[3..0] = w_data2085w[3..0]; - w_data2108w[3..0] = w_data2085w[7..4]; - w_data2154w[] = ( B"0", data[195..195], data[163..163], data[131..131], data[99..99], data[67..67], data[35..35], data[3..3]); - w_data2176w[3..0] = w_data2154w[3..0]; - w_data2177w[3..0] = w_data2154w[7..4]; - w_data2223w[] = ( B"0", data[196..196], data[164..164], data[132..132], data[100..100], data[68..68], data[36..36], data[4..4]); - w_data2245w[3..0] = w_data2223w[3..0]; - w_data2246w[3..0] = w_data2223w[7..4]; - w_data2292w[] = ( B"0", data[197..197], data[165..165], data[133..133], data[101..101], data[69..69], data[37..37], data[5..5]); - w_data2314w[3..0] = w_data2292w[3..0]; - w_data2315w[3..0] = w_data2292w[7..4]; - w_data2361w[] = ( B"0", data[198..198], data[166..166], data[134..134], data[102..102], data[70..70], data[38..38], data[6..6]); - w_data2383w[3..0] = w_data2361w[3..0]; - w_data2384w[3..0] = w_data2361w[7..4]; - w_data2430w[] = ( B"0", data[199..199], data[167..167], data[135..135], data[103..103], data[71..71], data[39..39], data[7..7]); - w_data2452w[3..0] = w_data2430w[3..0]; - w_data2453w[3..0] = w_data2430w[7..4]; - w_data2499w[] = ( B"0", data[200..200], data[168..168], data[136..136], data[104..104], data[72..72], data[40..40], data[8..8]); - w_data2521w[3..0] = w_data2499w[3..0]; - w_data2522w[3..0] = w_data2499w[7..4]; - w_data2568w[] = ( B"0", data[201..201], data[169..169], data[137..137], data[105..105], data[73..73], data[41..41], data[9..9]); - w_data2590w[3..0] = w_data2568w[3..0]; - w_data2591w[3..0] = w_data2568w[7..4]; - w_data2637w[] = ( B"0", data[202..202], data[170..170], data[138..138], data[106..106], data[74..74], data[42..42], data[10..10]); - w_data2659w[3..0] = w_data2637w[3..0]; - w_data2660w[3..0] = w_data2637w[7..4]; - w_data2706w[] = ( B"0", data[203..203], data[171..171], data[139..139], data[107..107], data[75..75], data[43..43], data[11..11]); - w_data2728w[3..0] = w_data2706w[3..0]; - w_data2729w[3..0] = w_data2706w[7..4]; - w_data2775w[] = ( B"0", data[204..204], data[172..172], data[140..140], data[108..108], data[76..76], data[44..44], data[12..12]); - w_data2797w[3..0] = w_data2775w[3..0]; - w_data2798w[3..0] = w_data2775w[7..4]; - w_data2844w[] = ( B"0", data[205..205], data[173..173], data[141..141], data[109..109], data[77..77], data[45..45], data[13..13]); - w_data2866w[3..0] = w_data2844w[3..0]; - w_data2867w[3..0] = w_data2844w[7..4]; - w_data2913w[] = ( B"0", data[206..206], data[174..174], data[142..142], data[110..110], data[78..78], data[46..46], data[14..14]); - w_data2935w[3..0] = w_data2913w[3..0]; - w_data2936w[3..0] = w_data2913w[7..4]; - w_data2982w[] = ( B"0", data[207..207], data[175..175], data[143..143], data[111..111], data[79..79], data[47..47], data[15..15]); - w_data3004w[3..0] = w_data2982w[3..0]; - w_data3005w[3..0] = w_data2982w[7..4]; - w_data3051w[] = ( B"0", data[208..208], data[176..176], data[144..144], data[112..112], data[80..80], data[48..48], data[16..16]); - w_data3073w[3..0] = w_data3051w[3..0]; - w_data3074w[3..0] = w_data3051w[7..4]; - w_data3120w[] = ( B"0", data[209..209], data[177..177], data[145..145], data[113..113], data[81..81], data[49..49], data[17..17]); - w_data3142w[3..0] = w_data3120w[3..0]; - w_data3143w[3..0] = w_data3120w[7..4]; - w_data3189w[] = ( B"0", data[210..210], data[178..178], data[146..146], data[114..114], data[82..82], data[50..50], data[18..18]); - w_data3211w[3..0] = w_data3189w[3..0]; - w_data3212w[3..0] = w_data3189w[7..4]; - w_data3258w[] = ( B"0", data[211..211], data[179..179], data[147..147], data[115..115], data[83..83], data[51..51], data[19..19]); - w_data3280w[3..0] = w_data3258w[3..0]; - w_data3281w[3..0] = w_data3258w[7..4]; - w_data3327w[] = ( B"0", data[212..212], data[180..180], data[148..148], data[116..116], data[84..84], data[52..52], data[20..20]); - w_data3349w[3..0] = w_data3327w[3..0]; - w_data3350w[3..0] = w_data3327w[7..4]; - w_data3396w[] = ( B"0", data[213..213], data[181..181], data[149..149], data[117..117], data[85..85], data[53..53], data[21..21]); - w_data3418w[3..0] = w_data3396w[3..0]; - w_data3419w[3..0] = w_data3396w[7..4]; - w_data3465w[] = ( B"0", data[214..214], data[182..182], data[150..150], data[118..118], data[86..86], data[54..54], data[22..22]); - w_data3487w[3..0] = w_data3465w[3..0]; - w_data3488w[3..0] = w_data3465w[7..4]; - w_data3534w[] = ( B"0", data[215..215], data[183..183], data[151..151], data[119..119], data[87..87], data[55..55], data[23..23]); - w_data3556w[3..0] = w_data3534w[3..0]; - w_data3557w[3..0] = w_data3534w[7..4]; - w_data3603w[] = ( B"0", data[216..216], data[184..184], data[152..152], data[120..120], data[88..88], data[56..56], data[24..24]); - w_data3625w[3..0] = w_data3603w[3..0]; - w_data3626w[3..0] = w_data3603w[7..4]; - w_data3672w[] = ( B"0", data[217..217], data[185..185], data[153..153], data[121..121], data[89..89], data[57..57], data[25..25]); - w_data3694w[3..0] = w_data3672w[3..0]; - w_data3695w[3..0] = w_data3672w[7..4]; - w_data3741w[] = ( B"0", data[218..218], data[186..186], data[154..154], data[122..122], data[90..90], data[58..58], data[26..26]); - w_data3763w[3..0] = w_data3741w[3..0]; - w_data3764w[3..0] = w_data3741w[7..4]; - w_data3810w[] = ( B"0", data[219..219], data[187..187], data[155..155], data[123..123], data[91..91], data[59..59], data[27..27]); - w_data3832w[3..0] = w_data3810w[3..0]; - w_data3833w[3..0] = w_data3810w[7..4]; - w_data3879w[] = ( B"0", data[220..220], data[188..188], data[156..156], data[124..124], data[92..92], data[60..60], data[28..28]); - w_data3901w[3..0] = w_data3879w[3..0]; - w_data3902w[3..0] = w_data3879w[7..4]; - w_data3948w[] = ( B"0", data[221..221], data[189..189], data[157..157], data[125..125], data[93..93], data[61..61], data[29..29]); - w_data3970w[3..0] = w_data3948w[3..0]; - w_data3971w[3..0] = w_data3948w[7..4]; - w_data4017w[] = ( B"0", data[222..222], data[190..190], data[158..158], data[126..126], data[94..94], data[62..62], data[30..30]); - w_data4039w[3..0] = w_data4017w[3..0]; - w_data4040w[3..0] = w_data4017w[7..4]; - w_data4086w[] = ( B"0", data[223..223], data[191..191], data[159..159], data[127..127], data[95..95], data[63..63], data[31..31]); - w_data4108w[3..0] = w_data4086w[3..0]; - w_data4109w[3..0] = w_data4086w[7..4]; - w_sel1969w[1..0] = sel_node[1..0]; - w_sel2040w[1..0] = sel_node[1..0]; - w_sel2109w[1..0] = sel_node[1..0]; - w_sel2178w[1..0] = sel_node[1..0]; - w_sel2247w[1..0] = sel_node[1..0]; - w_sel2316w[1..0] = sel_node[1..0]; - w_sel2385w[1..0] = sel_node[1..0]; - w_sel2454w[1..0] = sel_node[1..0]; - w_sel2523w[1..0] = sel_node[1..0]; - w_sel2592w[1..0] = sel_node[1..0]; - w_sel2661w[1..0] = sel_node[1..0]; - w_sel2730w[1..0] = sel_node[1..0]; - w_sel2799w[1..0] = sel_node[1..0]; - w_sel2868w[1..0] = sel_node[1..0]; - w_sel2937w[1..0] = sel_node[1..0]; - w_sel3006w[1..0] = sel_node[1..0]; - w_sel3075w[1..0] = sel_node[1..0]; - w_sel3144w[1..0] = sel_node[1..0]; - w_sel3213w[1..0] = sel_node[1..0]; - w_sel3282w[1..0] = sel_node[1..0]; - w_sel3351w[1..0] = sel_node[1..0]; - w_sel3420w[1..0] = sel_node[1..0]; - w_sel3489w[1..0] = sel_node[1..0]; - w_sel3558w[1..0] = sel_node[1..0]; - w_sel3627w[1..0] = sel_node[1..0]; - w_sel3696w[1..0] = sel_node[1..0]; - w_sel3765w[1..0] = sel_node[1..0]; - w_sel3834w[1..0] = sel_node[1..0]; - w_sel3903w[1..0] = sel_node[1..0]; - w_sel3972w[1..0] = sel_node[1..0]; - w_sel4041w[1..0] = sel_node[1..0]; - w_sel4110w[1..0] = sel_node[1..0]; -END; ---VALID FILE diff --git a/db/prev_cmp_lights.qmsg b/db/prev_cmp_lights.qmsg deleted file mode 100644 index 88e1361..0000000 --- a/db/prev_cmp_lights.qmsg +++ /dev/null @@ -1,572 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1480609244120 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1480609244121 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 01:20:43 2016 " "Processing started: Fri Dec 02 01:20:43 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1480609244121 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1480609244121 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lights -c lights " "Command: quartus_map --read_settings_files=on --write_settings_files=off lights -c lights" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1480609244121 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1480609244493 ""} -{ "Info" "ISGN_START_ELABORATION_QSYS" "nios_system.qsys " "Elaborating Qsys system entity \"nios_system.qsys\"" { } { } 0 12248 "Elaborating Qsys system entity \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609244532 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:45 Progress: Loading qsys_tutorial/nios_system.qsys " "2016.12.02.01:20:45 Progress: Loading qsys_tutorial/nios_system.qsys" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609245237 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:45 Progress: Reading input file " "2016.12.02.01:20:45 Progress: Reading input file" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609245421 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:45 Progress: Adding clk_0 \[clock_source 13.0\] " "2016.12.02.01:20:45 Progress: Adding clk_0 \[clock_source 13.0\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609245465 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:45 Progress: Parameterizing module clk_0 " "2016.12.02.01:20:45 Progress: Parameterizing module clk_0" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609245657 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:45 Progress: Adding nios2_processor \[altera_nios2_qsys 13.0\] " "2016.12.02.01:20:45 Progress: Adding nios2_processor \[altera_nios2_qsys 13.0\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609245661 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module nios2_processor " "2016.12.02.01:20:46 Progress: Parameterizing module nios2_processor" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246366 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding onchip_memory \[altera_avalon_onchip_memory2 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding onchip_memory \[altera_avalon_onchip_memory2 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246369 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module onchip_memory " "2016.12.02.01:20:46 Progress: Parameterizing module onchip_memory" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246433 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding jtag_uart \[altera_avalon_jtag_uart 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding jtag_uart \[altera_avalon_jtag_uart 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246434 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module jtag_uart " "2016.12.02.01:20:46 Progress: Parameterizing module jtag_uart" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246474 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding LEDs \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding LEDs \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246474 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module LEDs " "2016.12.02.01:20:46 Progress: Parameterizing module LEDs" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246518 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding LEDRs \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding LEDRs \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246519 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module LEDRs " "2016.12.02.01:20:46 Progress: Parameterizing module LEDRs" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246522 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding switches \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding switches \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246523 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module switches " "2016.12.02.01:20:46 Progress: Parameterizing module switches" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246524 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding push_switches \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding push_switches \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246524 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module push_switches " "2016.12.02.01:20:46 Progress: Parameterizing module push_switches" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246526 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding hex0 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding hex0 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246527 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module hex0 " "2016.12.02.01:20:46 Progress: Parameterizing module hex0" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246528 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding hex1 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding hex1 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246529 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module hex1 " "2016.12.02.01:20:46 Progress: Parameterizing module hex1" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246530 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding hex2 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding hex2 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246531 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module hex2 " "2016.12.02.01:20:46 Progress: Parameterizing module hex2" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246532 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding hex3 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding hex3 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246533 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module hex3 " "2016.12.02.01:20:46 Progress: Parameterizing module hex3" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246534 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding hex4 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding hex4 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246535 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module hex4 " "2016.12.02.01:20:46 Progress: Parameterizing module hex4" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246536 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding hex5 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding hex5 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246537 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module hex5 " "2016.12.02.01:20:46 Progress: Parameterizing module hex5" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246538 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding hex6 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding hex6 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246539 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module hex6 " "2016.12.02.01:20:46 Progress: Parameterizing module hex6" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246540 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding hex7 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding hex7 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246540 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module hex7 " "2016.12.02.01:20:46 Progress: Parameterizing module hex7" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246542 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding lcd_16207_0 \[altera_avalon_lcd_16207 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding lcd_16207_0 \[altera_avalon_lcd_16207 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246542 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module lcd_16207_0 " "2016.12.02.01:20:46 Progress: Parameterizing module lcd_16207_0" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246563 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding lcd_on \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding lcd_on \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246564 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module lcd_on " "2016.12.02.01:20:46 Progress: Parameterizing module lcd_on" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246566 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding lcd_blon \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding lcd_blon \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246567 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module lcd_blon " "2016.12.02.01:20:46 Progress: Parameterizing module lcd_blon" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246569 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Building connections " "2016.12.02.01:20:46 Progress: Building connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246569 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing connections " "2016.12.02.01:20:46 Progress: Parameterizing connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246883 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Validating " "2016.12.02.01:20:46 Progress: Validating" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246886 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:47 Progress: Done reading input file " "2016.12.02.01:20:47 Progress: Done reading input file" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609247552 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. " "Nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609247857 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. " "Nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609247857 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios_system: Generating nios_system \"nios_system\" for QUARTUS_SYNTH " "Nios_system: Generating nios_system \"nios_system\" for QUARTUS_SYNTH" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609248752 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Pipeline_bridge_swap_transform: After transform: 19 modules, 75 connections " "Pipeline_bridge_swap_transform: After transform: 19 modules, 75 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609248978 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "No custom instruction connections, skipping transform " "No custom instruction connections, skipping transform " { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609248985 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_translator_transform: After transform: 39 modules, 155 connections " "Merlin_translator_transform: After transform: 39 modules, 155 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609249536 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_domain_transform: After transform: 78 modules, 423 connections " "Merlin_domain_transform: After transform: 78 modules, 423 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609250547 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_router_transform: After transform: 98 modules, 503 connections " "Merlin_router_transform: After transform: 98 modules, 503 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609250874 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Reset_adaptation_transform: After transform: 99 modules, 390 connections " "Reset_adaptation_transform: After transform: 99 modules, 390 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609250950 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_network_to_switch_transform: After transform: 138 modules, 470 connections " "Merlin_network_to_switch_transform: After transform: 138 modules, 470 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609251203 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_mm_transform: After transform: 138 modules, 470 connections " "Merlin_mm_transform: After transform: 138 modules, 470 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609251295 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_interrupt_mapper_transform: After transform: 139 modules, 473 connections " "Merlin_interrupt_mapper_transform: After transform: 139 modules, 473 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609251335 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252303 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252303 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252304 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252304 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252304 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252304 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252304 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252305 ""} -{ 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found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252316 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252316 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252316 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for 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"Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252317 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252317 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252317 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req 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"%1!s!" 0 0 "Quartus II" 0 -1 1480609252318 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252318 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252318 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252318 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role 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(reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252322 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252322 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252322 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 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found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252323 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252323 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252324 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for 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"Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252325 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252325 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252325 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252326 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252326 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252326 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252326 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252326 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252327 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252327 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252327 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252327 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252327 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252328 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252328 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252328 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252328 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252329 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252329 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252329 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252329 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252329 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252330 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252330 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252330 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252330 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' " "Nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252709 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: Generation command is \[exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus \] " "Nios2_processor: Generation command is \[exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252709 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) Starting Nios II generation " "Nios2_processor: # 2016.12.02 01:20:53 (*) Starting Nios II generation" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256733 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) Checking for plaintext license. " "Nios2_processor: # 2016.12.02 01:20:53 (*) Checking for plaintext license." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256733 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus " "Nios2_processor: # 2016.12.02 01:20:53 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256733 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) Defaulting to contents of LM_LICENSE_FILE environment variable " "Nios2_processor: # 2016.12.02 01:20:53 (*) Defaulting to contents of LM_LICENSE_FILE environment variable" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256733 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) LM_LICENSE_FILE environment variable is empty " "Nios2_processor: # 2016.12.02 01:20:53 (*) LM_LICENSE_FILE environment variable is empty" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256733 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) Plaintext license not found. " "Nios2_processor: # 2016.12.02 01:20:53 (*) Plaintext license not found." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256734 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) No license required to generate encrypted Nios II/e. " "Nios2_processor: # 2016.12.02 01:20:53 (*) No license required to generate encrypted Nios II/e." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256734 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) Elaborating CPU configuration settings " "Nios2_processor: # 2016.12.02 01:20:53 (*) Elaborating CPU configuration settings" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256734 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) Creating all objects for CPU " "Nios2_processor: # 2016.12.02 01:20:53 (*) Creating all objects for CPU" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256734 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:54 (*) Generating RTL from CPU objects " "Nios2_processor: # 2016.12.02 01:20:54 (*) Generating RTL from CPU objects" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256734 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:54 (*) Creating plain-text RTL " "Nios2_processor: # 2016.12.02 01:20:54 (*) Creating plain-text RTL" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256734 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:56 (*) Done Nios II generation " "Nios2_processor: # 2016.12.02 01:20:56 (*) Done Nios II generation" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256734 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' " "Nios2_processor: Done RTL generation for module 'nios_system_nios2_processor'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256735 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: \"nios_system\" instantiated altera_nios2_qsys \"nios2_processor\" " "Nios2_processor: \"nios_system\" instantiated altera_nios2_qsys \"nios2_processor\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256747 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' " "Onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256787 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Onchip_memory: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 \] " "Onchip_memory: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256787 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' " "Onchip_memory: Done RTL generation for module 'nios_system_onchip_memory'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609257861 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Onchip_memory: \"nios_system\" instantiated altera_avalon_onchip_memory2 \"onchip_memory\" " "Onchip_memory: \"nios_system\" instantiated altera_avalon_onchip_memory2 \"onchip_memory\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609257874 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' " "Jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609257894 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Jtag_uart: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 \] " "Jtag_uart: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609257894 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' " "Jtag_uart: Done RTL generation for module 'nios_system_jtag_uart'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258183 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Jtag_uart: \"nios_system\" instantiated altera_avalon_jtag_uart \"jtag_uart\" " "Jtag_uart: \"nios_system\" instantiated altera_avalon_jtag_uart \"jtag_uart\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258187 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDs: Starting RTL generation for module 'nios_system_LEDs' " "LEDs: Starting RTL generation for module 'nios_system_LEDs'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258209 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDs: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 \] " "LEDs: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258209 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDs: Done RTL generation for module 'nios_system_LEDs' " "LEDs: Done RTL generation for module 'nios_system_LEDs'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258399 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDs: \"nios_system\" instantiated altera_avalon_pio \"LEDs\" " "LEDs: \"nios_system\" instantiated altera_avalon_pio \"LEDs\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258401 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDRs: Starting RTL generation for module 'nios_system_LEDRs' " "LEDRs: Starting RTL generation for module 'nios_system_LEDRs'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258414 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDRs: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 \] " "LEDRs: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258415 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDRs: Done RTL generation for module 'nios_system_LEDRs' " "LEDRs: Done RTL generation for module 'nios_system_LEDRs'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258596 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDRs: \"nios_system\" instantiated altera_avalon_pio \"LEDRs\" " "LEDRs: \"nios_system\" instantiated altera_avalon_pio \"LEDRs\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258598 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Switches: Starting RTL generation for module 'nios_system_switches' " "Switches: Starting RTL generation for module 'nios_system_switches'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258613 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Switches: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 \] " "Switches: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258613 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Switches: Done RTL generation for module 'nios_system_switches' " "Switches: Done RTL generation for module 'nios_system_switches'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258799 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Switches: \"nios_system\" instantiated altera_avalon_pio \"switches\" " "Switches: \"nios_system\" instantiated altera_avalon_pio \"switches\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258801 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Push_switches: Starting RTL generation for module 'nios_system_push_switches' " "Push_switches: Starting RTL generation for module 'nios_system_push_switches'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258817 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Push_switches: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 \] " "Push_switches: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258817 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Push_switches: Done RTL generation for module 'nios_system_push_switches' " "Push_switches: Done RTL generation for module 'nios_system_push_switches'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259002 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Push_switches: \"nios_system\" instantiated altera_avalon_pio \"push_switches\" " "Push_switches: \"nios_system\" instantiated altera_avalon_pio \"push_switches\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259005 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Hex0: Starting RTL generation for module 'nios_system_hex0' " "Hex0: Starting RTL generation for module 'nios_system_hex0'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259021 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Hex0: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 \] " "Hex0: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259021 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Hex0: Done RTL generation for module 'nios_system_hex0' " "Hex0: Done RTL generation for module 'nios_system_hex0'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259206 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Hex0: \"nios_system\" instantiated altera_avalon_pio \"hex0\" " "Hex0: \"nios_system\" instantiated altera_avalon_pio \"hex0\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259208 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_16207_0: Starting RTL generation for module 'nios_system_lcd_16207_0' " "Lcd_16207_0: Starting RTL generation for module 'nios_system_lcd_16207_0'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259222 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_16207_0: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 \] " "Lcd_16207_0: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259222 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_16207_0: Done RTL generation for module 'nios_system_lcd_16207_0' " "Lcd_16207_0: Done RTL generation for module 'nios_system_lcd_16207_0'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259404 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_16207_0: \"nios_system\" instantiated altera_avalon_lcd_16207 \"lcd_16207_0\" " "Lcd_16207_0: \"nios_system\" instantiated altera_avalon_lcd_16207 \"lcd_16207_0\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259407 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_on: Starting RTL generation for module 'nios_system_lcd_on' " "Lcd_on: Starting RTL generation for module 'nios_system_lcd_on'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259419 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_on: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 \] " "Lcd_on: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259420 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_on: Done RTL generation for module 'nios_system_lcd_on' " "Lcd_on: Done RTL generation for module 'nios_system_lcd_on'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259615 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_on: \"nios_system\" instantiated altera_avalon_pio \"lcd_on\" " "Lcd_on: \"nios_system\" instantiated altera_avalon_pio \"lcd_on\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259618 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_instruction_master_translator: \"nios_system\" instantiated altera_merlin_master_translator \"nios2_processor_instruction_master_translator\" " "Nios2_processor_instruction_master_translator: \"nios_system\" instantiated altera_merlin_master_translator \"nios2_processor_instruction_master_translator\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259620 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_jtag_debug_module_translator: \"nios_system\" instantiated altera_merlin_slave_translator \"nios2_processor_jtag_debug_module_translator\" " "Nios2_processor_jtag_debug_module_translator: \"nios_system\" instantiated altera_merlin_slave_translator \"nios2_processor_jtag_debug_module_translator\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259629 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: \"nios_system\" instantiated altera_merlin_master_agent \"nios2_processor_instruction_master_translator_avalon_universal_master_0_agent\" " "Nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: \"nios_system\" instantiated altera_merlin_master_agent \"nios2_processor_instruction_master_translator_avalon_universal_master_0_agent\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259637 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: \"nios_system\" instantiated altera_merlin_slave_agent \"nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\" " "Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: \"nios_system\" instantiated altera_merlin_slave_agent \"nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259645 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: \"nios_system\" instantiated altera_avalon_sc_fifo \"nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo\" " "Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: \"nios_system\" instantiated altera_avalon_sc_fifo \"nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259659 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Addr_router: \"nios_system\" instantiated altera_merlin_router \"addr_router\" " "Addr_router: \"nios_system\" instantiated altera_merlin_router \"addr_router\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259678 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Addr_router_001: \"nios_system\" instantiated altera_merlin_router \"addr_router_001\" " "Addr_router_001: \"nios_system\" instantiated altera_merlin_router \"addr_router_001\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259697 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Id_router: \"nios_system\" instantiated altera_merlin_router \"id_router\" " "Id_router: \"nios_system\" instantiated altera_merlin_router \"id_router\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259714 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Id_router_002: \"nios_system\" instantiated altera_merlin_router \"id_router_002\" " "Id_router_002: \"nios_system\" instantiated altera_merlin_router \"id_router_002\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259726 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rst_controller: \"nios_system\" instantiated altera_reset_controller \"rst_controller\" " "Rst_controller: \"nios_system\" instantiated altera_reset_controller \"rst_controller\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259729 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Cmd_xbar_demux: \"nios_system\" instantiated altera_merlin_demultiplexer \"cmd_xbar_demux\" " "Cmd_xbar_demux: \"nios_system\" instantiated altera_merlin_demultiplexer \"cmd_xbar_demux\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259754 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Cmd_xbar_demux_001: \"nios_system\" instantiated altera_merlin_demultiplexer \"cmd_xbar_demux_001\" " "Cmd_xbar_demux_001: \"nios_system\" instantiated altera_merlin_demultiplexer \"cmd_xbar_demux_001\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259787 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Cmd_xbar_mux: \"nios_system\" instantiated altera_merlin_multiplexer \"cmd_xbar_mux\" " "Cmd_xbar_mux: \"nios_system\" instantiated altera_merlin_multiplexer \"cmd_xbar_mux\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259831 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rsp_xbar_demux_002: \"nios_system\" instantiated altera_merlin_demultiplexer \"rsp_xbar_demux_002\" " "Rsp_xbar_demux_002: \"nios_system\" instantiated altera_merlin_demultiplexer \"rsp_xbar_demux_002\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259857 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rsp_xbar_mux: \"nios_system\" instantiated altera_merlin_multiplexer \"rsp_xbar_mux\" " "Rsp_xbar_mux: \"nios_system\" instantiated altera_merlin_multiplexer \"rsp_xbar_mux\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259890 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv " "Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259891 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rsp_xbar_mux_001: \"nios_system\" instantiated altera_merlin_multiplexer \"rsp_xbar_mux_001\" " "Rsp_xbar_mux_001: \"nios_system\" instantiated altera_merlin_multiplexer \"rsp_xbar_mux_001\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259951 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv " "Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259952 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Irq_mapper: \"nios_system\" instantiated altera_irq_mapper \"irq_mapper\" " "Irq_mapper: \"nios_system\" instantiated altera_irq_mapper \"irq_mapper\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259971 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios_system: Done nios_system\" with 28 modules, 155 files, 4086283 bytes " "Nios_system: Done nios_system\" with 28 modules, 155 files, 4086283 bytes" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259972 ""} -{ "Info" "ISGN_END_ELABORATION_QSYS" "nios_system.qsys " "Finished elaborating Qsys system entity \"nios_system.qsys\"" { } { } 0 12249 "Finished elaborating Qsys system entity \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609260929 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lights.vhd 2 1 " "Found 2 design units, including 1 entities, in source file lights.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lights-lights_rtl " "Found design unit 1: lights-lights_rtl" { } { { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 27 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261363 ""} { "Info" "ISGN_ENTITY_NAME" "1 lights " "Found entity 1: lights" { } { { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261363 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261363 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_system/synthesis/nios_system.v 1 1 " "Found 1 design units, including 1 entities, in source file nios_system/synthesis/nios_system.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system " "Found entity 1: nios_system" { } { { "nios_system/synthesis/nios_system.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261383 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261383 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/nios_system.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/nios_system.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system " "Found entity 1: nios_system" { } { { "db/ip/nios_system/nios_system.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/nios_system.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261402 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261402 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" { } { { "db/ip/nios_system/submodules/altera_avalon_sc_fifo.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_avalon_sc_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261406 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261406 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_arbitrator " "Found entity 1: altera_merlin_arbitrator" { } { { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 103 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261410 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_arb_adder " "Found entity 2: altera_merlin_arb_adder" { } { { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 228 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261410 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261410 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_uncompressor " "Found entity 1: altera_merlin_burst_uncompressor" { } { { "db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261414 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261414 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_master_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_master_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_agent " "Found entity 1: altera_merlin_master_agent" { } { { "db/ip/nios_system/submodules/altera_merlin_master_agent.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_agent.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261418 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261418 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_master_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_master_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_translator " "Found entity 1: altera_merlin_master_translator" { } { { "db/ip/nios_system/submodules/altera_merlin_master_translator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_translator.sv" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261422 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261422 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_slave_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_agent " "Found entity 1: altera_merlin_slave_agent" { } { { "db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261426 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261426 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_slave_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_slave_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_translator " "Found entity 1: altera_merlin_slave_translator" { } { { "db/ip/nios_system/submodules/altera_merlin_slave_translator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_translator.sv" 35 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261431 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261431 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_reset_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_reset_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_controller " "Found entity 1: altera_reset_controller" { } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261435 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261435 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_synchronizer " "Found entity 1: altera_reset_synchronizer" { } { { "db/ip/nios_system/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_synchronizer.v" 24 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261438 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261438 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_ledrs.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_ledrs.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_LEDRs " "Found entity 1: nios_system_LEDRs" { } { { "db/ip/nios_system/submodules/nios_system_LEDRs.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_LEDRs.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261441 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261441 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_leds.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_leds.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_LEDs " "Found entity 1: nios_system_LEDs" { } { { "db/ip/nios_system/submodules/nios_system_LEDs.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_LEDs.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261444 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261444 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel nios_system_addr_router.sv(48) " "Verilog HDL Declaration information at nios_system_addr_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609261447 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel nios_system_addr_router.sv(49) " "Verilog HDL Declaration information at nios_system_addr_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609261447 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_addr_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_addr_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_addr_router_default_decode " "Found entity 1: nios_system_addr_router_default_decode" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261448 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_addr_router " "Found entity 2: nios_system_addr_router" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261448 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261448 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel nios_system_addr_router_001.sv(48) " "Verilog HDL Declaration information at nios_system_addr_router_001.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609261451 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel nios_system_addr_router_001.sv(49) " "Verilog HDL Declaration information at nios_system_addr_router_001.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609261451 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_addr_router_001.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_addr_router_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_addr_router_001_default_decode " "Found entity 1: nios_system_addr_router_001_default_decode" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261452 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_addr_router_001 " "Found entity 2: nios_system_addr_router_001" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261452 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261452 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_cmd_xbar_demux " "Found entity 1: nios_system_cmd_xbar_demux" { } { { "db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261455 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261455 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_cmd_xbar_demux_001 " "Found entity 1: nios_system_cmd_xbar_demux_001" { } { { "db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261459 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261459 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_cmd_xbar_mux " "Found entity 1: nios_system_cmd_xbar_mux" { } { { "db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261463 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261463 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_hex0.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_hex0.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_hex0 " "Found entity 1: nios_system_hex0" { } { { "db/ip/nios_system/submodules/nios_system_hex0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_hex0.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261467 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel nios_system_id_router.sv(48) " "Verilog HDL Declaration information at nios_system_id_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609261470 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel nios_system_id_router.sv(49) " "Verilog HDL Declaration information at nios_system_id_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609261470 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_id_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_id_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_id_router_default_decode " "Found entity 1: nios_system_id_router_default_decode" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261471 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_id_router " "Found entity 2: nios_system_id_router" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261471 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261471 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel nios_system_id_router_002.sv(48) " "Verilog HDL Declaration information at nios_system_id_router_002.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609261474 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel nios_system_id_router_002.sv(49) " "Verilog HDL Declaration information at nios_system_id_router_002.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609261475 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_id_router_002.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_id_router_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_id_router_002_default_decode " "Found entity 1: nios_system_id_router_002_default_decode" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261476 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_id_router_002 " "Found entity 2: nios_system_id_router_002" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261476 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261476 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_irq_mapper.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_irq_mapper.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_irq_mapper " "Found entity 1: nios_system_irq_mapper" { } { { "db/ip/nios_system/submodules/nios_system_irq_mapper.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_irq_mapper.sv" 31 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261479 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261479 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_jtag_uart.v 5 5 " "Found 5 design units, including 5 entities, in source file db/ip/nios_system/submodules/nios_system_jtag_uart.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_jtag_uart_sim_scfifo_w " "Found entity 1: nios_system_jtag_uart_sim_scfifo_w" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261485 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_jtag_uart_scfifo_w " "Found entity 2: nios_system_jtag_uart_scfifo_w" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 77 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261485 ""} { "Info" "ISGN_ENTITY_NAME" "3 nios_system_jtag_uart_sim_scfifo_r " "Found entity 3: nios_system_jtag_uart_sim_scfifo_r" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 162 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261485 ""} { "Info" "ISGN_ENTITY_NAME" "4 nios_system_jtag_uart_scfifo_r " "Found entity 4: nios_system_jtag_uart_scfifo_r" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 240 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261485 ""} { "Info" "ISGN_ENTITY_NAME" "5 nios_system_jtag_uart " "Found entity 5: nios_system_jtag_uart" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 327 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261485 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261485 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_lcd_16207_0 " "Found entity 1: nios_system_lcd_16207_0" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261488 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261488 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_lcd_on.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_lcd_on.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_lcd_on " "Found entity 1: nios_system_lcd_on" { } { { "db/ip/nios_system/submodules/nios_system_lcd_on.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_on.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261492 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261492 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor.v 21 21 " "Found 21 design units, including 21 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_register_bank_a_module " "Found entity 1: nios_system_nios2_processor_register_bank_a_module" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_nios2_processor_register_bank_b_module " "Found entity 2: nios_system_nios2_processor_register_bank_b_module" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 84 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "3 nios_system_nios2_processor_nios2_oci_debug " "Found entity 3: nios_system_nios2_processor_nios2_oci_debug" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 147 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "4 nios_system_nios2_processor_ociram_sp_ram_module " "Found entity 4: nios_system_nios2_processor_ociram_sp_ram_module" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 288 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "5 nios_system_nios2_processor_nios2_ocimem " "Found entity 5: nios_system_nios2_processor_nios2_ocimem" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 346 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "6 nios_system_nios2_processor_nios2_avalon_reg " "Found entity 6: nios_system_nios2_processor_nios2_avalon_reg" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 524 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "7 nios_system_nios2_processor_nios2_oci_break " "Found entity 7: nios_system_nios2_processor_nios2_oci_break" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 616 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "8 nios_system_nios2_processor_nios2_oci_xbrk " "Found entity 8: nios_system_nios2_processor_nios2_oci_xbrk" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 910 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "9 nios_system_nios2_processor_nios2_oci_dbrk " "Found entity 9: nios_system_nios2_processor_nios2_oci_dbrk" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1116 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "10 nios_system_nios2_processor_nios2_oci_itrace " "Found entity 10: nios_system_nios2_processor_nios2_oci_itrace" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1302 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "11 nios_system_nios2_processor_nios2_oci_td_mode " "Found entity 11: nios_system_nios2_processor_nios2_oci_td_mode" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1599 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "12 nios_system_nios2_processor_nios2_oci_dtrace " "Found entity 12: nios_system_nios2_processor_nios2_oci_dtrace" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1666 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "13 nios_system_nios2_processor_nios2_oci_compute_tm_count " "Found entity 13: nios_system_nios2_processor_nios2_oci_compute_tm_count" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1760 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "14 nios_system_nios2_processor_nios2_oci_fifowp_inc " "Found entity 14: nios_system_nios2_processor_nios2_oci_fifowp_inc" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1831 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "15 nios_system_nios2_processor_nios2_oci_fifocount_inc " "Found entity 15: nios_system_nios2_processor_nios2_oci_fifocount_inc" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1873 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "16 nios_system_nios2_processor_nios2_oci_fifo " "Found entity 16: nios_system_nios2_processor_nios2_oci_fifo" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1919 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "17 nios_system_nios2_processor_nios2_oci_pib " "Found entity 17: nios_system_nios2_processor_nios2_oci_pib" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2424 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "18 nios_system_nios2_processor_nios2_oci_im " "Found entity 18: nios_system_nios2_processor_nios2_oci_im" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2492 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "19 nios_system_nios2_processor_nios2_performance_monitors " "Found entity 19: nios_system_nios2_processor_nios2_performance_monitors" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2608 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "20 nios_system_nios2_processor_nios2_oci " "Found entity 20: nios_system_nios2_processor_nios2_oci" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2624 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "21 nios_system_nios2_processor " "Found entity 21: nios_system_nios2_processor" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3129 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_jtag_debug_module_sysclk " "Found entity 1: nios_system_nios2_processor_jtag_debug_module_sysclk" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261516 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261516 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_jtag_debug_module_tck " "Found entity 1: nios_system_nios2_processor_jtag_debug_module_tck" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261519 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261519 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_jtag_debug_module_wrapper " "Found entity 1: nios_system_nios2_processor_jtag_debug_module_wrapper" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261523 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261523 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_oci_test_bench " "Found entity 1: nios_system_nios2_processor_oci_test_bench" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261526 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261526 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_test_bench " "Found entity 1: nios_system_nios2_processor_test_bench" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261530 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261530 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_onchip_memory.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_onchip_memory.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_onchip_memory " "Found entity 1: nios_system_onchip_memory" { } { { "db/ip/nios_system/submodules/nios_system_onchip_memory.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261533 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261533 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_push_switches.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_push_switches.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_push_switches " "Found entity 1: nios_system_push_switches" { } { { "db/ip/nios_system/submodules/nios_system_push_switches.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_push_switches.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261537 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261537 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_rsp_xbar_demux_002 " "Found entity 1: nios_system_rsp_xbar_demux_002" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261541 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261541 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_rsp_xbar_mux " "Found entity 1: nios_system_rsp_xbar_mux" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261545 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261545 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_rsp_xbar_mux_001 " "Found entity 1: nios_system_rsp_xbar_mux_001" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261550 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261550 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_switches.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_switches.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_switches " "Found entity 1: nios_system_switches" { } { { "db/ip/nios_system/submodules/nios_system_switches.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_switches.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261554 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261554 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "nios_system_nios2_processor.v(1567) " "Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1567): conditional expression evaluates to a constant" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1567 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "Quartus II" 0 -1 1480609261584 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "nios_system_nios2_processor.v(1569) " "Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1569): conditional expression evaluates to a constant" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1569 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "Quartus II" 0 -1 1480609261584 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "nios_system_nios2_processor.v(1725) " "Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1725): conditional expression evaluates to a constant" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1725 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "Quartus II" 0 -1 1480609261585 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "nios_system_nios2_processor.v(2553) " "Verilog HDL or VHDL warning at nios_system_nios2_processor.v(2553): conditional expression evaluates to a constant" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2553 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "Quartus II" 0 -1 1480609261588 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "lights " "Elaborating entity \"lights\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1480609261703 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system nios_system:NiosII " "Elaborating entity \"nios_system\" for hierarchy \"nios_system:NiosII\"" { } { { "lights.vhd" "NiosII" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 53 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609261724 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor nios_system:NiosII\|nios_system_nios2_processor:nios2_processor " "Elaborating entity \"nios_system_nios2_processor\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1103 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262516 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_test_bench nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench " "Elaborating entity \"nios_system_nios2_processor_test_bench\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_test_bench" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3794 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262643 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_register_bank_a_module nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a " "Elaborating entity \"nios_system_nios2_processor_register_bank_a_module\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_register_bank_a" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 4279 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262685 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_altsyncram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 55 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262737 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 55 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nios_system_nios2_processor_rf_ram_a.mif " "Parameter \"init_file\" = \"nios_system_nios2_processor_rf_ram_a.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 55 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609262758 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_0rh1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_0rh1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_0rh1 " "Found entity 1: altsyncram_0rh1" { } { { "db/altsyncram_0rh1.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_0rh1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609262827 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609262827 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_0rh1 nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_0rh1:auto_generated " "Elaborating entity \"altsyncram_0rh1\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_0rh1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262829 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_register_bank_b_module nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b " "Elaborating entity \"nios_system_nios2_processor_register_bank_b_module\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_register_bank_b" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 4300 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262955 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_altsyncram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 118 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262975 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 118 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nios_system_nios2_processor_rf_ram_b.mif " "Parameter \"init_file\" = \"nios_system_nios2_processor_rf_ram_b.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 118 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609262994 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_1rh1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_1rh1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_1rh1 " "Found entity 1: altsyncram_1rh1" { } { { "db/altsyncram_1rh1.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_1rh1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609263063 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609263063 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_1rh1 nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_1rh1:auto_generated " "Elaborating entity \"altsyncram_1rh1\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_1rh1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263066 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci " "Elaborating entity \"nios_system_nios2_processor_nios2_oci\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 4758 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263193 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_debug nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_debug\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_debug" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2802 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263239 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborating entity \"altera_std_synchronizer\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_altera_std_synchronizer" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 213 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263267 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 213 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609263279 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "depth 2 " "Parameter \"depth\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263279 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 213 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609263279 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_ocimem nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem " "Elaborating entity \"nios_system_nios2_processor_nios2_ocimem\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_ocimem" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2821 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263282 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_ociram_sp_ram_module nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram " "Elaborating entity \"nios_system_nios2_processor_ociram_sp_ram_module\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_ociram_sp_ram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 491 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263310 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_altsyncram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 322 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263727 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 322 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609263751 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nios_system_nios2_processor_ociram_default_contents.mif " "Parameter \"init_file\" = \"nios_system_nios2_processor_ociram_default_contents.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 322 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609263752 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4891.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_4891.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4891 " "Found entity 1: altsyncram_4891" { } { { "db/altsyncram_4891.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4891.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609263817 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609263817 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_4891 nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\|altsyncram_4891:auto_generated " "Elaborating entity \"altsyncram_4891\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\|altsyncram_4891:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263819 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_avalon_reg nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg " "Elaborating entity \"nios_system_nios2_processor_nios2_avalon_reg\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_avalon_reg" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2840 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263950 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_break nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_break\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_break" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2871 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263968 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_xbrk nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_xbrk\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_xbrk" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2892 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264008 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_dbrk nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_dbrk\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_dbrk" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2918 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264024 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_itrace nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_itrace:the_nios_system_nios2_processor_nios2_oci_itrace " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_itrace\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_itrace:the_nios_system_nios2_processor_nios2_oci_itrace\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_itrace" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2937 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264041 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_dtrace nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_dtrace\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_dtrace" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2952 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264068 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_td_mode nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace\|nios_system_nios2_processor_nios2_oci_td_mode:nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_td_mode\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace\|nios_system_nios2_processor_nios2_oci_td_mode:nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1714 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264093 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_fifo nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_fifo\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_fifo" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2971 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264108 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_compute_tm_count nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_compute_tm_count:nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_compute_tm_count\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_compute_tm_count:nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2046 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264154 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_fifowp_inc nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_fifowp_inc:nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_fifowp_inc\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_fifowp_inc:nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2056 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264171 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_fifocount_inc nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_fifocount_inc:nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_fifocount_inc\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_fifocount_inc:nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2066 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264189 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_oci_test_bench nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_oci_test_bench:the_nios_system_nios2_processor_oci_test_bench " "Elaborating entity \"nios_system_nios2_processor_oci_test_bench\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_oci_test_bench:the_nios_system_nios2_processor_oci_test_bench\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_oci_test_bench" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2075 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264205 ""} -{ "Warning" "WSGN_EMPTY_SHELL" "nios_system_nios2_processor_oci_test_bench " "Entity \"nios_system_nios2_processor_oci_test_bench\" contains only dangling pins" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_oci_test_bench" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2075 0 0 } } } 0 12158 "Entity \"%1!s!\" contains only dangling pins" 0 0 "Quartus II" 0 -1 1480609264206 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_pib nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_pib:the_nios_system_nios2_processor_nios2_oci_pib " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_pib\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_pib:the_nios_system_nios2_processor_nios2_oci_pib\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_pib" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2981 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264222 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_im nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_im:the_nios_system_nios2_processor_nios2_oci_im " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_im\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_im:the_nios_system_nios2_processor_nios2_oci_im\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_im" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3002 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264235 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_jtag_debug_module_wrapper nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper " "Elaborating entity \"nios_system_nios2_processor_jtag_debug_module_wrapper\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_jtag_debug_module_wrapper" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3107 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264430 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_jtag_debug_module_tck nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck " "Elaborating entity \"nios_system_nios2_processor_jtag_debug_module_tck\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "the_nios_system_nios2_processor_jtag_debug_module_tck" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 165 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264450 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_jtag_debug_module_sysclk nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk " "Elaborating entity \"nios_system_nios2_processor_jtag_debug_module_sysclk\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "the_nios_system_nios2_processor_jtag_debug_module_sysclk" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 188 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264479 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_basic nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy " "Elaborating entity \"sld_virtual_jtag_basic\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "nios_system_nios2_processor_jtag_debug_module_phy" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264517 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_auto_instance_index YES " "Parameter \"sld_auto_instance_index\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_instance_index 0 " "Parameter \"sld_instance_index\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_ir_width 2 " "Parameter \"sld_ir_width\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_mfg_id 70 " "Parameter \"sld_mfg_id\" = \"70\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_action " "Parameter \"sld_sim_action\" = \"\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_n_scan 0 " "Parameter \"sld_sim_n_scan\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_total_length 0 " "Parameter \"sld_sim_total_length\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_type_id 34 " "Parameter \"sld_type_id\" = \"34\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_version 3 " "Parameter \"sld_version\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609264531 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_impl nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst " "Elaborating entity \"sld_virtual_jtag_impl\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\"" { } { { "sld_virtual_jtag_basic.v" "sld_virtual_jtag_impl_inst" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264533 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\", which is child of megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\"" { } { { "sld_virtual_jtag_basic.v" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264548 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_onchip_memory nios_system:NiosII\|nios_system_onchip_memory:onchip_memory " "Elaborating entity \"nios_system_onchip_memory\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\"" { } { { "nios_system/synthesis/nios_system.v" "onchip_memory" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264552 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_onchip_memory.v" "the_altsyncram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v" 66 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264571 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_onchip_memory.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v" 66 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram " "Instantiated megafunction \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "byte_size 8 " "Parameter \"byte_size\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nios_system_onchip_memory.hex " "Parameter \"init_file\" = \"nios_system_onchip_memory.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 51200 " "Parameter \"maximum_depth\" = \"51200\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 51200 " "Parameter \"numwords_a\" = \"51200\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 16 " "Parameter \"widthad_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} } { { "db/ip/nios_system/submodules/nios_system_onchip_memory.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v" 66 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609264591 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4ed1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_4ed1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4ed1 " "Found entity 1: altsyncram_4ed1" { } { { "db/altsyncram_4ed1.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4ed1.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609264688 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609264688 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_4ed1 nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated " "Elaborating entity \"altsyncram_4ed1\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264690 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_qsa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_qsa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_qsa " "Found entity 1: decode_qsa" { } { { "db/decode_qsa.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/decode_qsa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609266788 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609266788 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_qsa nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\|decode_qsa:decode3 " "Elaborating entity \"decode_qsa\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\|decode_qsa:decode3\"" { } { { "db/altsyncram_4ed1.tdf" "decode3" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4ed1.tdf" 43 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609266790 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_nob.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_nob.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_nob " "Found entity 1: mux_nob" { } { { "db/mux_nob.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/mux_nob.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609266919 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609266919 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_nob nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\|mux_nob:mux2 " "Elaborating entity \"mux_nob\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\|mux_nob:mux2\"" { } { { "db/altsyncram_4ed1.tdf" "mux2" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4ed1.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609266921 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_jtag_uart nios_system:NiosII\|nios_system_jtag_uart:jtag_uart " "Elaborating entity \"nios_system_jtag_uart\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\"" { } { { "nios_system/synthesis/nios_system.v" "jtag_uart" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1129 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267161 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_jtag_uart_scfifo_w nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w " "Elaborating entity \"nios_system_jtag_uart_scfifo_w\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "the_nios_system_jtag_uart_scfifo_w" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 415 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267404 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo " "Elaborating entity \"scfifo\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "wfifo" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 137 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267473 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 137 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo " "Instantiated megafunction \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint RAM_BLOCK_TYPE=AUTO " "Parameter \"lpm_hint\" = \"RAM_BLOCK_TYPE=AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 64 " "Parameter \"lpm_numwords\" = \"64\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Parameter \"lpm_width\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 6 " "Parameter \"lpm_widthu\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Parameter \"overflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Parameter \"underflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 137 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609267488 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_jr21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_jr21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_jr21 " "Found entity 1: scfifo_jr21" { } { { "db/scfifo_jr21.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/scfifo_jr21.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609267556 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609267556 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_jr21 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated " "Elaborating entity \"scfifo_jr21\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267558 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_q131.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_q131.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_q131 " "Found entity 1: a_dpfifo_q131" { } { { "db/a_dpfifo_q131.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609267585 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609267585 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_q131 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo " "Elaborating entity \"a_dpfifo_q131\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\"" { } { { "db/scfifo_jr21.tdf" "dpfifo" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/scfifo_jr21.tdf" 37 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267588 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_7cf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_7cf " "Found entity 1: a_fefifo_7cf" { } { { "db/a_fefifo_7cf.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_fefifo_7cf.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609267611 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609267611 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_fefifo_7cf nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state " "Elaborating entity \"a_fefifo_7cf\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\"" { } { { "db/a_dpfifo_q131.tdf" "fifo_state" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf" 42 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267614 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_do7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_do7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_do7 " "Found entity 1: cntr_do7" { } { { "db/cntr_do7.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/cntr_do7.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609267703 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609267703 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_do7 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw " "Elaborating entity \"cntr_do7\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw\"" { } { { "db/a_fefifo_7cf.tdf" "count_usedw" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_fefifo_7cf.tdf" 38 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267705 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_nl21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dpram_nl21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_nl21 " "Found entity 1: dpram_nl21" { } { { "db/dpram_nl21.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/dpram_nl21.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609267794 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609267794 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpram_nl21 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram " "Elaborating entity \"dpram_nl21\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\"" { } { { "db/a_dpfifo_q131.tdf" "FIFOram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf" 43 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267797 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_r1m1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_r1m1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_r1m1 " "Found entity 1: altsyncram_r1m1" { } { { "db/altsyncram_r1m1.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_r1m1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609268450 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609268450 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_r1m1 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1 " "Elaborating entity \"altsyncram_r1m1\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1\"" { } { { "db/dpram_nl21.tdf" "altsyncram1" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/dpram_nl21.tdf" 36 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268452 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_1ob.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_1ob.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_1ob " "Found entity 1: cntr_1ob" { } { { "db/cntr_1ob.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/cntr_1ob.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609268547 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609268547 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_1ob nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count " "Elaborating entity \"cntr_1ob\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count\"" { } { { "db/a_dpfifo_q131.tdf" "rd_ptr_count" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268550 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_jtag_uart_scfifo_r nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r " "Elaborating entity \"nios_system_jtag_uart_scfifo_r\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "the_nios_system_jtag_uart_scfifo_r" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 429 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268582 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_jtag_atlantic nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic " "Elaborating entity \"alt_jtag_atlantic\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "nios_system_jtag_uart_alt_jtag_atlantic" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 564 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268734 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 564 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609268765 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic " "Instantiated megafunction \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "INSTANCE_ID 0 " "Parameter \"INSTANCE_ID\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268765 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_RXFIFO_DEPTH 6 " "Parameter \"LOG2_RXFIFO_DEPTH\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268765 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_TXFIFO_DEPTH 6 " "Parameter \"LOG2_TXFIFO_DEPTH\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268765 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_AUTO_INSTANCE_INDEX YES " "Parameter \"SLD_AUTO_INSTANCE_INDEX\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268765 ""} } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 564 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609268765 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_LEDs nios_system:NiosII\|nios_system_LEDs:leds " "Elaborating entity \"nios_system_LEDs\" for hierarchy \"nios_system:NiosII\|nios_system_LEDs:leds\"" { } { { "nios_system/synthesis/nios_system.v" "leds" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1140 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268774 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_LEDRs nios_system:NiosII\|nios_system_LEDRs:ledrs " "Elaborating entity \"nios_system_LEDRs\" for hierarchy \"nios_system:NiosII\|nios_system_LEDRs:ledrs\"" { } { { "nios_system/synthesis/nios_system.v" "ledrs" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1151 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268792 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_switches nios_system:NiosII\|nios_system_switches:switches " "Elaborating entity \"nios_system_switches\" for hierarchy \"nios_system:NiosII\|nios_system_switches:switches\"" { } { { "nios_system/synthesis/nios_system.v" "switches" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1159 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268812 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_push_switches nios_system:NiosII\|nios_system_push_switches:push_switches " "Elaborating entity \"nios_system_push_switches\" for hierarchy \"nios_system:NiosII\|nios_system_push_switches:push_switches\"" { } { { "nios_system/synthesis/nios_system.v" "push_switches" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1167 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268835 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_hex0 nios_system:NiosII\|nios_system_hex0:hex0 " "Elaborating entity \"nios_system_hex0\" for hierarchy \"nios_system:NiosII\|nios_system_hex0:hex0\"" { } { { "nios_system/synthesis/nios_system.v" "hex0" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1178 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268854 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_lcd_16207_0 nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0 " "Elaborating entity \"nios_system_lcd_16207_0\" for hierarchy \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\"" { } { { "nios_system/synthesis/nios_system.v" "lcd_16207_0" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1270 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268889 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_lcd_on nios_system:NiosII\|nios_system_lcd_on:lcd_on " "Elaborating entity \"nios_system_lcd_on\" for hierarchy \"nios_system:NiosII\|nios_system_lcd_on:lcd_on\"" { } { { "nios_system/synthesis/nios_system.v" "lcd_on" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1281 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268908 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator nios_system:NiosII\|altera_merlin_master_translator:nios2_processor_instruction_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_master_translator:nios2_processor_instruction_master_translator\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_instruction_master_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1354 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268928 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator nios_system:NiosII\|altera_merlin_master_translator:nios2_processor_data_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_master_translator:nios2_processor_data_master_translator\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_data_master_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1416 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268956 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_jtag_debug_module_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1482 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268985 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:onchip_memory_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:onchip_memory_s1_translator\"" { } { { "nios_system/synthesis/nios_system.v" "onchip_memory_s1_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1548 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269019 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:leds_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:leds_s1_translator\"" { } { { "nios_system/synthesis/nios_system.v" "leds_s1_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1614 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269051 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator\"" { } { { "nios_system/synthesis/nios_system.v" "jtag_uart_avalon_jtag_slave_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1680 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269081 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\"" { } { { "nios_system/synthesis/nios_system.v" "lcd_16207_0_control_slave_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2472 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269142 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent nios_system:NiosII\|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"nios_system:NiosII\|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2684 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269180 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent nios_system:NiosII\|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"nios_system:NiosII\|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_data_master_translator_avalon_universal_master_0_agent" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2764 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269242 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent nios_system:NiosII\|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2845 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269266 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor nios_system:NiosII\|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor\"" { } { { "db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" "uncompressor" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" 574 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269302 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo nios_system:NiosII\|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"nios_system:NiosII\|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2886 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269337 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_addr_router nios_system:NiosII\|nios_system_addr_router:addr_router " "Elaborating entity \"nios_system_addr_router\" for hierarchy \"nios_system:NiosII\|nios_system_addr_router:addr_router\"" { } { { "nios_system/synthesis/nios_system.v" "addr_router" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 4976 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269535 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_addr_router_default_decode nios_system:NiosII\|nios_system_addr_router:addr_router\|nios_system_addr_router_default_decode:the_default_decode " "Elaborating entity \"nios_system_addr_router_default_decode\" for hierarchy \"nios_system:NiosII\|nios_system_addr_router:addr_router\|nios_system_addr_router_default_decode:the_default_decode\"" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "the_default_decode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 177 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269571 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_addr_router_001 nios_system:NiosII\|nios_system_addr_router_001:addr_router_001 " "Elaborating entity \"nios_system_addr_router_001\" for hierarchy \"nios_system:NiosII\|nios_system_addr_router_001:addr_router_001\"" { } { { "nios_system/synthesis/nios_system.v" "addr_router_001" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 4992 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269589 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_addr_router_001_default_decode nios_system:NiosII\|nios_system_addr_router_001:addr_router_001\|nios_system_addr_router_001_default_decode:the_default_decode " "Elaborating entity \"nios_system_addr_router_001_default_decode\" for hierarchy \"nios_system:NiosII\|nios_system_addr_router_001:addr_router_001\|nios_system_addr_router_001_default_decode:the_default_decode\"" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "the_default_decode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 193 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269655 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_id_router nios_system:NiosII\|nios_system_id_router:id_router " "Elaborating entity \"nios_system_id_router\" for hierarchy \"nios_system:NiosII\|nios_system_id_router:id_router\"" { } { { "nios_system/synthesis/nios_system.v" "id_router" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5008 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269670 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_id_router_default_decode nios_system:NiosII\|nios_system_id_router:id_router\|nios_system_id_router_default_decode:the_default_decode " "Elaborating entity \"nios_system_id_router_default_decode\" for hierarchy \"nios_system:NiosII\|nios_system_id_router:id_router\|nios_system_id_router_default_decode:the_default_decode\"" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "the_default_decode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 175 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269696 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_id_router_002 nios_system:NiosII\|nios_system_id_router_002:id_router_002 " "Elaborating entity \"nios_system_id_router_002\" for hierarchy \"nios_system:NiosII\|nios_system_id_router_002:id_router_002\"" { } { { "nios_system/synthesis/nios_system.v" "id_router_002" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5040 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269717 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_id_router_002_default_decode nios_system:NiosII\|nios_system_id_router_002:id_router_002\|nios_system_id_router_002_default_decode:the_default_decode " "Elaborating entity \"nios_system_id_router_002_default_decode\" for hierarchy \"nios_system:NiosII\|nios_system_id_router_002:id_router_002\|nios_system_id_router_002_default_decode:the_default_decode\"" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "the_default_decode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 175 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269739 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_controller nios_system:NiosII\|altera_reset_controller:rst_controller " "Elaborating entity \"altera_reset_controller\" for hierarchy \"nios_system:NiosII\|altera_reset_controller:rst_controller\"" { } { { "nios_system/synthesis/nios_system.v" "rst_controller" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5307 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269835 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer nios_system:NiosII\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"nios_system:NiosII\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\"" { } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "alt_rst_sync_uq1" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 120 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269858 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_cmd_xbar_demux nios_system:NiosII\|nios_system_cmd_xbar_demux:cmd_xbar_demux " "Elaborating entity \"nios_system_cmd_xbar_demux\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_demux:cmd_xbar_demux\"" { } { { "nios_system/synthesis/nios_system.v" "cmd_xbar_demux" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5330 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269883 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_cmd_xbar_demux_001 nios_system:NiosII\|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001 " "Elaborating entity \"nios_system_cmd_xbar_demux_001\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001\"" { } { { "nios_system/synthesis/nios_system.v" "cmd_xbar_demux_001" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5449 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269910 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_cmd_xbar_mux nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux " "Elaborating entity \"nios_system_cmd_xbar_mux\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\"" { } { { "nios_system/synthesis/nios_system.v" "cmd_xbar_mux" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5472 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269979 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\"" { } { { "db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" "arb" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" 273 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270014 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270033 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_rsp_xbar_demux_002 nios_system:NiosII\|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_002 " "Elaborating entity \"nios_system_rsp_xbar_demux_002\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_002\"" { } { { "nios_system/synthesis/nios_system.v" "rsp_xbar_demux_002" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5558 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270061 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_rsp_xbar_mux nios_system:NiosII\|nios_system_rsp_xbar_mux:rsp_xbar_mux " "Elaborating entity \"nios_system_rsp_xbar_mux\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux:rsp_xbar_mux\"" { } { { "nios_system/synthesis/nios_system.v" "rsp_xbar_mux" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5836 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270124 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator nios_system:NiosII\|nios_system_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb\"" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" "arb" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" 296 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270155 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_rsp_xbar_mux_001 nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001 " "Elaborating entity \"nios_system_rsp_xbar_mux_001\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\"" { } { { "nios_system/synthesis/nios_system.v" "rsp_xbar_mux_001" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5955 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270177 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\"" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" "arb" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" 552 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270333 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270353 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_irq_mapper nios_system:NiosII\|nios_system_irq_mapper:irq_mapper " "Elaborating entity \"nios_system_irq_mapper\" for hierarchy \"nios_system:NiosII\|nios_system_irq_mapper:irq_mapper\"" { } { { "nios_system/synthesis/nios_system.v" "irq_mapper" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5962 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270368 ""} -{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "5 " "5 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1480609279462 ""} -{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[0\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[0\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[0\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[0\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609279649 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[1\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[1\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[1\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[1\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609279649 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[2\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[2\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[2\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[2\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609279649 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[3\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[3\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[3\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[3\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609279649 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[4\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[4\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[4\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[4\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609279649 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[5\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[5\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[5\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[5\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609279649 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[6\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[6\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[6\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[6\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609279649 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[7\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[7\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[7\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[7\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609279649 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1480609279649 ""} -{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "db/ip/nios_system/submodules/altera_merlin_master_agent.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_agent.sv" 276 -1 0 } } { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 348 -1 0 } } { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3167 -1 0 } } { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 203 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 291 -1 0 } } { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3740 -1 0 } } { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 393 -1 0 } } { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 599 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 224 -1 0 } } { "db/ip/nios_system/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_synchronizer.v" 62 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1480609279714 ""} -{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1480609279714 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609281555 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "166 " "166 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1480609284267 ""} -{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 384 -1 0 } } { "sld_jtag_hub.vhd" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 521 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1480609284431 ""} -{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1480609284431 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "sld_hub:auto_hub\|receive\[0\]\[0\] GND " "Pin \"sld_hub:auto_hub\|receive\[0\]\[0\]\" is stuck at GND" { } { { "sld_hub.vhd" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_hub.vhd" 181 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1480609284529 "|lights|sld_hub:auto_hub|receive[0][0]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1480609284529 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "sld_hub:auto_hub " "Timing-Driven Synthesis is running on partition \"sld_hub:auto_hub\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609284691 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.map.smsg " "Generated suppressed messages file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1480609285369 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1480609286405 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609286405 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "2880 " "Implemented 2880 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "26 " "Implemented 26 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1480609287063 ""} { "Info" "ICUT_CUT_TM_OPINS" "96 " "Implemented 96 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1480609287063 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2421 " "Implemented 2421 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1480609287063 ""} { "Info" "ICUT_CUT_TM_RAMS" "336 " "Implemented 336 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1480609287063 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1480609287063 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 150 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 150 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "650 " "Peak virtual memory: 650 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1480609287183 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 01:21:27 2016 " "Processing ended: Fri Dec 02 01:21:27 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1480609287183 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:44 " "Elapsed time: 00:00:44" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1480609287183 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1480609287183 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1480609287183 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1480609288328 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1480609288329 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 01:21:27 2016 " "Processing started: Fri Dec 02 01:21:27 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1480609288329 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1480609288329 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off lights -c lights " "Command: quartus_fit --read_settings_files=off --write_settings_files=off lights -c lights" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1480609288329 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1480609288398 ""} -{ "Info" "0" "" "Project = lights" { } { } 0 0 "Project = lights" 0 0 "Fitter" 0 0 1480609288399 ""} -{ "Info" "0" "" "Revision = lights" { } { } 0 0 "Revision = lights" 0 0 "Fitter" 0 0 1480609288399 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1480609288552 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "lights EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"lights\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1480609288596 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480609288662 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480609288662 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480609288662 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1480609288891 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1480609288902 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1480609289561 ""} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 11997 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1480609289572 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 11999 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1480609289572 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 12001 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1480609289572 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 12003 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1480609289572 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 12005 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1480609289572 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1480609289572 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1480609289576 ""} -{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1480609289623 ""} -{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 118 " "No exact pin location assignment(s) for 1 pins of 118 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LCD_E " "Pin LCD_E not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_E } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 21 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_E } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 363 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1480609292219 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1480609292219 ""} -{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\] " "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Fitter" 0 -1 1480609293128 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "lights.sdc " "Synopsys Design Constraints File file not found: 'lights.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1480609293201 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1480609293215 "|lights|CLOCK_50"} -{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609293273 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609293273 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609293273 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Fitter" 0 -1 1480609293273 ""} -{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1480609293273 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293274 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293274 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " " 100.000 altera_reserved_tck" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293274 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1480609293274 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p)) " "Automatically promoted node CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1480609293621 ""} } { { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 5 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 11965 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1480609293621 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP " "Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1480609293621 ""} } { { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 4020 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1480609293621 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "nios_system:NiosII\|altera_reset_controller:rst_controller\|r_sync_rst " "Automatically promoted node nios_system:NiosII\|altera_reset_controller:rst_controller\|r_sync_rst " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1480609293622 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "nios_system:NiosII\|altera_reset_controller:rst_controller\|WideOr0~0 " "Destination node nios_system:NiosII\|altera_reset_controller:rst_controller\|WideOr0~0" { } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 177 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|altera_reset_controller:rst_controller|WideOr0~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 4471 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1480609293622 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|W_rf_wren " "Destination node nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|W_rf_wren" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3700 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wren } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 3290 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1480609293622 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\|din_s1~0 " "Destination node nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\|din_s1~0" { } { { "altera_std_synchronizer.v" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altera_std_synchronizer.v" 45 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|din_s1~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 5951 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1480609293622 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1480609293622 ""} } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 172 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 906 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1480609293622 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "nios_system:NiosII\|altera_reset_controller:rst_controller\|merged_reset~0 " "Automatically promoted node nios_system:NiosII\|altera_reset_controller:rst_controller\|merged_reset~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1480609293623 ""} } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 68 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|altera_reset_controller:rst_controller|merged_reset~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 5707 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1480609293623 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1480609294840 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1480609294848 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1480609294848 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480609294859 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480609294870 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1480609294878 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1480609294879 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1480609294887 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1480609294987 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "8 EC " "Packed 8 registers into blocks of type EC" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1480609294996 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1480609294996 ""} -{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 2.5V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 2.5V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1480609295071 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1480609295071 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1480609295071 ""} -{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 20 40 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 20 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1480609295073 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 1 62 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 62 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1480609295073 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.3V 1 72 " "I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 1 total pin(s) used -- 72 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1480609295073 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.3V 32 39 " "I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 32 total pin(s) used -- 39 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1480609295073 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use 2.5V 34 31 " "I/O bank number 5 does not use VREF pins and has 2.5V VCCIO pins. 34 total pin(s) used -- 31 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1480609295073 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 2.5V 9 49 " "I/O bank number 6 does not use VREF pins and has 2.5V VCCIO pins. 9 total pin(s) used -- 49 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1480609295073 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 2.5V 29 43 " "I/O bank number 7 does not use VREF pins and has 2.5V VCCIO pins. 29 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1480609295073 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 71 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 71 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1480609295073 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1480609295073 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1480609295073 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN" "" "Ignored I/O standard assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_ADCDAT " "Ignored I/O standard assignment to node \"AUD_ADCDAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_ADCLRCK " "Ignored I/O standard assignment to node \"AUD_ADCLRCK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_BCLK " "Ignored I/O standard assignment to node \"AUD_BCLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_DACDAT " "Ignored I/O standard assignment to node \"AUD_DACDAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_DACLRCK " "Ignored I/O standard assignment to node \"AUD_DACLRCK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_XCK " "Ignored I/O standard assignment to node \"AUD_XCK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK2_50 " "Ignored I/O standard assignment to node \"CLOCK2_50\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK3_50 " "Ignored I/O standard assignment to node \"CLOCK3_50\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[0\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[10\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[11\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[12\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[1\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[2\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[3\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[4\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[5\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[6\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[7\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[8\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[9\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_BA\[0\] " "Ignored I/O standard assignment to node \"DRAM_BA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_BA\[1\] " "Ignored I/O standard assignment to node \"DRAM_BA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CAS_N " "Ignored I/O standard assignment to node \"DRAM_CAS_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CKE " "Ignored I/O standard assignment to node \"DRAM_CKE\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CLK " "Ignored I/O standard assignment to node \"DRAM_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CS_N " "Ignored I/O standard assignment to node \"DRAM_CS_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQM\[0\] " "Ignored I/O standard assignment to node \"DRAM_DQM\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQM\[1\] " "Ignored I/O standard assignment to node \"DRAM_DQM\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQM\[2\] " "Ignored I/O standard assignment to node \"DRAM_DQM\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQM\[3\] " "Ignored I/O standard assignment to node \"DRAM_DQM\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[0\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[10\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[11\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[12\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[13\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[14\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[15\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[16\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[17\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[17\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[18\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[18\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[19\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[19\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[1\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[20\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[20\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[21\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[21\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[22\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[22\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[23\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[23\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[24\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[24\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[25\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[25\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[26\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[26\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[27\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[27\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[28\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[28\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[29\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[29\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[2\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[30\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[30\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[31\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[31\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[3\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[4\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[5\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[6\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[7\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[8\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[9\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_RAS_N " "Ignored I/O standard assignment to node \"DRAM_RAS_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_WE_N " "Ignored I/O standard assignment to node \"DRAM_WE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EEP_I2C_SCLK " "Ignored I/O standard assignment to node \"EEP_I2C_SCLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EEP_I2C_SDAT " "Ignored I/O standard assignment to node \"EEP_I2C_SDAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_GTX_CLK " "Ignored I/O standard assignment to node \"ENET0_GTX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_INT_N " "Ignored I/O standard assignment to node \"ENET0_INT_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_LINK100 " "Ignored I/O standard assignment to node \"ENET0_LINK100\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_MDC " "Ignored I/O standard assignment to node \"ENET0_MDC\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_MDIO " "Ignored I/O standard assignment to node \"ENET0_MDIO\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RST_N " "Ignored I/O standard assignment to node \"ENET0_RST_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_CLK " "Ignored I/O standard assignment to node \"ENET0_RX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_COL " "Ignored I/O standard assignment to node \"ENET0_RX_COL\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_CRS " "Ignored I/O standard assignment to node \"ENET0_RX_CRS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Ignored I/O standard assignment to node \"ENET0_RX_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Ignored I/O standard assignment to node \"ENET0_RX_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Ignored I/O standard assignment to node \"ENET0_RX_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Ignored I/O standard assignment to node \"ENET0_RX_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DV " "Ignored I/O standard assignment to node \"ENET0_RX_DV\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_ER " "Ignored I/O standard assignment to node \"ENET0_RX_ER\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_CLK " "Ignored I/O standard assignment to node \"ENET0_TX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Ignored I/O standard assignment to node \"ENET0_TX_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Ignored I/O standard assignment to node \"ENET0_TX_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Ignored I/O standard assignment to node \"ENET0_TX_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Ignored I/O standard assignment to node \"ENET0_TX_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_EN " "Ignored I/O standard assignment to node \"ENET0_TX_EN\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_ER " "Ignored I/O standard assignment to node \"ENET0_TX_ER\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_GTX_CLK " "Ignored I/O standard assignment to node \"ENET1_GTX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_INT_N " "Ignored I/O standard assignment to node \"ENET1_INT_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_LINK100 " "Ignored I/O standard assignment to node \"ENET1_LINK100\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_MDC " "Ignored I/O standard assignment to node \"ENET1_MDC\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_MDIO " "Ignored I/O standard assignment to node \"ENET1_MDIO\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RST_N " "Ignored I/O standard assignment to node \"ENET1_RST_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_CLK " "Ignored I/O standard assignment to node \"ENET1_RX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_COL " "Ignored I/O standard assignment to node \"ENET1_RX_COL\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_CRS " "Ignored I/O standard assignment to node \"ENET1_RX_CRS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Ignored I/O standard assignment to node \"ENET1_RX_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Ignored I/O standard assignment to node \"ENET1_RX_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Ignored I/O standard assignment to node \"ENET1_RX_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Ignored I/O standard assignment to node \"ENET1_RX_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DV " "Ignored I/O standard assignment to node \"ENET1_RX_DV\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_ER " "Ignored I/O standard assignment to node \"ENET1_RX_ER\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_CLK " "Ignored I/O standard assignment to node \"ENET1_TX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Ignored I/O standard assignment to node \"ENET1_TX_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Ignored I/O standard assignment to node \"ENET1_TX_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Ignored I/O standard assignment to node \"ENET1_TX_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Ignored I/O standard assignment to node \"ENET1_TX_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_EN " "Ignored I/O standard assignment to node \"ENET1_TX_EN\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_ER " "Ignored I/O standard assignment to node \"ENET1_TX_ER\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENETCLK_25 " "Ignored I/O standard assignment to node \"ENETCLK_25\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[0\] " "Ignored I/O standard assignment to node \"EX_IO\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[1\] " "Ignored I/O standard assignment to node \"EX_IO\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[2\] " "Ignored I/O standard assignment to node \"EX_IO\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[3\] " "Ignored I/O standard assignment to node \"EX_IO\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[4\] " "Ignored I/O standard assignment to node \"EX_IO\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[5\] " "Ignored I/O standard assignment to node \"EX_IO\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[6\] " "Ignored I/O standard assignment to node \"EX_IO\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[0\] " "Ignored I/O standard assignment to node \"FL_ADDR\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[10\] " "Ignored I/O standard assignment to node \"FL_ADDR\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[11\] " "Ignored I/O standard assignment to node \"FL_ADDR\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[12\] " "Ignored I/O standard assignment to node \"FL_ADDR\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[13\] " "Ignored I/O standard assignment to node \"FL_ADDR\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[14\] " "Ignored I/O standard assignment to node \"FL_ADDR\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[15\] " "Ignored I/O standard assignment to node \"FL_ADDR\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[16\] " "Ignored I/O standard assignment to node \"FL_ADDR\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[17\] " "Ignored I/O standard assignment to node \"FL_ADDR\[17\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[18\] " "Ignored I/O standard assignment to node \"FL_ADDR\[18\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[19\] " "Ignored I/O standard assignment to node \"FL_ADDR\[19\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[1\] " "Ignored I/O standard assignment to node \"FL_ADDR\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[20\] " "Ignored I/O standard assignment to node \"FL_ADDR\[20\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[21\] " "Ignored I/O standard assignment to node \"FL_ADDR\[21\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[22\] " "Ignored I/O standard assignment to node \"FL_ADDR\[22\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[2\] " "Ignored I/O standard assignment to node \"FL_ADDR\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[3\] " "Ignored I/O standard assignment to node \"FL_ADDR\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[4\] " "Ignored I/O standard assignment to node \"FL_ADDR\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[5\] " "Ignored I/O standard assignment to node \"FL_ADDR\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[6\] " "Ignored I/O standard assignment to node \"FL_ADDR\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[7\] " "Ignored I/O standard assignment to node \"FL_ADDR\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[8\] " "Ignored I/O standard assignment to node \"FL_ADDR\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[9\] " "Ignored I/O standard assignment to node \"FL_ADDR\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_CE_N " "Ignored I/O standard assignment to node \"FL_CE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[0\] " "Ignored I/O standard assignment to node \"FL_DQ\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[1\] " "Ignored I/O standard assignment to node \"FL_DQ\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[2\] " "Ignored I/O standard assignment to node \"FL_DQ\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[3\] " "Ignored I/O standard assignment to node \"FL_DQ\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[4\] " "Ignored I/O standard assignment to node \"FL_DQ\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[5\] " "Ignored I/O standard assignment to node \"FL_DQ\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[6\] " "Ignored I/O standard assignment to node \"FL_DQ\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[7\] " "Ignored I/O standard assignment to node \"FL_DQ\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_OE_N " "Ignored I/O standard assignment to node \"FL_OE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_RST_N " "Ignored I/O standard assignment to node \"FL_RST_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_RY " "Ignored I/O standard assignment to node \"FL_RY\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_WE_N " "Ignored I/O standard assignment to node \"FL_WE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_WP_N " "Ignored I/O standard assignment to node \"FL_WP_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[0\] " "Ignored I/O standard assignment to node \"GPIO\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[10\] " "Ignored I/O standard assignment to node \"GPIO\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[11\] " "Ignored I/O standard assignment to node \"GPIO\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[12\] " "Ignored I/O standard assignment to node \"GPIO\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[13\] " "Ignored I/O standard assignment to node \"GPIO\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[14\] " "Ignored I/O standard assignment to node \"GPIO\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[15\] " "Ignored I/O standard assignment to node \"GPIO\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[16\] " "Ignored I/O standard assignment to node \"GPIO\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[17\] " "Ignored I/O standard assignment to node \"GPIO\[17\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[18\] " "Ignored I/O standard assignment to node \"GPIO\[18\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[19\] " "Ignored I/O standard assignment to node \"GPIO\[19\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[1\] " "Ignored I/O standard assignment to node \"GPIO\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[20\] " "Ignored I/O standard assignment to node \"GPIO\[20\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[21\] " "Ignored I/O standard assignment to node \"GPIO\[21\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[22\] " "Ignored I/O standard assignment to node \"GPIO\[22\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[23\] " "Ignored I/O standard assignment to node \"GPIO\[23\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[24\] " "Ignored I/O standard assignment to node \"GPIO\[24\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[25\] " "Ignored I/O standard assignment to node \"GPIO\[25\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[26\] " "Ignored I/O standard assignment to node \"GPIO\[26\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[27\] " "Ignored I/O standard assignment to node \"GPIO\[27\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[28\] " "Ignored I/O standard assignment to node \"GPIO\[28\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[29\] " "Ignored I/O standard assignment to node \"GPIO\[29\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[2\] " "Ignored I/O standard assignment to node \"GPIO\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[30\] " "Ignored I/O standard assignment to node \"GPIO\[30\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[31\] " "Ignored I/O standard assignment to node \"GPIO\[31\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[32\] " "Ignored I/O standard assignment to node \"GPIO\[32\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[33\] " "Ignored I/O standard assignment to node \"GPIO\[33\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[34\] " "Ignored I/O standard assignment to node \"GPIO\[34\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[35\] " "Ignored I/O standard assignment to node \"GPIO\[35\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[3\] " "Ignored I/O standard assignment to node \"GPIO\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[4\] " "Ignored I/O standard assignment to node \"GPIO\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[5\] " "Ignored I/O standard assignment to node \"GPIO\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[6\] " "Ignored I/O standard assignment to node \"GPIO\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[7\] " "Ignored I/O standard assignment to node \"GPIO\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[8\] " "Ignored I/O standard assignment to node \"GPIO\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[9\] " "Ignored I/O standard assignment to node \"GPIO\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN0 " "Ignored I/O standard assignment to node \"HSMC_CLKIN0\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN_N1 " "Ignored I/O standard assignment to node \"HSMC_CLKIN_N1\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN_N2 " "Ignored I/O standard assignment to node \"HSMC_CLKIN_N2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN_P1 " "Ignored I/O standard assignment to node \"HSMC_CLKIN_P1\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN_P2 " "Ignored I/O standard assignment to node \"HSMC_CLKIN_P2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT0 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT0\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT_N1 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT_N1\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT_N2 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT_N2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT_P1 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT_P1\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT_P2 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT_P2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_D\[0\] " "Ignored I/O standard assignment to node \"HSMC_D\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_D\[1\] " "Ignored I/O standard assignment to node \"HSMC_D\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_D\[2\] " "Ignored I/O standard assignment to node \"HSMC_D\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_D\[3\] " "Ignored I/O standard assignment to node \"HSMC_D\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "I2C_SCLK " "Ignored I/O standard assignment to node \"I2C_SCLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "I2C_SDAT " "Ignored I/O standard assignment to node \"I2C_SDAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "IRDA_RXD " "Ignored I/O standard assignment to node \"IRDA_RXD\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_EN " "Ignored I/O standard assignment to node \"LCD_EN\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LEDG\[8\] " "Ignored I/O standard assignment to node \"LEDG\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_ADDR\[0\] " "Ignored I/O standard assignment to node \"OTG_ADDR\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_ADDR\[1\] " "Ignored I/O standard assignment to node \"OTG_ADDR\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_CS_N " "Ignored I/O standard assignment to node \"OTG_CS_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DACK_N\[0\] " "Ignored I/O standard assignment to node \"OTG_DACK_N\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DACK_N\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DACK_N\[1\] " "Ignored I/O standard assignment to node \"OTG_DACK_N\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DACK_N\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[0\] " "Ignored I/O standard assignment to node \"OTG_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[10\] " "Ignored I/O standard assignment to node \"OTG_DATA\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[11\] " "Ignored I/O standard assignment to node \"OTG_DATA\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[12\] " "Ignored I/O standard assignment to node \"OTG_DATA\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[13\] " "Ignored I/O standard assignment to node \"OTG_DATA\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[14\] " "Ignored I/O standard assignment to node \"OTG_DATA\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[15\] " "Ignored I/O standard assignment to node \"OTG_DATA\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[1\] " "Ignored I/O standard assignment to node \"OTG_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[2\] " "Ignored I/O standard assignment to node \"OTG_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[3\] " "Ignored I/O standard assignment to node \"OTG_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[4\] " "Ignored I/O standard assignment to node \"OTG_DATA\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[5\] " "Ignored I/O standard assignment to node \"OTG_DATA\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[6\] " "Ignored I/O standard assignment to node \"OTG_DATA\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[7\] " "Ignored I/O standard assignment to node \"OTG_DATA\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[8\] " "Ignored I/O standard assignment to node \"OTG_DATA\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[9\] " "Ignored I/O standard assignment to node \"OTG_DATA\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DREQ\[0\] " "Ignored I/O standard assignment to node \"OTG_DREQ\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DREQ\[1\] " "Ignored I/O standard assignment to node \"OTG_DREQ\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_FSPEED " "Ignored I/O standard assignment to node \"OTG_FSPEED\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_FSPEED" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_INT\[0\] " "Ignored I/O standard assignment to node \"OTG_INT\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_INT\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_INT\[1\] " "Ignored I/O standard assignment to node \"OTG_INT\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_INT\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_LSPEED " "Ignored I/O standard assignment to node \"OTG_LSPEED\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_LSPEED" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_RD_N " "Ignored I/O standard assignment to node \"OTG_RD_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_RST_N " "Ignored I/O standard assignment to node \"OTG_RST_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_WR_N " "Ignored I/O standard assignment to node \"OTG_WR_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_CLK " "Ignored I/O standard assignment to node \"PS2_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_CLK2 " "Ignored I/O standard assignment to node \"PS2_CLK2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_DAT " "Ignored I/O standard assignment to node \"PS2_DAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_DAT2 " "Ignored I/O standard assignment to node \"PS2_DAT2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_CLK " "Ignored I/O standard assignment to node \"SD_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_CMD " "Ignored I/O standard assignment to node \"SD_CMD\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT\[0\] " "Ignored I/O standard assignment to node \"SD_DAT\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT\[1\] " "Ignored I/O standard assignment to node \"SD_DAT\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT\[2\] " "Ignored I/O standard assignment to node \"SD_DAT\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT\[3\] " "Ignored I/O standard assignment to node \"SD_DAT\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_WP_N " "Ignored I/O standard assignment to node \"SD_WP_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SMA_CLKIN " "Ignored I/O standard assignment to node \"SMA_CLKIN\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SMA_CLKOUT " "Ignored I/O standard assignment to node \"SMA_CLKOUT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[0\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[10\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[11\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[12\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[13\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[14\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[15\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[16\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[17\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[17\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[18\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[18\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[19\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[19\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[1\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[2\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[3\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[4\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[5\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[6\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[7\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[8\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[9\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_CE_N " "Ignored I/O standard assignment to node \"SRAM_CE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[0\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[10\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[11\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[12\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[13\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[14\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[15\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[1\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[2\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[3\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[4\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[5\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[6\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[7\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[8\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[9\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_LB_N " "Ignored I/O standard assignment to node \"SRAM_LB_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_OE_N " "Ignored I/O standard assignment to node \"SRAM_OE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_UB_N " "Ignored I/O standard assignment to node \"SRAM_UB_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_WE_N " "Ignored I/O standard assignment to node \"SRAM_WE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_CLK27 " "Ignored I/O standard assignment to node \"TD_CLK27\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[0\] " "Ignored I/O standard assignment to node \"TD_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[1\] " "Ignored I/O standard assignment to node \"TD_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[2\] " "Ignored I/O standard assignment to node \"TD_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[3\] " "Ignored I/O standard assignment to node \"TD_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[4\] " "Ignored I/O standard assignment to node \"TD_DATA\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[5\] " "Ignored I/O standard assignment to node \"TD_DATA\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[6\] " "Ignored I/O standard assignment to node \"TD_DATA\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[7\] " "Ignored I/O standard assignment to node \"TD_DATA\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_HS " "Ignored I/O standard assignment to node \"TD_HS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_RESET_N " "Ignored I/O standard assignment to node \"TD_RESET_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_VS " "Ignored I/O standard assignment to node \"TD_VS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_CTS " "Ignored I/O standard assignment to node \"UART_CTS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_RTS " "Ignored I/O standard assignment to node \"UART_RTS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_RXD " "Ignored I/O standard assignment to node \"UART_RXD\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_TXD " "Ignored I/O standard assignment to node \"UART_TXD\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_BLANK_N " "Ignored I/O standard assignment to node \"VGA_BLANK_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[0\] " "Ignored I/O standard assignment to node \"VGA_B\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[1\] " "Ignored I/O standard assignment to node \"VGA_B\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[2\] " "Ignored I/O standard assignment to node \"VGA_B\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[3\] " "Ignored I/O standard assignment to node \"VGA_B\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[4\] " "Ignored I/O standard assignment to node \"VGA_B\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[5\] " "Ignored I/O standard assignment to node \"VGA_B\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[6\] " "Ignored I/O standard assignment to node \"VGA_B\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[7\] " "Ignored I/O standard assignment to node \"VGA_B\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_CLK " "Ignored I/O standard assignment to node \"VGA_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[0\] " "Ignored I/O standard assignment to node \"VGA_G\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[1\] " "Ignored I/O standard assignment to node \"VGA_G\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[2\] " "Ignored I/O standard assignment to node \"VGA_G\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[3\] " "Ignored I/O standard assignment to node \"VGA_G\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[4\] " "Ignored I/O standard assignment to node \"VGA_G\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[5\] " "Ignored I/O standard assignment to node \"VGA_G\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[6\] " "Ignored I/O standard assignment to node \"VGA_G\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[7\] " "Ignored I/O standard assignment to node \"VGA_G\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_HS " "Ignored I/O standard assignment to node \"VGA_HS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[0\] " "Ignored I/O standard assignment to node \"VGA_R\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[1\] " "Ignored I/O standard assignment to node \"VGA_R\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[2\] " "Ignored I/O standard assignment to node \"VGA_R\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[3\] " "Ignored I/O standard assignment to node \"VGA_R\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[4\] " "Ignored I/O standard assignment to node \"VGA_R\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[5\] " "Ignored I/O standard assignment to node \"VGA_R\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[6\] " "Ignored I/O standard assignment to node \"VGA_R\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[7\] " "Ignored I/O standard assignment to node \"VGA_R\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_SYNC_N " "Ignored I/O standard assignment to node \"VGA_SYNC_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_VS " "Ignored I/O standard assignment to node \"VGA_VS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} } { } 0 15709 "Ignored I/O standard assignments to the following nodes" 0 0 "Fitter" 0 -1 1480609295298 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DACK_N\[0\] " "Node \"OTG_DACK_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DACK_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DACK_N\[1\] " "Node \"OTG_DACK_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DACK_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[1\] " "Node \"OTG_DREQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_FSPEED " "Node \"OTG_FSPEED\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_FSPEED" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT\[0\] " "Node \"OTG_INT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_INT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT\[1\] " "Node \"OTG_INT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_INT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_LSPEED " "Node \"OTG_LSPEED\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_LSPEED" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1480609295327 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:06 " "Fitter preparation operations ending: elapsed time is 00:00:06" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480609295357 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1480609302965 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Fitter placement preparation operations ending: elapsed time is 00:00:02" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480609304725 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1480609304769 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1480609307778 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480609307779 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1480609309715 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 " "Router estimated average interconnect usage is 2% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "22 X58_Y37 X68_Y48 " "Router estimated peak interconnect usage is 22% of the available device resources in the region that extends from location X58_Y37 to location X68_Y48" { } { { "loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 1 { 0 "Router estimated peak interconnect usage is 22% of the available device resources in the region that extends from location X58_Y37 to location X68_Y48"} { { 11 { 0 "Router estimated peak interconnect usage is 22% of the available device resources in the region that extends from location X58_Y37 to location X68_Y48"} 58 37 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1480609316983 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1480609316983 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Fitter routing operations ending: elapsed time is 00:00:04" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480609318123 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1480609318126 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1480609318126 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1480609318126 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.83 " "Total time spent on timing analysis during the Fitter is 0.83 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1480609318321 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480609318412 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480609319674 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480609319768 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480609320969 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480609322400 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1480609324348 ""} -{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "9 Cyclone IV E " "9 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[0\] 3.3-V LVTTL L3 " "Pin LCD_data\[0\] uses I/O standard 3.3-V LVTTL at L3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[0\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 352 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[1\] 3.3-V LVTTL L1 " "Pin LCD_data\[1\] uses I/O standard 3.3-V LVTTL at L1" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[1\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 353 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[2\] 3.3-V LVTTL L2 " "Pin LCD_data\[2\] uses I/O standard 3.3-V LVTTL at L2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[2\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 354 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[3\] 3.3-V LVTTL K7 " "Pin LCD_data\[3\] uses I/O standard 3.3-V LVTTL at K7" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[3\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 355 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[4\] 3.3-V LVTTL K1 " "Pin LCD_data\[4\] uses I/O standard 3.3-V LVTTL at K1" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[4\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 356 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[5\] 3.3-V LVTTL K2 " "Pin LCD_data\[5\] uses I/O standard 3.3-V LVTTL at K2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[5\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 357 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[6\] 3.3-V LVTTL M3 " "Pin LCD_data\[6\] uses I/O standard 3.3-V LVTTL at M3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[6\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 358 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[7\] 3.3-V LVTTL M5 " "Pin LCD_data\[7\] uses I/O standard 3.3-V LVTTL at M5" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[7\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 359 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL Y2 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at Y2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { CLOCK_50 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 5 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 360 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1480609324401 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.fit.smsg " "Generated suppressed messages file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1480609325076 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 830 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 830 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1010 " "Peak virtual memory: 1010 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1480609327596 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 01:22:07 2016 " "Processing ended: Fri Dec 02 01:22:07 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1480609327596 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:40 " "Elapsed time: 00:00:40" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1480609327596 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:37 " "Total CPU time (on all processors): 00:00:37" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1480609327596 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1480609327596 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1480609328752 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1480609328752 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 01:22:08 2016 " "Processing started: Fri Dec 02 01:22:08 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1480609328752 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1480609328752 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off lights -c lights " "Command: quartus_asm --read_settings_files=off --write_settings_files=off lights -c lights" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1480609328752 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1480609334141 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1480609334300 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "481 " "Peak virtual memory: 481 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1480609336088 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 01:22:16 2016 " "Processing ended: Fri Dec 02 01:22:16 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1480609336088 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1480609336088 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1480609336088 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1480609336088 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1480609336795 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1480609337278 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1480609337279 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 01:22:16 2016 " "Processing started: Fri Dec 02 01:22:16 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1480609337279 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1480609337279 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta lights -c lights " "Command: quartus_sta lights -c lights" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1480609337279 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1480609337369 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1480609337763 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1480609337763 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1480609337851 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1480609337851 ""} -{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\] " "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Quartus II" 0 -1 1480609338651 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "lights.sdc " "Synopsys Design Constraints File file not found: 'lights.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1480609338693 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1480609338703 "|lights|CLOCK_50"} -{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609339290 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609339290 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609339290 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1480609339290 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1480609339291 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1480609339369 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup 46.773 " "Worst-case setup slack is 46.773" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339398 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339398 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 46.773 0.000 altera_reserved_tck " " 46.773 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339398 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609339398 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.402 " "Worst-case hold slack is 0.402" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339405 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339405 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.402 0.000 altera_reserved_tck " " 0.402 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339405 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609339405 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 47.354 " "Worst-case recovery slack is 47.354" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 47.354 0.000 altera_reserved_tck " " 47.354 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339415 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609339415 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.459 " "Worst-case removal slack is 1.459" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339424 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339424 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.459 0.000 altera_reserved_tck " " 1.459 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339424 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609339424 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.549 " "Worst-case minimum pulse width slack is 49.549" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339433 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339433 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.549 0.000 altera_reserved_tck " " 49.549 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339433 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609339433 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 197.086 ns " "Worst Case Available Settling Time: 197.086 ns" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1480609339584 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1480609339634 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1480609341036 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1480609341383 "|lights|CLOCK_50"} -{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609341393 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609341393 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609341393 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1480609341393 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup 47.135 " "Worst-case setup slack is 47.135" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 47.135 0.000 altera_reserved_tck " " 47.135 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341447 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609341447 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.354 " "Worst-case hold slack is 0.354" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341634 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341634 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.354 0.000 altera_reserved_tck " " 0.354 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341634 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609341634 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 47.646 " "Worst-case recovery slack is 47.646" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341651 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341651 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 47.646 0.000 altera_reserved_tck " " 47.646 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341651 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609341651 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.333 " "Worst-case removal slack is 1.333" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341661 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341661 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.333 0.000 altera_reserved_tck " " 1.333 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341661 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609341661 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.477 " "Worst-case minimum pulse width slack is 49.477" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341670 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341670 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.477 0.000 altera_reserved_tck " " 49.477 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341670 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609341670 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 197.373 ns " "Worst Case Available Settling Time: 197.373 ns" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} -{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1480609341798 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1480609342233 "|lights|CLOCK_50"} -{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609342245 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609342245 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609342245 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1480609342245 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup 48.795 " "Worst-case setup slack is 48.795" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342295 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342295 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 48.795 0.000 altera_reserved_tck " " 48.795 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342295 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609342295 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.179 " "Worst-case hold slack is 0.179" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342310 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342310 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.179 0.000 altera_reserved_tck " " 0.179 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342310 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609342310 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 48.990 " "Worst-case recovery slack is 48.990" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342347 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342347 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 48.990 0.000 altera_reserved_tck " " 48.990 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342347 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609342347 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.677 " "Worst-case removal slack is 0.677" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342359 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342359 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.677 0.000 altera_reserved_tck " " 0.677 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342359 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609342359 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.299 " "Worst-case minimum pulse width slack is 49.299" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342403 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342403 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.299 0.000 altera_reserved_tck " " 49.299 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342403 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609342403 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 198.609 ns " "Worst Case Available Settling Time: 198.609 ns" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1480609344179 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1480609344179 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 17 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "603 " "Peak virtual memory: 603 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1480609344470 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 01:22:24 2016 " "Processing ended: Fri Dec 02 01:22:24 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1480609344470 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1480609344470 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1480609344470 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1480609344470 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 997 s " "Quartus II Full Compilation was successful. 0 errors, 997 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1480609345332 ""} diff --git a/db/scfifo_jr21.tdf b/db/scfifo_jr21.tdf deleted file mode 100644 index 3e1d114..0000000 --- a/db/scfifo_jr21.tdf +++ /dev/null @@ -1,53 +0,0 @@ ---scfifo DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=64 LPM_SHOWAHEAD="OFF" LPM_WIDTH=8 LPM_WIDTHU=6 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr clock data empty full q rdreq usedw wrreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=AUTO" RAM_BLOCK_TYPE="AUTO" ---VERSION_BEGIN 13.0 cbx_altdpram 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_fifo_common 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_scfifo 2013:06:12:18:03:43:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION a_dpfifo_q131 (aclr, clock, data[7..0], rreq, sclr, wreq) -RETURNS ( empty, full, q[7..0], usedw[5..0]); - ---synthesis_resources = lut 18 M9K 1 reg 20 -SUBDESIGN scfifo_jr21 -( - aclr : input; - clock : input; - data[7..0] : input; - empty : output; - full : output; - q[7..0] : output; - rdreq : input; - usedw[5..0] : output; - wrreq : input; -) -VARIABLE - dpfifo : a_dpfifo_q131; - sclr : NODE; - -BEGIN - dpfifo.aclr = aclr; - dpfifo.clock = clock; - dpfifo.data[] = data[]; - dpfifo.rreq = rdreq; - dpfifo.sclr = sclr; - dpfifo.wreq = wrreq; - empty = dpfifo.empty; - full = dpfifo.full; - q[] = dpfifo.q[]; - sclr = GND; - usedw[] = dpfifo.usedw[]; -END; ---VALID FILE diff --git a/incremental_db/README b/incremental_db/README deleted file mode 100644 index 6191fbe..0000000 --- a/incremental_db/README +++ /dev/null @@ -1,11 +0,0 @@ -This folder contains data for incremental compilation. - -The compiled_partitions sub-folder contains previous compilation results for each partition. -As long as this folder is preserved, incremental compilation results from earlier compiles -can be re-used. To perform a clean compilation from source files for all partitions, both -the db and incremental_db folder should be removed. - -The imported_partitions sub-folder contains the last imported QXP for each imported partition. -As long as this folder is preserved, imported partitions will be automatically re-imported -when the db or incremental_db/compiled_partitions folders are removed. - diff --git a/incremental_db/compiled_partitions/lights.autoh_e40e1.map.cdb b/incremental_db/compiled_partitions/lights.autoh_e40e1.map.cdb deleted file mode 100644 index 41f2979..0000000 --- a/incremental_db/compiled_partitions/lights.autoh_e40e1.map.cdb +++ /dev/null Binary files differ diff --git a/incremental_db/compiled_partitions/lights.autoh_e40e1.map.dpi b/incremental_db/compiled_partitions/lights.autoh_e40e1.map.dpi deleted file mode 100644 index 621683f..0000000 --- a/incremental_db/compiled_partitions/lights.autoh_e40e1.map.dpi +++ /dev/null Binary files differ diff --git a/incremental_db/compiled_partitions/lights.autoh_e40e1.map.hdb b/incremental_db/compiled_partitions/lights.autoh_e40e1.map.hdb deleted file mode 100644 index 7845a71..0000000 --- a/incremental_db/compiled_partitions/lights.autoh_e40e1.map.hdb +++ /dev/null Binary files differ diff --git a/incremental_db/compiled_partitions/lights.autoh_e40e1.map.kpt b/incremental_db/compiled_partitions/lights.autoh_e40e1.map.kpt deleted file mode 100644 index e797630..0000000 --- a/incremental_db/compiled_partitions/lights.autoh_e40e1.map.kpt +++ /dev/null Binary files differ diff --git a/incremental_db/compiled_partitions/lights.autoh_e40e1.map.logdb b/incremental_db/compiled_partitions/lights.autoh_e40e1.map.logdb deleted file mode 100644 index d45424f..0000000 --- a/incremental_db/compiled_partitions/lights.autoh_e40e1.map.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/incremental_db/compiled_partitions/lights.db_info b/incremental_db/compiled_partitions/lights.db_info deleted file mode 100644 index 7461abf..0000000 --- a/incremental_db/compiled_partitions/lights.db_info +++ /dev/null @@ -1,3 +0,0 @@ -Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition -Version_Index = 302049280 -Creation_Time = Thu Oct 20 11:14:55 2016 diff --git a/incremental_db/compiled_partitions/lights.root_partition.cmp.ammdb b/incremental_db/compiled_partitions/lights.root_partition.cmp.ammdb deleted file mode 100644 index 0f7344e..0000000 --- a/incremental_db/compiled_partitions/lights.root_partition.cmp.ammdb +++ /dev/null Binary files differ diff --git a/incremental_db/compiled_partitions/lights.root_partition.cmp.cdb b/incremental_db/compiled_partitions/lights.root_partition.cmp.cdb deleted file mode 100644 index 2825e6c..0000000 --- a/incremental_db/compiled_partitions/lights.root_partition.cmp.cdb +++ /dev/null Binary files differ diff --git a/incremental_db/compiled_partitions/lights.root_partition.cmp.dfp b/incremental_db/compiled_partitions/lights.root_partition.cmp.dfp deleted file mode 100644 index b1c67d6..0000000 --- a/incremental_db/compiled_partitions/lights.root_partition.cmp.dfp +++ /dev/null Binary files differ diff --git a/incremental_db/compiled_partitions/lights.root_partition.cmp.hdb b/incremental_db/compiled_partitions/lights.root_partition.cmp.hdb deleted file mode 100644 index 13d1bb1..0000000 --- a/incremental_db/compiled_partitions/lights.root_partition.cmp.hdb +++ /dev/null Binary files differ diff --git a/incremental_db/compiled_partitions/lights.root_partition.cmp.kpt b/incremental_db/compiled_partitions/lights.root_partition.cmp.kpt deleted file mode 100644 index 0d3ba5b..0000000 --- a/incremental_db/compiled_partitions/lights.root_partition.cmp.kpt +++ /dev/null Binary files differ diff --git a/incremental_db/compiled_partitions/lights.root_partition.cmp.logdb b/incremental_db/compiled_partitions/lights.root_partition.cmp.logdb deleted file mode 100644 index d45424f..0000000 --- a/incremental_db/compiled_partitions/lights.root_partition.cmp.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/incremental_db/compiled_partitions/lights.root_partition.cmp.rcfdb b/incremental_db/compiled_partitions/lights.root_partition.cmp.rcfdb deleted file mode 100644 index 0e23f08..0000000 --- a/incremental_db/compiled_partitions/lights.root_partition.cmp.rcfdb +++ /dev/null Binary files differ diff --git a/incremental_db/compiled_partitions/lights.root_partition.map.cdb b/incremental_db/compiled_partitions/lights.root_partition.map.cdb deleted file mode 100644 index 715b56d..0000000 --- a/incremental_db/compiled_partitions/lights.root_partition.map.cdb +++ /dev/null Binary files differ diff --git a/incremental_db/compiled_partitions/lights.root_partition.map.dpi b/incremental_db/compiled_partitions/lights.root_partition.map.dpi deleted file mode 100644 index 4fa1f93..0000000 --- a/incremental_db/compiled_partitions/lights.root_partition.map.dpi +++ /dev/null Binary files differ diff --git a/incremental_db/compiled_partitions/lights.root_partition.map.hbdb.cdb b/incremental_db/compiled_partitions/lights.root_partition.map.hbdb.cdb deleted file mode 100644 index ba9ddbf..0000000 --- a/incremental_db/compiled_partitions/lights.root_partition.map.hbdb.cdb +++ /dev/null Binary files differ diff --git a/incremental_db/compiled_partitions/lights.root_partition.map.hbdb.hb_info b/incremental_db/compiled_partitions/lights.root_partition.map.hbdb.hb_info deleted file mode 100644 index 8210c55..0000000 --- a/incremental_db/compiled_partitions/lights.root_partition.map.hbdb.hb_info +++ /dev/null Binary files differ diff --git a/incremental_db/compiled_partitions/lights.root_partition.map.hbdb.hdb b/incremental_db/compiled_partitions/lights.root_partition.map.hbdb.hdb deleted file mode 100644 index 2eacc54..0000000 --- a/incremental_db/compiled_partitions/lights.root_partition.map.hbdb.hdb +++ /dev/null Binary files differ diff --git a/incremental_db/compiled_partitions/lights.root_partition.map.hbdb.sig b/incremental_db/compiled_partitions/lights.root_partition.map.hbdb.sig deleted file mode 100644 index 6c0af65..0000000 --- a/incremental_db/compiled_partitions/lights.root_partition.map.hbdb.sig +++ /dev/null @@ -1 +0,0 @@ -c5eb7f6cdd530884c3b884e0a3668ea4 \ No newline at end of file diff --git a/incremental_db/compiled_partitions/lights.root_partition.map.hdb b/incremental_db/compiled_partitions/lights.root_partition.map.hdb deleted file mode 100644 index bd3d356..0000000 --- a/incremental_db/compiled_partitions/lights.root_partition.map.hdb +++ /dev/null Binary files differ diff --git a/incremental_db/compiled_partitions/lights.root_partition.map.kpt b/incremental_db/compiled_partitions/lights.root_partition.map.kpt deleted file mode 100644 index 9cf8527..0000000 --- a/incremental_db/compiled_partitions/lights.root_partition.map.kpt +++ /dev/null Binary files differ diff --git a/nios_system/synthesis/nios_system.qip b/nios_system/synthesis/nios_system.qip deleted file mode 100644 index 76e2e7b..0000000 --- a/nios_system/synthesis/nios_system.qip +++ /dev/null @@ -1,133 +0,0 @@ -set_global_assignment -entity "nios_system" -library "nios_system" -name IP_TOOL_NAME "Qsys" -set_global_assignment -entity "nios_system" -library "nios_system" -name IP_TOOL_VERSION "13.0sp1" -set_global_assignment -entity "nios_system" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -library "nios_system" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../nios_system.sopcinfo"] -set_instance_assignment -entity "nios_system" -library "nios_system" -name SLD_INFO "QSYS_NAME nios_system HAS_SOPCINFO 1 GENERATION_ID 1482368774" -set_global_assignment -library "nios_system" -name MISC_FILE [file join $::quartus(qip_path) "../../nios_system.cmp"] -set_global_assignment -name SYNTHESIS_ONLY_QIP ON -set_global_assignment -library "nios_system" -name MISC_FILE [file join $::quartus(qip_path) "../../nios_system.qsys"] - -set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "nios_system.v"] -set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_irq_mapper.sv"] -set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_arbitrator.sv"] -set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_rsp_xbar_mux_001.sv"] -set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_rsp_xbar_mux.sv"] -set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_rsp_xbar_demux_002.sv"] -set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_cmd_xbar_mux.sv"] -set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_cmd_xbar_demux_001.sv"] -set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_cmd_xbar_demux.sv"] -set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_reset_controller.v"] -set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_reset_synchronizer.v"] -set_global_assignment -library "nios_system" -name SDC_FILE [file join $::quartus(qip_path) "submodules/altera_reset_controller.sdc"] -set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_id_router_002.sv"] -set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_id_router.sv"] -set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_addr_router_001.sv"] -set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_addr_router.sv"] -set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_sc_fifo.v"] -set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_slave_agent.sv"] -set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_burst_uncompressor.sv"] -set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_master_agent.sv"] -set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_slave_translator.sv"] -set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_master_translator.sv"] -set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_lcd_on.v"] -set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_lcd_16207_0.v"] -set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_hex0.v"] -set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_push_switches.v"] -set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_switches.v"] -set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_LEDRs.v"] -set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_LEDs.v"] -set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_jtag_uart.v"] -set_global_assignment -library "nios_system" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/nios_system_onchip_memory.hex"] -set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_onchip_memory.v"] -set_global_assignment -library "nios_system" -name SDC_FILE [file join $::quartus(qip_path) "submodules/nios_system_nios2_processor.sdc"] -set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_nios2_processor.v"] -set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v"] -set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_nios2_processor_jtag_debug_module_tck.v"] -set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v"] -set_global_assignment -library "nios_system" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/nios_system_nios2_processor_ociram_default_contents.mif"] -set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_nios2_processor_oci_test_bench.v"] -set_global_assignment -library "nios_system" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/nios_system_nios2_processor_rf_ram_a.mif"] -set_global_assignment -library "nios_system" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/nios_system_nios2_processor_rf_ram_b.mif"] -set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_nios2_processor_test_bench.v"] - -set_global_assignment -entity "nios_system_irq_mapper" -library "nios_system" -name IP_TOOL_NAME "altera_irq_mapper" -set_global_assignment -entity "nios_system_irq_mapper" -library "nios_system" -name IP_TOOL_VERSION "13.0" -set_global_assignment -entity "nios_system_irq_mapper" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "nios_system_rsp_xbar_mux_001" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_multiplexer" -set_global_assignment -entity "nios_system_rsp_xbar_mux_001" -library "nios_system" -name IP_TOOL_VERSION "13.0" -set_global_assignment -entity "nios_system_rsp_xbar_mux_001" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "nios_system_rsp_xbar_mux" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_multiplexer" -set_global_assignment -entity "nios_system_rsp_xbar_mux" -library "nios_system" -name IP_TOOL_VERSION "13.0" -set_global_assignment -entity "nios_system_rsp_xbar_mux" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "nios_system_rsp_xbar_demux_002" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_demultiplexer" -set_global_assignment -entity "nios_system_rsp_xbar_demux_002" -library "nios_system" -name IP_TOOL_VERSION "13.0" -set_global_assignment -entity "nios_system_rsp_xbar_demux_002" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "nios_system_cmd_xbar_mux" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_multiplexer" -set_global_assignment -entity "nios_system_cmd_xbar_mux" -library "nios_system" -name IP_TOOL_VERSION "13.0" -set_global_assignment -entity "nios_system_cmd_xbar_mux" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "nios_system_cmd_xbar_demux_001" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_demultiplexer" -set_global_assignment -entity "nios_system_cmd_xbar_demux_001" -library "nios_system" -name IP_TOOL_VERSION "13.0" -set_global_assignment -entity "nios_system_cmd_xbar_demux_001" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "nios_system_cmd_xbar_demux" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_demultiplexer" -set_global_assignment -entity "nios_system_cmd_xbar_demux" -library "nios_system" -name IP_TOOL_VERSION "13.0" -set_global_assignment -entity "nios_system_cmd_xbar_demux" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "altera_reset_controller" -library "nios_system" -name IP_TOOL_NAME "altera_reset_controller" -set_global_assignment -entity "altera_reset_controller" -library "nios_system" -name IP_TOOL_VERSION "13.0" -set_global_assignment -entity "altera_reset_controller" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "nios_system_id_router_002" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_router" -set_global_assignment -entity "nios_system_id_router_002" -library "nios_system" -name IP_TOOL_VERSION "13.0" -set_global_assignment -entity "nios_system_id_router_002" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "nios_system_id_router" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_router" -set_global_assignment -entity "nios_system_id_router" -library "nios_system" -name IP_TOOL_VERSION "13.0" -set_global_assignment -entity "nios_system_id_router" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "nios_system_addr_router_001" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_router" -set_global_assignment -entity "nios_system_addr_router_001" -library "nios_system" -name IP_TOOL_VERSION "13.0" -set_global_assignment -entity "nios_system_addr_router_001" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "nios_system_addr_router" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_router" -set_global_assignment -entity "nios_system_addr_router" -library "nios_system" -name IP_TOOL_VERSION "13.0" -set_global_assignment -entity "nios_system_addr_router" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "altera_avalon_sc_fifo" -library "nios_system" -name IP_TOOL_NAME "altera_avalon_sc_fifo" -set_global_assignment -entity "altera_avalon_sc_fifo" -library "nios_system" -name IP_TOOL_VERSION "13.0" -set_global_assignment -entity "altera_avalon_sc_fifo" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "altera_merlin_slave_agent" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_slave_agent" -set_global_assignment -entity "altera_merlin_slave_agent" -library "nios_system" -name IP_TOOL_VERSION "13.0" -set_global_assignment -entity "altera_merlin_slave_agent" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "altera_merlin_master_agent" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_master_agent" -set_global_assignment -entity "altera_merlin_master_agent" -library "nios_system" -name IP_TOOL_VERSION "13.0" -set_global_assignment -entity "altera_merlin_master_agent" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "altera_merlin_slave_translator" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_slave_translator" -set_global_assignment -entity "altera_merlin_slave_translator" -library "nios_system" -name IP_TOOL_VERSION "13.0" -set_global_assignment -entity "altera_merlin_slave_translator" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "altera_merlin_master_translator" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_master_translator" -set_global_assignment -entity "altera_merlin_master_translator" -library "nios_system" -name IP_TOOL_VERSION "13.0" -set_global_assignment -entity "altera_merlin_master_translator" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "nios_system_lcd_on" -library "nios_system" -name IP_TOOL_NAME "altera_avalon_pio" -set_global_assignment -entity "nios_system_lcd_on" -library "nios_system" -name IP_TOOL_VERSION "13.0.1.99.2" -set_global_assignment -entity "nios_system_lcd_on" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "nios_system_lcd_16207_0" -library "nios_system" -name IP_TOOL_NAME "altera_avalon_lcd_16207" -set_global_assignment -entity "nios_system_lcd_16207_0" -library "nios_system" -name IP_TOOL_VERSION "13.0.1.99.2" -set_global_assignment -entity "nios_system_lcd_16207_0" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "nios_system_hex0" -library "nios_system" -name IP_TOOL_NAME "altera_avalon_pio" -set_global_assignment -entity "nios_system_hex0" -library "nios_system" -name IP_TOOL_VERSION "13.0.1.99.2" -set_global_assignment -entity "nios_system_hex0" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "nios_system_push_switches" -library "nios_system" -name IP_TOOL_NAME "altera_avalon_pio" -set_global_assignment -entity "nios_system_push_switches" -library "nios_system" -name IP_TOOL_VERSION "13.0.1.99.2" -set_global_assignment -entity "nios_system_push_switches" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "nios_system_switches" -library "nios_system" -name IP_TOOL_NAME "altera_avalon_pio" -set_global_assignment -entity "nios_system_switches" -library "nios_system" -name IP_TOOL_VERSION "13.0.1.99.2" -set_global_assignment -entity "nios_system_switches" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "nios_system_LEDRs" -library "nios_system" -name IP_TOOL_NAME "altera_avalon_pio" -set_global_assignment -entity "nios_system_LEDRs" -library "nios_system" -name IP_TOOL_VERSION "13.0.1.99.2" -set_global_assignment -entity "nios_system_LEDRs" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "nios_system_LEDs" -library "nios_system" -name IP_TOOL_NAME "altera_avalon_pio" -set_global_assignment -entity "nios_system_LEDs" -library "nios_system" -name IP_TOOL_VERSION "13.0.1.99.2" -set_global_assignment -entity "nios_system_LEDs" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "nios_system_jtag_uart" -library "nios_system" -name IP_TOOL_NAME "altera_avalon_jtag_uart" -set_global_assignment -entity "nios_system_jtag_uart" -library "nios_system" -name IP_TOOL_VERSION "13.0.1.99.2" -set_global_assignment -entity "nios_system_jtag_uart" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "nios_system_onchip_memory" -library "nios_system" -name IP_TOOL_NAME "altera_avalon_onchip_memory2" -set_global_assignment -entity "nios_system_onchip_memory" -library "nios_system" -name IP_TOOL_VERSION "13.0.1.99.2" -set_global_assignment -entity "nios_system_onchip_memory" -library "nios_system" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "nios_system_nios2_processor" -library "nios_system" -name IP_TOOL_NAME "altera_nios2_qsys" -set_global_assignment -entity "nios_system_nios2_processor" -library "nios_system" -name IP_TOOL_VERSION "13.0" -set_global_assignment -entity "nios_system_nios2_processor" -library "nios_system" -name IP_TOOL_ENV "Qsys" diff --git a/nios_system/synthesis/nios_system.v b/nios_system/synthesis/nios_system.v deleted file mode 100644 index 4626fed..0000000 --- a/nios_system/synthesis/nios_system.v +++ /dev/null @@ -1,5964 +0,0 @@ -// nios_system.v - -// Generated using ACDS version 13.0sp1 232 at 2016.12.22.10:06:19 - -`timescale 1 ps / 1 ps -module nios_system ( - input wire clk_clk, // clk.clk - output wire [7:0] leds_export, // leds.export - input wire reset_reset_n, // reset.reset_n - output wire [17:0] ledrs_export, // ledrs.export - input wire [17:0] switches_export, // switches.export - input wire [2:0] push_switches_export, // push_switches.export - output wire [6:0] hex0_export, // hex0.export - output wire [6:0] hex1_export, // hex1.export - output wire [6:0] hex2_export, // hex2.export - output wire [6:0] hex3_export, // hex3.export - output wire [6:0] hex4_export, // hex4.export - output wire [6:0] hex5_export, // hex5.export - output wire [6:0] hex6_export, // hex6.export - output wire [6:0] hex7_export, // hex7.export - output wire lcd_16207_0_RS, // lcd_16207_0.RS - output wire lcd_16207_0_RW, // .RW - inout wire [7:0] lcd_16207_0_data, // .data - output wire lcd_16207_0_E, // .E - output wire lcd_on_export, // lcd_on.export - output wire lcd_blon_export // lcd_blon.export - ); - - wire nios2_processor_instruction_master_waitrequest; // nios2_processor_instruction_master_translator:av_waitrequest -> nios2_processor:i_waitrequest - wire [18:0] nios2_processor_instruction_master_address; // nios2_processor:i_address -> nios2_processor_instruction_master_translator:av_address - wire nios2_processor_instruction_master_read; // nios2_processor:i_read -> nios2_processor_instruction_master_translator:av_read - wire [31:0] nios2_processor_instruction_master_readdata; // nios2_processor_instruction_master_translator:av_readdata -> nios2_processor:i_readdata - wire nios2_processor_data_master_waitrequest; // nios2_processor_data_master_translator:av_waitrequest -> nios2_processor:d_waitrequest - wire [31:0] nios2_processor_data_master_writedata; // nios2_processor:d_writedata -> nios2_processor_data_master_translator:av_writedata - wire [18:0] nios2_processor_data_master_address; // nios2_processor:d_address -> nios2_processor_data_master_translator:av_address - wire nios2_processor_data_master_write; // nios2_processor:d_write -> nios2_processor_data_master_translator:av_write - wire nios2_processor_data_master_read; // nios2_processor:d_read -> nios2_processor_data_master_translator:av_read - wire [31:0] nios2_processor_data_master_readdata; // nios2_processor_data_master_translator:av_readdata -> nios2_processor:d_readdata - wire nios2_processor_data_master_debugaccess; // nios2_processor:jtag_debug_module_debugaccess_to_roms -> nios2_processor_data_master_translator:av_debugaccess - wire [3:0] nios2_processor_data_master_byteenable; // nios2_processor:d_byteenable -> nios2_processor_data_master_translator:av_byteenable - wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest; // nios2_processor:jtag_debug_module_waitrequest -> nios2_processor_jtag_debug_module_translator:av_waitrequest - wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_writedata; // nios2_processor_jtag_debug_module_translator:av_writedata -> nios2_processor:jtag_debug_module_writedata - wire [8:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_address; // nios2_processor_jtag_debug_module_translator:av_address -> nios2_processor:jtag_debug_module_address - wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_write; // nios2_processor_jtag_debug_module_translator:av_write -> nios2_processor:jtag_debug_module_write - wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_read; // nios2_processor_jtag_debug_module_translator:av_read -> nios2_processor:jtag_debug_module_read - wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_readdata; // nios2_processor:jtag_debug_module_readdata -> nios2_processor_jtag_debug_module_translator:av_readdata - wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess; // nios2_processor_jtag_debug_module_translator:av_debugaccess -> nios2_processor:jtag_debug_module_debugaccess - wire [3:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_byteenable; // nios2_processor_jtag_debug_module_translator:av_byteenable -> nios2_processor:jtag_debug_module_byteenable - wire [31:0] onchip_memory_s1_translator_avalon_anti_slave_0_writedata; // onchip_memory_s1_translator:av_writedata -> onchip_memory:writedata - wire [15:0] onchip_memory_s1_translator_avalon_anti_slave_0_address; // onchip_memory_s1_translator:av_address -> onchip_memory:address - wire onchip_memory_s1_translator_avalon_anti_slave_0_chipselect; // onchip_memory_s1_translator:av_chipselect -> onchip_memory:chipselect - wire onchip_memory_s1_translator_avalon_anti_slave_0_clken; // onchip_memory_s1_translator:av_clken -> onchip_memory:clken - wire onchip_memory_s1_translator_avalon_anti_slave_0_write; // onchip_memory_s1_translator:av_write -> onchip_memory:write - wire [31:0] onchip_memory_s1_translator_avalon_anti_slave_0_readdata; // onchip_memory:readdata -> onchip_memory_s1_translator:av_readdata - wire [3:0] onchip_memory_s1_translator_avalon_anti_slave_0_byteenable; // onchip_memory_s1_translator:av_byteenable -> onchip_memory:byteenable - wire [31:0] leds_s1_translator_avalon_anti_slave_0_writedata; // LEDs_s1_translator:av_writedata -> LEDs:writedata - wire [1:0] leds_s1_translator_avalon_anti_slave_0_address; // LEDs_s1_translator:av_address -> LEDs:address - wire leds_s1_translator_avalon_anti_slave_0_chipselect; // LEDs_s1_translator:av_chipselect -> LEDs:chipselect - wire leds_s1_translator_avalon_anti_slave_0_write; // LEDs_s1_translator:av_write -> LEDs:write_n - wire [31:0] leds_s1_translator_avalon_anti_slave_0_readdata; // LEDs:readdata -> LEDs_s1_translator:av_readdata - wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest; // jtag_uart:av_waitrequest -> jtag_uart_avalon_jtag_slave_translator:av_waitrequest - wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata; // jtag_uart_avalon_jtag_slave_translator:av_writedata -> jtag_uart:av_writedata - wire [0:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_address; // jtag_uart_avalon_jtag_slave_translator:av_address -> jtag_uart:av_address - wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect; // jtag_uart_avalon_jtag_slave_translator:av_chipselect -> jtag_uart:av_chipselect - wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_write; // jtag_uart_avalon_jtag_slave_translator:av_write -> jtag_uart:av_write_n - wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_read; // jtag_uart_avalon_jtag_slave_translator:av_read -> jtag_uart:av_read_n - wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata; // jtag_uart:av_readdata -> jtag_uart_avalon_jtag_slave_translator:av_readdata - wire [31:0] ledrs_s1_translator_avalon_anti_slave_0_writedata; // LEDRs_s1_translator:av_writedata -> LEDRs:writedata - wire [1:0] ledrs_s1_translator_avalon_anti_slave_0_address; // LEDRs_s1_translator:av_address -> LEDRs:address - wire ledrs_s1_translator_avalon_anti_slave_0_chipselect; // LEDRs_s1_translator:av_chipselect -> LEDRs:chipselect - wire ledrs_s1_translator_avalon_anti_slave_0_write; // LEDRs_s1_translator:av_write -> LEDRs:write_n - wire [31:0] ledrs_s1_translator_avalon_anti_slave_0_readdata; // LEDRs:readdata -> LEDRs_s1_translator:av_readdata - wire [1:0] switches_s1_translator_avalon_anti_slave_0_address; // switches_s1_translator:av_address -> switches:address - wire [31:0] switches_s1_translator_avalon_anti_slave_0_readdata; // switches:readdata -> switches_s1_translator:av_readdata - wire [1:0] push_switches_s1_translator_avalon_anti_slave_0_address; // push_switches_s1_translator:av_address -> push_switches:address - wire [31:0] push_switches_s1_translator_avalon_anti_slave_0_readdata; // push_switches:readdata -> push_switches_s1_translator:av_readdata - wire [31:0] hex0_s1_translator_avalon_anti_slave_0_writedata; // hex0_s1_translator:av_writedata -> hex0:writedata - wire [1:0] hex0_s1_translator_avalon_anti_slave_0_address; // hex0_s1_translator:av_address -> hex0:address - wire hex0_s1_translator_avalon_anti_slave_0_chipselect; // hex0_s1_translator:av_chipselect -> hex0:chipselect - wire hex0_s1_translator_avalon_anti_slave_0_write; // hex0_s1_translator:av_write -> hex0:write_n - wire [31:0] hex0_s1_translator_avalon_anti_slave_0_readdata; // hex0:readdata -> hex0_s1_translator:av_readdata - wire [31:0] hex1_s1_translator_avalon_anti_slave_0_writedata; // hex1_s1_translator:av_writedata -> hex1:writedata - wire [1:0] hex1_s1_translator_avalon_anti_slave_0_address; // hex1_s1_translator:av_address -> hex1:address - wire hex1_s1_translator_avalon_anti_slave_0_chipselect; // hex1_s1_translator:av_chipselect -> hex1:chipselect - wire hex1_s1_translator_avalon_anti_slave_0_write; // hex1_s1_translator:av_write -> hex1:write_n - wire [31:0] hex1_s1_translator_avalon_anti_slave_0_readdata; // hex1:readdata -> hex1_s1_translator:av_readdata - wire [31:0] hex2_s1_translator_avalon_anti_slave_0_writedata; // hex2_s1_translator:av_writedata -> hex2:writedata - wire [1:0] hex2_s1_translator_avalon_anti_slave_0_address; // hex2_s1_translator:av_address -> hex2:address - wire hex2_s1_translator_avalon_anti_slave_0_chipselect; // hex2_s1_translator:av_chipselect -> hex2:chipselect - wire hex2_s1_translator_avalon_anti_slave_0_write; // hex2_s1_translator:av_write -> hex2:write_n - wire [31:0] hex2_s1_translator_avalon_anti_slave_0_readdata; // hex2:readdata -> hex2_s1_translator:av_readdata - wire [31:0] hex3_s1_translator_avalon_anti_slave_0_writedata; // hex3_s1_translator:av_writedata -> hex3:writedata - wire [1:0] hex3_s1_translator_avalon_anti_slave_0_address; // hex3_s1_translator:av_address -> hex3:address - wire hex3_s1_translator_avalon_anti_slave_0_chipselect; // hex3_s1_translator:av_chipselect -> hex3:chipselect - wire hex3_s1_translator_avalon_anti_slave_0_write; // hex3_s1_translator:av_write -> hex3:write_n - wire [31:0] hex3_s1_translator_avalon_anti_slave_0_readdata; // hex3:readdata -> hex3_s1_translator:av_readdata - wire [31:0] hex4_s1_translator_avalon_anti_slave_0_writedata; // hex4_s1_translator:av_writedata -> hex4:writedata - wire [1:0] hex4_s1_translator_avalon_anti_slave_0_address; // hex4_s1_translator:av_address -> hex4:address - wire hex4_s1_translator_avalon_anti_slave_0_chipselect; // hex4_s1_translator:av_chipselect -> hex4:chipselect - wire hex4_s1_translator_avalon_anti_slave_0_write; // hex4_s1_translator:av_write -> hex4:write_n - wire [31:0] hex4_s1_translator_avalon_anti_slave_0_readdata; // hex4:readdata -> hex4_s1_translator:av_readdata - wire [31:0] hex5_s1_translator_avalon_anti_slave_0_writedata; // hex5_s1_translator:av_writedata -> hex5:writedata - wire [1:0] hex5_s1_translator_avalon_anti_slave_0_address; // hex5_s1_translator:av_address -> hex5:address - wire hex5_s1_translator_avalon_anti_slave_0_chipselect; // hex5_s1_translator:av_chipselect -> hex5:chipselect - wire hex5_s1_translator_avalon_anti_slave_0_write; // hex5_s1_translator:av_write -> hex5:write_n - wire [31:0] hex5_s1_translator_avalon_anti_slave_0_readdata; // hex5:readdata -> hex5_s1_translator:av_readdata - wire [31:0] hex6_s1_translator_avalon_anti_slave_0_writedata; // hex6_s1_translator:av_writedata -> hex6:writedata - wire [1:0] hex6_s1_translator_avalon_anti_slave_0_address; // hex6_s1_translator:av_address -> hex6:address - wire hex6_s1_translator_avalon_anti_slave_0_chipselect; // hex6_s1_translator:av_chipselect -> hex6:chipselect - wire hex6_s1_translator_avalon_anti_slave_0_write; // hex6_s1_translator:av_write -> hex6:write_n - wire [31:0] hex6_s1_translator_avalon_anti_slave_0_readdata; // hex6:readdata -> hex6_s1_translator:av_readdata - wire [31:0] hex7_s1_translator_avalon_anti_slave_0_writedata; // hex7_s1_translator:av_writedata -> hex7:writedata - wire [1:0] hex7_s1_translator_avalon_anti_slave_0_address; // hex7_s1_translator:av_address -> hex7:address - wire hex7_s1_translator_avalon_anti_slave_0_chipselect; // hex7_s1_translator:av_chipselect -> hex7:chipselect - wire hex7_s1_translator_avalon_anti_slave_0_write; // hex7_s1_translator:av_write -> hex7:write_n - wire [31:0] hex7_s1_translator_avalon_anti_slave_0_readdata; // hex7:readdata -> hex7_s1_translator:av_readdata - wire [7:0] lcd_16207_0_control_slave_translator_avalon_anti_slave_0_writedata; // lcd_16207_0_control_slave_translator:av_writedata -> lcd_16207_0:writedata - wire [1:0] lcd_16207_0_control_slave_translator_avalon_anti_slave_0_address; // lcd_16207_0_control_slave_translator:av_address -> lcd_16207_0:address - wire lcd_16207_0_control_slave_translator_avalon_anti_slave_0_write; // lcd_16207_0_control_slave_translator:av_write -> lcd_16207_0:write - wire lcd_16207_0_control_slave_translator_avalon_anti_slave_0_read; // lcd_16207_0_control_slave_translator:av_read -> lcd_16207_0:read - wire [7:0] lcd_16207_0_control_slave_translator_avalon_anti_slave_0_readdata; // lcd_16207_0:readdata -> lcd_16207_0_control_slave_translator:av_readdata - wire lcd_16207_0_control_slave_translator_avalon_anti_slave_0_begintransfer; // lcd_16207_0_control_slave_translator:av_begintransfer -> lcd_16207_0:begintransfer - wire [31:0] lcd_on_s1_translator_avalon_anti_slave_0_writedata; // lcd_on_s1_translator:av_writedata -> lcd_on:writedata - wire [1:0] lcd_on_s1_translator_avalon_anti_slave_0_address; // lcd_on_s1_translator:av_address -> lcd_on:address - wire lcd_on_s1_translator_avalon_anti_slave_0_chipselect; // lcd_on_s1_translator:av_chipselect -> lcd_on:chipselect - wire lcd_on_s1_translator_avalon_anti_slave_0_write; // lcd_on_s1_translator:av_write -> lcd_on:write_n - wire [31:0] lcd_on_s1_translator_avalon_anti_slave_0_readdata; // lcd_on:readdata -> lcd_on_s1_translator:av_readdata - wire [31:0] lcd_blon_s1_translator_avalon_anti_slave_0_writedata; // lcd_blon_s1_translator:av_writedata -> lcd_blon:writedata - wire [1:0] lcd_blon_s1_translator_avalon_anti_slave_0_address; // lcd_blon_s1_translator:av_address -> lcd_blon:address - wire lcd_blon_s1_translator_avalon_anti_slave_0_chipselect; // lcd_blon_s1_translator:av_chipselect -> lcd_blon:chipselect - wire lcd_blon_s1_translator_avalon_anti_slave_0_write; // lcd_blon_s1_translator:av_write -> lcd_blon:write_n - wire [31:0] lcd_blon_s1_translator_avalon_anti_slave_0_readdata; // lcd_blon:readdata -> lcd_blon_s1_translator:av_readdata - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_processor_instruction_master_translator:uav_waitrequest - wire [2:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_processor_instruction_master_translator:uav_burstcount -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount - wire [31:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_processor_instruction_master_translator:uav_writedata -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_writedata - wire [18:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_address; // nios2_processor_instruction_master_translator:uav_address -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_address - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_lock; // nios2_processor_instruction_master_translator:uav_lock -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_lock - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_write; // nios2_processor_instruction_master_translator:uav_write -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_write - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_read; // nios2_processor_instruction_master_translator:uav_read -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_read - wire [31:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_processor_instruction_master_translator:uav_readdata - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_processor_instruction_master_translator:uav_debugaccess -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess - wire [3:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_processor_instruction_master_translator:uav_byteenable -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_processor_instruction_master_translator:uav_readdatavalid - wire nios2_processor_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_processor_data_master_translator:uav_waitrequest - wire [2:0] nios2_processor_data_master_translator_avalon_universal_master_0_burstcount; // nios2_processor_data_master_translator:uav_burstcount -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_burstcount - wire [31:0] nios2_processor_data_master_translator_avalon_universal_master_0_writedata; // nios2_processor_data_master_translator:uav_writedata -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_writedata - wire [18:0] nios2_processor_data_master_translator_avalon_universal_master_0_address; // nios2_processor_data_master_translator:uav_address -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_address - wire nios2_processor_data_master_translator_avalon_universal_master_0_lock; // nios2_processor_data_master_translator:uav_lock -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_lock - wire nios2_processor_data_master_translator_avalon_universal_master_0_write; // nios2_processor_data_master_translator:uav_write -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_write - wire nios2_processor_data_master_translator_avalon_universal_master_0_read; // nios2_processor_data_master_translator:uav_read -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_read - wire [31:0] nios2_processor_data_master_translator_avalon_universal_master_0_readdata; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_processor_data_master_translator:uav_readdata - wire nios2_processor_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_processor_data_master_translator:uav_debugaccess -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_debugaccess - wire [3:0] nios2_processor_data_master_translator_avalon_universal_master_0_byteenable; // nios2_processor_data_master_translator:uav_byteenable -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_byteenable - wire nios2_processor_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_processor_data_master_translator:uav_readdatavalid - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest; // nios2_processor_jtag_debug_module_translator:uav_waitrequest -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> nios2_processor_jtag_debug_module_translator:uav_burstcount - wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> nios2_processor_jtag_debug_module_translator:uav_writedata - wire [18:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> nios2_processor_jtag_debug_module_translator:uav_address - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> nios2_processor_jtag_debug_module_translator:uav_write - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> nios2_processor_jtag_debug_module_translator:uav_lock - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> nios2_processor_jtag_debug_module_translator:uav_read - wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata; // nios2_processor_jtag_debug_module_translator:uav_readdata -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // nios2_processor_jtag_debug_module_translator:uav_readdatavalid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> nios2_processor_jtag_debug_module_translator:uav_debugaccess - wire [3:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> nios2_processor_jtag_debug_module_translator:uav_byteenable - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // onchip_memory_s1_translator:uav_waitrequest -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory_s1_translator:uav_burstcount - wire [31:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory_s1_translator:uav_writedata - wire [18:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory_s1_translator:uav_address - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory_s1_translator:uav_write - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory_s1_translator:uav_lock - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory_s1_translator:uav_read - wire [31:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // onchip_memory_s1_translator:uav_readdata -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // onchip_memory_s1_translator:uav_readdatavalid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory_s1_translator:uav_debugaccess - wire [3:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory_s1_translator:uav_byteenable - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // LEDs_s1_translator:uav_waitrequest -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> LEDs_s1_translator:uav_burstcount - wire [31:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> LEDs_s1_translator:uav_writedata - wire [18:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_address; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_address -> LEDs_s1_translator:uav_address - wire leds_s1_translator_avalon_universal_slave_0_agent_m0_write; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_write -> LEDs_s1_translator:uav_write - wire leds_s1_translator_avalon_universal_slave_0_agent_m0_lock; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_lock -> LEDs_s1_translator:uav_lock - wire leds_s1_translator_avalon_universal_slave_0_agent_m0_read; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_read -> LEDs_s1_translator:uav_read - wire [31:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // LEDs_s1_translator:uav_readdata -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // LEDs_s1_translator:uav_readdatavalid -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> LEDs_s1_translator:uav_debugaccess - wire [3:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> LEDs_s1_translator:uav_byteenable - wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount - wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata - wire [18:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read - wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess - wire [3:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // LEDRs_s1_translator:uav_waitrequest -> LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> LEDRs_s1_translator:uav_burstcount - wire [31:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> LEDRs_s1_translator:uav_writedata - wire [18:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_address; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_address -> LEDRs_s1_translator:uav_address - wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_write; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_write -> LEDRs_s1_translator:uav_write - wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_lock; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_lock -> LEDRs_s1_translator:uav_lock - wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_read; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_read -> LEDRs_s1_translator:uav_read - wire [31:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // LEDRs_s1_translator:uav_readdata -> LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // LEDRs_s1_translator:uav_readdatavalid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> LEDRs_s1_translator:uav_debugaccess - wire [3:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> LEDRs_s1_translator:uav_byteenable - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // switches_s1_translator:uav_waitrequest -> switches_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // switches_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> switches_s1_translator:uav_burstcount - wire [31:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // switches_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> switches_s1_translator:uav_writedata - wire [18:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_address; // switches_s1_translator_avalon_universal_slave_0_agent:m0_address -> switches_s1_translator:uav_address - wire switches_s1_translator_avalon_universal_slave_0_agent_m0_write; // switches_s1_translator_avalon_universal_slave_0_agent:m0_write -> switches_s1_translator:uav_write - wire switches_s1_translator_avalon_universal_slave_0_agent_m0_lock; // switches_s1_translator_avalon_universal_slave_0_agent:m0_lock -> switches_s1_translator:uav_lock - wire switches_s1_translator_avalon_universal_slave_0_agent_m0_read; // switches_s1_translator_avalon_universal_slave_0_agent:m0_read -> switches_s1_translator:uav_read - wire [31:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // switches_s1_translator:uav_readdata -> switches_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // switches_s1_translator:uav_readdatavalid -> switches_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // switches_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> switches_s1_translator:uav_debugaccess - wire [3:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // switches_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> switches_s1_translator:uav_byteenable - wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // push_switches_s1_translator:uav_waitrequest -> push_switches_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> push_switches_s1_translator:uav_burstcount - wire [31:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> push_switches_s1_translator:uav_writedata - wire [18:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_address; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_address -> push_switches_s1_translator:uav_address - wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_write; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_write -> push_switches_s1_translator:uav_write - wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_lock; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_lock -> push_switches_s1_translator:uav_lock - wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_read; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_read -> push_switches_s1_translator:uav_read - wire [31:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // push_switches_s1_translator:uav_readdata -> push_switches_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // push_switches_s1_translator:uav_readdatavalid -> push_switches_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> push_switches_s1_translator:uav_debugaccess - wire [3:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> push_switches_s1_translator:uav_byteenable - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex0_s1_translator:uav_waitrequest -> hex0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex0_s1_translator:uav_burstcount - wire [31:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex0_s1_translator:uav_writedata - wire [18:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex0_s1_translator:uav_address - wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex0_s1_translator:uav_write - wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex0_s1_translator:uav_lock - wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex0_s1_translator:uav_read - wire [31:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex0_s1_translator:uav_readdata -> hex0_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex0_s1_translator:uav_readdatavalid -> hex0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex0_s1_translator:uav_debugaccess - wire [3:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex0_s1_translator:uav_byteenable - wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex1_s1_translator:uav_waitrequest -> hex1_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex1_s1_translator:uav_burstcount - wire [31:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex1_s1_translator:uav_writedata - wire [18:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex1_s1_translator:uav_address - wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex1_s1_translator:uav_write - wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex1_s1_translator:uav_lock - wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex1_s1_translator:uav_read - wire [31:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex1_s1_translator:uav_readdata -> hex1_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex1_s1_translator:uav_readdatavalid -> hex1_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex1_s1_translator:uav_debugaccess - wire [3:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex1_s1_translator:uav_byteenable - wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex2_s1_translator:uav_waitrequest -> hex2_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex2_s1_translator:uav_burstcount - wire [31:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex2_s1_translator:uav_writedata - wire [18:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex2_s1_translator:uav_address - wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex2_s1_translator:uav_write - wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex2_s1_translator:uav_lock - wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex2_s1_translator:uav_read - wire [31:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex2_s1_translator:uav_readdata -> hex2_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex2_s1_translator:uav_readdatavalid -> hex2_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex2_s1_translator:uav_debugaccess - wire [3:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex2_s1_translator:uav_byteenable - wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex3_s1_translator:uav_waitrequest -> hex3_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex3_s1_translator:uav_burstcount - wire [31:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex3_s1_translator:uav_writedata - wire [18:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex3_s1_translator:uav_address - wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex3_s1_translator:uav_write - wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex3_s1_translator:uav_lock - wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex3_s1_translator:uav_read - wire [31:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex3_s1_translator:uav_readdata -> hex3_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex3_s1_translator:uav_readdatavalid -> hex3_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex3_s1_translator:uav_debugaccess - wire [3:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex3_s1_translator:uav_byteenable - wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex4_s1_translator:uav_waitrequest -> hex4_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex4_s1_translator:uav_burstcount - wire [31:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex4_s1_translator:uav_writedata - wire [18:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex4_s1_translator:uav_address - wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex4_s1_translator:uav_write - wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex4_s1_translator:uav_lock - wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex4_s1_translator:uav_read - wire [31:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex4_s1_translator:uav_readdata -> hex4_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex4_s1_translator:uav_readdatavalid -> hex4_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex4_s1_translator:uav_debugaccess - wire [3:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex4_s1_translator:uav_byteenable - wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex5_s1_translator:uav_waitrequest -> hex5_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex5_s1_translator:uav_burstcount - wire [31:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex5_s1_translator:uav_writedata - wire [18:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex5_s1_translator:uav_address - wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex5_s1_translator:uav_write - wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex5_s1_translator:uav_lock - wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex5_s1_translator:uav_read - wire [31:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex5_s1_translator:uav_readdata -> hex5_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex5_s1_translator:uav_readdatavalid -> hex5_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex5_s1_translator:uav_debugaccess - wire [3:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex5_s1_translator:uav_byteenable - wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex6_s1_translator:uav_waitrequest -> hex6_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex6_s1_translator:uav_burstcount - wire [31:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex6_s1_translator:uav_writedata - wire [18:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex6_s1_translator:uav_address - wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex6_s1_translator:uav_write - wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex6_s1_translator:uav_lock - wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex6_s1_translator:uav_read - wire [31:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex6_s1_translator:uav_readdata -> hex6_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex6_s1_translator:uav_readdatavalid -> hex6_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex6_s1_translator:uav_debugaccess - wire [3:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex6_s1_translator:uav_byteenable - wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex7_s1_translator:uav_waitrequest -> hex7_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex7_s1_translator:uav_burstcount - wire [31:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex7_s1_translator:uav_writedata - wire [18:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex7_s1_translator:uav_address - wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex7_s1_translator:uav_write - wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex7_s1_translator:uav_lock - wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex7_s1_translator:uav_read - wire [31:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex7_s1_translator:uav_readdata -> hex7_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex7_s1_translator:uav_readdatavalid -> hex7_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex7_s1_translator:uav_debugaccess - wire [3:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex7_s1_translator:uav_byteenable - wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lcd_16207_0_control_slave_translator:uav_waitrequest -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> lcd_16207_0_control_slave_translator:uav_burstcount - wire [31:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> lcd_16207_0_control_slave_translator:uav_writedata - wire [18:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> lcd_16207_0_control_slave_translator:uav_address - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> lcd_16207_0_control_slave_translator:uav_write - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> lcd_16207_0_control_slave_translator:uav_lock - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> lcd_16207_0_control_slave_translator:uav_read - wire [31:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // lcd_16207_0_control_slave_translator:uav_readdata -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lcd_16207_0_control_slave_translator:uav_readdatavalid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lcd_16207_0_control_slave_translator:uav_debugaccess - wire [3:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> lcd_16207_0_control_slave_translator:uav_byteenable - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lcd_on_s1_translator:uav_waitrequest -> lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> lcd_on_s1_translator:uav_burstcount - wire [31:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> lcd_on_s1_translator:uav_writedata - wire [18:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_address; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_address -> lcd_on_s1_translator:uav_address - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_write; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_write -> lcd_on_s1_translator:uav_write - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_lock; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_lock -> lcd_on_s1_translator:uav_lock - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_read; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_read -> lcd_on_s1_translator:uav_read - wire [31:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // lcd_on_s1_translator:uav_readdata -> lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lcd_on_s1_translator:uav_readdatavalid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lcd_on_s1_translator:uav_debugaccess - wire [3:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> lcd_on_s1_translator:uav_byteenable - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lcd_blon_s1_translator:uav_waitrequest -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> lcd_blon_s1_translator:uav_burstcount - wire [31:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> lcd_blon_s1_translator:uav_writedata - wire [18:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_address; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_address -> lcd_blon_s1_translator:uav_address - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_write; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_write -> lcd_blon_s1_translator:uav_write - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_lock; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_lock -> lcd_blon_s1_translator:uav_lock - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_read; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_read -> lcd_blon_s1_translator:uav_read - wire [31:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // lcd_blon_s1_translator:uav_readdata -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lcd_blon_s1_translator:uav_readdatavalid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lcd_blon_s1_translator:uav_debugaccess - wire [3:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> lcd_blon_s1_translator:uav_byteenable - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket - wire [95:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_ready - wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket - wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid - wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket - wire [95:0] nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data - wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_ready - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket - wire [95:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket - wire [95:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket - wire leds_s1_translator_avalon_universal_slave_0_agent_rp_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid - wire leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket - wire [95:0] leds_s1_translator_avalon_universal_slave_0_agent_rp_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data - wire leds_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket - wire [95:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket - wire [95:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rp_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket - wire switches_s1_translator_avalon_universal_slave_0_agent_rp_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid - wire switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket - wire [95:0] switches_s1_translator_avalon_universal_slave_0_agent_rp_data; // switches_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data - wire switches_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket - wire [95:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rp_data; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_006:sink_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket - wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid - wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket - wire [95:0] hex0_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data - wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_007:sink_ready -> hex0_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket - wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid - wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket - wire [95:0] hex1_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data - wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_008:sink_ready -> hex1_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_009:sink_endofpacket - wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_009:sink_valid - wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_009:sink_startofpacket - wire [95:0] hex2_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_009:sink_data - wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_009:sink_ready -> hex2_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_010:sink_endofpacket - wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_010:sink_valid - wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_010:sink_startofpacket - wire [95:0] hex3_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_010:sink_data - wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_010:sink_ready -> hex3_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_011:sink_endofpacket - wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_011:sink_valid - wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_011:sink_startofpacket - wire [95:0] hex4_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_011:sink_data - wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_011:sink_ready -> hex4_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_012:sink_endofpacket - wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_012:sink_valid - wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_012:sink_startofpacket - wire [95:0] hex5_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_012:sink_data - wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_012:sink_ready -> hex5_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_013:sink_endofpacket - wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_013:sink_valid - wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_013:sink_startofpacket - wire [95:0] hex6_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_013:sink_data - wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_013:sink_ready -> hex6_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_014:sink_endofpacket - wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_014:sink_valid - wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_014:sink_startofpacket - wire [95:0] hex7_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_014:sink_data - wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_014:sink_ready -> hex7_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_015:sink_endofpacket - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_015:sink_valid - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_015:sink_startofpacket - wire [95:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_015:sink_data - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_015:sink_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_ready - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_016:sink_endofpacket - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_016:sink_valid - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_016:sink_startofpacket - wire [95:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_016:sink_data - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_016:sink_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_017:sink_endofpacket - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_017:sink_valid - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_017:sink_startofpacket - wire [95:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_017:sink_data - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_017:sink_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [LEDRs:reset_n, LEDRs_s1_translator:reset, LEDRs_s1_translator_avalon_universal_slave_0_agent:reset, LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, LEDs:reset_n, LEDs_s1_translator:reset, LEDs_s1_translator_avalon_universal_slave_0_agent:reset, LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, addr_router:reset, addr_router_001:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, hex0:reset_n, hex0_s1_translator:reset, hex0_s1_translator_avalon_universal_slave_0_agent:reset, hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex1:reset_n, hex1_s1_translator:reset, hex1_s1_translator_avalon_universal_slave_0_agent:reset, hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex2:reset_n, hex2_s1_translator:reset, hex2_s1_translator_avalon_universal_slave_0_agent:reset, hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex3:reset_n, hex3_s1_translator:reset, hex3_s1_translator_avalon_universal_slave_0_agent:reset, hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex4:reset_n, hex4_s1_translator:reset, hex4_s1_translator_avalon_universal_slave_0_agent:reset, hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex5:reset_n, hex5_s1_translator:reset, hex5_s1_translator_avalon_universal_slave_0_agent:reset, hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex6:reset_n, hex6_s1_translator:reset, hex6_s1_translator_avalon_universal_slave_0_agent:reset, hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex7:reset_n, hex7_s1_translator:reset, hex7_s1_translator_avalon_universal_slave_0_agent:reset, hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, id_router_008:reset, id_router_009:reset, id_router_010:reset, id_router_011:reset, id_router_012:reset, id_router_013:reset, id_router_014:reset, id_router_015:reset, id_router_016:reset, id_router_017:reset, irq_mapper:reset, jtag_uart:rst_n, jtag_uart_avalon_jtag_slave_translator:reset, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lcd_16207_0:reset_n, lcd_16207_0_control_slave_translator:reset, lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:reset, lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lcd_blon:reset_n, lcd_blon_s1_translator:reset, lcd_blon_s1_translator_avalon_universal_slave_0_agent:reset, lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lcd_on:reset_n, lcd_on_s1_translator:reset, lcd_on_s1_translator_avalon_universal_slave_0_agent:reset, lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, nios2_processor:reset_n, nios2_processor_data_master_translator:reset, nios2_processor_data_master_translator_avalon_universal_master_0_agent:reset, nios2_processor_instruction_master_translator:reset, nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:reset, nios2_processor_jtag_debug_module_translator:reset, nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, onchip_memory:reset, onchip_memory_s1_translator:reset, onchip_memory_s1_translator_avalon_universal_slave_0_agent:reset, onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, push_switches:reset_n, push_switches_s1_translator:reset, push_switches_s1_translator_avalon_universal_slave_0_agent:reset, push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_008:reset, rsp_xbar_demux_009:reset, rsp_xbar_demux_010:reset, rsp_xbar_demux_011:reset, rsp_xbar_demux_012:reset, rsp_xbar_demux_013:reset, rsp_xbar_demux_014:reset, rsp_xbar_demux_015:reset, rsp_xbar_demux_016:reset, rsp_xbar_demux_017:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, switches:reset_n, switches_s1_translator:reset, switches_s1_translator_avalon_universal_slave_0_agent:reset, switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset] - wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> onchip_memory:reset_req - wire nios2_processor_jtag_debug_module_reset_reset; // nios2_processor:jtag_debug_module_resetrequest -> rst_controller:reset_in1 - wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket - wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid - wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket - wire [95:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data - wire [17:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel - wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready - wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket - wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid - wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket - wire [95:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data - wire [17:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel - wire cmd_xbar_demux_src1_ready; // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready - wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket - wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid - wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket - wire [95:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data - wire [17:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel - wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready - wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket - wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid - wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket - wire [95:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data - wire [17:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel - wire cmd_xbar_demux_001_src1_ready; // cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready - wire cmd_xbar_demux_001_src2_endofpacket; // cmd_xbar_demux_001:src2_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src2_valid; // cmd_xbar_demux_001:src2_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src2_startofpacket; // cmd_xbar_demux_001:src2_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src2_data; // cmd_xbar_demux_001:src2_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src2_channel; // cmd_xbar_demux_001:src2_channel -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src3_endofpacket; // cmd_xbar_demux_001:src3_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src3_valid; // cmd_xbar_demux_001:src3_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src3_startofpacket; // cmd_xbar_demux_001:src3_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src3_data; // cmd_xbar_demux_001:src3_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src3_channel; // cmd_xbar_demux_001:src3_channel -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src4_endofpacket; // cmd_xbar_demux_001:src4_endofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src4_valid; // cmd_xbar_demux_001:src4_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src4_startofpacket; // cmd_xbar_demux_001:src4_startofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src4_data; // cmd_xbar_demux_001:src4_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src4_channel; // cmd_xbar_demux_001:src4_channel -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src5_endofpacket; // cmd_xbar_demux_001:src5_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src5_valid; // cmd_xbar_demux_001:src5_valid -> switches_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src5_startofpacket; // cmd_xbar_demux_001:src5_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src5_data; // cmd_xbar_demux_001:src5_data -> switches_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src5_channel; // cmd_xbar_demux_001:src5_channel -> switches_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src6_endofpacket; // cmd_xbar_demux_001:src6_endofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src6_valid; // cmd_xbar_demux_001:src6_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src6_startofpacket; // cmd_xbar_demux_001:src6_startofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src6_data; // cmd_xbar_demux_001:src6_data -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src6_channel; // cmd_xbar_demux_001:src6_channel -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src7_endofpacket; // cmd_xbar_demux_001:src7_endofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src7_valid; // cmd_xbar_demux_001:src7_valid -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src7_startofpacket; // cmd_xbar_demux_001:src7_startofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src7_data; // cmd_xbar_demux_001:src7_data -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src7_channel; // cmd_xbar_demux_001:src7_channel -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src8_endofpacket; // cmd_xbar_demux_001:src8_endofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src8_valid; // cmd_xbar_demux_001:src8_valid -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src8_startofpacket; // cmd_xbar_demux_001:src8_startofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src8_data; // cmd_xbar_demux_001:src8_data -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src8_channel; // cmd_xbar_demux_001:src8_channel -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src9_endofpacket; // cmd_xbar_demux_001:src9_endofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src9_valid; // cmd_xbar_demux_001:src9_valid -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src9_startofpacket; // cmd_xbar_demux_001:src9_startofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src9_data; // cmd_xbar_demux_001:src9_data -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src9_channel; // cmd_xbar_demux_001:src9_channel -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src10_endofpacket; // cmd_xbar_demux_001:src10_endofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src10_valid; // cmd_xbar_demux_001:src10_valid -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src10_startofpacket; // cmd_xbar_demux_001:src10_startofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src10_data; // cmd_xbar_demux_001:src10_data -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src10_channel; // cmd_xbar_demux_001:src10_channel -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src11_endofpacket; // cmd_xbar_demux_001:src11_endofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src11_valid; // cmd_xbar_demux_001:src11_valid -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src11_startofpacket; // cmd_xbar_demux_001:src11_startofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src11_data; // cmd_xbar_demux_001:src11_data -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src11_channel; // cmd_xbar_demux_001:src11_channel -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src12_endofpacket; // cmd_xbar_demux_001:src12_endofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src12_valid; // cmd_xbar_demux_001:src12_valid -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src12_startofpacket; // cmd_xbar_demux_001:src12_startofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src12_data; // cmd_xbar_demux_001:src12_data -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src12_channel; // cmd_xbar_demux_001:src12_channel -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src13_endofpacket; // cmd_xbar_demux_001:src13_endofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src13_valid; // cmd_xbar_demux_001:src13_valid -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src13_startofpacket; // cmd_xbar_demux_001:src13_startofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src13_data; // cmd_xbar_demux_001:src13_data -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src13_channel; // cmd_xbar_demux_001:src13_channel -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src14_endofpacket; // cmd_xbar_demux_001:src14_endofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src14_valid; // cmd_xbar_demux_001:src14_valid -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src14_startofpacket; // cmd_xbar_demux_001:src14_startofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src14_data; // cmd_xbar_demux_001:src14_data -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src14_channel; // cmd_xbar_demux_001:src14_channel -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src15_endofpacket; // cmd_xbar_demux_001:src15_endofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src15_valid; // cmd_xbar_demux_001:src15_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src15_startofpacket; // cmd_xbar_demux_001:src15_startofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src15_data; // cmd_xbar_demux_001:src15_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src15_channel; // cmd_xbar_demux_001:src15_channel -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src16_endofpacket; // cmd_xbar_demux_001:src16_endofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src16_valid; // cmd_xbar_demux_001:src16_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src16_startofpacket; // cmd_xbar_demux_001:src16_startofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src16_data; // cmd_xbar_demux_001:src16_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src16_channel; // cmd_xbar_demux_001:src16_channel -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src17_endofpacket; // cmd_xbar_demux_001:src17_endofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src17_valid; // cmd_xbar_demux_001:src17_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src17_startofpacket; // cmd_xbar_demux_001:src17_startofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src17_data; // cmd_xbar_demux_001:src17_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src17_channel; // cmd_xbar_demux_001:src17_channel -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket - wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid - wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket - wire [95:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data - wire [17:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel - wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready - wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket - wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid - wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket - wire [95:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data - wire [17:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel - wire rsp_xbar_demux_src1_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready - wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket - wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid - wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket - wire [95:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data - wire [17:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel - wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready - wire rsp_xbar_demux_001_src1_endofpacket; // rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket - wire rsp_xbar_demux_001_src1_valid; // rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid - wire rsp_xbar_demux_001_src1_startofpacket; // rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket - wire [95:0] rsp_xbar_demux_001_src1_data; // rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data - wire [17:0] rsp_xbar_demux_001_src1_channel; // rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel - wire rsp_xbar_demux_001_src1_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready - wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket - wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux_001:sink2_valid - wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket - wire [95:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux_001:sink2_data - wire [17:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux_001:sink2_channel - wire rsp_xbar_demux_002_src0_ready; // rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_002:src0_ready - wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket - wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux_001:sink3_valid - wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket - wire [95:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux_001:sink3_data - wire [17:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux_001:sink3_channel - wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src0_ready - wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket - wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux_001:sink4_valid - wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket - wire [95:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux_001:sink4_data - wire [17:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux_001:sink4_channel - wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src0_ready - wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket - wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid - wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket - wire [95:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data - wire [17:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel - wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready - wire rsp_xbar_demux_006_src0_endofpacket; // rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket - wire rsp_xbar_demux_006_src0_valid; // rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink6_valid - wire rsp_xbar_demux_006_src0_startofpacket; // rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket - wire [95:0] rsp_xbar_demux_006_src0_data; // rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink6_data - wire [17:0] rsp_xbar_demux_006_src0_channel; // rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink6_channel - wire rsp_xbar_demux_006_src0_ready; // rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_006:src0_ready - wire rsp_xbar_demux_007_src0_endofpacket; // rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket - wire rsp_xbar_demux_007_src0_valid; // rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink7_valid - wire rsp_xbar_demux_007_src0_startofpacket; // rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket - wire [95:0] rsp_xbar_demux_007_src0_data; // rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink7_data - wire [17:0] rsp_xbar_demux_007_src0_channel; // rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink7_channel - wire rsp_xbar_demux_007_src0_ready; // rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_007:src0_ready - wire rsp_xbar_demux_008_src0_endofpacket; // rsp_xbar_demux_008:src0_endofpacket -> rsp_xbar_mux_001:sink8_endofpacket - wire rsp_xbar_demux_008_src0_valid; // rsp_xbar_demux_008:src0_valid -> rsp_xbar_mux_001:sink8_valid - wire rsp_xbar_demux_008_src0_startofpacket; // rsp_xbar_demux_008:src0_startofpacket -> rsp_xbar_mux_001:sink8_startofpacket - wire [95:0] rsp_xbar_demux_008_src0_data; // rsp_xbar_demux_008:src0_data -> rsp_xbar_mux_001:sink8_data - wire [17:0] rsp_xbar_demux_008_src0_channel; // rsp_xbar_demux_008:src0_channel -> rsp_xbar_mux_001:sink8_channel - wire rsp_xbar_demux_008_src0_ready; // rsp_xbar_mux_001:sink8_ready -> rsp_xbar_demux_008:src0_ready - wire rsp_xbar_demux_009_src0_endofpacket; // rsp_xbar_demux_009:src0_endofpacket -> rsp_xbar_mux_001:sink9_endofpacket - wire rsp_xbar_demux_009_src0_valid; // rsp_xbar_demux_009:src0_valid -> rsp_xbar_mux_001:sink9_valid - wire rsp_xbar_demux_009_src0_startofpacket; // rsp_xbar_demux_009:src0_startofpacket -> rsp_xbar_mux_001:sink9_startofpacket - wire [95:0] rsp_xbar_demux_009_src0_data; // rsp_xbar_demux_009:src0_data -> rsp_xbar_mux_001:sink9_data - wire [17:0] rsp_xbar_demux_009_src0_channel; // rsp_xbar_demux_009:src0_channel -> rsp_xbar_mux_001:sink9_channel - wire rsp_xbar_demux_009_src0_ready; // rsp_xbar_mux_001:sink9_ready -> rsp_xbar_demux_009:src0_ready - wire rsp_xbar_demux_010_src0_endofpacket; // rsp_xbar_demux_010:src0_endofpacket -> rsp_xbar_mux_001:sink10_endofpacket - wire rsp_xbar_demux_010_src0_valid; // rsp_xbar_demux_010:src0_valid -> rsp_xbar_mux_001:sink10_valid - wire rsp_xbar_demux_010_src0_startofpacket; // rsp_xbar_demux_010:src0_startofpacket -> rsp_xbar_mux_001:sink10_startofpacket - wire [95:0] rsp_xbar_demux_010_src0_data; // rsp_xbar_demux_010:src0_data -> rsp_xbar_mux_001:sink10_data - wire [17:0] rsp_xbar_demux_010_src0_channel; // rsp_xbar_demux_010:src0_channel -> rsp_xbar_mux_001:sink10_channel - wire rsp_xbar_demux_010_src0_ready; // rsp_xbar_mux_001:sink10_ready -> rsp_xbar_demux_010:src0_ready - wire rsp_xbar_demux_011_src0_endofpacket; // rsp_xbar_demux_011:src0_endofpacket -> rsp_xbar_mux_001:sink11_endofpacket - wire rsp_xbar_demux_011_src0_valid; // rsp_xbar_demux_011:src0_valid -> rsp_xbar_mux_001:sink11_valid - wire rsp_xbar_demux_011_src0_startofpacket; // rsp_xbar_demux_011:src0_startofpacket -> rsp_xbar_mux_001:sink11_startofpacket - wire [95:0] rsp_xbar_demux_011_src0_data; // rsp_xbar_demux_011:src0_data -> rsp_xbar_mux_001:sink11_data - wire [17:0] rsp_xbar_demux_011_src0_channel; // rsp_xbar_demux_011:src0_channel -> rsp_xbar_mux_001:sink11_channel - wire rsp_xbar_demux_011_src0_ready; // rsp_xbar_mux_001:sink11_ready -> rsp_xbar_demux_011:src0_ready - wire rsp_xbar_demux_012_src0_endofpacket; // rsp_xbar_demux_012:src0_endofpacket -> rsp_xbar_mux_001:sink12_endofpacket - wire rsp_xbar_demux_012_src0_valid; // rsp_xbar_demux_012:src0_valid -> rsp_xbar_mux_001:sink12_valid - wire rsp_xbar_demux_012_src0_startofpacket; // rsp_xbar_demux_012:src0_startofpacket -> rsp_xbar_mux_001:sink12_startofpacket - wire [95:0] rsp_xbar_demux_012_src0_data; // rsp_xbar_demux_012:src0_data -> rsp_xbar_mux_001:sink12_data - wire [17:0] rsp_xbar_demux_012_src0_channel; // rsp_xbar_demux_012:src0_channel -> rsp_xbar_mux_001:sink12_channel - wire rsp_xbar_demux_012_src0_ready; // rsp_xbar_mux_001:sink12_ready -> rsp_xbar_demux_012:src0_ready - wire rsp_xbar_demux_013_src0_endofpacket; // rsp_xbar_demux_013:src0_endofpacket -> rsp_xbar_mux_001:sink13_endofpacket - wire rsp_xbar_demux_013_src0_valid; // rsp_xbar_demux_013:src0_valid -> rsp_xbar_mux_001:sink13_valid - wire rsp_xbar_demux_013_src0_startofpacket; // rsp_xbar_demux_013:src0_startofpacket -> rsp_xbar_mux_001:sink13_startofpacket - wire [95:0] rsp_xbar_demux_013_src0_data; // rsp_xbar_demux_013:src0_data -> rsp_xbar_mux_001:sink13_data - wire [17:0] rsp_xbar_demux_013_src0_channel; // rsp_xbar_demux_013:src0_channel -> rsp_xbar_mux_001:sink13_channel - wire rsp_xbar_demux_013_src0_ready; // rsp_xbar_mux_001:sink13_ready -> rsp_xbar_demux_013:src0_ready - wire rsp_xbar_demux_014_src0_endofpacket; // rsp_xbar_demux_014:src0_endofpacket -> rsp_xbar_mux_001:sink14_endofpacket - wire rsp_xbar_demux_014_src0_valid; // rsp_xbar_demux_014:src0_valid -> rsp_xbar_mux_001:sink14_valid - wire rsp_xbar_demux_014_src0_startofpacket; // rsp_xbar_demux_014:src0_startofpacket -> rsp_xbar_mux_001:sink14_startofpacket - wire [95:0] rsp_xbar_demux_014_src0_data; // rsp_xbar_demux_014:src0_data -> rsp_xbar_mux_001:sink14_data - wire [17:0] rsp_xbar_demux_014_src0_channel; // rsp_xbar_demux_014:src0_channel -> rsp_xbar_mux_001:sink14_channel - wire rsp_xbar_demux_014_src0_ready; // rsp_xbar_mux_001:sink14_ready -> rsp_xbar_demux_014:src0_ready - wire rsp_xbar_demux_015_src0_endofpacket; // rsp_xbar_demux_015:src0_endofpacket -> rsp_xbar_mux_001:sink15_endofpacket - wire rsp_xbar_demux_015_src0_valid; // rsp_xbar_demux_015:src0_valid -> rsp_xbar_mux_001:sink15_valid - wire rsp_xbar_demux_015_src0_startofpacket; // rsp_xbar_demux_015:src0_startofpacket -> rsp_xbar_mux_001:sink15_startofpacket - wire [95:0] rsp_xbar_demux_015_src0_data; // rsp_xbar_demux_015:src0_data -> rsp_xbar_mux_001:sink15_data - wire [17:0] rsp_xbar_demux_015_src0_channel; // rsp_xbar_demux_015:src0_channel -> rsp_xbar_mux_001:sink15_channel - wire rsp_xbar_demux_015_src0_ready; // rsp_xbar_mux_001:sink15_ready -> rsp_xbar_demux_015:src0_ready - wire rsp_xbar_demux_016_src0_endofpacket; // rsp_xbar_demux_016:src0_endofpacket -> rsp_xbar_mux_001:sink16_endofpacket - wire rsp_xbar_demux_016_src0_valid; // rsp_xbar_demux_016:src0_valid -> rsp_xbar_mux_001:sink16_valid - wire rsp_xbar_demux_016_src0_startofpacket; // rsp_xbar_demux_016:src0_startofpacket -> rsp_xbar_mux_001:sink16_startofpacket - wire [95:0] rsp_xbar_demux_016_src0_data; // rsp_xbar_demux_016:src0_data -> rsp_xbar_mux_001:sink16_data - wire [17:0] rsp_xbar_demux_016_src0_channel; // rsp_xbar_demux_016:src0_channel -> rsp_xbar_mux_001:sink16_channel - wire rsp_xbar_demux_016_src0_ready; // rsp_xbar_mux_001:sink16_ready -> rsp_xbar_demux_016:src0_ready - wire rsp_xbar_demux_017_src0_endofpacket; // rsp_xbar_demux_017:src0_endofpacket -> rsp_xbar_mux_001:sink17_endofpacket - wire rsp_xbar_demux_017_src0_valid; // rsp_xbar_demux_017:src0_valid -> rsp_xbar_mux_001:sink17_valid - wire rsp_xbar_demux_017_src0_startofpacket; // rsp_xbar_demux_017:src0_startofpacket -> rsp_xbar_mux_001:sink17_startofpacket - wire [95:0] rsp_xbar_demux_017_src0_data; // rsp_xbar_demux_017:src0_data -> rsp_xbar_mux_001:sink17_data - wire [17:0] rsp_xbar_demux_017_src0_channel; // rsp_xbar_demux_017:src0_channel -> rsp_xbar_mux_001:sink17_channel - wire rsp_xbar_demux_017_src0_ready; // rsp_xbar_mux_001:sink17_ready -> rsp_xbar_demux_017:src0_ready - wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket - wire addr_router_src_valid; // addr_router:src_valid -> cmd_xbar_demux:sink_valid - wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket - wire [95:0] addr_router_src_data; // addr_router:src_data -> cmd_xbar_demux:sink_data - wire [17:0] addr_router_src_channel; // addr_router:src_channel -> cmd_xbar_demux:sink_channel - wire addr_router_src_ready; // cmd_xbar_demux:sink_ready -> addr_router:src_ready - wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket - wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_valid - wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket - wire [95:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_data - wire [17:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_channel - wire rsp_xbar_mux_src_ready; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready - wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket - wire addr_router_001_src_valid; // addr_router_001:src_valid -> cmd_xbar_demux_001:sink_valid - wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket - wire [95:0] addr_router_001_src_data; // addr_router_001:src_data -> cmd_xbar_demux_001:sink_data - wire [17:0] addr_router_001_src_channel; // addr_router_001:src_channel -> cmd_xbar_demux_001:sink_channel - wire addr_router_001_src_ready; // cmd_xbar_demux_001:sink_ready -> addr_router_001:src_ready - wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket - wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_valid - wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket - wire [95:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_data - wire [17:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_channel - wire rsp_xbar_mux_001_src_ready; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux_001:src_ready - wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_mux_src_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready - wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket - wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid - wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket - wire [95:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data - wire [17:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel - wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready - wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_mux_001_src_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_001:src_ready - wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket - wire id_router_001_src_valid; // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid - wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket - wire [95:0] id_router_001_src_data; // id_router_001:src_data -> rsp_xbar_demux_001:sink_data - wire [17:0] id_router_001_src_channel; // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel - wire id_router_001_src_ready; // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready - wire cmd_xbar_demux_001_src2_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src2_ready - wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket - wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid - wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket - wire [95:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data - wire [17:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel - wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready - wire cmd_xbar_demux_001_src3_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src3_ready - wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket - wire id_router_003_src_valid; // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid - wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket - wire [95:0] id_router_003_src_data; // id_router_003:src_data -> rsp_xbar_demux_003:sink_data - wire [17:0] id_router_003_src_channel; // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel - wire id_router_003_src_ready; // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready - wire cmd_xbar_demux_001_src4_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src4_ready - wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket - wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid - wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket - wire [95:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data - wire [17:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel - wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready - wire cmd_xbar_demux_001_src5_ready; // switches_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready - wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket - wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid - wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket - wire [95:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data - wire [17:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel - wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready - wire cmd_xbar_demux_001_src6_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready - wire id_router_006_src_endofpacket; // id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket - wire id_router_006_src_valid; // id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid - wire id_router_006_src_startofpacket; // id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket - wire [95:0] id_router_006_src_data; // id_router_006:src_data -> rsp_xbar_demux_006:sink_data - wire [17:0] id_router_006_src_channel; // id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel - wire id_router_006_src_ready; // rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready - wire cmd_xbar_demux_001_src7_ready; // hex0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready - wire id_router_007_src_endofpacket; // id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket - wire id_router_007_src_valid; // id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid - wire id_router_007_src_startofpacket; // id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket - wire [95:0] id_router_007_src_data; // id_router_007:src_data -> rsp_xbar_demux_007:sink_data - wire [17:0] id_router_007_src_channel; // id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel - wire id_router_007_src_ready; // rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready - wire cmd_xbar_demux_001_src8_ready; // hex1_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src8_ready - wire id_router_008_src_endofpacket; // id_router_008:src_endofpacket -> rsp_xbar_demux_008:sink_endofpacket - wire id_router_008_src_valid; // id_router_008:src_valid -> rsp_xbar_demux_008:sink_valid - wire id_router_008_src_startofpacket; // id_router_008:src_startofpacket -> rsp_xbar_demux_008:sink_startofpacket - wire [95:0] id_router_008_src_data; // id_router_008:src_data -> rsp_xbar_demux_008:sink_data - wire [17:0] id_router_008_src_channel; // id_router_008:src_channel -> rsp_xbar_demux_008:sink_channel - wire id_router_008_src_ready; // rsp_xbar_demux_008:sink_ready -> id_router_008:src_ready - wire cmd_xbar_demux_001_src9_ready; // hex2_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src9_ready - wire id_router_009_src_endofpacket; // id_router_009:src_endofpacket -> rsp_xbar_demux_009:sink_endofpacket - wire id_router_009_src_valid; // id_router_009:src_valid -> rsp_xbar_demux_009:sink_valid - wire id_router_009_src_startofpacket; // id_router_009:src_startofpacket -> rsp_xbar_demux_009:sink_startofpacket - wire [95:0] id_router_009_src_data; // id_router_009:src_data -> rsp_xbar_demux_009:sink_data - wire [17:0] id_router_009_src_channel; // id_router_009:src_channel -> rsp_xbar_demux_009:sink_channel - wire id_router_009_src_ready; // rsp_xbar_demux_009:sink_ready -> id_router_009:src_ready - wire cmd_xbar_demux_001_src10_ready; // hex3_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src10_ready - wire id_router_010_src_endofpacket; // id_router_010:src_endofpacket -> rsp_xbar_demux_010:sink_endofpacket - wire id_router_010_src_valid; // id_router_010:src_valid -> rsp_xbar_demux_010:sink_valid - wire id_router_010_src_startofpacket; // id_router_010:src_startofpacket -> rsp_xbar_demux_010:sink_startofpacket - wire [95:0] id_router_010_src_data; // id_router_010:src_data -> rsp_xbar_demux_010:sink_data - wire [17:0] id_router_010_src_channel; // id_router_010:src_channel -> rsp_xbar_demux_010:sink_channel - wire id_router_010_src_ready; // rsp_xbar_demux_010:sink_ready -> id_router_010:src_ready - wire cmd_xbar_demux_001_src11_ready; // hex4_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src11_ready - wire id_router_011_src_endofpacket; // id_router_011:src_endofpacket -> rsp_xbar_demux_011:sink_endofpacket - wire id_router_011_src_valid; // id_router_011:src_valid -> rsp_xbar_demux_011:sink_valid - wire id_router_011_src_startofpacket; // id_router_011:src_startofpacket -> rsp_xbar_demux_011:sink_startofpacket - wire [95:0] id_router_011_src_data; // id_router_011:src_data -> rsp_xbar_demux_011:sink_data - wire [17:0] id_router_011_src_channel; // id_router_011:src_channel -> rsp_xbar_demux_011:sink_channel - wire id_router_011_src_ready; // rsp_xbar_demux_011:sink_ready -> id_router_011:src_ready - wire cmd_xbar_demux_001_src12_ready; // hex5_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src12_ready - wire id_router_012_src_endofpacket; // id_router_012:src_endofpacket -> rsp_xbar_demux_012:sink_endofpacket - wire id_router_012_src_valid; // id_router_012:src_valid -> rsp_xbar_demux_012:sink_valid - wire id_router_012_src_startofpacket; // id_router_012:src_startofpacket -> rsp_xbar_demux_012:sink_startofpacket - wire [95:0] id_router_012_src_data; // id_router_012:src_data -> rsp_xbar_demux_012:sink_data - wire [17:0] id_router_012_src_channel; // id_router_012:src_channel -> rsp_xbar_demux_012:sink_channel - wire id_router_012_src_ready; // rsp_xbar_demux_012:sink_ready -> id_router_012:src_ready - wire cmd_xbar_demux_001_src13_ready; // hex6_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src13_ready - wire id_router_013_src_endofpacket; // id_router_013:src_endofpacket -> rsp_xbar_demux_013:sink_endofpacket - wire id_router_013_src_valid; // id_router_013:src_valid -> rsp_xbar_demux_013:sink_valid - wire id_router_013_src_startofpacket; // id_router_013:src_startofpacket -> rsp_xbar_demux_013:sink_startofpacket - wire [95:0] id_router_013_src_data; // id_router_013:src_data -> rsp_xbar_demux_013:sink_data - wire [17:0] id_router_013_src_channel; // id_router_013:src_channel -> rsp_xbar_demux_013:sink_channel - wire id_router_013_src_ready; // rsp_xbar_demux_013:sink_ready -> id_router_013:src_ready - wire cmd_xbar_demux_001_src14_ready; // hex7_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src14_ready - wire id_router_014_src_endofpacket; // id_router_014:src_endofpacket -> rsp_xbar_demux_014:sink_endofpacket - wire id_router_014_src_valid; // id_router_014:src_valid -> rsp_xbar_demux_014:sink_valid - wire id_router_014_src_startofpacket; // id_router_014:src_startofpacket -> rsp_xbar_demux_014:sink_startofpacket - wire [95:0] id_router_014_src_data; // id_router_014:src_data -> rsp_xbar_demux_014:sink_data - wire [17:0] id_router_014_src_channel; // id_router_014:src_channel -> rsp_xbar_demux_014:sink_channel - wire id_router_014_src_ready; // rsp_xbar_demux_014:sink_ready -> id_router_014:src_ready - wire cmd_xbar_demux_001_src15_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src15_ready - wire id_router_015_src_endofpacket; // id_router_015:src_endofpacket -> rsp_xbar_demux_015:sink_endofpacket - wire id_router_015_src_valid; // id_router_015:src_valid -> rsp_xbar_demux_015:sink_valid - wire id_router_015_src_startofpacket; // id_router_015:src_startofpacket -> rsp_xbar_demux_015:sink_startofpacket - wire [95:0] id_router_015_src_data; // id_router_015:src_data -> rsp_xbar_demux_015:sink_data - wire [17:0] id_router_015_src_channel; // id_router_015:src_channel -> rsp_xbar_demux_015:sink_channel - wire id_router_015_src_ready; // rsp_xbar_demux_015:sink_ready -> id_router_015:src_ready - wire cmd_xbar_demux_001_src16_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src16_ready - wire id_router_016_src_endofpacket; // id_router_016:src_endofpacket -> rsp_xbar_demux_016:sink_endofpacket - wire id_router_016_src_valid; // id_router_016:src_valid -> rsp_xbar_demux_016:sink_valid - wire id_router_016_src_startofpacket; // id_router_016:src_startofpacket -> rsp_xbar_demux_016:sink_startofpacket - wire [95:0] id_router_016_src_data; // id_router_016:src_data -> rsp_xbar_demux_016:sink_data - wire [17:0] id_router_016_src_channel; // id_router_016:src_channel -> rsp_xbar_demux_016:sink_channel - wire id_router_016_src_ready; // rsp_xbar_demux_016:sink_ready -> id_router_016:src_ready - wire cmd_xbar_demux_001_src17_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src17_ready - wire id_router_017_src_endofpacket; // id_router_017:src_endofpacket -> rsp_xbar_demux_017:sink_endofpacket - wire id_router_017_src_valid; // id_router_017:src_valid -> rsp_xbar_demux_017:sink_valid - wire id_router_017_src_startofpacket; // id_router_017:src_startofpacket -> rsp_xbar_demux_017:sink_startofpacket - wire [95:0] id_router_017_src_data; // id_router_017:src_data -> rsp_xbar_demux_017:sink_data - wire [17:0] id_router_017_src_channel; // id_router_017:src_channel -> rsp_xbar_demux_017:sink_channel - wire id_router_017_src_ready; // rsp_xbar_demux_017:sink_ready -> id_router_017:src_ready - wire irq_mapper_receiver0_irq; // jtag_uart:av_irq -> irq_mapper:receiver0_irq - wire [31:0] nios2_processor_d_irq_irq; // irq_mapper:sender_irq -> nios2_processor:d_irq - - nios_system_nios2_processor nios2_processor ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n - .d_address (nios2_processor_data_master_address), // data_master.address - .d_byteenable (nios2_processor_data_master_byteenable), // .byteenable - .d_read (nios2_processor_data_master_read), // .read - .d_readdata (nios2_processor_data_master_readdata), // .readdata - .d_waitrequest (nios2_processor_data_master_waitrequest), // .waitrequest - .d_write (nios2_processor_data_master_write), // .write - .d_writedata (nios2_processor_data_master_writedata), // .writedata - .jtag_debug_module_debugaccess_to_roms (nios2_processor_data_master_debugaccess), // .debugaccess - .i_address (nios2_processor_instruction_master_address), // instruction_master.address - .i_read (nios2_processor_instruction_master_read), // .read - .i_readdata (nios2_processor_instruction_master_readdata), // .readdata - .i_waitrequest (nios2_processor_instruction_master_waitrequest), // .waitrequest - .d_irq (nios2_processor_d_irq_irq), // d_irq.irq - .jtag_debug_module_resetrequest (nios2_processor_jtag_debug_module_reset_reset), // jtag_debug_module_reset.reset - .jtag_debug_module_address (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_address), // jtag_debug_module.address - .jtag_debug_module_byteenable (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable - .jtag_debug_module_debugaccess (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess - .jtag_debug_module_read (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_read), // .read - .jtag_debug_module_readdata (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata - .jtag_debug_module_waitrequest (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest), // .waitrequest - .jtag_debug_module_write (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write - .jtag_debug_module_writedata (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata - .no_ci_readra () // custom_instruction_master.readra - ); - - nios_system_onchip_memory onchip_memory ( - .clk (clk_clk), // clk1.clk - .address (onchip_memory_s1_translator_avalon_anti_slave_0_address), // s1.address - .clken (onchip_memory_s1_translator_avalon_anti_slave_0_clken), // .clken - .chipselect (onchip_memory_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .write (onchip_memory_s1_translator_avalon_anti_slave_0_write), // .write - .readdata (onchip_memory_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .writedata (onchip_memory_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .byteenable (onchip_memory_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable - .reset (rst_controller_reset_out_reset), // reset1.reset - .reset_req (rst_controller_reset_out_reset_req) // .reset_req - ); - - nios_system_jtag_uart jtag_uart ( - .clk (clk_clk), // clk.clk - .rst_n (~rst_controller_reset_out_reset), // reset.reset_n - .av_chipselect (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // avalon_jtag_slave.chipselect - .av_address (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // .address - .av_read_n (~jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read_n - .av_readdata (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata - .av_write_n (~jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write_n - .av_writedata (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata - .av_waitrequest (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest - .av_irq (irq_mapper_receiver0_irq) // irq.irq - ); - - nios_system_LEDs leds ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (leds_s1_translator_avalon_anti_slave_0_address), // s1.address - .write_n (~leds_s1_translator_avalon_anti_slave_0_write), // .write_n - .writedata (leds_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .chipselect (leds_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .readdata (leds_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .out_port (leds_export) // external_connection.export - ); - - nios_system_LEDRs ledrs ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (ledrs_s1_translator_avalon_anti_slave_0_address), // s1.address - .write_n (~ledrs_s1_translator_avalon_anti_slave_0_write), // .write_n - .writedata (ledrs_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .chipselect (ledrs_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .readdata (ledrs_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .out_port (ledrs_export) // external_connection.export - ); - - nios_system_switches switches ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (switches_s1_translator_avalon_anti_slave_0_address), // s1.address - .readdata (switches_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .in_port (switches_export) // external_connection.export - ); - - nios_system_push_switches push_switches ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (push_switches_s1_translator_avalon_anti_slave_0_address), // s1.address - .readdata (push_switches_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .in_port (push_switches_export) // external_connection.export - ); - - nios_system_hex0 hex0 ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (hex0_s1_translator_avalon_anti_slave_0_address), // s1.address - .write_n (~hex0_s1_translator_avalon_anti_slave_0_write), // .write_n - .writedata (hex0_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .chipselect (hex0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .readdata (hex0_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .out_port (hex0_export) // external_connection.export - ); - - nios_system_hex0 hex1 ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (hex1_s1_translator_avalon_anti_slave_0_address), // s1.address - .write_n (~hex1_s1_translator_avalon_anti_slave_0_write), // .write_n - .writedata (hex1_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .chipselect (hex1_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .readdata (hex1_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .out_port (hex1_export) // external_connection.export - ); - - nios_system_hex0 hex2 ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (hex2_s1_translator_avalon_anti_slave_0_address), // s1.address - .write_n (~hex2_s1_translator_avalon_anti_slave_0_write), // .write_n - .writedata (hex2_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .chipselect (hex2_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .readdata (hex2_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .out_port (hex2_export) // external_connection.export - ); - - nios_system_hex0 hex3 ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (hex3_s1_translator_avalon_anti_slave_0_address), // s1.address - .write_n (~hex3_s1_translator_avalon_anti_slave_0_write), // .write_n - .writedata (hex3_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .chipselect (hex3_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .readdata (hex3_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .out_port (hex3_export) // external_connection.export - ); - - nios_system_hex0 hex4 ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (hex4_s1_translator_avalon_anti_slave_0_address), // s1.address - .write_n (~hex4_s1_translator_avalon_anti_slave_0_write), // .write_n - .writedata (hex4_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .chipselect (hex4_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .readdata (hex4_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .out_port (hex4_export) // external_connection.export - ); - - nios_system_hex0 hex5 ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (hex5_s1_translator_avalon_anti_slave_0_address), // s1.address - .write_n (~hex5_s1_translator_avalon_anti_slave_0_write), // .write_n - .writedata (hex5_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .chipselect (hex5_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .readdata (hex5_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .out_port (hex5_export) // external_connection.export - ); - - nios_system_hex0 hex6 ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (hex6_s1_translator_avalon_anti_slave_0_address), // s1.address - .write_n (~hex6_s1_translator_avalon_anti_slave_0_write), // .write_n - .writedata (hex6_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .chipselect (hex6_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .readdata (hex6_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .out_port (hex6_export) // external_connection.export - ); - - nios_system_hex0 hex7 ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (hex7_s1_translator_avalon_anti_slave_0_address), // s1.address - .write_n (~hex7_s1_translator_avalon_anti_slave_0_write), // .write_n - .writedata (hex7_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .chipselect (hex7_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .readdata (hex7_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .out_port (hex7_export) // external_connection.export - ); - - nios_system_lcd_16207_0 lcd_16207_0 ( - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .clk (clk_clk), // clk.clk - .begintransfer (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_begintransfer), // control_slave.begintransfer - .read (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_read), // .read - .write (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_write), // .write - .readdata (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata - .writedata (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_writedata), // .writedata - .address (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_address), // .address - .LCD_RS (lcd_16207_0_RS), // external.export - .LCD_RW (lcd_16207_0_RW), // .export - .LCD_data (lcd_16207_0_data), // .export - .LCD_E (lcd_16207_0_E) // .export - ); - - nios_system_lcd_on lcd_on ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (lcd_on_s1_translator_avalon_anti_slave_0_address), // s1.address - .write_n (~lcd_on_s1_translator_avalon_anti_slave_0_write), // .write_n - .writedata (lcd_on_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .chipselect (lcd_on_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .readdata (lcd_on_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .out_port (lcd_on_export) // external_connection.export - ); - - nios_system_lcd_on lcd_blon ( - .clk (clk_clk), // clk.clk - .reset_n (~rst_controller_reset_out_reset), // reset.reset_n - .address (lcd_blon_s1_translator_avalon_anti_slave_0_address), // s1.address - .write_n (~lcd_blon_s1_translator_avalon_anti_slave_0_write), // .write_n - .writedata (lcd_blon_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .chipselect (lcd_blon_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .readdata (lcd_blon_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .out_port (lcd_blon_export) // external_connection.export - ); - - altera_merlin_master_translator #( - .AV_ADDRESS_W (19), - .AV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .USE_READ (1), - .USE_WRITE (0), - .USE_BEGINBURSTTRANSFER (0), - .USE_BEGINTRANSFER (0), - .USE_CHIPSELECT (0), - .USE_BURSTCOUNT (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (1), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_LINEWRAPBURSTS (1), - .AV_REGISTERINCOMINGSIGNALS (0) - ) nios2_processor_instruction_master_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (nios2_processor_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address - .uav_burstcount (nios2_processor_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount - .uav_read (nios2_processor_instruction_master_translator_avalon_universal_master_0_read), // .read - .uav_write (nios2_processor_instruction_master_translator_avalon_universal_master_0_write), // .write - .uav_waitrequest (nios2_processor_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest - .uav_readdatavalid (nios2_processor_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid - .uav_byteenable (nios2_processor_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable - .uav_readdata (nios2_processor_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata - .uav_writedata (nios2_processor_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata - .uav_lock (nios2_processor_instruction_master_translator_avalon_universal_master_0_lock), // .lock - .uav_debugaccess (nios2_processor_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess - .av_address (nios2_processor_instruction_master_address), // avalon_anti_master_0.address - .av_waitrequest (nios2_processor_instruction_master_waitrequest), // .waitrequest - .av_read (nios2_processor_instruction_master_read), // .read - .av_readdata (nios2_processor_instruction_master_readdata), // .readdata - .av_burstcount (1'b1), // (terminated) - .av_byteenable (4'b1111), // (terminated) - .av_beginbursttransfer (1'b0), // (terminated) - .av_begintransfer (1'b0), // (terminated) - .av_chipselect (1'b0), // (terminated) - .av_readdatavalid (), // (terminated) - .av_write (1'b0), // (terminated) - .av_writedata (32'b00000000000000000000000000000000), // (terminated) - .av_lock (1'b0), // (terminated) - .av_debugaccess (1'b0), // (terminated) - .uav_clken (), // (terminated) - .av_clken (1'b1), // (terminated) - .uav_response (2'b00), // (terminated) - .av_response (), // (terminated) - .uav_writeresponserequest (), // (terminated) - .uav_writeresponsevalid (1'b0), // (terminated) - .av_writeresponserequest (1'b0), // (terminated) - .av_writeresponsevalid () // (terminated) - ); - - altera_merlin_master_translator #( - .AV_ADDRESS_W (19), - .AV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .USE_READ (1), - .USE_WRITE (1), - .USE_BEGINBURSTTRANSFER (0), - .USE_BEGINTRANSFER (0), - .USE_CHIPSELECT (0), - .USE_BURSTCOUNT (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (1), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_LINEWRAPBURSTS (0), - .AV_REGISTERINCOMINGSIGNALS (1) - ) nios2_processor_data_master_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (nios2_processor_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address - .uav_burstcount (nios2_processor_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount - .uav_read (nios2_processor_data_master_translator_avalon_universal_master_0_read), // .read - .uav_write (nios2_processor_data_master_translator_avalon_universal_master_0_write), // .write - .uav_waitrequest (nios2_processor_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest - .uav_readdatavalid (nios2_processor_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid - .uav_byteenable (nios2_processor_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable - .uav_readdata (nios2_processor_data_master_translator_avalon_universal_master_0_readdata), // .readdata - .uav_writedata (nios2_processor_data_master_translator_avalon_universal_master_0_writedata), // .writedata - .uav_lock (nios2_processor_data_master_translator_avalon_universal_master_0_lock), // .lock - .uav_debugaccess (nios2_processor_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess - .av_address (nios2_processor_data_master_address), // avalon_anti_master_0.address - .av_waitrequest (nios2_processor_data_master_waitrequest), // .waitrequest - .av_byteenable (nios2_processor_data_master_byteenable), // .byteenable - .av_read (nios2_processor_data_master_read), // .read - .av_readdata (nios2_processor_data_master_readdata), // .readdata - .av_write (nios2_processor_data_master_write), // .write - .av_writedata (nios2_processor_data_master_writedata), // .writedata - .av_debugaccess (nios2_processor_data_master_debugaccess), // .debugaccess - .av_burstcount (1'b1), // (terminated) - .av_beginbursttransfer (1'b0), // (terminated) - .av_begintransfer (1'b0), // (terminated) - .av_chipselect (1'b0), // (terminated) - .av_readdatavalid (), // (terminated) - .av_lock (1'b0), // (terminated) - .uav_clken (), // (terminated) - .av_clken (1'b1), // (terminated) - .uav_response (2'b00), // (terminated) - .av_response (), // (terminated) - .uav_writeresponserequest (), // (terminated) - .uav_writeresponsevalid (1'b0), // (terminated) - .av_writeresponserequest (1'b0), // (terminated) - .av_writeresponsevalid () // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (9), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (4), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (1), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) nios2_processor_jtag_debug_module_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write - .av_read (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_read), // .read - .av_readdata (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata - .av_byteenable (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable - .av_waitrequest (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest), // .waitrequest - .av_debugaccess (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_chipselect (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (16), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (4), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (1), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (0), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) onchip_memory_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (onchip_memory_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (onchip_memory_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (onchip_memory_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (onchip_memory_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_byteenable (onchip_memory_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable - .av_chipselect (onchip_memory_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_clken (onchip_memory_s1_translator_avalon_anti_slave_0_clken), // .clken - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) leds_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (leds_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (leds_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (leds_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (leds_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (leds_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (leds_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (leds_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (leds_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_chipselect (leds_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (1), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (1), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) jtag_uart_avalon_jtag_slave_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write - .av_read (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read - .av_readdata (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata - .av_waitrequest (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest - .av_chipselect (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) ledrs_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (ledrs_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (ledrs_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (ledrs_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (ledrs_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_chipselect (ledrs_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) switches_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (switches_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (switches_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (switches_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (switches_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (switches_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_readdata (switches_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_write (), // (terminated) - .av_read (), // (terminated) - .av_writedata (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_chipselect (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) push_switches_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (push_switches_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_readdata (push_switches_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_write (), // (terminated) - .av_read (), // (terminated) - .av_writedata (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_chipselect (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) hex0_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (hex0_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (hex0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (hex0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (hex0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (hex0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (hex0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (hex0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (hex0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (hex0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (hex0_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (hex0_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (hex0_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (hex0_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_chipselect (hex0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) hex1_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (hex1_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (hex1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (hex1_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (hex1_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (hex1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (hex1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (hex1_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (hex1_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (hex1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (hex1_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (hex1_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (hex1_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (hex1_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_chipselect (hex1_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) hex2_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (hex2_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (hex2_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (hex2_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (hex2_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (hex2_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (hex2_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (hex2_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (hex2_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (hex2_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (hex2_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (hex2_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (hex2_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (hex2_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_chipselect (hex2_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) hex3_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (hex3_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (hex3_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (hex3_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (hex3_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (hex3_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (hex3_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (hex3_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (hex3_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (hex3_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (hex3_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (hex3_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (hex3_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (hex3_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_chipselect (hex3_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) hex4_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (hex4_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (hex4_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (hex4_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (hex4_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (hex4_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (hex4_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (hex4_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (hex4_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (hex4_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (hex4_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (hex4_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (hex4_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (hex4_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_chipselect (hex4_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) hex5_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (hex5_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (hex5_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (hex5_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (hex5_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (hex5_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (hex5_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (hex5_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (hex5_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (hex5_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (hex5_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (hex5_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (hex5_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (hex5_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_chipselect (hex5_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) hex6_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (hex6_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (hex6_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (hex6_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (hex6_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (hex6_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (hex6_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (hex6_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (hex6_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (hex6_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (hex6_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (hex6_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (hex6_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (hex6_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_chipselect (hex6_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) hex7_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (hex7_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (hex7_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (hex7_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (hex7_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (hex7_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (hex7_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (hex7_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (hex7_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (hex7_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (hex7_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (hex7_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (hex7_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (hex7_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_chipselect (hex7_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (8), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (13), - .AV_WRITE_WAIT_CYCLES (13), - .AV_SETUP_WAIT_CYCLES (13), - .AV_DATA_HOLD_CYCLES (13) - ) lcd_16207_0_control_slave_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_write), // .write - .av_read (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_read), // .read - .av_readdata (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_writedata), // .writedata - .av_begintransfer (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_begintransfer), // .begintransfer - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_chipselect (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) lcd_on_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (lcd_on_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (lcd_on_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (lcd_on_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (lcd_on_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_chipselect (lcd_on_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) - ) lcd_blon_s1_translator ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // reset.reset - .uav_address (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address - .uav_burstcount (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .uav_read (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .uav_write (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .uav_waitrequest (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .uav_readdatavalid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .uav_byteenable (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .uav_readdata (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .uav_writedata (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .uav_lock (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .uav_debugaccess (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .av_address (lcd_blon_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address - .av_write (lcd_blon_s1_translator_avalon_anti_slave_0_write), // .write - .av_readdata (lcd_blon_s1_translator_avalon_anti_slave_0_readdata), // .readdata - .av_writedata (lcd_blon_s1_translator_avalon_anti_slave_0_writedata), // .writedata - .av_chipselect (lcd_blon_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect - .av_read (), // (terminated) - .av_begintransfer (), // (terminated) - .av_beginbursttransfer (), // (terminated) - .av_burstcount (), // (terminated) - .av_byteenable (), // (terminated) - .av_readdatavalid (1'b0), // (terminated) - .av_waitrequest (1'b0), // (terminated) - .av_writebyteenable (), // (terminated) - .av_lock (), // (terminated) - .av_clken (), // (terminated) - .uav_clken (1'b0), // (terminated) - .av_debugaccess (), // (terminated) - .av_outputenable (), // (terminated) - .uav_response (), // (terminated) - .av_response (2'b00), // (terminated) - .uav_writeresponserequest (1'b0), // (terminated) - .uav_writeresponsevalid (), // (terminated) - .av_writeresponserequest (), // (terminated) - .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_master_agent #( - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_BEGIN_BURST (74), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .PKT_BURST_TYPE_H (71), - .PKT_BURST_TYPE_L (70), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_TRANS_EXCLUSIVE (60), - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_THREAD_ID_H (86), - .PKT_THREAD_ID_L (86), - .PKT_CACHE_H (93), - .PKT_CACHE_L (90), - .PKT_DATA_SIDEBAND_H (73), - .PKT_DATA_SIDEBAND_L (73), - .PKT_QOS_H (75), - .PKT_QOS_L (75), - .PKT_ADDR_SIDEBAND_H (72), - .PKT_ADDR_SIDEBAND_L (72), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .ST_DATA_W (96), - .ST_CHANNEL_W (18), - .AV_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_RSP (0), - .ID (1), - .BURSTWRAP_VALUE (3), - .CACHE_VALUE (0), - .SECURE_ACCESS_BIT (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) nios2_processor_instruction_master_translator_avalon_universal_master_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .av_address (nios2_processor_instruction_master_translator_avalon_universal_master_0_address), // av.address - .av_write (nios2_processor_instruction_master_translator_avalon_universal_master_0_write), // .write - .av_read (nios2_processor_instruction_master_translator_avalon_universal_master_0_read), // .read - .av_writedata (nios2_processor_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata - .av_readdata (nios2_processor_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata - .av_waitrequest (nios2_processor_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest - .av_readdatavalid (nios2_processor_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid - .av_byteenable (nios2_processor_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable - .av_burstcount (nios2_processor_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount - .av_debugaccess (nios2_processor_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess - .av_lock (nios2_processor_instruction_master_translator_avalon_universal_master_0_lock), // .lock - .cp_valid (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid - .cp_data (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data - .cp_startofpacket (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket - .cp_endofpacket (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket - .cp_ready (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready - .rp_valid (rsp_xbar_mux_src_valid), // rp.valid - .rp_data (rsp_xbar_mux_src_data), // .data - .rp_channel (rsp_xbar_mux_src_channel), // .channel - .rp_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket - .rp_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket - .rp_ready (rsp_xbar_mux_src_ready), // .ready - .av_response (), // (terminated) - .av_writeresponserequest (1'b0), // (terminated) - .av_writeresponsevalid () // (terminated) - ); - - altera_merlin_master_agent #( - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_BEGIN_BURST (74), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .PKT_BURST_TYPE_H (71), - .PKT_BURST_TYPE_L (70), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_TRANS_EXCLUSIVE (60), - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_THREAD_ID_H (86), - .PKT_THREAD_ID_L (86), - .PKT_CACHE_H (93), - .PKT_CACHE_L (90), - .PKT_DATA_SIDEBAND_H (73), - .PKT_DATA_SIDEBAND_L (73), - .PKT_QOS_H (75), - .PKT_QOS_L (75), - .PKT_ADDR_SIDEBAND_H (72), - .PKT_ADDR_SIDEBAND_L (72), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .ST_DATA_W (96), - .ST_CHANNEL_W (18), - .AV_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_RSP (0), - .ID (0), - .BURSTWRAP_VALUE (7), - .CACHE_VALUE (0), - .SECURE_ACCESS_BIT (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) nios2_processor_data_master_translator_avalon_universal_master_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .av_address (nios2_processor_data_master_translator_avalon_universal_master_0_address), // av.address - .av_write (nios2_processor_data_master_translator_avalon_universal_master_0_write), // .write - .av_read (nios2_processor_data_master_translator_avalon_universal_master_0_read), // .read - .av_writedata (nios2_processor_data_master_translator_avalon_universal_master_0_writedata), // .writedata - .av_readdata (nios2_processor_data_master_translator_avalon_universal_master_0_readdata), // .readdata - .av_waitrequest (nios2_processor_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest - .av_readdatavalid (nios2_processor_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid - .av_byteenable (nios2_processor_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable - .av_burstcount (nios2_processor_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount - .av_debugaccess (nios2_processor_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess - .av_lock (nios2_processor_data_master_translator_avalon_universal_master_0_lock), // .lock - .cp_valid (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid - .cp_data (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data - .cp_startofpacket (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket - .cp_endofpacket (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket - .cp_ready (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready - .rp_valid (rsp_xbar_mux_001_src_valid), // rp.valid - .rp_data (rsp_xbar_mux_001_src_data), // .data - .rp_channel (rsp_xbar_mux_001_src_channel), // .channel - .rp_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket - .rp_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket - .rp_ready (rsp_xbar_mux_001_src_ready), // .ready - .av_response (), // (terminated) - .av_writeresponserequest (1'b0), // (terminated) - .av_writeresponsevalid () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_mux_src_ready), // cp.ready - .cp_valid (cmd_xbar_mux_src_valid), // .valid - .cp_data (cmd_xbar_mux_src_data), // .data - .cp_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_mux_src_channel), // .channel - .rf_sink_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) onchip_memory_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_mux_001_src_ready), // cp.ready - .cp_valid (cmd_xbar_mux_001_src_valid), // .valid - .cp_data (cmd_xbar_mux_001_src_data), // .data - .cp_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_mux_001_src_channel), // .channel - .rf_sink_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) leds_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (leds_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (leds_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (leds_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (leds_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (leds_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (leds_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (leds_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src2_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src2_valid), // .valid - .cp_data (cmd_xbar_demux_001_src2_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src2_channel), // .channel - .rf_sink_ready (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src3_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src3_valid), // .valid - .cp_data (cmd_xbar_demux_001_src3_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src3_channel), // .channel - .rf_sink_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) ledrs_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src4_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src4_valid), // .valid - .cp_data (cmd_xbar_demux_001_src4_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src4_channel), // .channel - .rf_sink_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) switches_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (switches_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (switches_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (switches_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (switches_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (switches_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (switches_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (switches_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src5_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src5_valid), // .valid - .cp_data (cmd_xbar_demux_001_src5_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src5_channel), // .channel - .rf_sink_ready (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) push_switches_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src6_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src6_valid), // .valid - .cp_data (cmd_xbar_demux_001_src6_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src6_channel), // .channel - .rf_sink_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) hex0_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (hex0_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (hex0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (hex0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (hex0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (hex0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (hex0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (hex0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (hex0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (hex0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (hex0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src7_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src7_valid), // .valid - .cp_data (cmd_xbar_demux_001_src7_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src7_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src7_channel), // .channel - .rf_sink_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) hex1_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (hex1_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (hex1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (hex1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (hex1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (hex1_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (hex1_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (hex1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (hex1_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (hex1_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (hex1_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src8_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src8_valid), // .valid - .cp_data (cmd_xbar_demux_001_src8_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src8_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src8_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src8_channel), // .channel - .rf_sink_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) hex2_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (hex2_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (hex2_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (hex2_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (hex2_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (hex2_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (hex2_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (hex2_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (hex2_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (hex2_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (hex2_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src9_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src9_valid), // .valid - .cp_data (cmd_xbar_demux_001_src9_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src9_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src9_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src9_channel), // .channel - .rf_sink_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) hex3_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (hex3_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (hex3_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (hex3_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (hex3_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (hex3_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (hex3_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (hex3_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (hex3_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (hex3_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (hex3_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src10_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src10_valid), // .valid - .cp_data (cmd_xbar_demux_001_src10_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src10_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src10_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src10_channel), // .channel - .rf_sink_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) hex4_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (hex4_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (hex4_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (hex4_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (hex4_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (hex4_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (hex4_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (hex4_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (hex4_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (hex4_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (hex4_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src11_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src11_valid), // .valid - .cp_data (cmd_xbar_demux_001_src11_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src11_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src11_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src11_channel), // .channel - .rf_sink_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) hex5_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (hex5_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (hex5_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (hex5_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (hex5_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (hex5_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (hex5_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (hex5_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (hex5_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (hex5_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (hex5_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src12_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src12_valid), // .valid - .cp_data (cmd_xbar_demux_001_src12_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src12_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src12_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src12_channel), // .channel - .rf_sink_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) hex6_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (hex6_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (hex6_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (hex6_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (hex6_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (hex6_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (hex6_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (hex6_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (hex6_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (hex6_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (hex6_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src13_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src13_valid), // .valid - .cp_data (cmd_xbar_demux_001_src13_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src13_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src13_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src13_channel), // .channel - .rf_sink_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) hex7_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (hex7_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (hex7_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (hex7_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (hex7_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (hex7_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (hex7_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (hex7_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (hex7_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (hex7_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (hex7_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src14_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src14_valid), // .valid - .cp_data (cmd_xbar_demux_001_src14_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src14_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src14_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src14_channel), // .channel - .rf_sink_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src15_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src15_valid), // .valid - .cp_data (cmd_xbar_demux_001_src15_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src15_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src15_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src15_channel), // .channel - .rf_sink_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) lcd_on_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src16_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src16_valid), // .valid - .cp_data (cmd_xbar_demux_001_src16_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src16_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src16_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src16_channel), // .channel - .rf_sink_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) - ) lcd_blon_s1_translator_avalon_universal_slave_0_agent ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .m0_address (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address - .m0_burstcount (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount - .m0_byteenable (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable - .m0_debugaccess (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess - .m0_lock (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock - .m0_readdata (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata - .m0_readdatavalid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid - .m0_read (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read - .m0_waitrequest (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest - .m0_writedata (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata - .m0_write (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write - .rp_endofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket - .rp_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready - .rp_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .rp_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .rp_startofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_xbar_demux_001_src17_ready), // cp.ready - .cp_valid (cmd_xbar_demux_001_src17_valid), // .valid - .cp_data (cmd_xbar_demux_001_src17_data), // .data - .cp_startofpacket (cmd_xbar_demux_001_src17_startofpacket), // .startofpacket - .cp_endofpacket (cmd_xbar_demux_001_src17_endofpacket), // .endofpacket - .cp_channel (cmd_xbar_demux_001_src17_channel), // .channel - .rf_sink_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready - .rf_sink_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .rf_sink_startofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .rf_sink_endofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .rf_sink_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data - .rf_source_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready - .rf_source_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .rf_source_startofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .rf_source_endofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .rf_source_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_sink_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .rdata_fifo_src_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready - .rdata_fifo_src_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid - .rdata_fifo_src_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data - .m0_response (2'b00), // (terminated) - .m0_writeresponserequest (), // (terminated) - .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ) lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .in_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data - .in_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid - .in_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready - .in_startofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket - .in_endofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket - .out_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data - .out_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid - .out_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready - .out_startofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket - .out_endofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket - .csr_address (2'b00), // (terminated) - .csr_read (1'b0), // (terminated) - .csr_write (1'b0), // (terminated) - .csr_readdata (), // (terminated) - .csr_writedata (32'b00000000000000000000000000000000), // (terminated) - .almost_full_data (), // (terminated) - .almost_empty_data (), // (terminated) - .in_empty (1'b0), // (terminated) - .out_empty (), // (terminated) - .in_error (1'b0), // (terminated) - .out_error (), // (terminated) - .in_channel (1'b0), // (terminated) - .out_channel () // (terminated) - ); - - nios_system_addr_router addr_router ( - .sink_ready (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready - .sink_valid (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid - .sink_data (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data - .sink_startofpacket (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket - .sink_endofpacket (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (addr_router_src_ready), // src.ready - .src_valid (addr_router_src_valid), // .valid - .src_data (addr_router_src_data), // .data - .src_channel (addr_router_src_channel), // .channel - .src_startofpacket (addr_router_src_startofpacket), // .startofpacket - .src_endofpacket (addr_router_src_endofpacket) // .endofpacket - ); - - nios_system_addr_router_001 addr_router_001 ( - .sink_ready (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready - .sink_valid (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid - .sink_data (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data - .sink_startofpacket (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket - .sink_endofpacket (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (addr_router_001_src_ready), // src.ready - .src_valid (addr_router_001_src_valid), // .valid - .src_data (addr_router_001_src_data), // .data - .src_channel (addr_router_001_src_channel), // .channel - .src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket - .src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket - ); - - nios_system_id_router id_router ( - .sink_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_src_ready), // src.ready - .src_valid (id_router_src_valid), // .valid - .src_data (id_router_src_data), // .data - .src_channel (id_router_src_channel), // .channel - .src_startofpacket (id_router_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_src_endofpacket) // .endofpacket - ); - - nios_system_id_router id_router_001 ( - .sink_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_001_src_ready), // src.ready - .src_valid (id_router_001_src_valid), // .valid - .src_data (id_router_001_src_data), // .data - .src_channel (id_router_001_src_channel), // .channel - .src_startofpacket (id_router_001_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_001_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_002 ( - .sink_ready (leds_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (leds_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (leds_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_002_src_ready), // src.ready - .src_valid (id_router_002_src_valid), // .valid - .src_data (id_router_002_src_data), // .data - .src_channel (id_router_002_src_channel), // .channel - .src_startofpacket (id_router_002_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_002_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_003 ( - .sink_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_003_src_ready), // src.ready - .src_valid (id_router_003_src_valid), // .valid - .src_data (id_router_003_src_data), // .data - .src_channel (id_router_003_src_channel), // .channel - .src_startofpacket (id_router_003_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_003_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_004 ( - .sink_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_004_src_ready), // src.ready - .src_valid (id_router_004_src_valid), // .valid - .src_data (id_router_004_src_data), // .data - .src_channel (id_router_004_src_channel), // .channel - .src_startofpacket (id_router_004_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_004_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_005 ( - .sink_ready (switches_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (switches_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (switches_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_005_src_ready), // src.ready - .src_valid (id_router_005_src_valid), // .valid - .src_data (id_router_005_src_data), // .data - .src_channel (id_router_005_src_channel), // .channel - .src_startofpacket (id_router_005_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_005_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_006 ( - .sink_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_006_src_ready), // src.ready - .src_valid (id_router_006_src_valid), // .valid - .src_data (id_router_006_src_data), // .data - .src_channel (id_router_006_src_channel), // .channel - .src_startofpacket (id_router_006_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_006_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_007 ( - .sink_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (hex0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_007_src_ready), // src.ready - .src_valid (id_router_007_src_valid), // .valid - .src_data (id_router_007_src_data), // .data - .src_channel (id_router_007_src_channel), // .channel - .src_startofpacket (id_router_007_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_007_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_008 ( - .sink_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (hex1_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_008_src_ready), // src.ready - .src_valid (id_router_008_src_valid), // .valid - .src_data (id_router_008_src_data), // .data - .src_channel (id_router_008_src_channel), // .channel - .src_startofpacket (id_router_008_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_008_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_009 ( - .sink_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (hex2_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_009_src_ready), // src.ready - .src_valid (id_router_009_src_valid), // .valid - .src_data (id_router_009_src_data), // .data - .src_channel (id_router_009_src_channel), // .channel - .src_startofpacket (id_router_009_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_009_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_010 ( - .sink_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (hex3_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_010_src_ready), // src.ready - .src_valid (id_router_010_src_valid), // .valid - .src_data (id_router_010_src_data), // .data - .src_channel (id_router_010_src_channel), // .channel - .src_startofpacket (id_router_010_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_010_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_011 ( - .sink_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (hex4_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_011_src_ready), // src.ready - .src_valid (id_router_011_src_valid), // .valid - .src_data (id_router_011_src_data), // .data - .src_channel (id_router_011_src_channel), // .channel - .src_startofpacket (id_router_011_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_011_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_012 ( - .sink_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (hex5_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_012_src_ready), // src.ready - .src_valid (id_router_012_src_valid), // .valid - .src_data (id_router_012_src_data), // .data - .src_channel (id_router_012_src_channel), // .channel - .src_startofpacket (id_router_012_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_012_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_013 ( - .sink_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (hex6_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_013_src_ready), // src.ready - .src_valid (id_router_013_src_valid), // .valid - .src_data (id_router_013_src_data), // .data - .src_channel (id_router_013_src_channel), // .channel - .src_startofpacket (id_router_013_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_013_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_014 ( - .sink_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (hex7_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_014_src_ready), // src.ready - .src_valid (id_router_014_src_valid), // .valid - .src_data (id_router_014_src_data), // .data - .src_channel (id_router_014_src_channel), // .channel - .src_startofpacket (id_router_014_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_014_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_015 ( - .sink_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_015_src_ready), // src.ready - .src_valid (id_router_015_src_valid), // .valid - .src_data (id_router_015_src_data), // .data - .src_channel (id_router_015_src_channel), // .channel - .src_startofpacket (id_router_015_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_015_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_016 ( - .sink_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_016_src_ready), // src.ready - .src_valid (id_router_016_src_valid), // .valid - .src_data (id_router_016_src_data), // .data - .src_channel (id_router_016_src_channel), // .channel - .src_startofpacket (id_router_016_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_016_src_endofpacket) // .endofpacket - ); - - nios_system_id_router_002 id_router_017 ( - .sink_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready - .sink_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid - .sink_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data - .sink_startofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (id_router_017_src_ready), // src.ready - .src_valid (id_router_017_src_valid), // .valid - .src_data (id_router_017_src_data), // .data - .src_channel (id_router_017_src_channel), // .channel - .src_startofpacket (id_router_017_src_startofpacket), // .startofpacket - .src_endofpacket (id_router_017_src_endofpacket) // .endofpacket - ); - - altera_reset_controller #( - .NUM_RESET_INPUTS (2), - .OUTPUT_RESET_SYNC_EDGES ("deassert"), - .SYNC_DEPTH (2), - .RESET_REQUEST_PRESENT (1) - ) rst_controller ( - .reset_in0 (~reset_reset_n), // reset_in0.reset - .reset_in1 (nios2_processor_jtag_debug_module_reset_reset), // reset_in1.reset - .clk (clk_clk), // clk.clk - .reset_out (rst_controller_reset_out_reset), // reset_out.reset - .reset_req (rst_controller_reset_out_reset_req), // .reset_req - .reset_in2 (1'b0), // (terminated) - .reset_in3 (1'b0), // (terminated) - .reset_in4 (1'b0), // (terminated) - .reset_in5 (1'b0), // (terminated) - .reset_in6 (1'b0), // (terminated) - .reset_in7 (1'b0), // (terminated) - .reset_in8 (1'b0), // (terminated) - .reset_in9 (1'b0), // (terminated) - .reset_in10 (1'b0), // (terminated) - .reset_in11 (1'b0), // (terminated) - .reset_in12 (1'b0), // (terminated) - .reset_in13 (1'b0), // (terminated) - .reset_in14 (1'b0), // (terminated) - .reset_in15 (1'b0) // (terminated) - ); - - nios_system_cmd_xbar_demux cmd_xbar_demux ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (addr_router_src_ready), // sink.ready - .sink_channel (addr_router_src_channel), // .channel - .sink_data (addr_router_src_data), // .data - .sink_startofpacket (addr_router_src_startofpacket), // .startofpacket - .sink_endofpacket (addr_router_src_endofpacket), // .endofpacket - .sink_valid (addr_router_src_valid), // .valid - .src0_ready (cmd_xbar_demux_src0_ready), // src0.ready - .src0_valid (cmd_xbar_demux_src0_valid), // .valid - .src0_data (cmd_xbar_demux_src0_data), // .data - .src0_channel (cmd_xbar_demux_src0_channel), // .channel - .src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket - .src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket - .src1_ready (cmd_xbar_demux_src1_ready), // src1.ready - .src1_valid (cmd_xbar_demux_src1_valid), // .valid - .src1_data (cmd_xbar_demux_src1_data), // .data - .src1_channel (cmd_xbar_demux_src1_channel), // .channel - .src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket - .src1_endofpacket (cmd_xbar_demux_src1_endofpacket) // .endofpacket - ); - - nios_system_cmd_xbar_demux_001 cmd_xbar_demux_001 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (addr_router_001_src_ready), // sink.ready - .sink_channel (addr_router_001_src_channel), // .channel - .sink_data (addr_router_001_src_data), // .data - .sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket - .sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket - .sink_valid (addr_router_001_src_valid), // .valid - .src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready - .src0_valid (cmd_xbar_demux_001_src0_valid), // .valid - .src0_data (cmd_xbar_demux_001_src0_data), // .data - .src0_channel (cmd_xbar_demux_001_src0_channel), // .channel - .src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket - .src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket - .src1_ready (cmd_xbar_demux_001_src1_ready), // src1.ready - .src1_valid (cmd_xbar_demux_001_src1_valid), // .valid - .src1_data (cmd_xbar_demux_001_src1_data), // .data - .src1_channel (cmd_xbar_demux_001_src1_channel), // .channel - .src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket - .src1_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket - .src2_ready (cmd_xbar_demux_001_src2_ready), // src2.ready - .src2_valid (cmd_xbar_demux_001_src2_valid), // .valid - .src2_data (cmd_xbar_demux_001_src2_data), // .data - .src2_channel (cmd_xbar_demux_001_src2_channel), // .channel - .src2_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket - .src2_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket - .src3_ready (cmd_xbar_demux_001_src3_ready), // src3.ready - .src3_valid (cmd_xbar_demux_001_src3_valid), // .valid - .src3_data (cmd_xbar_demux_001_src3_data), // .data - .src3_channel (cmd_xbar_demux_001_src3_channel), // .channel - .src3_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket - .src3_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket - .src4_ready (cmd_xbar_demux_001_src4_ready), // src4.ready - .src4_valid (cmd_xbar_demux_001_src4_valid), // .valid - .src4_data (cmd_xbar_demux_001_src4_data), // .data - .src4_channel (cmd_xbar_demux_001_src4_channel), // .channel - .src4_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket - .src4_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket - .src5_ready (cmd_xbar_demux_001_src5_ready), // src5.ready - .src5_valid (cmd_xbar_demux_001_src5_valid), // .valid - .src5_data (cmd_xbar_demux_001_src5_data), // .data - .src5_channel (cmd_xbar_demux_001_src5_channel), // .channel - .src5_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket - .src5_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket - .src6_ready (cmd_xbar_demux_001_src6_ready), // src6.ready - .src6_valid (cmd_xbar_demux_001_src6_valid), // .valid - .src6_data (cmd_xbar_demux_001_src6_data), // .data - .src6_channel (cmd_xbar_demux_001_src6_channel), // .channel - .src6_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket - .src6_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket - .src7_ready (cmd_xbar_demux_001_src7_ready), // src7.ready - .src7_valid (cmd_xbar_demux_001_src7_valid), // .valid - .src7_data (cmd_xbar_demux_001_src7_data), // .data - .src7_channel (cmd_xbar_demux_001_src7_channel), // .channel - .src7_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket - .src7_endofpacket (cmd_xbar_demux_001_src7_endofpacket), // .endofpacket - .src8_ready (cmd_xbar_demux_001_src8_ready), // src8.ready - .src8_valid (cmd_xbar_demux_001_src8_valid), // .valid - .src8_data (cmd_xbar_demux_001_src8_data), // .data - .src8_channel (cmd_xbar_demux_001_src8_channel), // .channel - .src8_startofpacket (cmd_xbar_demux_001_src8_startofpacket), // .startofpacket - .src8_endofpacket (cmd_xbar_demux_001_src8_endofpacket), // .endofpacket - .src9_ready (cmd_xbar_demux_001_src9_ready), // src9.ready - .src9_valid (cmd_xbar_demux_001_src9_valid), // .valid - .src9_data (cmd_xbar_demux_001_src9_data), // .data - .src9_channel (cmd_xbar_demux_001_src9_channel), // .channel - .src9_startofpacket (cmd_xbar_demux_001_src9_startofpacket), // .startofpacket - .src9_endofpacket (cmd_xbar_demux_001_src9_endofpacket), // .endofpacket - .src10_ready (cmd_xbar_demux_001_src10_ready), // src10.ready - .src10_valid (cmd_xbar_demux_001_src10_valid), // .valid - .src10_data (cmd_xbar_demux_001_src10_data), // .data - .src10_channel (cmd_xbar_demux_001_src10_channel), // .channel - .src10_startofpacket (cmd_xbar_demux_001_src10_startofpacket), // .startofpacket - .src10_endofpacket (cmd_xbar_demux_001_src10_endofpacket), // .endofpacket - .src11_ready (cmd_xbar_demux_001_src11_ready), // src11.ready - .src11_valid (cmd_xbar_demux_001_src11_valid), // .valid - .src11_data (cmd_xbar_demux_001_src11_data), // .data - .src11_channel (cmd_xbar_demux_001_src11_channel), // .channel - .src11_startofpacket (cmd_xbar_demux_001_src11_startofpacket), // .startofpacket - .src11_endofpacket (cmd_xbar_demux_001_src11_endofpacket), // .endofpacket - .src12_ready (cmd_xbar_demux_001_src12_ready), // src12.ready - .src12_valid (cmd_xbar_demux_001_src12_valid), // .valid - .src12_data (cmd_xbar_demux_001_src12_data), // .data - .src12_channel (cmd_xbar_demux_001_src12_channel), // .channel - .src12_startofpacket (cmd_xbar_demux_001_src12_startofpacket), // .startofpacket - .src12_endofpacket (cmd_xbar_demux_001_src12_endofpacket), // .endofpacket - .src13_ready (cmd_xbar_demux_001_src13_ready), // src13.ready - .src13_valid (cmd_xbar_demux_001_src13_valid), // .valid - .src13_data (cmd_xbar_demux_001_src13_data), // .data - .src13_channel (cmd_xbar_demux_001_src13_channel), // .channel - .src13_startofpacket (cmd_xbar_demux_001_src13_startofpacket), // .startofpacket - .src13_endofpacket (cmd_xbar_demux_001_src13_endofpacket), // .endofpacket - .src14_ready (cmd_xbar_demux_001_src14_ready), // src14.ready - .src14_valid (cmd_xbar_demux_001_src14_valid), // .valid - .src14_data (cmd_xbar_demux_001_src14_data), // .data - .src14_channel (cmd_xbar_demux_001_src14_channel), // .channel - .src14_startofpacket (cmd_xbar_demux_001_src14_startofpacket), // .startofpacket - .src14_endofpacket (cmd_xbar_demux_001_src14_endofpacket), // .endofpacket - .src15_ready (cmd_xbar_demux_001_src15_ready), // src15.ready - .src15_valid (cmd_xbar_demux_001_src15_valid), // .valid - .src15_data (cmd_xbar_demux_001_src15_data), // .data - .src15_channel (cmd_xbar_demux_001_src15_channel), // .channel - .src15_startofpacket (cmd_xbar_demux_001_src15_startofpacket), // .startofpacket - .src15_endofpacket (cmd_xbar_demux_001_src15_endofpacket), // .endofpacket - .src16_ready (cmd_xbar_demux_001_src16_ready), // src16.ready - .src16_valid (cmd_xbar_demux_001_src16_valid), // .valid - .src16_data (cmd_xbar_demux_001_src16_data), // .data - .src16_channel (cmd_xbar_demux_001_src16_channel), // .channel - .src16_startofpacket (cmd_xbar_demux_001_src16_startofpacket), // .startofpacket - .src16_endofpacket (cmd_xbar_demux_001_src16_endofpacket), // .endofpacket - .src17_ready (cmd_xbar_demux_001_src17_ready), // src17.ready - .src17_valid (cmd_xbar_demux_001_src17_valid), // .valid - .src17_data (cmd_xbar_demux_001_src17_data), // .data - .src17_channel (cmd_xbar_demux_001_src17_channel), // .channel - .src17_startofpacket (cmd_xbar_demux_001_src17_startofpacket), // .startofpacket - .src17_endofpacket (cmd_xbar_demux_001_src17_endofpacket) // .endofpacket - ); - - nios_system_cmd_xbar_mux cmd_xbar_mux ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (cmd_xbar_mux_src_ready), // src.ready - .src_valid (cmd_xbar_mux_src_valid), // .valid - .src_data (cmd_xbar_mux_src_data), // .data - .src_channel (cmd_xbar_mux_src_channel), // .channel - .src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket - .src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket - .sink0_ready (cmd_xbar_demux_src0_ready), // sink0.ready - .sink0_valid (cmd_xbar_demux_src0_valid), // .valid - .sink0_channel (cmd_xbar_demux_src0_channel), // .channel - .sink0_data (cmd_xbar_demux_src0_data), // .data - .sink0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket - .sink0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket - .sink1_ready (cmd_xbar_demux_001_src0_ready), // sink1.ready - .sink1_valid (cmd_xbar_demux_001_src0_valid), // .valid - .sink1_channel (cmd_xbar_demux_001_src0_channel), // .channel - .sink1_data (cmd_xbar_demux_001_src0_data), // .data - .sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket - .sink1_endofpacket (cmd_xbar_demux_001_src0_endofpacket) // .endofpacket - ); - - nios_system_cmd_xbar_mux cmd_xbar_mux_001 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (cmd_xbar_mux_001_src_ready), // src.ready - .src_valid (cmd_xbar_mux_001_src_valid), // .valid - .src_data (cmd_xbar_mux_001_src_data), // .data - .src_channel (cmd_xbar_mux_001_src_channel), // .channel - .src_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket - .src_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket - .sink0_ready (cmd_xbar_demux_src1_ready), // sink0.ready - .sink0_valid (cmd_xbar_demux_src1_valid), // .valid - .sink0_channel (cmd_xbar_demux_src1_channel), // .channel - .sink0_data (cmd_xbar_demux_src1_data), // .data - .sink0_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket - .sink0_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket - .sink1_ready (cmd_xbar_demux_001_src1_ready), // sink1.ready - .sink1_valid (cmd_xbar_demux_001_src1_valid), // .valid - .sink1_channel (cmd_xbar_demux_001_src1_channel), // .channel - .sink1_data (cmd_xbar_demux_001_src1_data), // .data - .sink1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket - .sink1_endofpacket (cmd_xbar_demux_001_src1_endofpacket) // .endofpacket - ); - - nios_system_cmd_xbar_demux rsp_xbar_demux ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_src_ready), // sink.ready - .sink_channel (id_router_src_channel), // .channel - .sink_data (id_router_src_data), // .data - .sink_startofpacket (id_router_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_src_endofpacket), // .endofpacket - .sink_valid (id_router_src_valid), // .valid - .src0_ready (rsp_xbar_demux_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_src0_valid), // .valid - .src0_data (rsp_xbar_demux_src0_data), // .data - .src0_channel (rsp_xbar_demux_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket - .src1_ready (rsp_xbar_demux_src1_ready), // src1.ready - .src1_valid (rsp_xbar_demux_src1_valid), // .valid - .src1_data (rsp_xbar_demux_src1_data), // .data - .src1_channel (rsp_xbar_demux_src1_channel), // .channel - .src1_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket - .src1_endofpacket (rsp_xbar_demux_src1_endofpacket) // .endofpacket - ); - - nios_system_cmd_xbar_demux rsp_xbar_demux_001 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_001_src_ready), // sink.ready - .sink_channel (id_router_001_src_channel), // .channel - .sink_data (id_router_001_src_data), // .data - .sink_startofpacket (id_router_001_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_001_src_endofpacket), // .endofpacket - .sink_valid (id_router_001_src_valid), // .valid - .src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_001_src0_valid), // .valid - .src0_data (rsp_xbar_demux_001_src0_data), // .data - .src0_channel (rsp_xbar_demux_001_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket - .src1_ready (rsp_xbar_demux_001_src1_ready), // src1.ready - .src1_valid (rsp_xbar_demux_001_src1_valid), // .valid - .src1_data (rsp_xbar_demux_001_src1_data), // .data - .src1_channel (rsp_xbar_demux_001_src1_channel), // .channel - .src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket - .src1_endofpacket (rsp_xbar_demux_001_src1_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_002 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_002_src_ready), // sink.ready - .sink_channel (id_router_002_src_channel), // .channel - .sink_data (id_router_002_src_data), // .data - .sink_startofpacket (id_router_002_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_002_src_endofpacket), // .endofpacket - .sink_valid (id_router_002_src_valid), // .valid - .src0_ready (rsp_xbar_demux_002_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_002_src0_valid), // .valid - .src0_data (rsp_xbar_demux_002_src0_data), // .data - .src0_channel (rsp_xbar_demux_002_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_002_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_003 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_003_src_ready), // sink.ready - .sink_channel (id_router_003_src_channel), // .channel - .sink_data (id_router_003_src_data), // .data - .sink_startofpacket (id_router_003_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_003_src_endofpacket), // .endofpacket - .sink_valid (id_router_003_src_valid), // .valid - .src0_ready (rsp_xbar_demux_003_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_003_src0_valid), // .valid - .src0_data (rsp_xbar_demux_003_src0_data), // .data - .src0_channel (rsp_xbar_demux_003_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_003_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_004 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_004_src_ready), // sink.ready - .sink_channel (id_router_004_src_channel), // .channel - .sink_data (id_router_004_src_data), // .data - .sink_startofpacket (id_router_004_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_004_src_endofpacket), // .endofpacket - .sink_valid (id_router_004_src_valid), // .valid - .src0_ready (rsp_xbar_demux_004_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_004_src0_valid), // .valid - .src0_data (rsp_xbar_demux_004_src0_data), // .data - .src0_channel (rsp_xbar_demux_004_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_004_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_005 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_005_src_ready), // sink.ready - .sink_channel (id_router_005_src_channel), // .channel - .sink_data (id_router_005_src_data), // .data - .sink_startofpacket (id_router_005_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_005_src_endofpacket), // .endofpacket - .sink_valid (id_router_005_src_valid), // .valid - .src0_ready (rsp_xbar_demux_005_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_005_src0_valid), // .valid - .src0_data (rsp_xbar_demux_005_src0_data), // .data - .src0_channel (rsp_xbar_demux_005_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_006 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_006_src_ready), // sink.ready - .sink_channel (id_router_006_src_channel), // .channel - .sink_data (id_router_006_src_data), // .data - .sink_startofpacket (id_router_006_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_006_src_endofpacket), // .endofpacket - .sink_valid (id_router_006_src_valid), // .valid - .src0_ready (rsp_xbar_demux_006_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_006_src0_valid), // .valid - .src0_data (rsp_xbar_demux_006_src0_data), // .data - .src0_channel (rsp_xbar_demux_006_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_006_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_007 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_007_src_ready), // sink.ready - .sink_channel (id_router_007_src_channel), // .channel - .sink_data (id_router_007_src_data), // .data - .sink_startofpacket (id_router_007_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_007_src_endofpacket), // .endofpacket - .sink_valid (id_router_007_src_valid), // .valid - .src0_ready (rsp_xbar_demux_007_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_007_src0_valid), // .valid - .src0_data (rsp_xbar_demux_007_src0_data), // .data - .src0_channel (rsp_xbar_demux_007_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_007_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_008 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_008_src_ready), // sink.ready - .sink_channel (id_router_008_src_channel), // .channel - .sink_data (id_router_008_src_data), // .data - .sink_startofpacket (id_router_008_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_008_src_endofpacket), // .endofpacket - .sink_valid (id_router_008_src_valid), // .valid - .src0_ready (rsp_xbar_demux_008_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_008_src0_valid), // .valid - .src0_data (rsp_xbar_demux_008_src0_data), // .data - .src0_channel (rsp_xbar_demux_008_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_008_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_009 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_009_src_ready), // sink.ready - .sink_channel (id_router_009_src_channel), // .channel - .sink_data (id_router_009_src_data), // .data - .sink_startofpacket (id_router_009_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_009_src_endofpacket), // .endofpacket - .sink_valid (id_router_009_src_valid), // .valid - .src0_ready (rsp_xbar_demux_009_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_009_src0_valid), // .valid - .src0_data (rsp_xbar_demux_009_src0_data), // .data - .src0_channel (rsp_xbar_demux_009_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_009_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_009_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_010 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_010_src_ready), // sink.ready - .sink_channel (id_router_010_src_channel), // .channel - .sink_data (id_router_010_src_data), // .data - .sink_startofpacket (id_router_010_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_010_src_endofpacket), // .endofpacket - .sink_valid (id_router_010_src_valid), // .valid - .src0_ready (rsp_xbar_demux_010_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_010_src0_valid), // .valid - .src0_data (rsp_xbar_demux_010_src0_data), // .data - .src0_channel (rsp_xbar_demux_010_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_010_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_010_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_011 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_011_src_ready), // sink.ready - .sink_channel (id_router_011_src_channel), // .channel - .sink_data (id_router_011_src_data), // .data - .sink_startofpacket (id_router_011_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_011_src_endofpacket), // .endofpacket - .sink_valid (id_router_011_src_valid), // .valid - .src0_ready (rsp_xbar_demux_011_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_011_src0_valid), // .valid - .src0_data (rsp_xbar_demux_011_src0_data), // .data - .src0_channel (rsp_xbar_demux_011_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_011_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_011_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_012 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_012_src_ready), // sink.ready - .sink_channel (id_router_012_src_channel), // .channel - .sink_data (id_router_012_src_data), // .data - .sink_startofpacket (id_router_012_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_012_src_endofpacket), // .endofpacket - .sink_valid (id_router_012_src_valid), // .valid - .src0_ready (rsp_xbar_demux_012_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_012_src0_valid), // .valid - .src0_data (rsp_xbar_demux_012_src0_data), // .data - .src0_channel (rsp_xbar_demux_012_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_012_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_012_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_013 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_013_src_ready), // sink.ready - .sink_channel (id_router_013_src_channel), // .channel - .sink_data (id_router_013_src_data), // .data - .sink_startofpacket (id_router_013_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_013_src_endofpacket), // .endofpacket - .sink_valid (id_router_013_src_valid), // .valid - .src0_ready (rsp_xbar_demux_013_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_013_src0_valid), // .valid - .src0_data (rsp_xbar_demux_013_src0_data), // .data - .src0_channel (rsp_xbar_demux_013_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_013_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_013_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_014 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_014_src_ready), // sink.ready - .sink_channel (id_router_014_src_channel), // .channel - .sink_data (id_router_014_src_data), // .data - .sink_startofpacket (id_router_014_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_014_src_endofpacket), // .endofpacket - .sink_valid (id_router_014_src_valid), // .valid - .src0_ready (rsp_xbar_demux_014_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_014_src0_valid), // .valid - .src0_data (rsp_xbar_demux_014_src0_data), // .data - .src0_channel (rsp_xbar_demux_014_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_014_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_014_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_015 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_015_src_ready), // sink.ready - .sink_channel (id_router_015_src_channel), // .channel - .sink_data (id_router_015_src_data), // .data - .sink_startofpacket (id_router_015_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_015_src_endofpacket), // .endofpacket - .sink_valid (id_router_015_src_valid), // .valid - .src0_ready (rsp_xbar_demux_015_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_015_src0_valid), // .valid - .src0_data (rsp_xbar_demux_015_src0_data), // .data - .src0_channel (rsp_xbar_demux_015_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_015_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_015_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_016 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_016_src_ready), // sink.ready - .sink_channel (id_router_016_src_channel), // .channel - .sink_data (id_router_016_src_data), // .data - .sink_startofpacket (id_router_016_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_016_src_endofpacket), // .endofpacket - .sink_valid (id_router_016_src_valid), // .valid - .src0_ready (rsp_xbar_demux_016_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_016_src0_valid), // .valid - .src0_data (rsp_xbar_demux_016_src0_data), // .data - .src0_channel (rsp_xbar_demux_016_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_016_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_016_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_demux_002 rsp_xbar_demux_017 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .sink_ready (id_router_017_src_ready), // sink.ready - .sink_channel (id_router_017_src_channel), // .channel - .sink_data (id_router_017_src_data), // .data - .sink_startofpacket (id_router_017_src_startofpacket), // .startofpacket - .sink_endofpacket (id_router_017_src_endofpacket), // .endofpacket - .sink_valid (id_router_017_src_valid), // .valid - .src0_ready (rsp_xbar_demux_017_src0_ready), // src0.ready - .src0_valid (rsp_xbar_demux_017_src0_valid), // .valid - .src0_data (rsp_xbar_demux_017_src0_data), // .data - .src0_channel (rsp_xbar_demux_017_src0_channel), // .channel - .src0_startofpacket (rsp_xbar_demux_017_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_xbar_demux_017_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_mux rsp_xbar_mux ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (rsp_xbar_mux_src_ready), // src.ready - .src_valid (rsp_xbar_mux_src_valid), // .valid - .src_data (rsp_xbar_mux_src_data), // .data - .src_channel (rsp_xbar_mux_src_channel), // .channel - .src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket - .src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket - .sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready - .sink0_valid (rsp_xbar_demux_src0_valid), // .valid - .sink0_channel (rsp_xbar_demux_src0_channel), // .channel - .sink0_data (rsp_xbar_demux_src0_data), // .data - .sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket - .sink0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket - .sink1_ready (rsp_xbar_demux_001_src0_ready), // sink1.ready - .sink1_valid (rsp_xbar_demux_001_src0_valid), // .valid - .sink1_channel (rsp_xbar_demux_001_src0_channel), // .channel - .sink1_data (rsp_xbar_demux_001_src0_data), // .data - .sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket - .sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket) // .endofpacket - ); - - nios_system_rsp_xbar_mux_001 rsp_xbar_mux_001 ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .src_ready (rsp_xbar_mux_001_src_ready), // src.ready - .src_valid (rsp_xbar_mux_001_src_valid), // .valid - .src_data (rsp_xbar_mux_001_src_data), // .data - .src_channel (rsp_xbar_mux_001_src_channel), // .channel - .src_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket - .src_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket - .sink0_ready (rsp_xbar_demux_src1_ready), // sink0.ready - .sink0_valid (rsp_xbar_demux_src1_valid), // .valid - .sink0_channel (rsp_xbar_demux_src1_channel), // .channel - .sink0_data (rsp_xbar_demux_src1_data), // .data - .sink0_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket - .sink0_endofpacket (rsp_xbar_demux_src1_endofpacket), // .endofpacket - .sink1_ready (rsp_xbar_demux_001_src1_ready), // sink1.ready - .sink1_valid (rsp_xbar_demux_001_src1_valid), // .valid - .sink1_channel (rsp_xbar_demux_001_src1_channel), // .channel - .sink1_data (rsp_xbar_demux_001_src1_data), // .data - .sink1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket - .sink1_endofpacket (rsp_xbar_demux_001_src1_endofpacket), // .endofpacket - .sink2_ready (rsp_xbar_demux_002_src0_ready), // sink2.ready - .sink2_valid (rsp_xbar_demux_002_src0_valid), // .valid - .sink2_channel (rsp_xbar_demux_002_src0_channel), // .channel - .sink2_data (rsp_xbar_demux_002_src0_data), // .data - .sink2_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket - .sink2_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket - .sink3_ready (rsp_xbar_demux_003_src0_ready), // sink3.ready - .sink3_valid (rsp_xbar_demux_003_src0_valid), // .valid - .sink3_channel (rsp_xbar_demux_003_src0_channel), // .channel - .sink3_data (rsp_xbar_demux_003_src0_data), // .data - .sink3_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket - .sink3_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket - .sink4_ready (rsp_xbar_demux_004_src0_ready), // sink4.ready - .sink4_valid (rsp_xbar_demux_004_src0_valid), // .valid - .sink4_channel (rsp_xbar_demux_004_src0_channel), // .channel - .sink4_data (rsp_xbar_demux_004_src0_data), // .data - .sink4_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket - .sink4_endofpacket (rsp_xbar_demux_004_src0_endofpacket), // .endofpacket - .sink5_ready (rsp_xbar_demux_005_src0_ready), // sink5.ready - .sink5_valid (rsp_xbar_demux_005_src0_valid), // .valid - .sink5_channel (rsp_xbar_demux_005_src0_channel), // .channel - .sink5_data (rsp_xbar_demux_005_src0_data), // .data - .sink5_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket - .sink5_endofpacket (rsp_xbar_demux_005_src0_endofpacket), // .endofpacket - .sink6_ready (rsp_xbar_demux_006_src0_ready), // sink6.ready - .sink6_valid (rsp_xbar_demux_006_src0_valid), // .valid - .sink6_channel (rsp_xbar_demux_006_src0_channel), // .channel - .sink6_data (rsp_xbar_demux_006_src0_data), // .data - .sink6_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket - .sink6_endofpacket (rsp_xbar_demux_006_src0_endofpacket), // .endofpacket - .sink7_ready (rsp_xbar_demux_007_src0_ready), // sink7.ready - .sink7_valid (rsp_xbar_demux_007_src0_valid), // .valid - .sink7_channel (rsp_xbar_demux_007_src0_channel), // .channel - .sink7_data (rsp_xbar_demux_007_src0_data), // .data - .sink7_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket - .sink7_endofpacket (rsp_xbar_demux_007_src0_endofpacket), // .endofpacket - .sink8_ready (rsp_xbar_demux_008_src0_ready), // sink8.ready - .sink8_valid (rsp_xbar_demux_008_src0_valid), // .valid - .sink8_channel (rsp_xbar_demux_008_src0_channel), // .channel - .sink8_data (rsp_xbar_demux_008_src0_data), // .data - .sink8_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket - .sink8_endofpacket (rsp_xbar_demux_008_src0_endofpacket), // .endofpacket - .sink9_ready (rsp_xbar_demux_009_src0_ready), // sink9.ready - .sink9_valid (rsp_xbar_demux_009_src0_valid), // .valid - .sink9_channel (rsp_xbar_demux_009_src0_channel), // .channel - .sink9_data (rsp_xbar_demux_009_src0_data), // .data - .sink9_startofpacket (rsp_xbar_demux_009_src0_startofpacket), // .startofpacket - .sink9_endofpacket (rsp_xbar_demux_009_src0_endofpacket), // .endofpacket - .sink10_ready (rsp_xbar_demux_010_src0_ready), // sink10.ready - .sink10_valid (rsp_xbar_demux_010_src0_valid), // .valid - .sink10_channel (rsp_xbar_demux_010_src0_channel), // .channel - .sink10_data (rsp_xbar_demux_010_src0_data), // .data - .sink10_startofpacket (rsp_xbar_demux_010_src0_startofpacket), // .startofpacket - .sink10_endofpacket (rsp_xbar_demux_010_src0_endofpacket), // .endofpacket - .sink11_ready (rsp_xbar_demux_011_src0_ready), // sink11.ready - .sink11_valid (rsp_xbar_demux_011_src0_valid), // .valid - .sink11_channel (rsp_xbar_demux_011_src0_channel), // .channel - .sink11_data (rsp_xbar_demux_011_src0_data), // .data - .sink11_startofpacket (rsp_xbar_demux_011_src0_startofpacket), // .startofpacket - .sink11_endofpacket (rsp_xbar_demux_011_src0_endofpacket), // .endofpacket - .sink12_ready (rsp_xbar_demux_012_src0_ready), // sink12.ready - .sink12_valid (rsp_xbar_demux_012_src0_valid), // .valid - .sink12_channel (rsp_xbar_demux_012_src0_channel), // .channel - .sink12_data (rsp_xbar_demux_012_src0_data), // .data - .sink12_startofpacket (rsp_xbar_demux_012_src0_startofpacket), // .startofpacket - .sink12_endofpacket (rsp_xbar_demux_012_src0_endofpacket), // .endofpacket - .sink13_ready (rsp_xbar_demux_013_src0_ready), // sink13.ready - .sink13_valid (rsp_xbar_demux_013_src0_valid), // .valid - .sink13_channel (rsp_xbar_demux_013_src0_channel), // .channel - .sink13_data (rsp_xbar_demux_013_src0_data), // .data - .sink13_startofpacket (rsp_xbar_demux_013_src0_startofpacket), // .startofpacket - .sink13_endofpacket (rsp_xbar_demux_013_src0_endofpacket), // .endofpacket - .sink14_ready (rsp_xbar_demux_014_src0_ready), // sink14.ready - .sink14_valid (rsp_xbar_demux_014_src0_valid), // .valid - .sink14_channel (rsp_xbar_demux_014_src0_channel), // .channel - .sink14_data (rsp_xbar_demux_014_src0_data), // .data - .sink14_startofpacket (rsp_xbar_demux_014_src0_startofpacket), // .startofpacket - .sink14_endofpacket (rsp_xbar_demux_014_src0_endofpacket), // .endofpacket - .sink15_ready (rsp_xbar_demux_015_src0_ready), // sink15.ready - .sink15_valid (rsp_xbar_demux_015_src0_valid), // .valid - .sink15_channel (rsp_xbar_demux_015_src0_channel), // .channel - .sink15_data (rsp_xbar_demux_015_src0_data), // .data - .sink15_startofpacket (rsp_xbar_demux_015_src0_startofpacket), // .startofpacket - .sink15_endofpacket (rsp_xbar_demux_015_src0_endofpacket), // .endofpacket - .sink16_ready (rsp_xbar_demux_016_src0_ready), // sink16.ready - .sink16_valid (rsp_xbar_demux_016_src0_valid), // .valid - .sink16_channel (rsp_xbar_demux_016_src0_channel), // .channel - .sink16_data (rsp_xbar_demux_016_src0_data), // .data - .sink16_startofpacket (rsp_xbar_demux_016_src0_startofpacket), // .startofpacket - .sink16_endofpacket (rsp_xbar_demux_016_src0_endofpacket), // .endofpacket - .sink17_ready (rsp_xbar_demux_017_src0_ready), // sink17.ready - .sink17_valid (rsp_xbar_demux_017_src0_valid), // .valid - .sink17_channel (rsp_xbar_demux_017_src0_channel), // .channel - .sink17_data (rsp_xbar_demux_017_src0_data), // .data - .sink17_startofpacket (rsp_xbar_demux_017_src0_startofpacket), // .startofpacket - .sink17_endofpacket (rsp_xbar_demux_017_src0_endofpacket) // .endofpacket - ); - - nios_system_irq_mapper irq_mapper ( - .clk (clk_clk), // clk.clk - .reset (rst_controller_reset_out_reset), // clk_reset.reset - .receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq - .sender_irq (nios2_processor_d_irq_irq) // sender.irq - ); - -endmodule diff --git a/nios_system/synthesis/submodules/altera_avalon_sc_fifo.v b/nios_system/synthesis/submodules/altera_avalon_sc_fifo.v deleted file mode 100644 index 94e2787..0000000 --- a/nios_system/synthesis/submodules/altera_avalon_sc_fifo.v +++ /dev/null @@ -1,877 +0,0 @@ -// ----------------------------------------------------------- -// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your -// use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any -// output files any of the foregoing (including device programming or -// simulation files), and any associated documentation or information are -// expressly subject to the terms and conditions of the Altera Program -// License Subscription Agreement or other applicable license agreement, -// including, without limitation, that your use is for the sole purpose -// of programming logic devices manufactured by Altera and sold by Altera -// or its authorized distributors. Please refer to the applicable -// agreement for further details. -// -// Description: Single clock Avalon-ST FIFO. -// ----------------------------------------------------------- - -`timescale 1 ns / 1 ns - - -//altera message_off 10036 -module altera_avalon_sc_fifo -#( - // -------------------------------------------------- - // Parameters - // -------------------------------------------------- - parameter SYMBOLS_PER_BEAT = 1, - parameter BITS_PER_SYMBOL = 8, - parameter FIFO_DEPTH = 16, - parameter CHANNEL_WIDTH = 0, - parameter ERROR_WIDTH = 0, - parameter USE_PACKETS = 0, - parameter USE_FILL_LEVEL = 0, - parameter USE_STORE_FORWARD = 0, - parameter USE_ALMOST_FULL_IF = 0, - parameter USE_ALMOST_EMPTY_IF = 0, - - // -------------------------------------------------- - // Empty latency is defined as the number of cycles - // required for a write to deassert the empty flag. - // For example, a latency of 1 means that the empty - // flag is deasserted on the cycle after a write. - // - // Another way to think of it is the latency for a - // write to propagate to the output. - // - // An empty latency of 0 implies lookahead, which is - // only implemented for the register-based FIFO. - // -------------------------------------------------- - parameter EMPTY_LATENCY = 3, - parameter USE_MEMORY_BLOCKS = 1, - - // -------------------------------------------------- - // Internal Parameters - // -------------------------------------------------- - parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL, - parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT) -) -( - // -------------------------------------------------- - // Ports - // -------------------------------------------------- - input clk, - input reset, - - input [DATA_WIDTH-1: 0] in_data, - input in_valid, - input in_startofpacket, - input in_endofpacket, - input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty, - input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error, - input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel, - output in_ready, - - output [DATA_WIDTH-1 : 0] out_data, - output reg out_valid, - output out_startofpacket, - output out_endofpacket, - output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty, - output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error, - output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel, - input out_ready, - - input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address, - input csr_write, - input csr_read, - input [31 : 0] csr_writedata, - output reg [31 : 0] csr_readdata, - - output wire almost_full_data, - output wire almost_empty_data -); - - // -------------------------------------------------- - // Local Parameters - // -------------------------------------------------- - localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH); - localparam DEPTH = FIFO_DEPTH; - localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH; - localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ? - 2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH: - DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH; - - // -------------------------------------------------- - // Internal Signals - // -------------------------------------------------- - genvar i; - - reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0]; - reg [ADDR_WIDTH-1 : 0] wr_ptr; - reg [ADDR_WIDTH-1 : 0] rd_ptr; - reg [DEPTH-1 : 0] mem_used; - - wire [ADDR_WIDTH-1 : 0] next_wr_ptr; - wire [ADDR_WIDTH-1 : 0] next_rd_ptr; - wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr; - wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr; - - wire [ADDR_WIDTH-1 : 0] mem_rd_ptr; - - wire read; - wire write; - - reg empty; - reg next_empty; - reg full; - reg next_full; - - wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals; - wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals; - wire [PAYLOAD_WIDTH-1 : 0] in_payload; - reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload; - reg [PAYLOAD_WIDTH-1 : 0] out_payload; - - reg internal_out_valid; - wire internal_out_ready; - - reg [ADDR_WIDTH : 0] fifo_fill_level; - reg [ADDR_WIDTH : 0] fill_level; - - reg [ADDR_WIDTH-1 : 0] sop_ptr = 0; - reg [23:0] almost_full_threshold; - reg [23:0] almost_empty_threshold; - reg [23:0] cut_through_threshold; - reg [15:0] pkt_cnt; - reg [15:0] pkt_cnt_r; - reg [15:0] pkt_cnt_plusone; - reg [15:0] pkt_cnt_minusone; - reg drop_on_error_en; - reg error_in_pkt; - reg pkt_has_started; - reg sop_has_left_fifo; - reg fifo_too_small_r; - reg pkt_cnt_eq_zero; - reg pkt_cnt_eq_one; - reg pkt_cnt_changed; - - wire wait_for_threshold; - reg pkt_mode; - wire wait_for_pkt; - wire ok_to_forward; - wire in_pkt_eop_arrive; - wire out_pkt_leave; - wire in_pkt_start; - wire in_pkt_error; - wire drop_on_error; - wire fifo_too_small; - wire out_pkt_sop_leave; - wire [31:0] max_fifo_size; - reg fifo_fill_level_lt_cut_through_threshold; - - // -------------------------------------------------- - // Define Payload - // - // Icky part where we decide which signals form the - // payload to the FIFO with generate blocks. - // -------------------------------------------------- - generate - if (EMPTY_WIDTH > 0) begin - assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty}; - assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals; - end - else begin - assign out_empty = in_error; - assign in_packet_signals = {in_startofpacket, in_endofpacket}; - assign {out_startofpacket, out_endofpacket} = out_packet_signals; - end - endgenerate - - generate - if (USE_PACKETS) begin - if (ERROR_WIDTH > 0) begin - if (CHANNEL_WIDTH > 0) begin - assign in_payload = {in_packet_signals, in_data, in_error, in_channel}; - assign {out_packet_signals, out_data, out_error, out_channel} = out_payload; - end - else begin - assign out_channel = in_channel; - assign in_payload = {in_packet_signals, in_data, in_error}; - assign {out_packet_signals, out_data, out_error} = out_payload; - end - end - else begin - assign out_error = in_error; - if (CHANNEL_WIDTH > 0) begin - assign in_payload = {in_packet_signals, in_data, in_channel}; - assign {out_packet_signals, out_data, out_channel} = out_payload; - end - else begin - assign out_channel = in_channel; - assign in_payload = {in_packet_signals, in_data}; - assign {out_packet_signals, out_data} = out_payload; - end - end - end - else begin - assign out_packet_signals = 0; - if (ERROR_WIDTH > 0) begin - if (CHANNEL_WIDTH > 0) begin - assign in_payload = {in_data, in_error, in_channel}; - assign {out_data, out_error, out_channel} = out_payload; - end - else begin - assign out_channel = in_channel; - assign in_payload = {in_data, in_error}; - assign {out_data, out_error} = out_payload; - end - end - else begin - assign out_error = in_error; - if (CHANNEL_WIDTH > 0) begin - assign in_payload = {in_data, in_channel}; - assign {out_data, out_channel} = out_payload; - end - else begin - assign out_channel = in_channel; - assign in_payload = in_data; - assign out_data = out_payload; - end - end - end - endgenerate - - // -------------------------------------------------- - // Memory-based FIFO storage - // - // To allow a ready latency of 0, the read index is - // obtained from the next read pointer and memory - // outputs are unregistered. - // - // If the empty latency is 1, we infer bypass logic - // around the memory so writes propagate to the - // outputs on the next cycle. - // - // Do not change the way this is coded: Quartus needs - // a perfect match to the template, and any attempt to - // refactor the two always blocks into one will break - // memory inference. - // -------------------------------------------------- - generate if (USE_MEMORY_BLOCKS == 1) begin - - if (EMPTY_LATENCY == 1) begin - - always @(posedge clk) begin - if (in_valid && in_ready) - mem[wr_ptr] = in_payload; - - internal_out_payload = mem[mem_rd_ptr]; - end - - end else begin - - always @(posedge clk) begin - if (in_valid && in_ready) - mem[wr_ptr] <= in_payload; - - internal_out_payload <= mem[mem_rd_ptr]; - end - - end - - assign mem_rd_ptr = next_rd_ptr; - - end else begin - - // -------------------------------------------------- - // Register-based FIFO storage - // - // Uses a shift register as the storage element. Each - // shift register slot has a bit which indicates if - // the slot is occupied (credit to Sam H for the idea). - // The occupancy bits are contiguous and start from the - // lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep - // FIFO. - // - // Each slot is enabled during a read or when it - // is unoccupied. New data is always written to every - // going-to-be-empty slot (we keep track of which ones - // are actually useful with the occupancy bits). On a - // read we shift occupied slots. - // - // The exception is the last slot, which always gets - // new data when it is unoccupied. - // -------------------------------------------------- - for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg - always @(posedge clk or posedge reset) begin - if (reset) begin - mem[i] <= 0; - end - else if (read || !mem_used[i]) begin - if (!mem_used[i+1]) - mem[i] <= in_payload; - else - mem[i] <= mem[i+1]; - end - end - end - - always @(posedge clk, posedge reset) begin - if (reset) begin - mem[DEPTH-1] <= 0; - end - else begin - if (!mem_used[DEPTH-1]) - mem[DEPTH-1] <= in_payload; - - if (DEPTH == 1) begin - if (write) - mem[DEPTH-1] <= in_payload; - end - end - end - - end - endgenerate - - assign read = internal_out_ready && internal_out_valid && ok_to_forward; - assign write = in_ready && in_valid; - - // -------------------------------------------------- - // Pointer Management - // -------------------------------------------------- - generate if (USE_MEMORY_BLOCKS == 1) begin - - assign incremented_wr_ptr = wr_ptr + 1'b1; - assign incremented_rd_ptr = rd_ptr + 1'b1; - assign next_wr_ptr = drop_on_error ? sop_ptr : write ? incremented_wr_ptr : wr_ptr; - assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr; - - always @(posedge clk or posedge reset) begin - if (reset) begin - wr_ptr <= 0; - rd_ptr <= 0; - end - else begin - wr_ptr <= next_wr_ptr; - rd_ptr <= next_rd_ptr; - end - end - - end else begin - - // -------------------------------------------------- - // Shift Register Occupancy Bits - // - // Consider a 4-deep FIFO with 2 entries: 0011 - // On a read and write, do not modify the bits. - // On a write, left-shift the bits to get 0111. - // On a read, right-shift the bits to get 0001. - // - // Also, on a write we set bit0 (the head), while - // clearing the tail on a read. - // -------------------------------------------------- - always @(posedge clk or posedge reset) begin - if (reset) begin - mem_used[0] <= 0; - end - else begin - if (write ^ read) begin - if (read) begin - if (DEPTH > 1) - mem_used[0] <= mem_used[1]; - else - mem_used[0] <= 0; - end - if (write) - mem_used[0] <= 1; - end - end - end - - if (DEPTH > 1) begin - always @(posedge clk or posedge reset) begin - if (reset) begin - mem_used[DEPTH-1] <= 0; - end - else begin - if (write ^ read) begin - mem_used[DEPTH-1] <= 0; - if (write) - mem_used[DEPTH-1] <= mem_used[DEPTH-2]; - end - end - end - end - - for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic - always @(posedge clk, posedge reset) begin - if (reset) begin - mem_used[i] <= 0; - end - else begin - if (write ^ read) begin - if (read) - mem_used[i] <= mem_used[i+1]; - if (write) - mem_used[i] <= mem_used[i-1]; - end - end - end - end - - end - endgenerate - - - // -------------------------------------------------- - // Memory FIFO Status Management - // - // Generates the full and empty signals from the - // pointers. The FIFO is full when the next write - // pointer will be equal to the read pointer after - // a write. Reading from a FIFO clears full. - // - // The FIFO is empty when the next read pointer will - // be equal to the write pointer after a read. Writing - // to a FIFO clears empty. - // - // A simultaneous read and write must not change any of - // the empty or full flags unless there is a drop on error event. - // -------------------------------------------------- - generate if (USE_MEMORY_BLOCKS == 1) begin - - always @* begin - next_full = full; - next_empty = empty; - - if (read && !write) begin - next_full = 1'b0; - - if (incremented_rd_ptr == wr_ptr) - next_empty = 1'b1; - end - - if (write && !read) begin - if (!drop_on_error) - next_empty = 1'b0; - else if (sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo - next_empty = 1'b1; - - if (incremented_wr_ptr == rd_ptr && !drop_on_error) - next_full = 1'b1; - end - - if (write && read && drop_on_error) begin - if (sop_ptr == next_rd_ptr) - next_empty = 1'b1; - end - end - - always @(posedge clk or posedge reset) begin - if (reset) begin - empty <= 1; - full <= 0; - end - else begin - empty <= next_empty; - full <= next_full; - end - end - - end else begin - // -------------------------------------------------- - // Register FIFO Status Management - // - // Full when the tail occupancy bit is 1. Empty when - // the head occupancy bit is 0. - // -------------------------------------------------- - always @* begin - full = mem_used[DEPTH-1]; - empty = !mem_used[0]; - - // ------------------------------------------ - // For a single slot FIFO, reading clears the - // full status immediately. - // ------------------------------------------ - if (DEPTH == 1) - full = mem_used[0] && !read; - - internal_out_payload = mem[0]; - - // ------------------------------------------ - // Writes clear empty immediately for lookahead modes. - // Note that we use in_valid instead of write to avoid - // combinational loops (in lookahead mode, qualifying - // with in_ready is meaningless). - // - // In a 1-deep FIFO, a possible combinational loop runs - // from write -> out_valid -> out_ready -> write - // ------------------------------------------ - if (EMPTY_LATENCY == 0) begin - empty = !mem_used[0] && !in_valid; - - if (!mem_used[0] && in_valid) - internal_out_payload = in_payload; - end - end - - end - endgenerate - - // -------------------------------------------------- - // Avalon-ST Signals - // - // The in_ready signal is straightforward. - // - // To match memory latency when empty latency > 1, - // out_valid assertions must be delayed by one clock - // cycle. - // - // Note: out_valid deassertions must not be delayed or - // the FIFO will underflow. - // -------------------------------------------------- - assign in_ready = !full; - assign internal_out_ready = out_ready || !out_valid; - - generate if (EMPTY_LATENCY > 1) begin - always @(posedge clk or posedge reset) begin - if (reset) - internal_out_valid <= 0; - else begin - internal_out_valid <= !empty & ok_to_forward & ~drop_on_error; - - if (read) begin - if (incremented_rd_ptr == wr_ptr) - internal_out_valid <= 1'b0; - end - end - end - end else begin - always @* begin - internal_out_valid = !empty & ok_to_forward; - end - end - endgenerate - - // -------------------------------------------------- - // Single Output Pipeline Stage - // - // This output pipeline stage is enabled if the FIFO's - // empty latency is set to 3 (default). It is disabled - // for all other allowed latencies. - // - // Reason: The memory outputs are unregistered, so we have to - // register the output or fmax will drop if combinatorial - // logic is present on the output datapath. - // - // Q: The Avalon-ST spec says that I have to register my outputs - // But isn't the memory counted as a register? - // A: The path from the address lookup to the memory output is - // slow. Registering the memory outputs is a good idea. - // - // The registers get packed into the memory by the fitter - // which means minimal resources are consumed (the result - // is a altsyncram with registered outputs, available on - // all modern Altera devices). - // - // This output stage acts as an extra slot in the FIFO, - // and complicates the fill level. - // -------------------------------------------------- - generate if (EMPTY_LATENCY == 3) begin - always @(posedge clk or posedge reset) begin - if (reset) begin - out_valid <= 0; - out_payload <= 0; - end - else begin - if (internal_out_ready) begin - out_valid <= internal_out_valid & ok_to_forward; - out_payload <= internal_out_payload; - end - end - end - end - else begin - always @* begin - out_valid = internal_out_valid; - out_payload = internal_out_payload; - end - end - endgenerate - - // -------------------------------------------------- - // Fill Level - // - // The fill level is calculated from the next write - // and read pointers to avoid unnecessary latency. - // - // If the output pipeline is enabled, the fill level - // must account for it, or we'll always be off by one. - // This may, or may not be important depending on the - // application. - // - // For now, we'll always calculate the exact fill level - // at the cost of an extra adder when the output stage - // is enabled. - // -------------------------------------------------- - generate if (USE_FILL_LEVEL) begin - wire [31:0] depth32; - assign depth32 = DEPTH; - always @(posedge clk or posedge reset) begin - if (reset) - fifo_fill_level <= 0; - else if (next_full & !drop_on_error) - fifo_fill_level <= depth32[ADDR_WIDTH:0]; - else begin - fifo_fill_level[ADDR_WIDTH] <= 1'b0; - fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr; - end - end - - always @* begin - fill_level = fifo_fill_level; - - if (EMPTY_LATENCY == 3) - fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid}; - end - end - else begin - initial fill_level = 0; - end - endgenerate - - generate if (USE_ALMOST_FULL_IF) begin - assign almost_full_data = (fill_level >= almost_full_threshold); - end - else - assign almost_full_data = 0; - endgenerate - - generate if (USE_ALMOST_EMPTY_IF) begin - assign almost_empty_data = (fill_level <= almost_empty_threshold); - end - else - assign almost_empty_data = 0; - endgenerate - - // -------------------------------------------------- - // Avalon-MM Status & Control Connection Point - // - // Register map: - // - // | Addr | RW | 31 - 0 | - // | 0 | R | Fill level | - // - // The registering of this connection point means - // that there is a cycle of latency between - // reads/writes and the updating of the fill level. - // -------------------------------------------------- - generate if (USE_STORE_FORWARD) begin - assign max_fifo_size = FIFO_DEPTH - 1; - always @(posedge clk or posedge reset) begin - if (reset) begin - almost_full_threshold <= max_fifo_size[23 : 0]; - almost_empty_threshold <= 0; - cut_through_threshold <= 0; - drop_on_error_en <= 0; - csr_readdata <= 0; - pkt_mode <= 1'b1; - end - else begin - if (csr_write) begin - if(csr_address == 3'b010) - almost_full_threshold <= csr_writedata[23:0]; - if(csr_address == 3'b011) - almost_empty_threshold <= csr_writedata[23:0]; - if(csr_address == 3'b100) begin - cut_through_threshold <= csr_writedata[23:0]; - pkt_mode <= (csr_writedata[23:0] == 0); - end - if(csr_address == 3'b101) - drop_on_error_en <= csr_writedata[0]; - end - - if (csr_read) begin - csr_readdata <= 32'b0; - if (csr_address == 0) - csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level}; - if (csr_address == 2) - csr_readdata <= {8'b0, almost_full_threshold}; - if (csr_address == 3) - csr_readdata <= {8'b0, almost_empty_threshold}; - if (csr_address == 4) - csr_readdata <= {8'b0, cut_through_threshold}; - if (csr_address == 5) - csr_readdata <= {31'b0, drop_on_error_en}; - end - end - end - end - else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin - assign max_fifo_size = FIFO_DEPTH - 1; - always @(posedge clk or posedge reset) begin - if (reset) begin - almost_full_threshold <= max_fifo_size[23 : 0]; - almost_empty_threshold <= 0; - csr_readdata <= 0; - end - else begin - if (csr_write) begin - if(csr_address == 3'b010) - almost_full_threshold <= csr_writedata[23:0]; - if(csr_address == 3'b011) - almost_empty_threshold <= csr_writedata[23:0]; - end - - if (csr_read) begin - csr_readdata <= 32'b0; - if (csr_address == 0) - csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level}; - if (csr_address == 2) - csr_readdata <= {8'b0, almost_full_threshold}; - if (csr_address == 3) - csr_readdata <= {8'b0, almost_empty_threshold}; - end - end - end - end - else begin - always @(posedge clk or posedge reset) begin - if (reset) begin - csr_readdata <= 0; - end - else if (csr_read) begin - csr_readdata <= 0; - - if (csr_address == 0) - csr_readdata <= fill_level; - end - end - end - endgenerate - - // -------------------------------------------------- - // Store and forward logic - // -------------------------------------------------- - // if the fifo gets full before the entire packet or the - // cut-threshold condition is met then start sending out - // data in order to avoid dead-lock situation - - generate if (USE_STORE_FORWARD) begin - assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ; - assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave); - assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) : - ~wait_for_threshold) | fifo_too_small_r; - assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket; - assign in_pkt_start = in_valid & in_ready & in_startofpacket; - assign in_pkt_error = in_valid & in_ready & |in_error; - assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket; - assign out_pkt_leave = out_valid & out_ready & out_endofpacket; - assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready; - - // count packets coming and going into the fifo - always @(posedge clk or posedge reset) begin - if (reset) begin - pkt_cnt <= 0; - pkt_cnt_r <= 0; - pkt_cnt_plusone <= 1; - pkt_cnt_minusone <= 0; - pkt_cnt_changed <= 0; - pkt_has_started <= 0; - sop_has_left_fifo <= 0; - fifo_too_small_r <= 0; - pkt_cnt_eq_zero <= 1'b1; - pkt_cnt_eq_one <= 1'b0; - fifo_fill_level_lt_cut_through_threshold <= 1'b1; - end - else begin - fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold; - fifo_too_small_r <= fifo_too_small; - pkt_cnt_plusone <= pkt_cnt + 1'b1; - pkt_cnt_minusone <= pkt_cnt - 1'b1; - pkt_cnt_r <= pkt_cnt; - pkt_cnt_changed <= 1'b0; - - if( in_pkt_eop_arrive ) - sop_has_left_fifo <= 1'b0; - else if (out_pkt_sop_leave & pkt_cnt_eq_zero ) - sop_has_left_fifo <= 1'b1; - - if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin - pkt_cnt_changed <= 1'b1; - pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_plusone; - pkt_cnt_eq_zero <= 0; - if (pkt_cnt == 0) - pkt_cnt_eq_one <= 1'b1; - else - pkt_cnt_eq_one <= 1'b0; - end - else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin - pkt_cnt_changed <= 1'b1; - pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_minusone; - if (pkt_cnt == 1) - pkt_cnt_eq_zero <= 1'b1; - else - pkt_cnt_eq_zero <= 1'b0; - if (pkt_cnt == 2) - pkt_cnt_eq_one <= 1'b1; - else - pkt_cnt_eq_one <= 1'b0; - end - - if (in_pkt_start) - pkt_has_started <= 1'b1; - else if (in_pkt_eop_arrive) - pkt_has_started <= 1'b0; - end - end - - // drop on error logic - always @(posedge clk or posedge reset) begin - if (reset) begin - sop_ptr <= 0; - error_in_pkt <= 0; - end - else begin - // save the location of the SOP - if ( in_pkt_start ) - sop_ptr <= wr_ptr; - - // remember if error in pkt - // log error only if packet has already started - if (in_pkt_eop_arrive) - error_in_pkt <= 1'b0; - else if ( in_pkt_error & (pkt_has_started | in_pkt_start)) - error_in_pkt <= 1'b1; - end - end - assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive & - ~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero); - - end - else begin - assign ok_to_forward = 1'b1; - assign drop_on_error = 1'b0; - end - endgenerate - - - // -------------------------------------------------- - // Calculates the log2ceil of the input value - // -------------------------------------------------- - function integer log2ceil; - input integer val; - integer i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - -endmodule diff --git a/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv b/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv deleted file mode 100644 index 00dc788..0000000 --- a/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv +++ /dev/null @@ -1,270 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2010 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $ -// $Revision: #3 $ -// $Date: 2010/07/07 $ -// $Author: jyeap $ - -/* ----------------------------------------------------------------------- -Round-robin/fixed arbitration implementation. - -Q: how do you find the least-significant set-bit in an n-bit binary number, X? - -A: M = X & (~X + 1) - -Example: X = 101000100 - 101000100 & - 010111011 + 1 = - - 101000100 & - 010111100 = - ----------- - 000000100 - -The method can be generalized to find the first set-bit -at a bit index no lower than bit-index N, simply by adding -2**N rather than 1. - - -Q: how does this relate to round-robin arbitration? -A: -Let X be the concatenation of all request signals. -Let the number to be added to X (hereafter called the -top_priority) initialize to 1, and be assigned from the -concatenation of the previous saved-grant, left-rotated -by one position, each time arbitration occurs. The -concatenation of grants is then M. - -Problem: consider this case: - -top_priority = 010000 -request = 001001 -~request + top_priority = 000110 -next_grant = 000000 <- no one is granted! - -There was no "set bit at a bit index no lower than bit-index 4", so -the result was 0. - -We need to propagate the carry out from (~request + top_priority) to the LSB, so -that the sum becomes 000111, and next_grant is 000001. This operation could be -called a "circular add". - -A bit of experimentation on the circular add reveals a significant amount of -delay in exiting and re-entering the carry chain - this will vary with device -family. Quartus also reports a combinational loop warning. Finally, -Modelsim 6.3g has trouble with the expression, evaluating it to 'X'. But -Modelsim _doesn't_ report a combinational loop!) - -An alternate solution: concatenate the request vector with itself, and OR -corresponding bits from the top and bottom halves to determine next_grant. - -Example: - -top_priority = 010000 -{request, request} = 001001 001001 -{~request, ~request} + top_priority = 110111 000110 -result of & operation = 000001 000000 -next_grant = 000001 - -Notice that if request = 0, the sum operation will overflow, but we can ignore -this; the next_grant result is 0 (no one granted), as you might expect. -In the implementation, the last-granted value must be maintained as -a non-zero value - best probably simply not to update it when no requests -occur. - ------------------------------------------------------------------------ */ - -`timescale 1 ns / 1 ns - -module altera_merlin_arbitrator -#( - parameter NUM_REQUESTERS = 8, - // -------------------------------------- - // Implemented schemes - // "round-robin" - // "fixed-priority" - // "no-arb" - // -------------------------------------- - parameter SCHEME = "round-robin", - parameter PIPELINE = 0 -) -( - input clk, - input reset, - - // -------------------------------------- - // Requests - // -------------------------------------- - input [NUM_REQUESTERS-1:0] request, - - // -------------------------------------- - // Grants - // -------------------------------------- - output [NUM_REQUESTERS-1:0] grant, - - // -------------------------------------- - // Control Signals - // -------------------------------------- - input increment_top_priority, - input save_top_priority -); - - // -------------------------------------- - // Signals - // -------------------------------------- - wire [NUM_REQUESTERS-1:0] top_priority; - reg [NUM_REQUESTERS-1:0] top_priority_reg; - reg [NUM_REQUESTERS-1:0] last_grant; - wire [2*NUM_REQUESTERS-1:0] result; - - // -------------------------------------- - // Scheme Selection - // -------------------------------------- - generate - if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin - assign top_priority = top_priority_reg; - end - else begin - // Fixed arbitration (or single-requester corner case) - assign top_priority = 1'b1; - end - endgenerate - - // -------------------------------------- - // Decision Logic - // -------------------------------------- - altera_merlin_arb_adder - #( - .WIDTH (2 * NUM_REQUESTERS) - ) - adder - ( - .a ({ ~request, ~request }), - .b ({{NUM_REQUESTERS{1'b0}}, top_priority}), - .sum (result) - ); - - - generate if (SCHEME == "no-arb") begin - - // -------------------------------------- - // No arbitration: just wire request directly to grant - // -------------------------------------- - assign grant = request; - - end else begin - // Do the math in double-vector domain - wire [2*NUM_REQUESTERS-1:0] grant_double_vector; - assign grant_double_vector = {request, request} & result; - - // -------------------------------------- - // Extract grant from the top and bottom halves - // of the double vector. - // -------------------------------------- - assign grant = - grant_double_vector[NUM_REQUESTERS - 1 : 0] | - grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS]; - - end - endgenerate - - // -------------------------------------- - // Left-rotate the last grant vector to create top_priority. - // -------------------------------------- - always @(posedge clk or posedge reset) begin - if (reset) begin - top_priority_reg <= 1'b1; - end - else begin - if (PIPELINE) begin - if (increment_top_priority) begin - top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0], - grant[NUM_REQUESTERS-1]} : top_priority_reg; - end - end else begin - if (save_top_priority) begin - top_priority_reg <= grant; - end - if (increment_top_priority) begin - if (|request) - top_priority_reg <= { grant[NUM_REQUESTERS-2:0], - grant[NUM_REQUESTERS-1] }; - else - top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] }; - end - end - end - end - -endmodule - -// ---------------------------------------------- -// Adder for the standard arbitrator -// ---------------------------------------------- -module altera_merlin_arb_adder -#( - parameter WIDTH = 8 -) -( - input [WIDTH-1:0] a, - input [WIDTH-1:0] b, - - output [WIDTH-1:0] sum -); - - // ---------------------------------------------- - // Benchmarks indicate that for small widths, the full - // adder has higher fmax because synthesis can merge - // it with the mux, allowing partial decisions to be - // made early. - // - // The magic number is 4 requesters, which means an - // 8 bit adder. - // ---------------------------------------------- - genvar i; - generate if (WIDTH <= 8) begin : full_adder - - wire cout[WIDTH-1:0]; - - assign sum[0] = (a[0] ^ b[0]); - assign cout[0] = (a[0] & b[0]); - - for (i = 1; i < WIDTH; i = i+1) begin : arb - - assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1]; - assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i])); - - end - - end else begin : carry_chain - - assign sum = a + b; - - end - endgenerate - -endmodule diff --git a/nios_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv b/nios_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv deleted file mode 100644 index 9b49c44..0000000 --- a/nios_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv +++ /dev/null @@ -1,286 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2012 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_slave_agent/altera_merlin_burst_uncompressor.sv#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------ -// Merlin Burst Uncompressor -// -// Compressed read bursts -> uncompressed -// ------------------------------------------ - -`timescale 1 ns / 1 ns - -module altera_merlin_burst_uncompressor -#( - parameter ADDR_W = 16, - parameter BURSTWRAP_W = 3, - parameter BYTE_CNT_W = 4, - parameter PKT_SYMBOLS = 4, - parameter BURST_SIZE_W = 3 -) -( - input clk, - input reset, - - // sink ST signals - input sink_startofpacket, - input sink_endofpacket, - input sink_valid, - output sink_ready, - - // sink ST "data" - input [ADDR_W - 1: 0] sink_addr, - input [BURSTWRAP_W - 1 : 0] sink_burstwrap, - input [BYTE_CNT_W - 1 : 0] sink_byte_cnt, - input sink_is_compressed, - input [BURST_SIZE_W-1 : 0] sink_burstsize, - - // source ST signals - output source_startofpacket, - output source_endofpacket, - output source_valid, - input source_ready, - - // source ST "data" - output [ADDR_W - 1: 0] source_addr, - output [BURSTWRAP_W - 1 : 0] source_burstwrap, - output [BYTE_CNT_W - 1 : 0] source_byte_cnt, - - // Note: in the slave agent, the output should always be uncompressed. In - // other applications, it may be required to leave-compressed or not. How to - // control? Seems like a simple mux - pass-through if no uncompression is - // required. - output source_is_compressed, - output [BURST_SIZE_W-1 : 0] source_burstsize -); - -//---------------------------------------------------- -// AXSIZE decoding -// -// Turns the axsize value into the actual number of bytes -// being transferred. -// --------------------------------------------------- -function reg[63:0] bytes_in_transfer; - input [2:0] axsize; - case (axsize) - 3'b000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001; - 3'b001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010; - 3'b010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100; - 3'b011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000; - 3'b100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000; - 3'b101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000; - 3'b110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000; - 3'b111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000; - default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001; - endcase - -endfunction - - // num_symbols is PKT_SYMBOLS, appropriately sized. - wire [31:0] int_num_symbols = PKT_SYMBOLS; - wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0]; - - // def: Burst Compression. In a merlin network, a compressed burst is one - // which is transmitted in a single beat. Example: read burst. In - // constrast, an uncompressed burst (example: write burst) is transmitted in - // one beat per writedata item. - // - // For compressed bursts which require response packets, burst - // uncompression is required. Concrete example: a read burst of size 8 - // occupies one response-fifo position. When that fifo position reaches the - // front of the FIFO, the slave starts providing the required 8 readdatavalid - // pulses. The 8 return response beats must be provided in a single packet, - // with incrementing address and decrementing byte_cnt fields. Upon receipt - // of the final readdata item of the burst, the response FIFO item is - // retired. - // Burst uncompression logic provides: - // a) 2-state FSM (idle, busy) - // reset to idle state - // transition to busy state for 2nd and subsequent rdv pulses - // - a single-cycle burst (aka non-burst read) causes no transition to - // busy state. - // b) response startofpacket/endofpacket logic. The response FIFO item - // will have sop asserted, and may have eop asserted. (In the case of - // multiple read bursts transmit in the command fabric in a single packet, - // the eop assertion will come in a later FIFO item.) To support packet - // conservation, and emit a well-formed packet on the response fabric, - // i) response fabric startofpacket is asserted only for the first resp. - // beat; - // ii) response fabric endofpacket is asserted only for the last resp. - // beat. - // c) response address field. The response address field contains an - // incrementing sequence, such that each readdata item is associated with - // its slave-map location. N.b. a) computing the address correctly requires - // knowledge of burstwrap behavior b) there may be no clients of the address - // field, which makes this field a good target for optimization. See - // burst_uncompress_address_counter below. - // d) response byte_cnt field. The response byte_cnt field contains a - // decrementing sequence, such that each beat of the response contains the - // count of bytes to follow. In the case of sub-bursts in a single packet, - // the byte_cnt field may decrement down to num_symbols, then back up to - // some value, multiple times in the packet. - - reg burst_uncompress_busy; - reg [BYTE_CNT_W-1:0] burst_uncompress_byte_counter; - wire first_packet_beat; - wire last_packet_beat; - - assign first_packet_beat = sink_valid & ~burst_uncompress_busy; - - // First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to - // the output. - assign source_byte_cnt = - first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter; - assign source_valid = sink_valid; - - // Last packet beat is set throughout receipt of an uncompressed read burst - // from the response FIFO - this forces all the burst uncompression machinery - // idle. - assign last_packet_beat = ~sink_is_compressed | - ( - burst_uncompress_busy ? - (sink_valid & (burst_uncompress_byte_counter == num_symbols)) : - sink_valid & (sink_byte_cnt == num_symbols) - ); - - always @(posedge clk or posedge reset) begin - if (reset) begin - burst_uncompress_busy <= '0; - burst_uncompress_byte_counter <= '0; - end - else begin - if (source_valid & source_ready & sink_valid) begin - // No matter what the current state, last_packet_beat leads to - // idle. - if (last_packet_beat) begin - burst_uncompress_busy <= '0; - burst_uncompress_byte_counter <= '0; - end - else begin - if (burst_uncompress_busy) begin - burst_uncompress_byte_counter <= burst_uncompress_byte_counter ? - (burst_uncompress_byte_counter - num_symbols) : - (sink_byte_cnt - num_symbols); - end - else begin // not busy, at least one more beat to go - burst_uncompress_byte_counter <= sink_byte_cnt - num_symbols; - // To do: should busy go true for numsymbols-size compressed - // bursts? - burst_uncompress_busy <= '1; - end - end - end - end - end - - wire [ADDR_W - 1 : 0 ] addr_width_burstwrap; - reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base; - reg [ADDR_W - 1 : 0] burst_uncompress_address_offset; - - wire [63:0] decoded_burstsize_wire; - wire [ADDR_W-1:0] decoded_burstsize; - - // The input burstwrap value can be used as a mask against address values, - // but with one caveat: the address width may be (probably is) wider than - // the burstwrap width. The spec says: extend the msb of the burstwrap - // value out over the entire address width (but only if the address width - // actually is wider than the burstwrap width; otherwise it's a 0-width or - // negative range and concatenation multiplier). - assign addr_width_burstwrap[BURSTWRAP_W - 1 : 0] = sink_burstwrap; - generate - if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend - // Sign-extend, just wires: - assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] = - {(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}}; - end - endgenerate - - always @(posedge clk or posedge reset) begin - if (reset) begin - burst_uncompress_address_base <= '0; - end - else if (first_packet_beat & source_ready) begin - burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap; - end - end - - assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize); //expand it to 64 bits - assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0]; //then take the width that is needed - - wire [ADDR_W - 1 : 0] p1_burst_uncompress_address_offset = - ( - (first_packet_beat ? - sink_addr : - burst_uncompress_address_offset) + decoded_burstsize - ) & - addr_width_burstwrap; - - always @(posedge clk or posedge reset) begin - if (reset) begin - burst_uncompress_address_offset <= '0; - end - else begin - if (source_ready & source_valid) begin - burst_uncompress_address_offset <= p1_burst_uncompress_address_offset; - // if (first_packet_beat) begin - // burst_uncompress_address_offset <= - // (sink_addr + num_symbols) & addr_width_burstwrap; - // end - // else begin - // burst_uncompress_address_offset <= - // (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap; - // end - end - end - end - - // On the first packet beat, send the input address out unchanged, - // while values are computed/registered for 2nd and subsequent beats. - assign source_addr = first_packet_beat ? sink_addr : - burst_uncompress_address_base | burst_uncompress_address_offset; - assign source_burstwrap = sink_burstwrap; - assign source_burstsize = sink_burstsize; - - //------------------------------------------------------------------- - // A single (compressed) read burst will have sop/eop in the same beat. - // A sequence of read sub-bursts emitted by a burst adapter in response to a - // single read burst will have sop on the first sub-burst, eop on the last. - // Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve - // packet conservation. - assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy; - assign source_endofpacket = sink_endofpacket & last_packet_beat; - assign sink_ready = source_valid & source_ready & last_packet_beat; - - // This is correct for the slave agent usage, but won't always be true in the - // width adapter. To do: add an "please uncompress" input, and use it to - // pass-through or modify, and set source_is_compressed accordingly. - assign source_is_compressed = 1'b0; -endmodule - diff --git a/nios_system/synthesis/submodules/altera_merlin_master_agent.sv b/nios_system/synthesis/submodules/altera_merlin_master_agent.sv deleted file mode 100644 index 070f26f..0000000 --- a/nios_system/synthesis/submodules/altera_merlin_master_agent.sv +++ /dev/null @@ -1,309 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_master_agent/altera_merlin_master_agent.sv#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// -------------------------------------- -// Merlin Master Agent -// -// Converts Avalon-MM transactions into -// Merlin network packets. -// -------------------------------------- - -`timescale 1 ns / 1 ns - -module altera_merlin_master_agent -#( - // ------------------- - // Packet Format Parameters - // ------------------- - parameter PKT_QOS_H = 109, - PKT_QOS_L = 106, - PKT_DATA_SIDEBAND_H = 105, - PKT_DATA_SIDEBAND_L = 98, - PKT_ADDR_SIDEBAND_H = 97, - PKT_ADDR_SIDEBAND_L = 93, - PKT_CACHE_H = 92, - PKT_CACHE_L = 89, - PKT_THREAD_ID_H = 88, - PKT_THREAD_ID_L = 87, - PKT_BEGIN_BURST = 81, - PKT_PROTECTION_H = 80, - PKT_PROTECTION_L = 80, - PKT_BURSTWRAP_H = 79, - PKT_BURSTWRAP_L = 77, - PKT_BYTE_CNT_H = 76, - PKT_BYTE_CNT_L = 74, - PKT_ADDR_H = 73, - PKT_ADDR_L = 42, - PKT_BURST_SIZE_H = 86, - PKT_BURST_SIZE_L = 84, - PKT_BURST_TYPE_H = 94, - PKT_BURST_TYPE_L = 93, - PKT_TRANS_EXCLUSIVE = 83, - PKT_TRANS_LOCK = 82, - PKT_TRANS_COMPRESSED_READ = 41, - PKT_TRANS_POSTED = 40, - PKT_TRANS_WRITE = 39, - PKT_TRANS_READ = 38, - PKT_DATA_H = 37, - PKT_DATA_L = 6, - PKT_BYTEEN_H = 5, - PKT_BYTEEN_L = 2, - PKT_SRC_ID_H = 1, - PKT_SRC_ID_L = 1, - PKT_DEST_ID_H = 0, - PKT_DEST_ID_L = 0, - PKT_RESPONSE_STATUS_L = 110, - PKT_RESPONSE_STATUS_H = 111, - ST_DATA_W = 112, - ST_CHANNEL_W = 1, - - // ------------------- - // Agent Parameters - // ------------------- - AV_BURSTCOUNT_W = 3, - ID = 1, - SUPPRESS_0_BYTEEN_RSP = 1, - BURSTWRAP_VALUE = 4, - CACHE_VALUE = 0, - SECURE_ACCESS_BIT = 1, - USE_READRESPONSE = 0, - USE_WRITERESPONSE = 0, - - // ------------------- - // Derived Parameters - // ------------------- - PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1, - PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1, - PKT_PROTECTION_W= PKT_PROTECTION_H - PKT_PROTECTION_L + 1, - PKT_ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1, - PKT_DATA_W = PKT_DATA_H - PKT_DATA_L + 1, - PKT_BYTEEN_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, - PKT_SRC_ID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1, - PKT_DEST_ID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1 -) -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // Avalon-MM Anti-Master - // ------------------- - input [PKT_ADDR_W-1 : 0] av_address, - input av_write, - input av_read, - input [PKT_DATA_W-1 : 0] av_writedata, - output reg [PKT_DATA_W-1 : 0] av_readdata, - output reg av_waitrequest, - output reg av_readdatavalid, - input [PKT_BYTEEN_W-1 : 0] av_byteenable, - input [AV_BURSTCOUNT_W-1 : 0] av_burstcount, - input av_debugaccess, - input av_lock, - output reg [1:0] av_response, - input av_writeresponserequest, - output reg av_writeresponsevalid, - - // ------------------- - // Command Source - // ------------------- - output reg cp_valid, - output reg [ST_DATA_W-1 : 0] cp_data, - output wire cp_startofpacket, - output wire cp_endofpacket, - input cp_ready, - - // ------------------- - // Response Sink - // ------------------- - input rp_valid, - input [ST_DATA_W-1 : 0] rp_data, - input [ST_CHANNEL_W-1 : 0] rp_channel, - input rp_startofpacket, - input rp_endofpacket, - output reg rp_ready -); - // ------------------------------------------------------------ - // Utility Functions - // ------------------------------------------------------------ - function integer clogb2; - input [31:0] value; - begin - for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) - value = value >> 1; - clogb2 = clogb2 - 1; - end - endfunction // clogb2 - - localparam MAX_BURST = 1 << (AV_BURSTCOUNT_W - 1); - localparam NUMSYMBOLS = PKT_BYTEEN_W; - localparam BURSTING = (MAX_BURST > NUMSYMBOLS); - localparam BITS_TO_ZERO = clogb2(NUMSYMBOLS); - localparam BURST_SIZE = clogb2(NUMSYMBOLS); - - typedef enum bit [1:0] - { - FIXED = 2'b00, - INCR = 2'b01, - WRAP = 2'b10, - OTHER_WRAP = 2'b11 - } MerlinBurstType; - - // -------------------------------------- - // Potential optimization: compare in words to save bits? - // -------------------------------------- - wire is_burst; - assign is_burst = (BURSTING) & (av_burstcount > NUMSYMBOLS); - - wire [31:0] burstwrap_value_int = BURSTWRAP_VALUE; - wire [31:0] id_int = ID; - wire [2:0] burstsize_sig = BURST_SIZE[2:0]; - wire [1:0] bursttype_value = burstwrap_value_int[PKT_BURSTWRAP_W-1] ? INCR : WRAP; - - // -------------------------------------- - // Address alignment - // - // The packet format requires that addresses be aligned to - // the transaction size. - // -------------------------------------- - wire [PKT_ADDR_W-1 : 0] av_address_aligned; - generate - if (NUMSYMBOLS > 1) begin - assign av_address_aligned = - {av_address[PKT_ADDR_W-1 : BITS_TO_ZERO], {BITS_TO_ZERO {1'b0}}}; - end - else begin - assign av_address_aligned = av_address; - end - endgenerate - - // -------------------------------------- - // Command & Response Construction - // -------------------------------------- - always @* begin - cp_data = '0; // default assignment; override below as needed. - - cp_data[PKT_PROTECTION_L] = av_debugaccess; - cp_data[PKT_PROTECTION_L+1] = SECURE_ACCESS_BIT[0]; // Default Non-secured (AXI) - cp_data[PKT_PROTECTION_L+2] = 1'b0; // Default Data access (AXI) - cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L ] = burstwrap_value_int[PKT_BURSTWRAP_W-1:0]; - cp_data[PKT_BYTE_CNT_H :PKT_BYTE_CNT_L ] = av_burstcount; - cp_data[PKT_ADDR_H :PKT_ADDR_L ] = av_address_aligned; - cp_data[PKT_TRANS_EXCLUSIVE ] = 1'b0; - cp_data[PKT_TRANS_LOCK ] = av_lock; - cp_data[PKT_TRANS_COMPRESSED_READ ] = av_read & is_burst; - cp_data[PKT_TRANS_READ ] = av_read; - cp_data[PKT_TRANS_WRITE ] = av_write; - // posted and non-posted write avaiable now - cp_data[PKT_TRANS_POSTED ] = av_write & !av_writeresponserequest; - cp_data[PKT_DATA_H :PKT_DATA_L ] = av_writedata; - cp_data[PKT_BYTEEN_H :PKT_BYTEEN_L ] = av_byteenable; - cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = burstsize_sig; - cp_data[PKT_BURST_TYPE_H:PKT_BURST_TYPE_L] = bursttype_value; - cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L ] = id_int[PKT_SRC_ID_W-1:0]; - cp_data[PKT_THREAD_ID_H:PKT_THREAD_ID_L ] = '0; - cp_data[PKT_CACHE_H :PKT_CACHE_L ] = CACHE_VALUE[3:0]; - cp_data[PKT_QOS_H : PKT_QOS_L] = '0; - cp_data[PKT_ADDR_SIDEBAND_H:PKT_ADDR_SIDEBAND_L] = '0; - cp_data[PKT_DATA_SIDEBAND_H :PKT_DATA_SIDEBAND_L] = '0; - - av_readdata = rp_data[PKT_DATA_H : PKT_DATA_L]; - if (USE_WRITERESPONSE || USE_READRESPONSE) - av_response = rp_data[PKT_RESPONSE_STATUS_H : PKT_RESPONSE_STATUS_L]; - else - av_response = '0; - - end - - // -------------------------------------- - // Command Control - // -------------------------------------- - always @* begin - cp_valid = 0; - - if (av_write || av_read) - cp_valid = 1; - end - - generate if (BURSTING) begin - reg sop_enable; - - always @(posedge clk, posedge reset) begin - if (reset) begin - sop_enable <= 1'b1; - end - else begin - if (cp_valid && cp_ready) begin - sop_enable <= 1'b0; - if (cp_endofpacket) - sop_enable <= 1'b1; - end - end - end - - assign cp_startofpacket = sop_enable; - assign cp_endofpacket = (av_read) | (av_burstcount == NUMSYMBOLS); - - end - else begin - - assign cp_startofpacket = 1'b1; - assign cp_endofpacket = 1'b1; - - end - endgenerate - - // -------------------------------------- - // Backpressure & Readdatavalid - // -------------------------------------- - reg hold_waitrequest; - - always @ (posedge clk, posedge reset) begin - if (reset) - hold_waitrequest <= 1'b1; - else - hold_waitrequest <= 1'b0; - end - - always @* begin - rp_ready = 1; - av_readdatavalid = 0; - av_writeresponsevalid = 0; - av_waitrequest = hold_waitrequest | !cp_ready; - - // -------------------------------------- - // Currently, responses are _always_ read responses because - // this Avalon agent only issues posted writes, which do - // not have responses. -> not true for now - // Now Avalon supports response, so based on type of transaction - // return, assert correct thing - // -------------------------------------- - if (rp_data[PKT_TRANS_WRITE] == 1) - av_writeresponsevalid = rp_valid; - else - av_readdatavalid = rp_valid; - - if (SUPPRESS_0_BYTEEN_RSP) begin - if (rp_data[PKT_BYTEEN_H:PKT_BYTEEN_L] == 0) - av_readdatavalid = 0; - end - end - -endmodule diff --git a/nios_system/synthesis/submodules/altera_merlin_master_translator.sv b/nios_system/synthesis/submodules/altera_merlin_master_translator.sv deleted file mode 100644 index a43760f..0000000 --- a/nios_system/synthesis/submodules/altera_merlin_master_translator.sv +++ /dev/null @@ -1,554 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_master_translator/altera_merlin_master_translator.sv#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// -------------------------------------- -// Merlin Master Translator -// -// Converts Avalon-MM Master Interfaces into -// Avalon-MM Universal Master Interfaces -// -------------------------------------- - -`timescale 1 ns / 1 ns - - - -module altera_merlin_master_translator #( - parameter - AV_ADDRESS_W = 32, - AV_DATA_W = 32, - AV_BURSTCOUNT_W = 4, - AV_BYTEENABLE_W = 4, - - //Optional Port Declarations - - USE_BURSTCOUNT = 1, - USE_BEGINBURSTTRANSFER = 0, - USE_BEGINTRANSFER = 0, - USE_CHIPSELECT = 0, - USE_READ = 1, - USE_READDATAVALID = 1, - USE_WRITE = 1, - USE_WAITREQUEST = 1, - USE_WRITERESPONSE = 0, - USE_READRESPONSE = 0, - - AV_REGISTERINCOMINGSIGNALS = 0, - AV_SYMBOLS_PER_WORD = 4, - AV_ADDRESS_SYMBOLS = 0, - AV_CONSTANT_BURST_BEHAVIOR = 1, - AV_BURSTCOUNT_SYMBOLS = 0, - AV_LINEWRAPBURSTS = 0, - UAV_ADDRESS_W = 38, - UAV_BURSTCOUNT_W = 10, - UAV_CONSTANT_BURST_BEHAVIOR = 0 - )( - //Universal Avalon Master - input wire clk, - input wire reset, - output reg uav_write, - output reg uav_read, - output reg [UAV_ADDRESS_W -1 : 0] uav_address, - output reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount, - output wire [AV_BYTEENABLE_W -1 : 0] uav_byteenable, - output wire [AV_DATA_W -1 : 0] uav_writedata, - output wire uav_lock, - output wire uav_debugaccess, - output wire uav_clken, - - input wire [ AV_DATA_W -1 : 0] uav_readdata, - input wire uav_readdatavalid, - input wire uav_waitrequest, - input wire [1:0] uav_response, - output reg uav_writeresponserequest, - input wire uav_writeresponsevalid, - - //Avalon-MM !Master - input reg av_write, - input reg av_read, - input wire [AV_ADDRESS_W -1 : 0] av_address, - input wire [AV_BYTEENABLE_W -1 : 0] av_byteenable, - input wire [AV_BURSTCOUNT_W -1 : 0] av_burstcount, - input wire [AV_DATA_W -1 : 0] av_writedata, - input wire av_begintransfer, - input wire av_beginbursttransfer, - input wire av_lock, - input wire av_chipselect, - input wire av_debugaccess, - input wire av_clken, - - output wire [AV_DATA_W -1 : 0] av_readdata, - output wire av_readdatavalid, - output reg av_waitrequest, - output reg [1:0] av_response, - input wire av_writeresponserequest, - output reg av_writeresponsevalid - - ); - - - localparam BITS_PER_WORD = clog2(AV_SYMBOLS_PER_WORD - 1); - localparam AV_MAX_SYMBOL_BURST = flog2( pow2(AV_BURSTCOUNT_W - 1) * (AV_BURSTCOUNT_SYMBOLS ? 1 : (AV_SYMBOLS_PER_WORD)) ); - localparam AV_MAX_SYMBOL_BURST_MINUS_ONE = AV_MAX_SYMBOL_BURST ? AV_MAX_SYMBOL_BURST - 1 : 0 ; - - localparam UAV_BURSTCOUNT_W_OR_32 = UAV_BURSTCOUNT_W > 32 ? 31 : UAV_BURSTCOUNT_W -1; - localparam UAV_ADDRESS_W_OR_32 = UAV_ADDRESS_W > 32 ? 31 : UAV_ADDRESS_W -1; - - - // -1 for burstcount restriction 2^(n-1) - - localparam BITS_PER_WORD_BURSTCOUNT = UAV_BURSTCOUNT_W == 1 ? 0 : BITS_PER_WORD; - localparam BITS_PER_WORD_ADDRESS = UAV_ADDRESS_W == 1 ? 0 : BITS_PER_WORD; - - localparam ADDRESS_LOW = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD_ADDRESS; - localparam BURSTCOUNT_LOW = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD_BURSTCOUNT; - - localparam ADDRESS_HIGH = UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_LOW ? AV_ADDRESS_W : UAV_ADDRESS_W - ADDRESS_LOW; - localparam BURSTCOUNT_HIGH = UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_LOW ? AV_BURSTCOUNT_W : UAV_BURSTCOUNT_W - BURSTCOUNT_LOW; - - function integer flog2; - input [31:0] Depth; - integer i; - begin - i = Depth; - if ( i <= 0 ) flog2 = 0; - else begin - for(flog2 = -1; i > 0; flog2 = flog2 + 1) - i = i >> 1; - end - end - - endfunction // flog2 - - function integer clog2; - input [31:0] Depth; - integer i; - begin - i = Depth; - for(clog2 = 0; i > 0; clog2 = clog2 + 1) - i = i >> 1; - end - - endfunction - - function integer pow2; - input [31:0] toShift; - begin - pow2=1; - pow2= pow2 << toShift; - end - endfunction // pow2 - - // ------------------------------------------------- - // Assign some constants to appropriately-sized signals to - // avoid synthesis warnings. This also helps some simulators - // with their inferred sensitivity lists. - // ------------------------------------------------- - // Calculate the symbols per word as the power of 2 extended symbols per word - wire [31:0] symbols_per_word_int = 2**(clog2(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W_OR_32 : 0] - 1)); - wire [UAV_BURSTCOUNT_W_OR_32 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W_OR_32 : 0]; - - - reg internal_beginbursttransfer; - reg internal_begintransfer; - reg [UAV_ADDRESS_W - 1: 0 ] uav_address_pre; - reg [UAV_BURSTCOUNT_W - 1 : 0 ] uav_burstcount_pre; - - - - reg uav_read_pre; - reg uav_write_pre; - reg read_accepted; - - //Passthru assignmenst - - assign uav_writedata = av_writedata; - assign av_readdata = uav_readdata; - assign uav_byteenable = av_byteenable; - assign uav_lock = av_lock; - assign av_readdatavalid = uav_readdatavalid; - assign uav_debugaccess = av_debugaccess; - assign uav_clken = av_clken; - - //Response signals - always_comb - begin - if (!USE_READRESPONSE && !USE_WRITERESPONSE) - av_response = '0; - else - av_response = uav_response; - if (USE_WRITERESPONSE) begin - uav_writeresponserequest = av_writeresponserequest; - av_writeresponsevalid = uav_writeresponsevalid; - end else begin - uav_writeresponserequest = '0; - av_writeresponsevalid = '0; - end - end - - //address + burstcount assignment - - reg [UAV_ADDRESS_W - 1 : 0] address_register; - reg [UAV_BURSTCOUNT_W - 1 : 0] burstcount_register; - - always @* begin - uav_address=uav_address_pre; - uav_burstcount=uav_burstcount_pre; - - if(AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~internal_beginbursttransfer) begin - uav_address=address_register; - uav_burstcount=burstcount_register; - end - end - - reg first_burst_stalled; - reg burst_stalled; - - - wire[UAV_ADDRESS_W-1:0] combi_burst_addr_reg; - wire [UAV_ADDRESS_W-1:0] combi_addr_reg; - generate - if(AV_LINEWRAPBURSTS && AV_MAX_SYMBOL_BURST!=0) begin - if(AV_MAX_SYMBOL_BURST > UAV_ADDRESS_W - 1) begin - assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] }; - assign combi_addr_reg = { address_register[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] }; - end - else begin - assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], uav_address_pre[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] }; - assign combi_addr_reg = { address_register[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], address_register[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] }; - end - end - else begin - assign combi_burst_addr_reg = - uav_address_pre + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W_OR_32:0]; - assign combi_addr_reg = - address_register + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W_OR_32:0]; - end - endgenerate - - always@(posedge clk, posedge reset) begin - - if(reset) begin - address_register <= '0; - burstcount_register <= '0; - first_burst_stalled <= 1'b0; - burst_stalled <= 1'b0; - end - else begin - address_register <= address_register; - burstcount_register <= burstcount_register; - - if(internal_beginbursttransfer||first_burst_stalled) begin - - if(av_waitrequest) begin - first_burst_stalled <= 1'b1; - address_register <= uav_address_pre; - burstcount_register <= uav_burstcount_pre; - end else begin - first_burst_stalled <= 1'b0; - address_register <= combi_burst_addr_reg; - burstcount_register <= uav_burstcount_pre - symbols_per_word; - end - end - - else if(internal_begintransfer || burst_stalled) begin - if(~av_waitrequest) begin - burst_stalled <= 1'b0; - address_register <= combi_addr_reg; - burstcount_register <= burstcount_register - symbols_per_word; - end else - burst_stalled<=1'b1; - end - end - - end - - //Address - always @* begin - uav_address_pre = '0; - - if(AV_ADDRESS_SYMBOLS) - uav_address_pre=av_address[ ( ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0 ) : 0 ]; - else begin - uav_address_pre[ UAV_ADDRESS_W - 1 : ADDRESS_LOW ] = av_address[( ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0 ]; - end - end - - //Burstcount - always@* begin - uav_burstcount_pre = symbols_per_word; // default to a single transfer - - if(USE_BURSTCOUNT) begin - uav_burstcount_pre = '0; - - if(AV_BURSTCOUNT_SYMBOLS) - uav_burstcount_pre = av_burstcount[( BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0 ) :0 ]; - else begin - uav_burstcount_pre[ UAV_BURSTCOUNT_W - 1 : BURSTCOUNT_LOW] = av_burstcount[( BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0 ) : 0 ]; - end - - end - - end - - - //waitrequest translation - - always@(posedge clk, posedge reset) begin - if(reset) - read_accepted <= 1'b0; - else begin - read_accepted <= read_accepted; - - if(read_accepted == 1 && uav_readdatavalid == 1) // reset acceptance only when rdv arrives - read_accepted <= 1'b0; - - if(read_accepted == 0) - read_accepted<=av_waitrequest ? uav_read_pre & ~uav_waitrequest : 1'b0; - end - - end - - reg write_accepted = 0; - generate if (AV_REGISTERINCOMINGSIGNALS) begin - always@(posedge clk, posedge reset) begin - if(reset) - write_accepted <= 1'b0; - else begin - write_accepted <= - ~av_waitrequest ? 1'b0 : - uav_write & ~uav_waitrequest? 1'b1 : - write_accepted; - end - end - end endgenerate - - always@* begin - av_waitrequest = uav_waitrequest; - - if(USE_READDATAVALID == 0 ) begin - av_waitrequest = uav_read_pre ? ~uav_readdatavalid : uav_waitrequest; - end - - if (AV_REGISTERINCOMINGSIGNALS) begin - av_waitrequest = - uav_read_pre ? ~uav_readdatavalid : - uav_write_pre ? (internal_begintransfer | uav_waitrequest) & ~write_accepted : - 1'b1; - end - - if(USE_WAITREQUEST == 0) begin - av_waitrequest = 0; - end - end - - //read/write generation - always@* begin - - uav_write = 1'b0; - uav_write_pre = 1'b0; - uav_read = 1'b0; - uav_read_pre = 1'b0; - - if(!USE_CHIPSELECT) begin - if (USE_READ) begin - uav_read_pre=av_read; - end - - if (USE_WRITE) begin - uav_write_pre=av_write; - end - end - else begin - if(!USE_WRITE && USE_READ) begin - uav_read_pre=av_read; - uav_write_pre=av_chipselect & ~av_read; - end - else if(!USE_READ && USE_WRITE) begin - uav_write_pre=av_write; - uav_read_pre = av_chipselect & ~av_write; - end - else if (USE_READ && USE_WRITE) begin - uav_write_pre=av_write; - uav_read_pre=av_read; - end - end - - if(USE_READDATAVALID == 0) - uav_read = uav_read_pre & ~read_accepted; - else - uav_read = uav_read_pre; - - if(AV_REGISTERINCOMINGSIGNALS == 0) - uav_write=uav_write_pre; - else - uav_write=uav_write_pre & ~write_accepted; - - - end - - // ------------------- - // Begintransfer Assigment - // ------------------- - - reg end_begintransfer; - - always@* begin - if(USE_BEGINTRANSFER) begin - internal_begintransfer = av_begintransfer; - end else begin - internal_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer; - end - end - - always@ ( posedge clk or posedge reset ) begin - - if(reset) begin - end_begintransfer <= 1'b0; - end - else begin - - if(internal_begintransfer == 1 && uav_waitrequest) - end_begintransfer <= 1'b1; - else if(uav_waitrequest) - end_begintransfer <= end_begintransfer; - else - end_begintransfer <= 1'b0; - - end - - end - - // ------------------- - // Beginbursttransfer Assigment - // ------------------- - - reg end_beginbursttransfer; - wire last_burst_transfer_pre; - wire last_burst_transfer_reg; - wire last_burst_transfer; - - // compare values before the mux to shorten critical path; benchmark before changing - assign last_burst_transfer_pre = (uav_burstcount_pre == symbols_per_word); - assign last_burst_transfer_reg = (burstcount_register == symbols_per_word); - assign last_burst_transfer = (internal_beginbursttransfer) ? last_burst_transfer_pre : last_burst_transfer_reg; - - always@* begin - if(USE_BEGINBURSTTRANSFER) begin - internal_beginbursttransfer = av_beginbursttransfer; - end else begin - internal_beginbursttransfer = uav_read ? internal_begintransfer : internal_begintransfer && ~end_beginbursttransfer; - end - end - - always@ ( posedge clk or posedge reset ) begin - - if(reset) begin - end_beginbursttransfer <= 1'b0; - end - else begin - end_beginbursttransfer <= end_beginbursttransfer; - if( last_burst_transfer && internal_begintransfer || uav_read ) begin - end_beginbursttransfer <= 1'b0; - end - else if(uav_write && internal_begintransfer) begin - end_beginbursttransfer <= 1'b1; - end - end - - end - - // synthesis translate_off - - // ------------------------------------------------ - // check_1 : for waitrequest signal violation - // Ensure that when waitreqeust is asserted, the master is not allowed to change its controls - // Exception : begintransfer / beginbursttransfer - // : previously not in any transaction (idle) - // Note : Not checking clken which is not exactly part of Avalon controls/inputs - // : Not using system verilog assertions (seq/prop) since it is not supported if using Modelsim_SE - // ------------------------------------------------ - - reg av_waitrequest_r; - reg av_write_r,av_writeresponserequest_r,av_read_r,av_lock_r,av_chipselect_r,av_debugaccess_r; - reg [AV_ADDRESS_W-1:0] av_address_r; - reg [AV_BYTEENABLE_W-1:0] av_byteenable_r; - reg [AV_BURSTCOUNT_W-1:0] av_burstcount_r; - reg [AV_DATA_W-1:0] av_writedata_r; - - always @(posedge clk or posedge reset) begin - if (reset) begin - av_waitrequest_r <= '0; - av_write_r <= '0; - av_writeresponserequest_r <= '0; - av_read_r <= '0; - av_lock_r <= '0; - av_chipselect_r <= '0; - av_debugaccess_r <= '0; - av_address_r <= '0; - av_byteenable_r <= '0; - av_burstcount_r <= '0; - av_writedata_r <= '0; - - end - else begin - av_waitrequest_r <= av_waitrequest; - av_write_r <= av_write; - av_writeresponserequest_r <= av_writeresponserequest; - av_read_r <= av_read; - av_lock_r <= av_lock; - av_chipselect_r <= av_chipselect; - av_debugaccess_r <= av_debugaccess; - av_address_r <= av_address; - av_byteenable_r <= av_byteenable; - av_burstcount_r <= av_burstcount; - av_writedata_r <= av_writedata; - - if ( av_waitrequest_r && // When waitrequest is asserted - ( (av_write != av_write_r) || // Checks that : Input controls/data does not change - (av_writeresponserequest != av_writeresponserequest_r) || - (av_read != av_read_r) || - (av_lock != av_lock_r) || - (av_debugaccess != av_debugaccess_r) || - (av_address != av_address_r) || - (av_byteenable != av_byteenable_r) || - (av_burstcount != av_burstcount_r) - ) && - (av_write_r | av_read_r) && // Check only when : previously initiated a write/read - (!USE_CHIPSELECT | av_chipselect_r) // and chipselect was asserted (or unused) - ) - $display("%t: %m: Error: Input controls/data changed while av_waitrequest is asserted.\nav_address %x --> %x\nav_byteenable %x --> %x\nav_burstcount %x --> %x\nav_writedata %x --> %x\nav_writeresponserequest %x --> %x\nav_write %x --> %x\nav_read %x --> %x\nav_lock %x --> %x\nav_chipselect %x --> %x\nav_debugaccess %x --> %x ", $time(), - av_address_r , av_address, - av_byteenable_r , av_byteenable, - av_burstcount_r , av_burstcount, - av_writedata_r , av_writedata, - av_writeresponserequest_r, av_writeresponserequest, - av_write_r , av_write, - av_read_r , av_read, - av_lock_r , av_lock, - av_chipselect_r, av_chipselect, - av_debugaccess_r, av_debugaccess); - end - - // end check_1 - - end - - // synthesis translate_on - - - endmodule diff --git a/nios_system/synthesis/submodules/altera_merlin_slave_agent.sv b/nios_system/synthesis/submodules/altera_merlin_slave_agent.sv deleted file mode 100644 index ea599eb..0000000 --- a/nios_system/synthesis/submodules/altera_merlin_slave_agent.sv +++ /dev/null @@ -1,588 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2011 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent.sv#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -`timescale 1 ns / 1 ns - -module altera_merlin_slave_agent -#( - // Packet parameters - parameter PKT_BEGIN_BURST = 81, - parameter PKT_DATA_H = 31, - parameter PKT_DATA_L = 0, - parameter PKT_SYMBOL_W = 8, - parameter PKT_BYTEEN_H = 71, - parameter PKT_BYTEEN_L = 68, - parameter PKT_ADDR_H = 63, - parameter PKT_ADDR_L = 32, - parameter PKT_TRANS_LOCK = 87, - parameter PKT_TRANS_COMPRESSED_READ = 67, - parameter PKT_TRANS_POSTED = 66, - parameter PKT_TRANS_WRITE = 65, - parameter PKT_TRANS_READ = 64, - parameter PKT_SRC_ID_H = 74, - parameter PKT_SRC_ID_L = 72, - parameter PKT_DEST_ID_H = 77, - parameter PKT_DEST_ID_L = 75, - parameter PKT_BURSTWRAP_H = 85, - parameter PKT_BURSTWRAP_L = 82, - parameter PKT_BYTE_CNT_H = 81, - parameter PKT_BYTE_CNT_L = 78, - parameter PKT_PROTECTION_H = 86, - parameter PKT_PROTECTION_L = 86, - parameter PKT_RESPONSE_STATUS_H = 89, - parameter PKT_RESPONSE_STATUS_L = 88, - parameter PKT_BURST_SIZE_H = 92, - parameter PKT_BURST_SIZE_L = 90, - parameter ST_DATA_W = 93, - parameter ST_CHANNEL_W = 32, - - // Slave parameters - parameter ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1, - parameter AVS_DATA_W = PKT_DATA_H - PKT_DATA_L + 1, - parameter AVS_BURSTCOUNT_W = 4, - parameter PKT_SYMBOLS = AVS_DATA_W / PKT_SYMBOL_W, - - // Slave agent parameters - parameter PREVENT_FIFO_OVERFLOW = 0, - parameter SUPPRESS_0_BYTEEN_CMD = 1, - parameter USE_READRESPONSE = 0, - parameter USE_WRITERESPONSE = 0, - - // Derived slave parameters - parameter AVS_BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, - parameter BURST_SIZE_W = 3, - - // Derived FIFO width - parameter FIFO_DATA_W = ST_DATA_W + 1 -) -( - - input clk, - input reset, - - // Universal-Avalon anti-slave - output [ADDR_W-1:0] m0_address, - output [AVS_BURSTCOUNT_W-1:0] m0_burstcount, - output [AVS_BE_W-1:0] m0_byteenable, - output m0_read, - input [AVS_DATA_W-1:0] m0_readdata, - input m0_waitrequest, - output m0_write, - output [AVS_DATA_W-1:0] m0_writedata, - input m0_readdatavalid, - output m0_debugaccess, - output m0_lock, - input [1:0] m0_response, - output m0_writeresponserequest, - input m0_writeresponsevalid, - - // Avalon-ST FIFO interfaces. - // Note: there's no need to include the "data" field here, at least for - // reads, since readdata is filled in from slave info. To keep life - // simple, have a data field, but fill it with 0s. - // Av-st response fifo source interface - output reg [FIFO_DATA_W-1:0] rf_source_data, - output rf_source_valid, - output rf_source_startofpacket, - output rf_source_endofpacket, - input rf_source_ready, - - // Av-st response fifo sink interface - input [FIFO_DATA_W-1:0] rf_sink_data, - input rf_sink_valid, - input rf_sink_startofpacket, - input rf_sink_endofpacket, - output rf_sink_ready, - - // Av-st readdata fifo src interface, data and response - // extra 2 bits for storing RESPONSE STATUS - output [AVS_DATA_W+1:0] rdata_fifo_src_data, - output rdata_fifo_src_valid, - input rdata_fifo_src_ready, - - // Av-st readdata fifo sink interface - input [AVS_DATA_W+1:0] rdata_fifo_sink_data, - input rdata_fifo_sink_valid, - output rdata_fifo_sink_ready, - - // Av-st sink command packet interface - output cp_ready, - input cp_valid, - input [ST_DATA_W-1:0] cp_data, - input [ST_CHANNEL_W-1:0] cp_channel, - input cp_startofpacket, - input cp_endofpacket, - - // Av-st source response packet interface - input rp_ready, - output reg rp_valid, - output reg [ST_DATA_W-1:0] rp_data, - output rp_startofpacket, - output rp_endofpacket -); - - // -------------------------------------------------- - // Ceil(log2()) function log2ceil of 4 = 2 - // -------------------------------------------------- - function integer log2ceil; - input reg[63:0] val; - reg [63:0] i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - - // ------------------------------------------------ - // Local Parameters - // ------------------------------------------------ - localparam DATA_W = PKT_DATA_H - PKT_DATA_L + 1; - localparam BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1; - localparam MID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1; - localparam SID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1; - localparam BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1; - localparam BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1; - localparam BURSTSIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1; - localparam BITS_TO_MASK = log2ceil(PKT_SYMBOLS); - - // ------------------------------------------------ - // Signals - // ------------------------------------------------ - wire [DATA_W-1:0] cmd_data; - wire [BE_W-1:0] cmd_byteen; - wire [ADDR_W-1:0] cmd_addr; - wire [MID_W-1:0] cmd_mid; - wire [SID_W-1:0] cmd_sid; - wire cmd_read; - wire cmd_write; - wire cmd_compressed; - wire cmd_posted; - wire [BYTE_CNT_W-1:0] cmd_byte_cnt; - wire [BURSTWRAP_W-1:0] cmd_burstwrap; - wire [BURSTSIZE_W-1:0] cmd_burstsize; - wire cmd_debugaccess; - - wire byteen_asserted; - wire needs_response_synthesis; - wire generate_response; - - // Assign command fields - assign cmd_data = cp_data[PKT_DATA_H :PKT_DATA_L ]; - assign cmd_byteen = cp_data[PKT_BYTEEN_H:PKT_BYTEEN_L]; - assign cmd_addr = cp_data[PKT_ADDR_H :PKT_ADDR_L ]; - assign cmd_compressed = cp_data[PKT_TRANS_COMPRESSED_READ]; - assign cmd_posted = cp_data[PKT_TRANS_POSTED]; - assign cmd_write = cp_data[PKT_TRANS_WRITE]; - assign cmd_read = cp_data[PKT_TRANS_READ]; - assign cmd_mid = cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L]; - assign cmd_sid = cp_data[PKT_DEST_ID_H:PKT_DEST_ID_L]; - assign cmd_byte_cnt = cp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]; - assign cmd_burstwrap = cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]; - assign cmd_burstsize = cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]; - assign cmd_debugaccess = cp_data[PKT_PROTECTION_L]; - - // Local "ready_for_command" signal: deasserted when the agent is unable to accept - // another command, e.g. rdv FIFO is full, (local readdata storage is full && - // ~rp_ready), ... - // Say, this could depend on the type of command, for example, even if the - // rdv FIFO is full, a write request can be accepted. For later. - wire ready_for_command; - - wire local_lock = cp_valid & cp_data[PKT_TRANS_LOCK]; - wire local_write = cp_valid & cp_data[PKT_TRANS_WRITE]; - wire local_read = cp_valid & cp_data[PKT_TRANS_READ]; - wire local_compressed_read = cp_valid & cp_data[PKT_TRANS_COMPRESSED_READ]; - wire nonposted_write_endofpacket = ~cp_data[PKT_TRANS_POSTED] & local_write & cp_endofpacket; - - // num_symbols is PKT_SYMBOLS, appropriately sized. - wire [31:0] int_num_symbols = PKT_SYMBOLS; - wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0]; - - generate - if (PREVENT_FIFO_OVERFLOW) begin : prevent_fifo_overflow - // --------------------------------------------------- - // Backpressure if the slave says to, or if FIFO overflow may occur. - // - // All commands are backpressured once the FIFO is full - // even if they don't need storage. This breaks a long - // combinatorial path from the master read/write through - // this logic and back to the master via the backpressure - // path. - // - // To avoid a loss of throughput the FIFO will be parameterized - // one slot deeper. The extra slot should never be used in normal - // operation, but should a slave misbehave and accept one more - // read than it should then backpressure will kick in. - // - // An example: assume a slave with MPRT = 2. It can accept a - // command sequence RRWW without backpressuring. If the FIFO is - // only 2 deep, we'd backpressure the writes leading to loss of - // throughput. If the FIFO is 3 deep, we'll only backpressure when - // RRR... which is an illegal condition anyway. - // --------------------------------------------------- - - assign ready_for_command = rf_source_ready; - assign cp_ready = (~m0_waitrequest | ~byteen_asserted) && ready_for_command; - - end else begin : no_prevent_fifo_overflow - - // Do not suppress the command or the slave will - // not be able to waitrequest - assign ready_for_command = 1'b1; - // Backpressure only if the slave says to. - assign cp_ready = ~m0_waitrequest | ~byteen_asserted; - - end - endgenerate - - generate if (SUPPRESS_0_BYTEEN_CMD) begin : suppress_0_byteen_cmd - assign byteen_asserted = |cmd_byteen; - end else begin : no_suppress_0_byteen_cmd - assign byteen_asserted = 1'b1; - end - endgenerate - - // ------------------------------------------------------------------- - // Extract avalon signals from command packet. - // ------------------------------------------------------------------- - // Mask off the lower bits of address. - // The burst adapter before this component will break narrow sized packets - // into sub-bursts of length 1. However, the packet addresses are preserved, - // which means this component may see size-aligned addresses. - // - // Masking ensures that the addresses seen by an Avalon slave are aligned to - // the full data width instead of the size. - // - // Example: - // output from burst adapter (datawidth=4, size=2 bytes): - // subburst1 addr=0, subburst2 addr=2, subburst3 addr=4, subburst4 addr=6 - // expected output from slave agent: - // subburst1 addr=0, subburst2 addr=0, subburst3 addr=4, subburst4 addr=4 - generate - if (BITS_TO_MASK > 0) begin : mask_address - - assign m0_address = { cmd_addr[ADDR_W-1:BITS_TO_MASK], {BITS_TO_MASK{1'b0}} }; - - end else begin : no_mask_address - - assign m0_address = cmd_addr; - - end - endgenerate - - assign m0_byteenable = cmd_byteen; - assign m0_writedata = cmd_data; - - // Note: no Avalon-MM slave in existence accepts uncompressed read bursts - - // this sort of burst exists only in merlin fabric ST packets. What to do - // if we see such a burst? All beats in that burst need to be transmitted - // to the slave so we have enough space-time for byteenable expression. - // - // There can be multiple bursts in a packet, but only one beat per burst - // in cases. The exception is when we've decided not to insert a - // burst adapter for efficiency reasons, in which case this agent is also - // responsible for driving burstcount to 1 on each beat of an uncompressed - // read burst. - - assign m0_read = ready_for_command & byteen_asserted & - (local_compressed_read | local_read); - - generate - begin : m0_burstcount_zero_pad - // AVS_BURSTCOUNT_W and BYTE_CNT_W may not be equal. Assign m0_burstcount - // from a sub-range, or 0-pad, as appropriate. - if (AVS_BURSTCOUNT_W > BYTE_CNT_W) begin - wire [AVS_BURSTCOUNT_W - BYTE_CNT_W - 1 : 0] zero_pad = - {(AVS_BURSTCOUNT_W - BYTE_CNT_W) {1'b0}}; - assign m0_burstcount = (local_read & ~local_compressed_read) ? - {zero_pad, num_symbols} : - {zero_pad, cmd_byte_cnt}; - end - else begin : m0_burstcount_no_pad - assign m0_burstcount = (local_read & ~local_compressed_read) ? - num_symbols[AVS_BURSTCOUNT_W-1:0] : - cmd_byte_cnt[AVS_BURSTCOUNT_W-1:0]; - end - end - endgenerate - - assign m0_write = ready_for_command & local_write & byteen_asserted; - assign m0_lock = ready_for_command & local_lock & (m0_read | m0_write); - assign m0_debugaccess = cmd_debugaccess; - // For now, to support write response - assign m0_writeresponserequest = ready_for_command & local_write & byteen_asserted & !cmd_posted; - //assign m0_writeresponserequest = '0; - - // ------------------------------------------------------------------- - // Indirection layer for response packet values. Some may always wire - // directly from the slave translator; others will no doubt emerge from - // various FIFOs. - // What to put in resp_data when a write occured? Answer: it does not - // matter, because only response status is needed for non-posted writes, - // and the packet already has a field for that. - - // tgngo:Use the rdata_fifo to store write response as well - // So that we wont lost response if master can back-pressured - // as well as it needs for write response merging - assign rdata_fifo_src_valid = m0_readdatavalid | m0_writeresponsevalid; - //assign rdata_fifo_src_valid = m0_readdatavalid; - assign rdata_fifo_src_data = {m0_response,m0_readdata}; - - // ------------------------------------------------------------------ - // Generate a token when read commands are suppressed. The token - // is stored in the response FIFO, and will be used to synthesize - // a read response. The same token is used for non-posted write - // response synthesis. - // - // Note: this token is not generated for suppressed uncompressed read cycles; - // the burst uncompression logic at the read side of the response FIFO - // generates the correct number of responses. - // ------------------------------------------------------------------ - // When the slave can return the response, let it does its works. Dont generate sysnthesis response - assign needs_response_synthesis = ((local_read | local_compressed_read) & !byteen_asserted) | (nonposted_write_endofpacket && !USE_WRITERESPONSE); - - // Avalon-ST interfaces to external response fifo: - // tgngo:Currently, with "generate response synthesis", only one write command is allowed to write in at eop of non-posted write - // To support response from slave, we need to store each sub-burst of write command into fifo. - // Each sub-burst will return a response and these two command and response are popped out together - // Resposne merging will happen and at end_of_packet of the command - the last sub-burst write - // the slave agent will send out the final merged response - - wire internal_cp_endofburst; - wire [31:0] minimum_bytecount_wire = PKT_SYMBOLS; // to solve qis warning - wire [AVS_BURSTCOUNT_W-1:0] minimum_bytecount; - assign minimum_bytecount = minimum_bytecount_wire[AVS_BURSTCOUNT_W-1:0]; - assign internal_cp_endofburst = (cmd_byte_cnt == minimum_bytecount); - wire local_nonposted_write = ~cp_data[PKT_TRANS_POSTED] & local_write; - wire nonposted_end_of_subburst = local_nonposted_write & internal_cp_endofburst; - - assign rf_source_valid = (local_read | local_compressed_read | (nonposted_write_endofpacket && !USE_WRITERESPONSE) | (USE_WRITERESPONSE && nonposted_end_of_subburst)) - & ready_for_command & cp_ready; - assign rf_source_startofpacket = cp_startofpacket; - assign rf_source_endofpacket = cp_endofpacket; - always @* begin - // default: assign every command packet field to the response FIFO... - rf_source_data = {1'b0, cp_data}; - - // ... and override select fields as needed. - rf_source_data[FIFO_DATA_W-1] = needs_response_synthesis; - rf_source_data[PKT_DATA_H :PKT_DATA_L] = {DATA_W {1'b0}}; - rf_source_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = cmd_byteen; - rf_source_data[PKT_ADDR_H :PKT_ADDR_L] = cmd_addr; - //rf_source_data[PKT_ADDR_H :PKT_ADDR_L] = m0_address; - rf_source_data[PKT_TRANS_COMPRESSED_READ] = cmd_compressed; - rf_source_data[PKT_TRANS_POSTED] = cmd_posted; - rf_source_data[PKT_TRANS_WRITE] = cmd_write; - rf_source_data[PKT_TRANS_READ] = cmd_read; - rf_source_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = cmd_mid; - rf_source_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = cmd_sid; - rf_source_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = cmd_byte_cnt; - rf_source_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = cmd_burstwrap; - rf_source_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = cmd_burstsize; - rf_source_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = '0; - rf_source_data[PKT_PROTECTION_L] = cmd_debugaccess; - end - - wire uncompressor_source_valid; - wire [BURSTSIZE_W-1:0] uncompressor_burstsize; - - //assign rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; - // tgngo: last_write_response indicates the last response of the burst (incase need sub-burst) - // at this time, the final response merged will send out, and rp_valid is only asserted - // for one response for whole burst - generate - if (USE_READRESPONSE & USE_WRITERESPONSE) begin - wire last_write_response = rf_sink_data[PKT_TRANS_WRITE] & !rf_sink_data[PKT_TRANS_POSTED] & rf_sink_endofpacket; - always @* begin - if (rf_sink_data[PKT_TRANS_WRITE] == 1) - rp_valid = rdata_fifo_sink_valid & last_write_response; - else - rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; - end - end else begin - always @* begin - rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; - end - end - endgenerate - // ------------------------------------------------------------------ - // Response merging - // ------------------------------------------------------------------ - wire [1:0] current_response = rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W]; - reg [1:0] response_merged; - generate - begin: response_merging - if (USE_READRESPONSE & USE_WRITERESPONSE) begin - reg first_write_response; - reg reset_merged_output; - reg [1:0] previous_response_in; - reg [1:0] previous_response; - - always_ff @(posedge clk, posedge reset) begin - if (reset) begin - first_write_response <= 1'b1; - end - else begin // Merging work for write response, for read: previous_response_in = current_response - if (rf_sink_valid & rdata_fifo_sink_valid & rf_sink_data[PKT_TRANS_WRITE]) begin - first_write_response <= 1'b0; - if (rf_sink_endofpacket) - first_write_response <= 1'b1; - end - end - end - - always_comb begin - reset_merged_output = first_write_response && rdata_fifo_sink_valid; - previous_response_in = reset_merged_output ? current_response : previous_response; - response_merged = current_response >= previous_response ? current_response: previous_response_in; - end - - always_ff @(posedge clk or posedge reset) begin - if (reset) begin - previous_response <= 2'b00; - end - else begin - if (rf_sink_valid & rdata_fifo_sink_valid) begin - previous_response <= response_merged; - end - end - end - end else begin - always @* begin - response_merged = current_response; - end - end - end - endgenerate - - assign generate_response = rf_sink_data[FIFO_DATA_W-1]; - - wire [BYTE_CNT_W-1:0] rf_sink_byte_cnt = rf_sink_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]; - wire rf_sink_compressed = rf_sink_data[PKT_TRANS_COMPRESSED_READ]; - wire [BURSTWRAP_W-1:0] rf_sink_burstwrap = rf_sink_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]; - wire [BURSTSIZE_W-1:0] rf_sink_burstsize = rf_sink_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]; - wire [ADDR_W-1:0] rf_sink_addr = rf_sink_data[PKT_ADDR_H:PKT_ADDR_L]; - // a non posted write response is always completed in 1 cycle. Modify the startofpacket signal to 1'b1 instead of taking whatever is in the rf_fifo - wire rf_sink_startofpacket_wire = rf_sink_data[PKT_TRANS_WRITE] ? 1'b1 : rf_sink_startofpacket; - - wire [BYTE_CNT_W-1:0] burst_byte_cnt; - wire [BURSTWRAP_W-1:0] rp_burstwrap; - wire [ADDR_W-1:0] rp_address; - wire rp_is_compressed; - - // ------------------------------------------------------------------ - // Backpressure the readdata fifo if we're supposed to synthesize a response. - // This may be a read response (for suppressed reads) or a write response - // (for non-posted writes). - // ------------------------------------------------------------------ - assign rdata_fifo_sink_ready = rdata_fifo_sink_valid & rp_ready & ~(rf_sink_valid & generate_response); - - always @* begin - // By default, return all fields... - rp_data = rf_sink_data[ST_DATA_W - 1 : 0]; - - // ... and override specific fields. - rp_data[PKT_DATA_H :PKT_DATA_L] = rdata_fifo_sink_data[AVS_DATA_W-1:0]; - // Assignments directly from the response fifo. - rp_data[PKT_TRANS_POSTED] = rf_sink_data[PKT_TRANS_POSTED]; - rp_data[PKT_TRANS_WRITE] = rf_sink_data[PKT_TRANS_WRITE]; - rp_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = rf_sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; - rp_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = rf_sink_data[PKT_SRC_ID_H : PKT_SRC_ID_L]; - rp_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = rf_sink_data[PKT_BYTEEN_H : PKT_BYTEEN_L]; - rp_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = rf_sink_data[PKT_PROTECTION_H:PKT_PROTECTION_L]; - - // Burst uncompressor assignments - rp_data[PKT_ADDR_H :PKT_ADDR_L] = rp_address; - rp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = rp_burstwrap; - rp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = burst_byte_cnt; - rp_data[PKT_TRANS_READ] = rf_sink_data[PKT_TRANS_READ] | rf_sink_data[PKT_TRANS_COMPRESSED_READ]; - rp_data[PKT_TRANS_COMPRESSED_READ] = rp_is_compressed; - - // avalon slaves always respond with "okay" -> not true for now - //rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L] = {RESPONSE_W{ 1'b0 }}; - rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L] = response_merged; - rp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = uncompressor_burstsize; - end - - // ------------------------------------------------------------------ - // Note: the burst uncompressor may be asked to generate responses for - // write packets; these are treated the same as single-cycle uncompressed - // reads. - // ------------------------------------------------------------------ - altera_merlin_burst_uncompressor #( - .ADDR_W (ADDR_W), - .BURSTWRAP_W (BURSTWRAP_W), - .BYTE_CNT_W (BYTE_CNT_W), - .PKT_SYMBOLS (PKT_SYMBOLS) - ) uncompressor - ( - .clk (clk), - .reset (reset), - .sink_startofpacket (rf_sink_startofpacket_wire), - .sink_endofpacket (rf_sink_endofpacket), - .sink_valid (rf_sink_valid & (rdata_fifo_sink_valid | generate_response)), - .sink_ready (rf_sink_ready), - .sink_addr (rf_sink_addr), - .sink_burstwrap (rf_sink_burstwrap), - .sink_byte_cnt (rf_sink_byte_cnt), - .sink_is_compressed (rf_sink_compressed), - .sink_burstsize (rf_sink_burstsize), - - .source_startofpacket (rp_startofpacket), - .source_endofpacket (rp_endofpacket), - .source_valid (uncompressor_source_valid), - .source_ready (rp_ready), - .source_addr (rp_address), - .source_burstwrap (rp_burstwrap), - .source_byte_cnt (burst_byte_cnt), - .source_is_compressed (rp_is_compressed), - .source_burstsize (uncompressor_burstsize) - ); - -//-------------------------------------- -// Assertion: In case slave support response. Yhe slave needs return response in order -// Ex: non-posted write followed by a read: write response must complete before read data -//-------------------------------------- -// synthesis translate_off -ERROR_write_response_and_read_response_cannot_happen_same_time: - assert property ( @(posedge clk) - disable iff (reset) !(m0_writeresponsevalid && m0_readdatavalid) - ); - -// synthesis translate_on -endmodule - diff --git a/nios_system/synthesis/submodules/altera_merlin_slave_translator.sv b/nios_system/synthesis/submodules/altera_merlin_slave_translator.sv deleted file mode 100644 index bcb2311..0000000 --- a/nios_system/synthesis/submodules/altera_merlin_slave_translator.sv +++ /dev/null @@ -1,533 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------- -// Merlin Slave Translator -// -// Translates Universal Avalon MM Slave -// to any Avalon MM Slave -// ------------------------------------- -// -//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one -//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero -//The key feature here is that no same cycle turnaround data is processed through the fabric. - -//import avalon_utilities_pkg::*; - -`timescale 1 ns / 1 ns - -module altera_merlin_slave_translator - #( - parameter - //Widths - AV_ADDRESS_W = 32, - AV_DATA_W = 32, - AV_BURSTCOUNT_W = 4, - AV_BYTEENABLE_W = 4, - UAV_BYTEENABLE_W = 4, - - //Read Latency - AV_READLATENCY = 1, - - //Timing - AV_READ_WAIT_CYCLES = 0, - AV_WRITE_WAIT_CYCLES = 0, - AV_SETUP_WAIT_CYCLES = 0, - AV_DATA_HOLD_CYCLES = 0, - - //Optional Port Declarations - USE_READDATAVALID = 1, - USE_WAITREQUEST = 1, - USE_READRESPONSE = 0, - USE_WRITERESPONSE = 0, - - //Variable Addressing - AV_SYMBOLS_PER_WORD = 4, - AV_ADDRESS_SYMBOLS = 0, - AV_BURSTCOUNT_SYMBOLS = 0, - BITS_PER_WORD = clog2_plusone(AV_SYMBOLS_PER_WORD - 1), - UAV_ADDRESS_W = 38, - UAV_BURSTCOUNT_W = 10, - UAV_DATA_W = 32, - - AV_CONSTANT_BURST_BEHAVIOR = 0, - UAV_CONSTANT_BURST_BEHAVIOR = 0, - CHIPSELECT_THROUGH_READLATENCY = 0, - - // Tightly-Coupled Options - USE_UAV_CLKEN = 0, - AV_REQUIRE_UNALIGNED_ADDRESSES = 0 - ) - ( - - // ------------------- - // Clock & Reset - // ------------------- - input wire clk, - input wire reset, - - // ------------------- - // Universal Avalon Slave - // ------------------- - - input wire [UAV_ADDRESS_W - 1 : 0] uav_address, - input wire [UAV_DATA_W - 1 : 0] uav_writedata, - input wire uav_write, - input wire uav_read, - input wire [UAV_BURSTCOUNT_W - 1 : 0] uav_burstcount, - input wire [UAV_BYTEENABLE_W - 1 : 0] uav_byteenable, - input wire uav_lock, - input wire uav_debugaccess, - input wire uav_clken, - - output logic uav_readdatavalid, - output logic uav_waitrequest, - output logic [UAV_DATA_W - 1 : 0] uav_readdata, - output logic [1:0] uav_response, - input wire uav_writeresponserequest, - output logic uav_writeresponsevalid, - - // ------------------- - // Customizable Avalon Master - // ------------------- - output logic [AV_ADDRESS_W - 1 : 0] av_address, - output logic [AV_DATA_W - 1 : 0] av_writedata, - output logic av_write, - output logic av_read, - output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount, - output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable, - output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable, - output logic av_begintransfer, - output wire av_chipselect, - output logic av_beginbursttransfer, - output logic av_lock, - output wire av_clken, - output wire av_debugaccess, - output wire av_outputenable, - - input logic [AV_DATA_W - 1 : 0] av_readdata, - input logic av_readdatavalid, - input logic av_waitrequest, - - input logic [1:0] av_response, - output logic av_writeresponserequest, - input wire av_writeresponsevalid - - ); - - function integer clog2_plusone; - input [31:0] Depth; - integer i; - begin - i = Depth; - for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1) - i = i >> 1; - end - - endfunction - - function integer max; - //returns the larger of two passed arguments - input [31:0] one; - input [31:0] two; - - if(one > two) - max=one; - else - max=two; - endfunction // int - - localparam AV_READ_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES); - localparam AV_WRITE_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES); - localparam AV_DATA_HOLD_INDEXED = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES); - localparam LOG2_OF_LATENCY_SUM = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1)); - localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD; - localparam ADDRESS_SHIFT_SELECTOR = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD; - - localparam ADDRESS_HIGH = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ? - AV_ADDRESS_W : - UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR; - - localparam BURSTCOUNT_HIGH = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ? - AV_BURSTCOUNT_W : - UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR; - localparam BYTEENABLE_ADDRESS_BITS = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1; - - - // Calculate the symbols per word as the power of 2 extended symbols per word - wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1)); - wire [UAV_BURSTCOUNT_W : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W : 0]; - - // +-------------------------------- - // |Backwards Compatibility Signals - // +-------------------------------- - assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1; - assign av_debugaccess = uav_debugaccess; - - // +------------------- - // |Passthru Signals - // +------------------- - always_comb - begin - if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin - uav_response = '0; - end else begin - uav_response = av_response; - end - end - assign av_writeresponserequest = uav_writeresponserequest; - assign uav_writeresponsevalid = av_writeresponsevalid; - - //------------------------- - //Writedata and Byteenable - //------------------------- - - always@* begin - av_byteenable = '0; - av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0]; - end - - always@* begin - av_writedata = '0; - av_writedata = uav_writedata[AV_DATA_W - 1 : 0]; - end - - // +------------------- - // |Calculated Signals - // +------------------- - - logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address; - - function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable; - input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable; - - for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin - if(byteenable[i] == 1) begin - return i; - end - end - - return '0; - - endfunction - - reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg; - reg [AV_ADDRESS_W - 1 : 0] address_reg; - - - always@(posedge clk, posedge reset) begin - if(reset) begin - burstcount_reg <= '0; - address_reg <= '0; - end - else begin - burstcount_reg <= burstcount_reg; - address_reg <= address_reg; - - if(av_beginbursttransfer) begin - burstcount_reg <= uav_burstcount [BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ]; - address_reg <= real_uav_address [ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ]; - - end - end - end - - - logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire; - - always@* begin - if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin - temp_wire = decode_byteenable(uav_byteenable); - - real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] }; - end - else begin - real_uav_address = uav_address; - end - - av_address = real_uav_address[ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ]; - - if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer ) - av_address = address_reg; - end - - always@* begin - av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ]; - - if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer ) - av_burstcount = burstcount_reg; - end - - always@* begin - av_lock = uav_lock; - end - - // ------------------- - // Writebyteenable Assignment - // ------------------- - -always@* begin - av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0]; -end - - // ------------------- - // Waitrequest Assignment - // ------------------- - - reg av_waitrequest_generated; - reg av_waitrequest_generated_read; - reg av_waitrequest_generated_write; - reg waitrequest_reset_override; - - reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter; - - always@(posedge reset, posedge clk) begin - - if(reset) begin - wait_latency_counter <= '0; - waitrequest_reset_override <= 1'h1; - end - else begin - waitrequest_reset_override <= 1'h0; - - wait_latency_counter <= '0; - - if( uav_read | uav_write ) - wait_latency_counter <= wait_latency_counter + 1'h1; - - if( ~uav_waitrequest | waitrequest_reset_override ) - wait_latency_counter <= '0; - - end - - end - - - always @* begin - - av_read = uav_read; - av_write = uav_write; - - av_waitrequest_generated = 1'h1; - av_waitrequest_generated_read = 1'h1; - av_waitrequest_generated_write = 1'h1; - - if(LOG2_OF_LATENCY_SUM == 1) - av_waitrequest_generated = 0; - - if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin - av_read = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read; - av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED; - - av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED; - av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED; - - if(uav_write) - av_waitrequest_generated = av_waitrequest_generated_write; - else - av_waitrequest_generated = av_waitrequest_generated_read; - - end - - if(USE_WAITREQUEST) begin - uav_waitrequest = av_waitrequest; - end - else begin - uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override; - end - - end - - // -------------- - // Readdata Assignment - // -------------- - - reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre; - - always@(posedge clk, posedge reset) begin - if(reset) - av_readdata_pre <= 'b0; - else - av_readdata_pre <= av_readdata; - end - - always@* begin - uav_readdata = '0; - - if( AV_READLATENCY != 0 || USE_READDATAVALID ) begin - uav_readdata = av_readdata; - end - else begin - uav_readdata = av_readdata_pre; - end - end - // ------------------- - // Readdatavalid Assigment - // ------------------- - - reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg; - reg top_read_latency_shift_reg; - - - - always@* begin - - uav_readdatavalid=top_read_latency_shift_reg; - - if(USE_READDATAVALID) begin - uav_readdatavalid = av_readdatavalid; - end - - end - - always@* begin - - top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override; - - if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin - top_read_latency_shift_reg=read_latency_shift_reg; - end - - if (AV_READLATENCY > 1) begin - top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)]; - end - - end - - always@(posedge reset, posedge clk) begin - - if (reset) begin - read_latency_shift_reg <= '0; - end - else if (av_clken) begin - - read_latency_shift_reg <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override; - - for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin - read_latency_shift_reg[i+1] <= read_latency_shift_reg[i]; - end - - end - - end - - // ------------ - // Chipselect and OutputEnable - // ------------ - - reg av_chipselect_pre; - wire cs_extension; - reg av_outputenable_pre; - - - assign av_chipselect = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre; - assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg)); - - assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre; - - always@(posedge reset, posedge clk) begin - if(reset) - av_outputenable_pre <= 1'b0; - else if( AV_READLATENCY == 0 && AV_READ_WAIT_INDEXED != 0 ) - av_outputenable_pre <= 0; - else - av_outputenable_pre <= cs_extension | uav_read; - end - - always@(posedge reset, posedge clk) begin - if(reset) begin - av_chipselect_pre <= 1'b0; - end - else begin - av_chipselect_pre <= 1'b0; - - if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin - //The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall. - //There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator. - if(uav_read) begin - av_chipselect_pre <= 1'b1; - end - else if(cs_extension == 1) begin - av_chipselect_pre <= 1'b1; - end - - end - end - end - - // ------------------- - // Begintransfer Assigment - // ------------------- - - reg end_begintransfer; - - always@* begin - av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer; - end - - always@ ( posedge clk or posedge reset ) begin - - if(reset) begin - end_begintransfer <= 1'b0; - end - else begin - - if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override) - end_begintransfer <= 1'b1; - else if(uav_waitrequest) - end_begintransfer <= end_begintransfer; - else - end_begintransfer <= 1'b0; - - end - - end - - // ------------------- - // Beginbursttransfer Assigment - // ------------------- - - reg end_beginbursttransfer; - reg in_transfer; - - - - always@* begin - av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer); - end - - always@ ( posedge clk or posedge reset ) begin - if(reset) begin - end_beginbursttransfer <= 1'b0; - in_transfer <= 1'b0; - end - else begin - - end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word ); - - if(uav_write && uav_burstcount == symbols_per_word) - in_transfer <=1'b0; - else if(uav_write) - in_transfer <=1'b1; - - end - - end - -endmodule diff --git a/nios_system/synthesis/submodules/altera_reset_controller.sdc b/nios_system/synthesis/submodules/altera_reset_controller.sdc deleted file mode 100644 index d58dd05..0000000 --- a/nios_system/synthesis/submodules/altera_reset_controller.sdc +++ /dev/null @@ -1,33 +0,0 @@ -# (C) 2001-2013 Altera Corporation. All rights reserved. -# Your use of Altera Corporation's design tools, logic functions and other -# software and tools, and its AMPP partner logic functions, and any output -# files any of the foregoing (including device programming or simulation -# files), and any associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License Subscription -# Agreement, Altera MegaCore Function License Agreement, or other applicable -# license agreement, including, without limitation, that your use is for the -# sole purpose of programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the applicable -# agreement for further details. - - -# +--------------------------------------------------- -# | Cut the async clear paths -# +--------------------------------------------------- -set aclr_counter 0 -set clrn_counter 0 -set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] -set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] -foreach_in_collection aclr_pin $aclr_collection { - set aclr_counter [expr $aclr_counter + 1] -} -foreach_in_collection clrn_pin $clrn_collection { - set clrn_counter [expr $clrn_counter + 1] -} -if {$aclr_counter > 0} { - set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] -} - -if {$clrn_counter > 0} { - set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] -} diff --git a/nios_system/synthesis/submodules/altera_reset_controller.v b/nios_system/synthesis/submodules/altera_reset_controller.v deleted file mode 100644 index 7c250c7..0000000 --- a/nios_system/synthesis/submodules/altera_reset_controller.v +++ /dev/null @@ -1,206 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_reset_controller/altera_reset_controller.v#2 $ -// $Revision: #2 $ -// $Date: 2013/06/03 $ -// $Author: wkleong $ - -// -------------------------------------- -// Reset controller -// -// Combines all the input resets and synchronizes -// the result to the clk. -// ACDS13.1 - Added reset request as part of reset sequencing -// -------------------------------------- - -`timescale 1 ns / 1 ns - -module altera_reset_controller -#( - parameter NUM_RESET_INPUTS = 6, - parameter OUTPUT_RESET_SYNC_EDGES = "deassert", - parameter SYNC_DEPTH = 2, - parameter RESET_REQUEST_PRESENT = 0 -) -( - // -------------------------------------- - // We support up to 16 reset inputs, for now - // -------------------------------------- - input reset_in0, - input reset_in1, - input reset_in2, - input reset_in3, - input reset_in4, - input reset_in5, - input reset_in6, - input reset_in7, - input reset_in8, - input reset_in9, - input reset_in10, - input reset_in11, - input reset_in12, - input reset_in13, - input reset_in14, - input reset_in15, - - input clk, - output reg reset_out, - output reg reset_req -); - - localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert"); - - localparam DEPTH = 2; - localparam CLKEN_LAGS_RESET = 0; - localparam EARLY_RST_TAP = (CLKEN_LAGS_RESET != 0) ? 0 : 1; - - wire merged_reset; - wire reset_out_pre; - - // Registers and Interconnect - (*preserve*) reg [SYNC_DEPTH: 0] altera_reset_synchronizer_int_chain; - reg [(SYNC_DEPTH-1): 0] r_sync_rst_chain; - reg r_sync_rst_dly; - reg r_sync_rst; - reg r_early_rst; - - // -------------------------------------- - // "Or" all the input resets together - // -------------------------------------- - assign merged_reset = ( - reset_in0 | - reset_in1 | - reset_in2 | - reset_in3 | - reset_in4 | - reset_in5 | - reset_in6 | - reset_in7 | - reset_in8 | - reset_in9 | - reset_in10 | - reset_in11 | - reset_in12 | - reset_in13 | - reset_in14 | - reset_in15 - ); - - // -------------------------------------- - // And if required, synchronize it to the required clock domain, - // with the correct synchronization type - // -------------------------------------- - generate if (OUTPUT_RESET_SYNC_EDGES == "none") begin - - assign reset_out_pre = merged_reset; - - end else begin - - altera_reset_synchronizer - #( - .DEPTH (SYNC_DEPTH), - .ASYNC_RESET(ASYNC_RESET) - ) - alt_rst_sync_uq1 - ( - .clk (clk), - .reset_in (merged_reset), - .reset_out (reset_out_pre) - ); - - end - endgenerate - - generate if (RESET_REQUEST_PRESENT == 0) begin - always @* begin - reset_out = reset_out_pre; - reset_req = 1'b0; - end - end - else begin - - // 3-FF Metastability Synchronizer - initial - begin - altera_reset_synchronizer_int_chain <= 3'b111; - end - - always @(posedge clk) - begin - altera_reset_synchronizer_int_chain[2:0] <= {altera_reset_synchronizer_int_chain[1:0], reset_out_pre}; - end - - - // Synchronous reset pipe - initial - begin - r_sync_rst_chain <= {DEPTH{1'b1}}; - end - - always @(posedge clk) - begin - if (altera_reset_synchronizer_int_chain[2] == 1'b1) - begin - r_sync_rst_chain <= {DEPTH{1'b1}}; - end - else - begin - r_sync_rst_chain <= {1'b0, r_sync_rst_chain[DEPTH-1:1]}; - end - end - - // Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition - // matches the early input. - initial - begin - r_sync_rst_dly <= 1'b1; - r_sync_rst <= 1'b1; - r_early_rst <= 1'b1; - end - - always @(posedge clk) - begin - // Delayed reset pipeline register - r_sync_rst_dly <= r_sync_rst_chain[DEPTH-1]; - - case ({r_sync_rst_dly, r_sync_rst_chain[1], r_sync_rst}) - 3'b000: r_sync_rst <= 1'b0; // Not reset - 3'b001: r_sync_rst <= 1'b0; - 3'b010: r_sync_rst <= 1'b0; - 3'b011: r_sync_rst <= 1'b1; - 3'b100: r_sync_rst <= 1'b1; - 3'b101: r_sync_rst <= 1'b1; - 3'b110: r_sync_rst <= 1'b1; - 3'b111: r_sync_rst <= 1'b1; // In Reset - default: r_sync_rst <= 1'b1; - endcase - - case ({r_sync_rst_chain[DEPTH-1], r_sync_rst_chain[EARLY_RST_TAP]}) - 2'b00: r_early_rst <= 1'b0; // Not reset - 2'b01: r_early_rst <= 1'b1; // Coming out of reset - 2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design. - 2'b11: r_early_rst <= 1'b1; // Held in reset - default: r_early_rst <= 1'b1; - endcase - end - - always @* begin - reset_out = r_sync_rst; - reset_req = r_early_rst; - end - - end - endgenerate - -endmodule diff --git a/nios_system/synthesis/submodules/altera_reset_synchronizer.v b/nios_system/synthesis/submodules/altera_reset_synchronizer.v deleted file mode 100644 index 14936c3..0000000 --- a/nios_system/synthesis/submodules/altera_reset_synchronizer.v +++ /dev/null @@ -1,87 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ----------------------------------------------- -// Reset Synchronizer -// ----------------------------------------------- -`timescale 1 ns / 1 ns - -module altera_reset_synchronizer -#( - parameter ASYNC_RESET = 1, - parameter DEPTH = 2 -) -( - input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, - - input clk, - output reset_out -); - - // ----------------------------------------------- - // Synchronizer register chain. We cannot reuse the - // standard synchronizer in this implementation - // because our timing constraints are different. - // - // Instead of cutting the timing path to the d-input - // on the first flop we need to cut the aclr input. - // - // We omit the "preserve" attribute on the final - // output register, so that the synthesis tool can - // duplicate it where needed. - // ----------------------------------------------- - (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; - reg altera_reset_synchronizer_int_chain_out; - - generate if (ASYNC_RESET) begin - - // ----------------------------------------------- - // Assert asynchronously, deassert synchronously. - // ----------------------------------------------- - always @(posedge clk or posedge reset_in) begin - if (reset_in) begin - altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; - altera_reset_synchronizer_int_chain_out <= 1'b1; - end - else begin - altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; - altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; - altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; - end - end - - assign reset_out = altera_reset_synchronizer_int_chain_out; - - end else begin - - // ----------------------------------------------- - // Assert synchronously, deassert synchronously. - // ----------------------------------------------- - always @(posedge clk) begin - altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; - altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; - altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; - end - - assign reset_out = altera_reset_synchronizer_int_chain_out; - - end - endgenerate - -endmodule - diff --git a/nios_system/synthesis/submodules/nios_system_LEDRs.v b/nios_system/synthesis/submodules/nios_system_LEDRs.v deleted file mode 100644 index 63ed909..0000000 --- a/nios_system/synthesis/submodules/nios_system_LEDRs.v +++ /dev/null @@ -1,66 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_LEDRs ( - // inputs: - address, - chipselect, - clk, - reset_n, - write_n, - writedata, - - // outputs: - out_port, - readdata - ) -; - - output [ 17: 0] out_port; - output [ 31: 0] readdata; - input [ 1: 0] address; - input chipselect; - input clk; - input reset_n; - input write_n; - input [ 31: 0] writedata; - - wire clk_en; - reg [ 17: 0] data_out; - wire [ 17: 0] out_port; - wire [ 17: 0] read_mux_out; - wire [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {18 {(address == 0)}} & data_out; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - data_out <= 0; - else if (chipselect && ~write_n && (address == 0)) - data_out <= writedata[17 : 0]; - end - - - assign readdata = {32'b0 | read_mux_out}; - assign out_port = data_out; - -endmodule - diff --git a/nios_system/synthesis/submodules/nios_system_LEDs.v b/nios_system/synthesis/submodules/nios_system_LEDs.v deleted file mode 100644 index 4e22fe4..0000000 --- a/nios_system/synthesis/submodules/nios_system_LEDs.v +++ /dev/null @@ -1,66 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_LEDs ( - // inputs: - address, - chipselect, - clk, - reset_n, - write_n, - writedata, - - // outputs: - out_port, - readdata - ) -; - - output [ 7: 0] out_port; - output [ 31: 0] readdata; - input [ 1: 0] address; - input chipselect; - input clk; - input reset_n; - input write_n; - input [ 31: 0] writedata; - - wire clk_en; - reg [ 7: 0] data_out; - wire [ 7: 0] out_port; - wire [ 7: 0] read_mux_out; - wire [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {8 {(address == 0)}} & data_out; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - data_out <= 0; - else if (chipselect && ~write_n && (address == 0)) - data_out <= writedata[7 : 0]; - end - - - assign readdata = {32'b0 | read_mux_out}; - assign out_port = data_out; - -endmodule - diff --git a/nios_system/synthesis/submodules/nios_system_addr_router.sv b/nios_system/synthesis/submodules/nios_system_addr_router.sv deleted file mode 100644 index 3c8760e..0000000 --- a/nios_system/synthesis/submodules/nios_system_addr_router.sv +++ /dev/null @@ -1,224 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------------------- -// Merlin Router -// -// Asserts the appropriate one-hot encoded channel based on -// either (a) the address or (b) the dest id. The DECODER_TYPE -// parameter controls this behaviour. 0 means address decoder, -// 1 means dest id decoder. -// -// In the case of (a), it also sets the destination id. -// ------------------------------------------------------- - -`timescale 1 ns / 1 ns - -module nios_system_addr_router_default_decode - #( - parameter DEFAULT_CHANNEL = 1, - DEFAULT_WR_CHANNEL = -1, - DEFAULT_RD_CHANNEL = -1, - DEFAULT_DESTID = 15 - ) - (output [85 - 81 : 0] default_destination_id, - output [18-1 : 0] default_wr_channel, - output [18-1 : 0] default_rd_channel, - output [18-1 : 0] default_src_channel - ); - - assign default_destination_id = - DEFAULT_DESTID[85 - 81 : 0]; - - generate begin : default_decode - if (DEFAULT_CHANNEL == -1) begin - assign default_src_channel = '0; - end - else begin - assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; - end - end - endgenerate - - generate begin : default_decode_rw - if (DEFAULT_RD_CHANNEL == -1) begin - assign default_wr_channel = '0; - assign default_rd_channel = '0; - end - else begin - assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; - assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; - end - end - endgenerate - -endmodule - - -module nios_system_addr_router -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // Command Sink (Input) - // ------------------- - input sink_valid, - input [96-1 : 0] sink_data, - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Command Source (Output) - // ------------------- - output src_valid, - output reg [96-1 : 0] src_data, - output reg [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready -); - - // ------------------------------------------------------- - // Local parameters and variables - // ------------------------------------------------------- - localparam PKT_ADDR_H = 54; - localparam PKT_ADDR_L = 36; - localparam PKT_DEST_ID_H = 85; - localparam PKT_DEST_ID_L = 81; - localparam PKT_PROTECTION_H = 89; - localparam PKT_PROTECTION_L = 87; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam DECODER_TYPE = 0; - - localparam PKT_TRANS_WRITE = 57; - localparam PKT_TRANS_READ = 58; - - localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; - localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; - - - - // ------------------------------------------------------- - // Figure out the number of bits to mask off for each slave span - // during address decoding - // ------------------------------------------------------- - localparam PAD0 = log2ceil(64'h40000 - 64'h0); - localparam PAD1 = log2ceil(64'h41000 - 64'h40800); - // ------------------------------------------------------- - // Work out which address bits are significant based on the - // address range of the slaves. If the required width is too - // large or too small, we use the address field width instead. - // ------------------------------------------------------- - localparam ADDR_RANGE = 64'h41000; - localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); - localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || - (RANGE_ADDR_WIDTH == 0) ? - PKT_ADDR_H : - PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; - - localparam RG = RANGE_ADDR_WIDTH-1; - - wire [PKT_ADDR_W-1 : 0] address = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L]; - - // ------------------------------------------------------- - // Pass almost everything through, untouched - // ------------------------------------------------------- - assign sink_ready = src_ready; - assign src_valid = sink_valid; - assign src_startofpacket = sink_startofpacket; - assign src_endofpacket = sink_endofpacket; - - wire [PKT_DEST_ID_W-1:0] default_destid; - wire [18-1 : 0] default_src_channel; - - - - - - nios_system_addr_router_default_decode the_default_decode( - .default_destination_id (default_destid), - .default_wr_channel (), - .default_rd_channel (), - .default_src_channel (default_src_channel) - ); - - always @* begin - src_data = sink_data; - src_channel = default_src_channel; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid; - - // -------------------------------------------------- - // Address Decoder - // Sets the channel and destination ID based on the address - // -------------------------------------------------- - - // ( 0x0 .. 0x40000 ) - if ( {address[RG:PAD0],{PAD0{1'b0}}} == 19'h0 ) begin - src_channel = 18'b10; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 15; - end - - // ( 0x40800 .. 0x41000 ) - if ( {address[RG:PAD1],{PAD1{1'b0}}} == 19'h40800 ) begin - src_channel = 18'b01; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 14; - end - -end - - - // -------------------------------------------------- - // Ceil(log2()) function - // -------------------------------------------------- - function integer log2ceil; - input reg[65:0] val; - reg [65:0] i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - -endmodule - - diff --git a/nios_system/synthesis/submodules/nios_system_addr_router_001.sv b/nios_system/synthesis/submodules/nios_system_addr_router_001.sv deleted file mode 100644 index 7b8c2d0..0000000 --- a/nios_system/synthesis/submodules/nios_system_addr_router_001.sv +++ /dev/null @@ -1,336 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------------------- -// Merlin Router -// -// Asserts the appropriate one-hot encoded channel based on -// either (a) the address or (b) the dest id. The DECODER_TYPE -// parameter controls this behaviour. 0 means address decoder, -// 1 means dest id decoder. -// -// In the case of (a), it also sets the destination id. -// ------------------------------------------------------- - -`timescale 1 ns / 1 ns - -module nios_system_addr_router_001_default_decode - #( - parameter DEFAULT_CHANNEL = 1, - DEFAULT_WR_CHANNEL = -1, - DEFAULT_RD_CHANNEL = -1, - DEFAULT_DESTID = 15 - ) - (output [85 - 81 : 0] default_destination_id, - output [18-1 : 0] default_wr_channel, - output [18-1 : 0] default_rd_channel, - output [18-1 : 0] default_src_channel - ); - - assign default_destination_id = - DEFAULT_DESTID[85 - 81 : 0]; - - generate begin : default_decode - if (DEFAULT_CHANNEL == -1) begin - assign default_src_channel = '0; - end - else begin - assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; - end - end - endgenerate - - generate begin : default_decode_rw - if (DEFAULT_RD_CHANNEL == -1) begin - assign default_wr_channel = '0; - assign default_rd_channel = '0; - end - else begin - assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; - assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; - end - end - endgenerate - -endmodule - - -module nios_system_addr_router_001 -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // Command Sink (Input) - // ------------------- - input sink_valid, - input [96-1 : 0] sink_data, - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Command Source (Output) - // ------------------- - output src_valid, - output reg [96-1 : 0] src_data, - output reg [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready -); - - // ------------------------------------------------------- - // Local parameters and variables - // ------------------------------------------------------- - localparam PKT_ADDR_H = 54; - localparam PKT_ADDR_L = 36; - localparam PKT_DEST_ID_H = 85; - localparam PKT_DEST_ID_L = 81; - localparam PKT_PROTECTION_H = 89; - localparam PKT_PROTECTION_L = 87; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam DECODER_TYPE = 0; - - localparam PKT_TRANS_WRITE = 57; - localparam PKT_TRANS_READ = 58; - - localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; - localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; - - - - // ------------------------------------------------------- - // Figure out the number of bits to mask off for each slave span - // during address decoding - // ------------------------------------------------------- - localparam PAD0 = log2ceil(64'h40000 - 64'h0); - localparam PAD1 = log2ceil(64'h41000 - 64'h40800); - localparam PAD2 = log2ceil(64'h41020 - 64'h41010); - localparam PAD3 = log2ceil(64'h41030 - 64'h41020); - localparam PAD4 = log2ceil(64'h41040 - 64'h41030); - localparam PAD5 = log2ceil(64'h41050 - 64'h41040); - localparam PAD6 = log2ceil(64'h41060 - 64'h41050); - localparam PAD7 = log2ceil(64'h41070 - 64'h41060); - localparam PAD8 = log2ceil(64'h41080 - 64'h41070); - localparam PAD9 = log2ceil(64'h41090 - 64'h41080); - localparam PAD10 = log2ceil(64'h410a0 - 64'h41090); - localparam PAD11 = log2ceil(64'h410b0 - 64'h410a0); - localparam PAD12 = log2ceil(64'h410c0 - 64'h410b0); - localparam PAD13 = log2ceil(64'h410d0 - 64'h410c0); - localparam PAD14 = log2ceil(64'h410e0 - 64'h410d0); - localparam PAD15 = log2ceil(64'h410f0 - 64'h410e0); - localparam PAD16 = log2ceil(64'h41100 - 64'h410f0); - localparam PAD17 = log2ceil(64'h41108 - 64'h41100); - // ------------------------------------------------------- - // Work out which address bits are significant based on the - // address range of the slaves. If the required width is too - // large or too small, we use the address field width instead. - // ------------------------------------------------------- - localparam ADDR_RANGE = 64'h41108; - localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); - localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || - (RANGE_ADDR_WIDTH == 0) ? - PKT_ADDR_H : - PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; - - localparam RG = RANGE_ADDR_WIDTH-1; - - wire [PKT_ADDR_W-1 : 0] address = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L]; - - // ------------------------------------------------------- - // Pass almost everything through, untouched - // ------------------------------------------------------- - assign sink_ready = src_ready; - assign src_valid = sink_valid; - assign src_startofpacket = sink_startofpacket; - assign src_endofpacket = sink_endofpacket; - - wire [PKT_DEST_ID_W-1:0] default_destid; - wire [18-1 : 0] default_src_channel; - - - - - - nios_system_addr_router_001_default_decode the_default_decode( - .default_destination_id (default_destid), - .default_wr_channel (), - .default_rd_channel (), - .default_src_channel (default_src_channel) - ); - - always @* begin - src_data = sink_data; - src_channel = default_src_channel; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid; - - // -------------------------------------------------- - // Address Decoder - // Sets the channel and destination ID based on the address - // -------------------------------------------------- - - // ( 0x0 .. 0x40000 ) - if ( {address[RG:PAD0],{PAD0{1'b0}}} == 19'h0 ) begin - src_channel = 18'b000000000000000010; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 15; - end - - // ( 0x40800 .. 0x41000 ) - if ( {address[RG:PAD1],{PAD1{1'b0}}} == 19'h40800 ) begin - src_channel = 18'b000000000000000001; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 14; - end - - // ( 0x41010 .. 0x41020 ) - if ( {address[RG:PAD2],{PAD2{1'b0}}} == 19'h41010 ) begin - src_channel = 18'b010000000000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 13; - end - - // ( 0x41020 .. 0x41030 ) - if ( {address[RG:PAD3],{PAD3{1'b0}}} == 19'h41020 ) begin - src_channel = 18'b100000000000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 12; - end - - // ( 0x41030 .. 0x41040 ) - if ( {address[RG:PAD4],{PAD4{1'b0}}} == 19'h41030 ) begin - src_channel = 18'b001000000000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 11; - end - - // ( 0x41040 .. 0x41050 ) - if ( {address[RG:PAD5],{PAD5{1'b0}}} == 19'h41040 ) begin - src_channel = 18'b000100000000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 9; - end - - // ( 0x41050 .. 0x41060 ) - if ( {address[RG:PAD6],{PAD6{1'b0}}} == 19'h41050 ) begin - src_channel = 18'b000010000000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8; - end - - // ( 0x41060 .. 0x41070 ) - if ( {address[RG:PAD7],{PAD7{1'b0}}} == 19'h41060 ) begin - src_channel = 18'b000001000000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7; - end - - // ( 0x41070 .. 0x41080 ) - if ( {address[RG:PAD8],{PAD8{1'b0}}} == 19'h41070 ) begin - src_channel = 18'b000000100000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6; - end - - // ( 0x41080 .. 0x41090 ) - if ( {address[RG:PAD9],{PAD9{1'b0}}} == 19'h41080 ) begin - src_channel = 18'b000000010000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5; - end - - // ( 0x41090 .. 0x410a0 ) - if ( {address[RG:PAD10],{PAD10{1'b0}}} == 19'h41090 ) begin - src_channel = 18'b000000001000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4; - end - - // ( 0x410a0 .. 0x410b0 ) - if ( {address[RG:PAD11],{PAD11{1'b0}}} == 19'h410a0 ) begin - src_channel = 18'b000000000100000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3; - end - - // ( 0x410b0 .. 0x410c0 ) - if ( {address[RG:PAD12],{PAD12{1'b0}}} == 19'h410b0 ) begin - src_channel = 18'b000000000010000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2; - end - - // ( 0x410c0 .. 0x410d0 ) - if ( {address[RG:PAD13],{PAD13{1'b0}}} == 19'h410c0 ) begin - src_channel = 18'b000000000001000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 16; - end - - // ( 0x410d0 .. 0x410e0 ) - if ( {address[RG:PAD14],{PAD14{1'b0}}} == 19'h410d0 ) begin - src_channel = 18'b000000000000100000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 17; - end - - // ( 0x410e0 .. 0x410f0 ) - if ( {address[RG:PAD15],{PAD15{1'b0}}} == 19'h410e0 ) begin - src_channel = 18'b000000000000010000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0; - end - - // ( 0x410f0 .. 0x41100 ) - if ( {address[RG:PAD16],{PAD16{1'b0}}} == 19'h410f0 ) begin - src_channel = 18'b000000000000000100; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1; - end - - // ( 0x41100 .. 0x41108 ) - if ( {address[RG:PAD17],{PAD17{1'b0}}} == 19'h41100 ) begin - src_channel = 18'b000000000000001000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 10; - end - -end - - - // -------------------------------------------------- - // Ceil(log2()) function - // -------------------------------------------------- - function integer log2ceil; - input reg[65:0] val; - reg [65:0] i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - -endmodule - - diff --git a/nios_system/synthesis/submodules/nios_system_cmd_xbar_demux.sv b/nios_system/synthesis/submodules/nios_system_cmd_xbar_demux.sv deleted file mode 100644 index 0aef300..0000000 --- a/nios_system/synthesis/submodules/nios_system_cmd_xbar_demux.sv +++ /dev/null @@ -1,116 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------- -// Merlin Demultiplexer -// -// Asserts valid on the appropriate output -// given a one-hot channel signal. -// ------------------------------------- - -`timescale 1 ns / 1 ns - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_cmd_xbar_demux -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// NUM_OUTPUTS: 2 -// VALID_WIDTH: 1 -// ------------------------------------------ - -//------------------------------------------ -// Message Supression Used -// QIS Warnings -// 15610 - Warning: Design contains x input pin(s) that do not drive logic -//------------------------------------------ - -module nios_system_cmd_xbar_demux -( - // ------------------- - // Sink - // ------------------- - input [1-1 : 0] sink_valid, - input [96-1 : 0] sink_data, // ST_DATA_W=96 - input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Sources - // ------------------- - output reg src0_valid, - output reg [96-1 : 0] src0_data, // ST_DATA_W=96 - output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 - output reg src0_startofpacket, - output reg src0_endofpacket, - input src0_ready, - - output reg src1_valid, - output reg [96-1 : 0] src1_data, // ST_DATA_W=96 - output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18 - output reg src1_startofpacket, - output reg src1_endofpacket, - input src1_ready, - - - // ------------------- - // Clock & Reset - // ------------------- - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk - input clk, - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset - input reset - -); - - localparam NUM_OUTPUTS = 2; - wire [NUM_OUTPUTS - 1 : 0] ready_vector; - - // ------------------- - // Demux - // ------------------- - always @* begin - src0_data = sink_data; - src0_startofpacket = sink_startofpacket; - src0_endofpacket = sink_endofpacket; - src0_channel = sink_channel >> NUM_OUTPUTS; - - src0_valid = sink_channel[0] && sink_valid; - - src1_data = sink_data; - src1_startofpacket = sink_startofpacket; - src1_endofpacket = sink_endofpacket; - src1_channel = sink_channel >> NUM_OUTPUTS; - - src1_valid = sink_channel[1] && sink_valid; - - end - - // ------------------- - // Backpressure - // ------------------- - assign ready_vector[0] = src0_ready; - assign ready_vector[1] = src1_ready; - - assign sink_ready = |(sink_channel & {{16{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); - -endmodule - - diff --git a/nios_system/synthesis/submodules/nios_system_cmd_xbar_demux_001.sv b/nios_system/synthesis/submodules/nios_system_cmd_xbar_demux_001.sv deleted file mode 100644 index 433e8d0..0000000 --- a/nios_system/synthesis/submodules/nios_system_cmd_xbar_demux_001.sv +++ /dev/null @@ -1,356 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------- -// Merlin Demultiplexer -// -// Asserts valid on the appropriate output -// given a one-hot channel signal. -// ------------------------------------- - -`timescale 1 ns / 1 ns - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_cmd_xbar_demux_001 -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// NUM_OUTPUTS: 18 -// VALID_WIDTH: 1 -// ------------------------------------------ - -//------------------------------------------ -// Message Supression Used -// QIS Warnings -// 15610 - Warning: Design contains x input pin(s) that do not drive logic -//------------------------------------------ - -module nios_system_cmd_xbar_demux_001 -( - // ------------------- - // Sink - // ------------------- - input [1-1 : 0] sink_valid, - input [96-1 : 0] sink_data, // ST_DATA_W=96 - input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Sources - // ------------------- - output reg src0_valid, - output reg [96-1 : 0] src0_data, // ST_DATA_W=96 - output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 - output reg src0_startofpacket, - output reg src0_endofpacket, - input src0_ready, - - output reg src1_valid, - output reg [96-1 : 0] src1_data, // ST_DATA_W=96 - output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18 - output reg src1_startofpacket, - output reg src1_endofpacket, - input src1_ready, - - output reg src2_valid, - output reg [96-1 : 0] src2_data, // ST_DATA_W=96 - output reg [18-1 : 0] src2_channel, // ST_CHANNEL_W=18 - output reg src2_startofpacket, - output reg src2_endofpacket, - input src2_ready, - - output reg src3_valid, - output reg [96-1 : 0] src3_data, // ST_DATA_W=96 - output reg [18-1 : 0] src3_channel, // ST_CHANNEL_W=18 - output reg src3_startofpacket, - output reg src3_endofpacket, - input src3_ready, - - output reg src4_valid, - output reg [96-1 : 0] src4_data, // ST_DATA_W=96 - output reg [18-1 : 0] src4_channel, // ST_CHANNEL_W=18 - output reg src4_startofpacket, - output reg src4_endofpacket, - input src4_ready, - - output reg src5_valid, - output reg [96-1 : 0] src5_data, // ST_DATA_W=96 - output reg [18-1 : 0] src5_channel, // ST_CHANNEL_W=18 - output reg src5_startofpacket, - output reg src5_endofpacket, - input src5_ready, - - output reg src6_valid, - output reg [96-1 : 0] src6_data, // ST_DATA_W=96 - output reg [18-1 : 0] src6_channel, // ST_CHANNEL_W=18 - output reg src6_startofpacket, - output reg src6_endofpacket, - input src6_ready, - - output reg src7_valid, - output reg [96-1 : 0] src7_data, // ST_DATA_W=96 - output reg [18-1 : 0] src7_channel, // ST_CHANNEL_W=18 - output reg src7_startofpacket, - output reg src7_endofpacket, - input src7_ready, - - output reg src8_valid, - output reg [96-1 : 0] src8_data, // ST_DATA_W=96 - output reg [18-1 : 0] src8_channel, // ST_CHANNEL_W=18 - output reg src8_startofpacket, - output reg src8_endofpacket, - input src8_ready, - - output reg src9_valid, - output reg [96-1 : 0] src9_data, // ST_DATA_W=96 - output reg [18-1 : 0] src9_channel, // ST_CHANNEL_W=18 - output reg src9_startofpacket, - output reg src9_endofpacket, - input src9_ready, - - output reg src10_valid, - output reg [96-1 : 0] src10_data, // ST_DATA_W=96 - output reg [18-1 : 0] src10_channel, // ST_CHANNEL_W=18 - output reg src10_startofpacket, - output reg src10_endofpacket, - input src10_ready, - - output reg src11_valid, - output reg [96-1 : 0] src11_data, // ST_DATA_W=96 - output reg [18-1 : 0] src11_channel, // ST_CHANNEL_W=18 - output reg src11_startofpacket, - output reg src11_endofpacket, - input src11_ready, - - output reg src12_valid, - output reg [96-1 : 0] src12_data, // ST_DATA_W=96 - output reg [18-1 : 0] src12_channel, // ST_CHANNEL_W=18 - output reg src12_startofpacket, - output reg src12_endofpacket, - input src12_ready, - - output reg src13_valid, - output reg [96-1 : 0] src13_data, // ST_DATA_W=96 - output reg [18-1 : 0] src13_channel, // ST_CHANNEL_W=18 - output reg src13_startofpacket, - output reg src13_endofpacket, - input src13_ready, - - output reg src14_valid, - output reg [96-1 : 0] src14_data, // ST_DATA_W=96 - output reg [18-1 : 0] src14_channel, // ST_CHANNEL_W=18 - output reg src14_startofpacket, - output reg src14_endofpacket, - input src14_ready, - - output reg src15_valid, - output reg [96-1 : 0] src15_data, // ST_DATA_W=96 - output reg [18-1 : 0] src15_channel, // ST_CHANNEL_W=18 - output reg src15_startofpacket, - output reg src15_endofpacket, - input src15_ready, - - output reg src16_valid, - output reg [96-1 : 0] src16_data, // ST_DATA_W=96 - output reg [18-1 : 0] src16_channel, // ST_CHANNEL_W=18 - output reg src16_startofpacket, - output reg src16_endofpacket, - input src16_ready, - - output reg src17_valid, - output reg [96-1 : 0] src17_data, // ST_DATA_W=96 - output reg [18-1 : 0] src17_channel, // ST_CHANNEL_W=18 - output reg src17_startofpacket, - output reg src17_endofpacket, - input src17_ready, - - - // ------------------- - // Clock & Reset - // ------------------- - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk - input clk, - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset - input reset - -); - - localparam NUM_OUTPUTS = 18; - wire [NUM_OUTPUTS - 1 : 0] ready_vector; - - // ------------------- - // Demux - // ------------------- - always @* begin - src0_data = sink_data; - src0_startofpacket = sink_startofpacket; - src0_endofpacket = sink_endofpacket; - src0_channel = sink_channel >> NUM_OUTPUTS; - - src0_valid = sink_channel[0] && sink_valid; - - src1_data = sink_data; - src1_startofpacket = sink_startofpacket; - src1_endofpacket = sink_endofpacket; - src1_channel = sink_channel >> NUM_OUTPUTS; - - src1_valid = sink_channel[1] && sink_valid; - - src2_data = sink_data; - src2_startofpacket = sink_startofpacket; - src2_endofpacket = sink_endofpacket; - src2_channel = sink_channel >> NUM_OUTPUTS; - - src2_valid = sink_channel[2] && sink_valid; - - src3_data = sink_data; - src3_startofpacket = sink_startofpacket; - src3_endofpacket = sink_endofpacket; - src3_channel = sink_channel >> NUM_OUTPUTS; - - src3_valid = sink_channel[3] && sink_valid; - - src4_data = sink_data; - src4_startofpacket = sink_startofpacket; - src4_endofpacket = sink_endofpacket; - src4_channel = sink_channel >> NUM_OUTPUTS; - - src4_valid = sink_channel[4] && sink_valid; - - src5_data = sink_data; - src5_startofpacket = sink_startofpacket; - src5_endofpacket = sink_endofpacket; - src5_channel = sink_channel >> NUM_OUTPUTS; - - src5_valid = sink_channel[5] && sink_valid; - - src6_data = sink_data; - src6_startofpacket = sink_startofpacket; - src6_endofpacket = sink_endofpacket; - src6_channel = sink_channel >> NUM_OUTPUTS; - - src6_valid = sink_channel[6] && sink_valid; - - src7_data = sink_data; - src7_startofpacket = sink_startofpacket; - src7_endofpacket = sink_endofpacket; - src7_channel = sink_channel >> NUM_OUTPUTS; - - src7_valid = sink_channel[7] && sink_valid; - - src8_data = sink_data; - src8_startofpacket = sink_startofpacket; - src8_endofpacket = sink_endofpacket; - src8_channel = sink_channel >> NUM_OUTPUTS; - - src8_valid = sink_channel[8] && sink_valid; - - src9_data = sink_data; - src9_startofpacket = sink_startofpacket; - src9_endofpacket = sink_endofpacket; - src9_channel = sink_channel >> NUM_OUTPUTS; - - src9_valid = sink_channel[9] && sink_valid; - - src10_data = sink_data; - src10_startofpacket = sink_startofpacket; - src10_endofpacket = sink_endofpacket; - src10_channel = sink_channel >> NUM_OUTPUTS; - - src10_valid = sink_channel[10] && sink_valid; - - src11_data = sink_data; - src11_startofpacket = sink_startofpacket; - src11_endofpacket = sink_endofpacket; - src11_channel = sink_channel >> NUM_OUTPUTS; - - src11_valid = sink_channel[11] && sink_valid; - - src12_data = sink_data; - src12_startofpacket = sink_startofpacket; - src12_endofpacket = sink_endofpacket; - src12_channel = sink_channel >> NUM_OUTPUTS; - - src12_valid = sink_channel[12] && sink_valid; - - src13_data = sink_data; - src13_startofpacket = sink_startofpacket; - src13_endofpacket = sink_endofpacket; - src13_channel = sink_channel >> NUM_OUTPUTS; - - src13_valid = sink_channel[13] && sink_valid; - - src14_data = sink_data; - src14_startofpacket = sink_startofpacket; - src14_endofpacket = sink_endofpacket; - src14_channel = sink_channel >> NUM_OUTPUTS; - - src14_valid = sink_channel[14] && sink_valid; - - src15_data = sink_data; - src15_startofpacket = sink_startofpacket; - src15_endofpacket = sink_endofpacket; - src15_channel = sink_channel >> NUM_OUTPUTS; - - src15_valid = sink_channel[15] && sink_valid; - - src16_data = sink_data; - src16_startofpacket = sink_startofpacket; - src16_endofpacket = sink_endofpacket; - src16_channel = sink_channel >> NUM_OUTPUTS; - - src16_valid = sink_channel[16] && sink_valid; - - src17_data = sink_data; - src17_startofpacket = sink_startofpacket; - src17_endofpacket = sink_endofpacket; - src17_channel = sink_channel >> NUM_OUTPUTS; - - src17_valid = sink_channel[17] && sink_valid; - - end - - // ------------------- - // Backpressure - // ------------------- - assign ready_vector[0] = src0_ready; - assign ready_vector[1] = src1_ready; - assign ready_vector[2] = src2_ready; - assign ready_vector[3] = src3_ready; - assign ready_vector[4] = src4_ready; - assign ready_vector[5] = src5_ready; - assign ready_vector[6] = src6_ready; - assign ready_vector[7] = src7_ready; - assign ready_vector[8] = src8_ready; - assign ready_vector[9] = src9_ready; - assign ready_vector[10] = src10_ready; - assign ready_vector[11] = src11_ready; - assign ready_vector[12] = src12_ready; - assign ready_vector[13] = src13_ready; - assign ready_vector[14] = src14_ready; - assign ready_vector[15] = src15_ready; - assign ready_vector[16] = src16_ready; - assign ready_vector[17] = src17_ready; - - assign sink_ready = |(sink_channel & ready_vector); - -endmodule - - diff --git a/nios_system/synthesis/submodules/nios_system_cmd_xbar_mux.sv b/nios_system/synthesis/submodules/nios_system_cmd_xbar_mux.sv deleted file mode 100644 index 76ec5b4..0000000 --- a/nios_system/synthesis/submodules/nios_system_cmd_xbar_mux.sv +++ /dev/null @@ -1,308 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------ -// Merlin Multiplexer -// ------------------------------------------ - -`timescale 1 ns / 1 ns - - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_cmd_xbar_mux -// NUM_INPUTS: 2 -// ARBITRATION_SHARES: 1 1 -// ARBITRATION_SCHEME "round-robin" -// PIPELINE_ARB: 1 -// PKT_TRANS_LOCK: 59 (arbitration locking enabled) -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// ------------------------------------------ - -module nios_system_cmd_xbar_mux -( - // ---------------------- - // Sinks - // ---------------------- - input sink0_valid, - input [96-1 : 0] sink0_data, - input [18-1: 0] sink0_channel, - input sink0_startofpacket, - input sink0_endofpacket, - output sink0_ready, - - input sink1_valid, - input [96-1 : 0] sink1_data, - input [18-1: 0] sink1_channel, - input sink1_startofpacket, - input sink1_endofpacket, - output sink1_ready, - - - // ---------------------- - // Source - // ---------------------- - output src_valid, - output [96-1 : 0] src_data, - output [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready, - - // ---------------------- - // Clock & Reset - // ---------------------- - input clk, - input reset -); - localparam PAYLOAD_W = 96 + 18 + 2; - localparam NUM_INPUTS = 2; - localparam SHARE_COUNTER_W = 1; - localparam PIPELINE_ARB = 1; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam PKT_TRANS_LOCK = 59; - - // ------------------------------------------ - // Signals - // ------------------------------------------ - wire [NUM_INPUTS - 1 : 0] request; - wire [NUM_INPUTS - 1 : 0] valid; - wire [NUM_INPUTS - 1 : 0] grant; - wire [NUM_INPUTS - 1 : 0] next_grant; - reg [NUM_INPUTS - 1 : 0] saved_grant; - reg [PAYLOAD_W - 1 : 0] src_payload; - wire last_cycle; - reg packet_in_progress; - reg update_grant; - - wire [PAYLOAD_W - 1 : 0] sink0_payload; - wire [PAYLOAD_W - 1 : 0] sink1_payload; - - assign valid[0] = sink0_valid; - assign valid[1] = sink1_valid; - - wire [NUM_INPUTS - 1 : 0] eop; - assign eop[0] = sink0_endofpacket; - assign eop[1] = sink1_endofpacket; - - // ------------------------------------------ - // ------------------------------------------ - // Grant Logic & Updates - // ------------------------------------------ - // ------------------------------------------ - reg [NUM_INPUTS - 1 : 0] lock; - always @* begin - lock[0] = sink0_data[59]; - lock[1] = sink1_data[59]; - end - reg [NUM_INPUTS - 1 : 0] locked = '0; - always @(posedge clk or posedge reset) begin - if (reset) begin - locked <= '0; - end - else begin - locked <= next_grant & lock; - end - end - - assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); - - // ------------------------------------------ - // We're working on a packet at any time valid is high, except - // when this is the endofpacket. - // ------------------------------------------ - always @(posedge clk or posedge reset) begin - if (reset) begin - packet_in_progress <= 1'b0; - end - else begin - if (src_valid) - packet_in_progress <= 1'b1; - if (last_cycle) - packet_in_progress <= 1'b0; - end - end - - - // ------------------------------------------ - // Shares - // - // Special case: all-equal shares _should_ be optimized into assigning a - // constant to next_grant_share. - // Special case: all-1's shares _should_ result in the share counter - // being optimized away. - // ------------------------------------------ - // Input | arb shares | counter load value - // 0 | 1 | 0 - // 1 | 1 | 0 - wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; - - // ------------------------------------------ - // Choose the share value corresponding to the grant. - // ------------------------------------------ - reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; - always @* begin - next_grant_share = - share_0 & { SHARE_COUNTER_W {next_grant[0]} } | - share_1 & { SHARE_COUNTER_W {next_grant[1]} }; - end - - // ------------------------------------------ - // Flag to indicate first packet of an arb sequence. - // ------------------------------------------ - - // ------------------------------------------ - // Compute the next share-count value. - // ------------------------------------------ - reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; - reg [SHARE_COUNTER_W - 1 : 0] share_count; - reg share_count_zero_flag; - - always @* begin - // Update the counter, but don't decrement below 0. - p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; - end - - // ------------------------------------------ - // Update the share counter and share-counter=zero flag. - // ------------------------------------------ - always @(posedge clk or posedge reset) begin - if (reset) begin - share_count <= '0; - share_count_zero_flag <= 1'b1; - end - else begin - if (update_grant) begin - share_count <= next_grant_share; - share_count_zero_flag <= (next_grant_share == '0); - end - else if (last_cycle) begin - share_count <= p1_share_count; - share_count_zero_flag <= (p1_share_count == '0); - end - end - end - - - always @* begin - update_grant = 0; - - // ------------------------------------------ - // The pipeline delays grant by one cycle, so - // we have to calculate the update_grant signal - // one cycle ahead of time. - // - // Possible optimization: omit the first clause - // "if (!packet_in_progress & ~src_valid) ..." - // cost: one idle cycle at the the beginning of each - // grant cycle. - // benefit: save a small amount of logic. - // ------------------------------------------ - if (!packet_in_progress & !src_valid) - update_grant = 1; - if (last_cycle && share_count_zero_flag) - update_grant = 1; - end - - wire save_grant; - assign save_grant = update_grant; - assign grant = saved_grant; - - always @(posedge clk, posedge reset) begin - if (reset) - saved_grant <= '0; - else if (save_grant) - saved_grant <= next_grant; - end - - // ------------------------------------------ - // ------------------------------------------ - // Arbitrator - // ------------------------------------------ - // ------------------------------------------ - - // ------------------------------------------ - // Create a request vector that stays high during - // the packet for unpipelined arbitration. - // - // The pipelined arbitration scheme does not require - // request to be held high during the packet. - // ------------------------------------------ - reg [NUM_INPUTS - 1 : 0] prev_request; - always @(posedge clk, posedge reset) begin - if (reset) - prev_request <= '0; - else - prev_request <= request & ~(valid & eop); - end - - assign request = (PIPELINE_ARB == 1) ? valid | locked : - prev_request | valid | locked; - - - altera_merlin_arbitrator - #( - .NUM_REQUESTERS(NUM_INPUTS), - .SCHEME ("round-robin"), - .PIPELINE (1) - ) arb ( - .clk (clk), - .reset (reset), - .request (request), - .grant (next_grant), - .save_top_priority (src_valid), - .increment_top_priority (update_grant) - ); - - // ------------------------------------------ - // ------------------------------------------ - // Mux - // - // Implemented as a sum of products. - // ------------------------------------------ - // ------------------------------------------ - - assign sink0_ready = src_ready && grant[0]; - assign sink1_ready = src_ready && grant[1]; - - assign src_valid = |(grant & valid); - - always @* begin - src_payload = - sink0_payload & {PAYLOAD_W {grant[0]} } | - sink1_payload & {PAYLOAD_W {grant[1]} }; - end - - // ------------------------------------------ - // Mux Payload Mapping - // ------------------------------------------ - - assign sink0_payload = {sink0_channel,sink0_data, - sink0_startofpacket,sink0_endofpacket}; - assign sink1_payload = {sink1_channel,sink1_data, - sink1_startofpacket,sink1_endofpacket}; - - assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; - -endmodule - - - diff --git a/nios_system/synthesis/submodules/nios_system_hex0.v b/nios_system/synthesis/submodules/nios_system_hex0.v deleted file mode 100644 index 365eed9..0000000 --- a/nios_system/synthesis/submodules/nios_system_hex0.v +++ /dev/null @@ -1,66 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_hex0 ( - // inputs: - address, - chipselect, - clk, - reset_n, - write_n, - writedata, - - // outputs: - out_port, - readdata - ) -; - - output [ 6: 0] out_port; - output [ 31: 0] readdata; - input [ 1: 0] address; - input chipselect; - input clk; - input reset_n; - input write_n; - input [ 31: 0] writedata; - - wire clk_en; - reg [ 6: 0] data_out; - wire [ 6: 0] out_port; - wire [ 6: 0] read_mux_out; - wire [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {7 {(address == 0)}} & data_out; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - data_out <= 0; - else if (chipselect && ~write_n && (address == 0)) - data_out <= writedata[6 : 0]; - end - - - assign readdata = {32'b0 | read_mux_out}; - assign out_port = data_out; - -endmodule - diff --git a/nios_system/synthesis/submodules/nios_system_id_router.sv b/nios_system/synthesis/submodules/nios_system_id_router.sv deleted file mode 100644 index 90937e8..0000000 --- a/nios_system/synthesis/submodules/nios_system_id_router.sv +++ /dev/null @@ -1,221 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------------------- -// Merlin Router -// -// Asserts the appropriate one-hot encoded channel based on -// either (a) the address or (b) the dest id. The DECODER_TYPE -// parameter controls this behaviour. 0 means address decoder, -// 1 means dest id decoder. -// -// In the case of (a), it also sets the destination id. -// ------------------------------------------------------- - -`timescale 1 ns / 1 ns - -module nios_system_id_router_default_decode - #( - parameter DEFAULT_CHANNEL = 0, - DEFAULT_WR_CHANNEL = -1, - DEFAULT_RD_CHANNEL = -1, - DEFAULT_DESTID = 1 - ) - (output [85 - 81 : 0] default_destination_id, - output [18-1 : 0] default_wr_channel, - output [18-1 : 0] default_rd_channel, - output [18-1 : 0] default_src_channel - ); - - assign default_destination_id = - DEFAULT_DESTID[85 - 81 : 0]; - - generate begin : default_decode - if (DEFAULT_CHANNEL == -1) begin - assign default_src_channel = '0; - end - else begin - assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; - end - end - endgenerate - - generate begin : default_decode_rw - if (DEFAULT_RD_CHANNEL == -1) begin - assign default_wr_channel = '0; - assign default_rd_channel = '0; - end - else begin - assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; - assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; - end - end - endgenerate - -endmodule - - -module nios_system_id_router -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // Command Sink (Input) - // ------------------- - input sink_valid, - input [96-1 : 0] sink_data, - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Command Source (Output) - // ------------------- - output src_valid, - output reg [96-1 : 0] src_data, - output reg [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready -); - - // ------------------------------------------------------- - // Local parameters and variables - // ------------------------------------------------------- - localparam PKT_ADDR_H = 54; - localparam PKT_ADDR_L = 36; - localparam PKT_DEST_ID_H = 85; - localparam PKT_DEST_ID_L = 81; - localparam PKT_PROTECTION_H = 89; - localparam PKT_PROTECTION_L = 87; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam DECODER_TYPE = 1; - - localparam PKT_TRANS_WRITE = 57; - localparam PKT_TRANS_READ = 58; - - localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; - localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; - - - - // ------------------------------------------------------- - // Figure out the number of bits to mask off for each slave span - // during address decoding - // ------------------------------------------------------- - // ------------------------------------------------------- - // Work out which address bits are significant based on the - // address range of the slaves. If the required width is too - // large or too small, we use the address field width instead. - // ------------------------------------------------------- - localparam ADDR_RANGE = 64'h0; - localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); - localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || - (RANGE_ADDR_WIDTH == 0) ? - PKT_ADDR_H : - PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; - - localparam RG = RANGE_ADDR_WIDTH; - - reg [PKT_DEST_ID_W-1 : 0] destid; - - // ------------------------------------------------------- - // Pass almost everything through, untouched - // ------------------------------------------------------- - assign sink_ready = src_ready; - assign src_valid = sink_valid; - assign src_startofpacket = sink_startofpacket; - assign src_endofpacket = sink_endofpacket; - - wire [PKT_DEST_ID_W-1:0] default_destid; - wire [18-1 : 0] default_src_channel; - - - - - - nios_system_id_router_default_decode the_default_decode( - .default_destination_id (default_destid), - .default_wr_channel (), - .default_rd_channel (), - .default_src_channel (default_src_channel) - ); - - always @* begin - src_data = sink_data; - src_channel = default_src_channel; - - // -------------------------------------------------- - // DestinationID Decoder - // Sets the channel based on the destination ID. - // -------------------------------------------------- - destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; - - - - if (destid == 1 ) begin - src_channel = 18'b01; - end - - if (destid == 0 ) begin - src_channel = 18'b10; - end - - -end - - - // -------------------------------------------------- - // Ceil(log2()) function - // -------------------------------------------------- - function integer log2ceil; - input reg[65:0] val; - reg [65:0] i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - -endmodule - - diff --git a/nios_system/synthesis/submodules/nios_system_id_router_002.sv b/nios_system/synthesis/submodules/nios_system_id_router_002.sv deleted file mode 100644 index a80e831..0000000 --- a/nios_system/synthesis/submodules/nios_system_id_router_002.sv +++ /dev/null @@ -1,217 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------------------- -// Merlin Router -// -// Asserts the appropriate one-hot encoded channel based on -// either (a) the address or (b) the dest id. The DECODER_TYPE -// parameter controls this behaviour. 0 means address decoder, -// 1 means dest id decoder. -// -// In the case of (a), it also sets the destination id. -// ------------------------------------------------------- - -`timescale 1 ns / 1 ns - -module nios_system_id_router_002_default_decode - #( - parameter DEFAULT_CHANNEL = 0, - DEFAULT_WR_CHANNEL = -1, - DEFAULT_RD_CHANNEL = -1, - DEFAULT_DESTID = 0 - ) - (output [85 - 81 : 0] default_destination_id, - output [18-1 : 0] default_wr_channel, - output [18-1 : 0] default_rd_channel, - output [18-1 : 0] default_src_channel - ); - - assign default_destination_id = - DEFAULT_DESTID[85 - 81 : 0]; - - generate begin : default_decode - if (DEFAULT_CHANNEL == -1) begin - assign default_src_channel = '0; - end - else begin - assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; - end - end - endgenerate - - generate begin : default_decode_rw - if (DEFAULT_RD_CHANNEL == -1) begin - assign default_wr_channel = '0; - assign default_rd_channel = '0; - end - else begin - assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; - assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; - end - end - endgenerate - -endmodule - - -module nios_system_id_router_002 -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // Command Sink (Input) - // ------------------- - input sink_valid, - input [96-1 : 0] sink_data, - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Command Source (Output) - // ------------------- - output src_valid, - output reg [96-1 : 0] src_data, - output reg [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready -); - - // ------------------------------------------------------- - // Local parameters and variables - // ------------------------------------------------------- - localparam PKT_ADDR_H = 54; - localparam PKT_ADDR_L = 36; - localparam PKT_DEST_ID_H = 85; - localparam PKT_DEST_ID_L = 81; - localparam PKT_PROTECTION_H = 89; - localparam PKT_PROTECTION_L = 87; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam DECODER_TYPE = 1; - - localparam PKT_TRANS_WRITE = 57; - localparam PKT_TRANS_READ = 58; - - localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; - localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; - - - - // ------------------------------------------------------- - // Figure out the number of bits to mask off for each slave span - // during address decoding - // ------------------------------------------------------- - // ------------------------------------------------------- - // Work out which address bits are significant based on the - // address range of the slaves. If the required width is too - // large or too small, we use the address field width instead. - // ------------------------------------------------------- - localparam ADDR_RANGE = 64'h0; - localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); - localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || - (RANGE_ADDR_WIDTH == 0) ? - PKT_ADDR_H : - PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; - - localparam RG = RANGE_ADDR_WIDTH; - - reg [PKT_DEST_ID_W-1 : 0] destid; - - // ------------------------------------------------------- - // Pass almost everything through, untouched - // ------------------------------------------------------- - assign sink_ready = src_ready; - assign src_valid = sink_valid; - assign src_startofpacket = sink_startofpacket; - assign src_endofpacket = sink_endofpacket; - - wire [PKT_DEST_ID_W-1:0] default_destid; - wire [18-1 : 0] default_src_channel; - - - - - - nios_system_id_router_002_default_decode the_default_decode( - .default_destination_id (default_destid), - .default_wr_channel (), - .default_rd_channel (), - .default_src_channel (default_src_channel) - ); - - always @* begin - src_data = sink_data; - src_channel = default_src_channel; - - // -------------------------------------------------- - // DestinationID Decoder - // Sets the channel based on the destination ID. - // -------------------------------------------------- - destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; - - - - if (destid == 0 ) begin - src_channel = 18'b1; - end - - -end - - - // -------------------------------------------------- - // Ceil(log2()) function - // -------------------------------------------------- - function integer log2ceil; - input reg[65:0] val; - reg [65:0] i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - -endmodule - - diff --git a/nios_system/synthesis/submodules/nios_system_id_router_003.sv b/nios_system/synthesis/submodules/nios_system_id_router_003.sv deleted file mode 100644 index 5eb343c..0000000 --- a/nios_system/synthesis/submodules/nios_system_id_router_003.sv +++ /dev/null @@ -1,217 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------------------- -// Merlin Router -// -// Asserts the appropriate one-hot encoded channel based on -// either (a) the address or (b) the dest id. The DECODER_TYPE -// parameter controls this behaviour. 0 means address decoder, -// 1 means dest id decoder. -// -// In the case of (a), it also sets the destination id. -// ------------------------------------------------------- - -`timescale 1 ns / 1 ns - -module nios_system_id_router_003_default_decode - #( - parameter DEFAULT_CHANNEL = 0, - DEFAULT_WR_CHANNEL = -1, - DEFAULT_RD_CHANNEL = -1, - DEFAULT_DESTID = 0 - ) - (output [85 - 81 : 0] default_destination_id, - output [18-1 : 0] default_wr_channel, - output [18-1 : 0] default_rd_channel, - output [18-1 : 0] default_src_channel - ); - - assign default_destination_id = - DEFAULT_DESTID[85 - 81 : 0]; - - generate begin : default_decode - if (DEFAULT_CHANNEL == -1) begin - assign default_src_channel = '0; - end - else begin - assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; - end - end - endgenerate - - generate begin : default_decode_rw - if (DEFAULT_RD_CHANNEL == -1) begin - assign default_wr_channel = '0; - assign default_rd_channel = '0; - end - else begin - assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; - assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; - end - end - endgenerate - -endmodule - - -module nios_system_id_router_003 -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // Command Sink (Input) - // ------------------- - input sink_valid, - input [96-1 : 0] sink_data, - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Command Source (Output) - // ------------------- - output src_valid, - output reg [96-1 : 0] src_data, - output reg [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready -); - - // ------------------------------------------------------- - // Local parameters and variables - // ------------------------------------------------------- - localparam PKT_ADDR_H = 54; - localparam PKT_ADDR_L = 36; - localparam PKT_DEST_ID_H = 85; - localparam PKT_DEST_ID_L = 81; - localparam PKT_PROTECTION_H = 89; - localparam PKT_PROTECTION_L = 87; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam DECODER_TYPE = 1; - - localparam PKT_TRANS_WRITE = 57; - localparam PKT_TRANS_READ = 58; - - localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; - localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; - - - - // ------------------------------------------------------- - // Figure out the number of bits to mask off for each slave span - // during address decoding - // ------------------------------------------------------- - // ------------------------------------------------------- - // Work out which address bits are significant based on the - // address range of the slaves. If the required width is too - // large or too small, we use the address field width instead. - // ------------------------------------------------------- - localparam ADDR_RANGE = 64'h0; - localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); - localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || - (RANGE_ADDR_WIDTH == 0) ? - PKT_ADDR_H : - PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; - - localparam RG = RANGE_ADDR_WIDTH; - - reg [PKT_DEST_ID_W-1 : 0] destid; - - // ------------------------------------------------------- - // Pass almost everything through, untouched - // ------------------------------------------------------- - assign sink_ready = src_ready; - assign src_valid = sink_valid; - assign src_startofpacket = sink_startofpacket; - assign src_endofpacket = sink_endofpacket; - - wire [PKT_DEST_ID_W-1:0] default_destid; - wire [18-1 : 0] default_src_channel; - - - - - - nios_system_id_router_003_default_decode the_default_decode( - .default_destination_id (default_destid), - .default_wr_channel (), - .default_rd_channel (), - .default_src_channel (default_src_channel) - ); - - always @* begin - src_data = sink_data; - src_channel = default_src_channel; - - // -------------------------------------------------- - // DestinationID Decoder - // Sets the channel based on the destination ID. - // -------------------------------------------------- - destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; - - - - if (destid == 0 ) begin - src_channel = 18'b1; - end - - -end - - - // -------------------------------------------------- - // Ceil(log2()) function - // -------------------------------------------------- - function integer log2ceil; - input reg[65:0] val; - reg [65:0] i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - -endmodule - - diff --git a/nios_system/synthesis/submodules/nios_system_irq_mapper.sv b/nios_system/synthesis/submodules/nios_system_irq_mapper.sv deleted file mode 100644 index cc0a8bb..0000000 --- a/nios_system/synthesis/submodules/nios_system_irq_mapper.sv +++ /dev/null @@ -1,59 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------------------- -// Altera IRQ Mapper -// -// Parameters -// NUM_RCVRS : 1 -// SENDER_IRW_WIDTH : 32 -// IRQ_MAP : 0:5 -// -// ------------------------------------------------------- - -`timescale 1 ns / 1 ns - -module nios_system_irq_mapper -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // IRQ Receivers - // ------------------- - input receiver0_irq, - - // ------------------- - // Command Source (Output) - // ------------------- - output reg [31 : 0] sender_irq -); - - - always @* begin - sender_irq = 0; - - sender_irq[5] = receiver0_irq; - end - -endmodule - - diff --git a/nios_system/synthesis/submodules/nios_system_jtag_uart.v b/nios_system/synthesis/submodules/nios_system_jtag_uart.v deleted file mode 100644 index 0d02445..0000000 --- a/nios_system/synthesis/submodules/nios_system_jtag_uart.v +++ /dev/null @@ -1,583 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_jtag_uart_sim_scfifo_w ( - // inputs: - clk, - fifo_wdata, - fifo_wr, - - // outputs: - fifo_FF, - r_dat, - wfifo_empty, - wfifo_used - ) -; - - output fifo_FF; - output [ 7: 0] r_dat; - output wfifo_empty; - output [ 5: 0] wfifo_used; - input clk; - input [ 7: 0] fifo_wdata; - input fifo_wr; - - wire fifo_FF; - wire [ 7: 0] r_dat; - wire wfifo_empty; - wire [ 5: 0] wfifo_used; - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - always @(posedge clk) - begin - if (fifo_wr) - $write("%c", fifo_wdata); - end - - - assign wfifo_used = {6{1'b0}}; - assign r_dat = {8{1'b0}}; - assign fifo_FF = 1'b0; - assign wfifo_empty = 1'b1; - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_jtag_uart_scfifo_w ( - // inputs: - clk, - fifo_clear, - fifo_wdata, - fifo_wr, - rd_wfifo, - - // outputs: - fifo_FF, - r_dat, - wfifo_empty, - wfifo_used - ) -; - - output fifo_FF; - output [ 7: 0] r_dat; - output wfifo_empty; - output [ 5: 0] wfifo_used; - input clk; - input fifo_clear; - input [ 7: 0] fifo_wdata; - input fifo_wr; - input rd_wfifo; - - wire fifo_FF; - wire [ 7: 0] r_dat; - wire wfifo_empty; - wire [ 5: 0] wfifo_used; - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - nios_system_jtag_uart_sim_scfifo_w the_nios_system_jtag_uart_sim_scfifo_w - ( - .clk (clk), - .fifo_FF (fifo_FF), - .fifo_wdata (fifo_wdata), - .fifo_wr (fifo_wr), - .r_dat (r_dat), - .wfifo_empty (wfifo_empty), - .wfifo_used (wfifo_used) - ); - - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on -//synthesis read_comments_as_HDL on -// scfifo wfifo -// ( -// .aclr (fifo_clear), -// .clock (clk), -// .data (fifo_wdata), -// .empty (wfifo_empty), -// .full (fifo_FF), -// .q (r_dat), -// .rdreq (rd_wfifo), -// .usedw (wfifo_used), -// .wrreq (fifo_wr) -// ); -// -// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO", -// wfifo.lpm_numwords = 64, -// wfifo.lpm_showahead = "OFF", -// wfifo.lpm_type = "scfifo", -// wfifo.lpm_width = 8, -// wfifo.lpm_widthu = 6, -// wfifo.overflow_checking = "OFF", -// wfifo.underflow_checking = "OFF", -// wfifo.use_eab = "ON"; -// -//synthesis read_comments_as_HDL off - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_jtag_uart_sim_scfifo_r ( - // inputs: - clk, - fifo_rd, - rst_n, - - // outputs: - fifo_EF, - fifo_rdata, - rfifo_full, - rfifo_used - ) -; - - output fifo_EF; - output [ 7: 0] fifo_rdata; - output rfifo_full; - output [ 5: 0] rfifo_used; - input clk; - input fifo_rd; - input rst_n; - - reg [ 31: 0] bytes_left; - wire fifo_EF; - reg fifo_rd_d; - wire [ 7: 0] fifo_rdata; - wire new_rom; - wire [ 31: 0] num_bytes; - wire [ 6: 0] rfifo_entries; - wire rfifo_full; - wire [ 5: 0] rfifo_used; - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - // Generate rfifo_entries for simulation - always @(posedge clk or negedge rst_n) - begin - if (rst_n == 0) - begin - bytes_left <= 32'h0; - fifo_rd_d <= 1'b0; - end - else - begin - fifo_rd_d <= fifo_rd; - // decrement on read - if (fifo_rd_d) - bytes_left <= bytes_left - 1'b1; - // catch new contents - if (new_rom) - bytes_left <= num_bytes; - end - end - - - assign fifo_EF = bytes_left == 32'b0; - assign rfifo_full = bytes_left > 7'h40; - assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left; - assign rfifo_used = rfifo_entries[5 : 0]; - assign new_rom = 1'b0; - assign num_bytes = 32'b0; - assign fifo_rdata = 8'b0; - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_jtag_uart_scfifo_r ( - // inputs: - clk, - fifo_clear, - fifo_rd, - rst_n, - t_dat, - wr_rfifo, - - // outputs: - fifo_EF, - fifo_rdata, - rfifo_full, - rfifo_used - ) -; - - output fifo_EF; - output [ 7: 0] fifo_rdata; - output rfifo_full; - output [ 5: 0] rfifo_used; - input clk; - input fifo_clear; - input fifo_rd; - input rst_n; - input [ 7: 0] t_dat; - input wr_rfifo; - - wire fifo_EF; - wire [ 7: 0] fifo_rdata; - wire rfifo_full; - wire [ 5: 0] rfifo_used; - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - nios_system_jtag_uart_sim_scfifo_r the_nios_system_jtag_uart_sim_scfifo_r - ( - .clk (clk), - .fifo_EF (fifo_EF), - .fifo_rd (fifo_rd), - .fifo_rdata (fifo_rdata), - .rfifo_full (rfifo_full), - .rfifo_used (rfifo_used), - .rst_n (rst_n) - ); - - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on -//synthesis read_comments_as_HDL on -// scfifo rfifo -// ( -// .aclr (fifo_clear), -// .clock (clk), -// .data (t_dat), -// .empty (fifo_EF), -// .full (rfifo_full), -// .q (fifo_rdata), -// .rdreq (fifo_rd), -// .usedw (rfifo_used), -// .wrreq (wr_rfifo) -// ); -// -// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO", -// rfifo.lpm_numwords = 64, -// rfifo.lpm_showahead = "OFF", -// rfifo.lpm_type = "scfifo", -// rfifo.lpm_width = 8, -// rfifo.lpm_widthu = 6, -// rfifo.overflow_checking = "OFF", -// rfifo.underflow_checking = "OFF", -// rfifo.use_eab = "ON"; -// -//synthesis read_comments_as_HDL off - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_jtag_uart ( - // inputs: - av_address, - av_chipselect, - av_read_n, - av_write_n, - av_writedata, - clk, - rst_n, - - // outputs: - av_irq, - av_readdata, - av_waitrequest, - dataavailable, - readyfordata - ) - /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ; - - output av_irq; - output [ 31: 0] av_readdata; - output av_waitrequest; - output dataavailable; - output readyfordata; - input av_address; - input av_chipselect; - input av_read_n; - input av_write_n; - input [ 31: 0] av_writedata; - input clk; - input rst_n; - - reg ac; - wire activity; - wire av_irq; - wire [ 31: 0] av_readdata; - reg av_waitrequest; - reg dataavailable; - reg fifo_AE; - reg fifo_AF; - wire fifo_EF; - wire fifo_FF; - wire fifo_clear; - wire fifo_rd; - wire [ 7: 0] fifo_rdata; - wire [ 7: 0] fifo_wdata; - reg fifo_wr; - reg ien_AE; - reg ien_AF; - wire ipen_AE; - wire ipen_AF; - reg pause_irq; - wire [ 7: 0] r_dat; - wire r_ena; - reg r_val; - wire rd_wfifo; - reg read_0; - reg readyfordata; - wire rfifo_full; - wire [ 5: 0] rfifo_used; - reg rvalid; - reg sim_r_ena; - reg sim_t_dat; - reg sim_t_ena; - reg sim_t_pause; - wire [ 7: 0] t_dat; - reg t_dav; - wire t_ena; - wire t_pause; - wire wfifo_empty; - wire [ 5: 0] wfifo_used; - reg woverflow; - wire wr_rfifo; - //avalon_jtag_slave, which is an e_avalon_slave - assign rd_wfifo = r_ena & ~wfifo_empty; - assign wr_rfifo = t_ena & ~rfifo_full; - assign fifo_clear = ~rst_n; - nios_system_jtag_uart_scfifo_w the_nios_system_jtag_uart_scfifo_w - ( - .clk (clk), - .fifo_FF (fifo_FF), - .fifo_clear (fifo_clear), - .fifo_wdata (fifo_wdata), - .fifo_wr (fifo_wr), - .r_dat (r_dat), - .rd_wfifo (rd_wfifo), - .wfifo_empty (wfifo_empty), - .wfifo_used (wfifo_used) - ); - - nios_system_jtag_uart_scfifo_r the_nios_system_jtag_uart_scfifo_r - ( - .clk (clk), - .fifo_EF (fifo_EF), - .fifo_clear (fifo_clear), - .fifo_rd (fifo_rd), - .fifo_rdata (fifo_rdata), - .rfifo_full (rfifo_full), - .rfifo_used (rfifo_used), - .rst_n (rst_n), - .t_dat (t_dat), - .wr_rfifo (wr_rfifo) - ); - - assign ipen_AE = ien_AE & fifo_AE; - assign ipen_AF = ien_AF & (pause_irq | fifo_AF); - assign av_irq = ipen_AE | ipen_AF; - assign activity = t_pause | t_ena; - always @(posedge clk or negedge rst_n) - begin - if (rst_n == 0) - pause_irq <= 1'b0; - else // only if fifo is not empty... - if (t_pause & ~fifo_EF) - pause_irq <= 1'b1; - else if (read_0) - pause_irq <= 1'b0; - end - - - always @(posedge clk or negedge rst_n) - begin - if (rst_n == 0) - begin - r_val <= 1'b0; - t_dav <= 1'b1; - end - else - begin - r_val <= r_ena & ~wfifo_empty; - t_dav <= ~rfifo_full; - end - end - - - always @(posedge clk or negedge rst_n) - begin - if (rst_n == 0) - begin - fifo_AE <= 1'b0; - fifo_AF <= 1'b0; - fifo_wr <= 1'b0; - rvalid <= 1'b0; - read_0 <= 1'b0; - ien_AE <= 1'b0; - ien_AF <= 1'b0; - ac <= 1'b0; - woverflow <= 1'b0; - av_waitrequest <= 1'b1; - end - else - begin - fifo_AE <= {fifo_FF,wfifo_used} <= 8; - fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8; - fifo_wr <= 1'b0; - read_0 <= 1'b0; - av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest); - if (activity) - ac <= 1'b1; - // write - if (av_chipselect & ~av_write_n & av_waitrequest) - // addr 1 is control; addr 0 is data - if (av_address) - begin - ien_AF <= av_writedata[0]; - ien_AE <= av_writedata[1]; - if (av_writedata[10] & ~activity) - ac <= 1'b0; - end - else - begin - fifo_wr <= ~fifo_FF; - woverflow <= fifo_FF; - end - // read - if (av_chipselect & ~av_read_n & av_waitrequest) - begin - // addr 1 is interrupt; addr 0 is data - if (~av_address) - rvalid <= ~fifo_EF; - read_0 <= ~av_address; - end - end - end - - - assign fifo_wdata = av_writedata[7 : 0]; - assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0; - assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF }; - always @(posedge clk or negedge rst_n) - begin - if (rst_n == 0) - readyfordata <= 0; - else - readyfordata <= ~fifo_FF; - end - - - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - // Tie off Atlantic Interface signals not used for simulation - always @(posedge clk) - begin - sim_t_pause <= 1'b0; - sim_t_ena <= 1'b0; - sim_t_dat <= t_dav ? r_dat : {8{r_val}}; - sim_r_ena <= 1'b0; - end - - - assign r_ena = sim_r_ena; - assign t_ena = sim_t_ena; - assign t_dat = sim_t_dat; - assign t_pause = sim_t_pause; - always @(fifo_EF) - begin - dataavailable = ~fifo_EF; - end - - - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on -//synthesis read_comments_as_HDL on -// alt_jtag_atlantic nios_system_jtag_uart_alt_jtag_atlantic -// ( -// .clk (clk), -// .r_dat (r_dat), -// .r_ena (r_ena), -// .r_val (r_val), -// .rst_n (rst_n), -// .t_dat (t_dat), -// .t_dav (t_dav), -// .t_ena (t_ena), -// .t_pause (t_pause) -// ); -// -// defparam nios_system_jtag_uart_alt_jtag_atlantic.INSTANCE_ID = 0, -// nios_system_jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6, -// nios_system_jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6, -// nios_system_jtag_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES"; -// -// always @(posedge clk or negedge rst_n) -// begin -// if (rst_n == 0) -// dataavailable <= 0; -// else -// dataavailable <= ~fifo_EF; -// end -// -// -//synthesis read_comments_as_HDL off - -endmodule - diff --git a/nios_system/synthesis/submodules/nios_system_lcd.v b/nios_system/synthesis/submodules/nios_system_lcd.v deleted file mode 100644 index 18c2d15..0000000 --- a/nios_system/synthesis/submodules/nios_system_lcd.v +++ /dev/null @@ -1,66 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_lcd ( - // inputs: - address, - begintransfer, - clk, - read, - reset_n, - write, - writedata, - - // outputs: - LCD_E, - LCD_RS, - LCD_RW, - LCD_data, - readdata - ) -; - - output LCD_E; - output LCD_RS; - output LCD_RW; - inout [ 7: 0] LCD_data; - output [ 7: 0] readdata; - input [ 1: 0] address; - input begintransfer; - input clk; - input read; - input reset_n; - input write; - input [ 7: 0] writedata; - - wire LCD_E; - wire LCD_RS; - wire LCD_RW; - wire [ 7: 0] LCD_data; - wire [ 7: 0] readdata; - assign LCD_RW = address[0]; - assign LCD_RS = address[1]; - assign LCD_E = read | write; - assign LCD_data = (address[0]) ? {8{1'bz}} : writedata; - assign readdata = LCD_data; - //control_slave, which is an e_avalon_slave - -endmodule - diff --git a/nios_system/synthesis/submodules/nios_system_lcd_16207_0.v b/nios_system/synthesis/submodules/nios_system_lcd_16207_0.v deleted file mode 100644 index f58d30f..0000000 --- a/nios_system/synthesis/submodules/nios_system_lcd_16207_0.v +++ /dev/null @@ -1,66 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_lcd_16207_0 ( - // inputs: - address, - begintransfer, - clk, - read, - reset_n, - write, - writedata, - - // outputs: - LCD_E, - LCD_RS, - LCD_RW, - LCD_data, - readdata - ) -; - - output LCD_E; - output LCD_RS; - output LCD_RW; - inout [ 7: 0] LCD_data; - output [ 7: 0] readdata; - input [ 1: 0] address; - input begintransfer; - input clk; - input read; - input reset_n; - input write; - input [ 7: 0] writedata; - - wire LCD_E; - wire LCD_RS; - wire LCD_RW; - wire [ 7: 0] LCD_data; - wire [ 7: 0] readdata; - assign LCD_RW = address[0]; - assign LCD_RS = address[1]; - assign LCD_E = read | write; - assign LCD_data = (address[0]) ? {8{1'bz}} : writedata; - assign readdata = LCD_data; - //control_slave, which is an e_avalon_slave - -endmodule - diff --git a/nios_system/synthesis/submodules/nios_system_lcd_E.v b/nios_system/synthesis/submodules/nios_system_lcd_E.v deleted file mode 100644 index c5680d0..0000000 --- a/nios_system/synthesis/submodules/nios_system_lcd_E.v +++ /dev/null @@ -1,66 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_lcd_E ( - // inputs: - address, - chipselect, - clk, - reset_n, - write_n, - writedata, - - // outputs: - out_port, - readdata - ) -; - - output out_port; - output [ 31: 0] readdata; - input [ 1: 0] address; - input chipselect; - input clk; - input reset_n; - input write_n; - input [ 31: 0] writedata; - - wire clk_en; - reg data_out; - wire out_port; - wire read_mux_out; - wire [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {1 {(address == 0)}} & data_out; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - data_out <= 0; - else if (chipselect && ~write_n && (address == 0)) - data_out <= writedata; - end - - - assign readdata = {32'b0 | read_mux_out}; - assign out_port = data_out; - -endmodule - diff --git a/nios_system/synthesis/submodules/nios_system_lcd_on.v b/nios_system/synthesis/submodules/nios_system_lcd_on.v deleted file mode 100644 index 4e9a8dc..0000000 --- a/nios_system/synthesis/submodules/nios_system_lcd_on.v +++ /dev/null @@ -1,66 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_lcd_on ( - // inputs: - address, - chipselect, - clk, - reset_n, - write_n, - writedata, - - // outputs: - out_port, - readdata - ) -; - - output out_port; - output [ 31: 0] readdata; - input [ 1: 0] address; - input chipselect; - input clk; - input reset_n; - input write_n; - input [ 31: 0] writedata; - - wire clk_en; - reg data_out; - wire out_port; - wire read_mux_out; - wire [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {1 {(address == 0)}} & data_out; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - data_out <= 0; - else if (chipselect && ~write_n && (address == 0)) - data_out <= writedata; - end - - - assign readdata = {32'b0 | read_mux_out}; - assign out_port = data_out; - -endmodule - diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor.sdc b/nios_system/synthesis/submodules/nios_system_nios2_processor.sdc deleted file mode 100644 index 4848c5a..0000000 --- a/nios_system/synthesis/submodules/nios_system_nios2_processor.sdc +++ /dev/null @@ -1,53 +0,0 @@ -# Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -# use of Altera Corporation's design tools, logic functions and other -# software and tools, and its AMPP partner logic functions, and any -# output files any of the foregoing (including device programming or -# simulation files), and any associated documentation or information are -# expressly subject to the terms and conditions of the Altera Program -# License Subscription Agreement or other applicable license agreement, -# including, without limitation, that your use is for the sole purpose -# of programming logic devices manufactured by Altera and sold by Altera -# or its authorized distributors. Please refer to the applicable -# agreement for further details. - -#************************************************************** -# Timequest JTAG clock definition -# Uncommenting the following lines will define the JTAG -# clock in TimeQuest Timing Analyzer -#************************************************************** - -#create_clock -period 10MHz {altera_reserved_tck} -#set_clock_groups -asynchronous -group {altera_reserved_tck} - -#************************************************************** -# Set TCL Path Variables -#************************************************************** - -set nios_system_nios2_processor nios_system_nios2_processor:* -set nios_system_nios2_processor_oci nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci -set nios_system_nios2_processor_oci_break nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break -set nios_system_nios2_processor_ocimem nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem -set nios_system_nios2_processor_oci_debug nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug -set nios_system_nios2_processor_wrapper nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper -set nios_system_nios2_processor_jtag_tck nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck -set nios_system_nios2_processor_jtag_sysclk nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk -set nios_system_nios2_processor_oci_path [format "%s|%s" $nios_system_nios2_processor $nios_system_nios2_processor_oci] -set nios_system_nios2_processor_oci_break_path [format "%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_oci_break] -set nios_system_nios2_processor_ocimem_path [format "%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_ocimem] -set nios_system_nios2_processor_oci_debug_path [format "%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_oci_debug] -set nios_system_nios2_processor_jtag_tck_path [format "%s|%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_wrapper $nios_system_nios2_processor_jtag_tck] -set nios_system_nios2_processor_jtag_sysclk_path [format "%s|%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_wrapper $nios_system_nios2_processor_jtag_sysclk] -set nios_system_nios2_processor_jtag_sr [format "%s|*sr" $nios_system_nios2_processor_jtag_tck_path] - -#************************************************************** -# Set False Paths -#************************************************************** - -set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_break_path|break_readreg*] -to [get_keepers *$nios_system_nios2_processor_jtag_sr*] -set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_debug_path|*resetlatch] -to [get_keepers *$nios_system_nios2_processor_jtag_sr[33]] -set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_debug_path|monitor_ready] -to [get_keepers *$nios_system_nios2_processor_jtag_sr[0]] -set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_debug_path|monitor_error] -to [get_keepers *$nios_system_nios2_processor_jtag_sr[34]] -set_false_path -from [get_keepers *$nios_system_nios2_processor_ocimem_path|*MonDReg*] -to [get_keepers *$nios_system_nios2_processor_jtag_sr*] -set_false_path -from *$nios_system_nios2_processor_jtag_sr* -to *$nios_system_nios2_processor_jtag_sysclk_path|*jdo* -set_false_path -from sld_hub:*|irf_reg* -to *$nios_system_nios2_processor_jtag_sysclk_path|ir* -set_false_path -from sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1] -to *$nios_system_nios2_processor_oci_debug_path|monitor_go diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor.v b/nios_system/synthesis/submodules/nios_system_nios2_processor.v deleted file mode 100644 index 7e8e063..0000000 --- a/nios_system/synthesis/submodules/nios_system_nios2_processor.v +++ /dev/null @@ -1,5672 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_register_bank_a_module ( - // inputs: - clock, - data, - rdaddress, - wraddress, - wren, - - // outputs: - q - ) -; - - parameter lpm_file = "UNUSED"; - - - output [ 31: 0] q; - input clock; - input [ 31: 0] data; - input [ 4: 0] rdaddress; - input [ 4: 0] wraddress; - input wren; - - wire [ 31: 0] q; - wire [ 31: 0] ram_q; - assign q = ram_q; - altsyncram the_altsyncram - ( - .address_a (wraddress), - .address_b (rdaddress), - .clock0 (clock), - .data_a (data), - .q_b (ram_q), - .wren_a (wren) - ); - - defparam the_altsyncram.address_reg_b = "CLOCK0", - the_altsyncram.init_file = lpm_file, - the_altsyncram.maximum_depth = 0, - the_altsyncram.numwords_a = 32, - the_altsyncram.numwords_b = 32, - the_altsyncram.operation_mode = "DUAL_PORT", - the_altsyncram.outdata_reg_b = "UNREGISTERED", - the_altsyncram.ram_block_type = "AUTO", - the_altsyncram.rdcontrol_reg_b = "CLOCK0", - the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", - the_altsyncram.width_a = 32, - the_altsyncram.width_b = 32, - the_altsyncram.widthad_a = 5, - the_altsyncram.widthad_b = 5; - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_register_bank_b_module ( - // inputs: - clock, - data, - rdaddress, - wraddress, - wren, - - // outputs: - q - ) -; - - parameter lpm_file = "UNUSED"; - - - output [ 31: 0] q; - input clock; - input [ 31: 0] data; - input [ 4: 0] rdaddress; - input [ 4: 0] wraddress; - input wren; - - wire [ 31: 0] q; - wire [ 31: 0] ram_q; - assign q = ram_q; - altsyncram the_altsyncram - ( - .address_a (wraddress), - .address_b (rdaddress), - .clock0 (clock), - .data_a (data), - .q_b (ram_q), - .wren_a (wren) - ); - - defparam the_altsyncram.address_reg_b = "CLOCK0", - the_altsyncram.init_file = lpm_file, - the_altsyncram.maximum_depth = 0, - the_altsyncram.numwords_a = 32, - the_altsyncram.numwords_b = 32, - the_altsyncram.operation_mode = "DUAL_PORT", - the_altsyncram.outdata_reg_b = "UNREGISTERED", - the_altsyncram.ram_block_type = "AUTO", - the_altsyncram.rdcontrol_reg_b = "CLOCK0", - the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", - the_altsyncram.width_a = 32, - the_altsyncram.width_b = 32, - the_altsyncram.widthad_a = 5, - the_altsyncram.widthad_b = 5; - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_debug ( - // inputs: - clk, - dbrk_break, - debugreq, - hbreak_enabled, - jdo, - jrst_n, - ocireg_ers, - ocireg_mrs, - reset, - st_ready_test_idle, - take_action_ocimem_a, - take_action_ocireg, - xbrk_break, - - // outputs: - debugack, - monitor_error, - monitor_go, - monitor_ready, - oci_hbreak_req, - resetlatch, - resetrequest - ) -; - - output debugack; - output monitor_error; - output monitor_go; - output monitor_ready; - output oci_hbreak_req; - output resetlatch; - output resetrequest; - input clk; - input dbrk_break; - input debugreq; - input hbreak_enabled; - input [ 37: 0] jdo; - input jrst_n; - input ocireg_ers; - input ocireg_mrs; - input reset; - input st_ready_test_idle; - input take_action_ocimem_a; - input take_action_ocireg; - input xbrk_break; - - reg break_on_reset /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - wire debugack; - reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; - reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; - reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; - wire oci_hbreak_req; - wire reset_sync; - reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - wire unxcomplemented_resetxx0; - assign unxcomplemented_resetxx0 = jrst_n; - altera_std_synchronizer the_altera_std_synchronizer - ( - .clk (clk), - .din (reset), - .dout (reset_sync), - .reset_n (unxcomplemented_resetxx0) - ); - - defparam the_altera_std_synchronizer.depth = 2; - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - break_on_reset <= 1'b0; - resetrequest <= 1'b0; - jtag_break <= 1'b0; - end - else if (take_action_ocimem_a) - begin - resetrequest <= jdo[22]; - jtag_break <= jdo[21] ? 1 - : jdo[20] ? 0 - : jtag_break; - - break_on_reset <= jdo[19] ? 1 - : jdo[18] ? 0 - : break_on_reset; - - resetlatch <= jdo[24] ? 0 : resetlatch; - end - else if (reset_sync) - begin - jtag_break <= break_on_reset; - resetlatch <= 1; - end - else if (debugreq & ~debugack & break_on_reset) - jtag_break <= 1'b1; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - monitor_ready <= 1'b0; - monitor_error <= 1'b0; - monitor_go <= 1'b0; - end - else - begin - if (take_action_ocimem_a && jdo[25]) - monitor_ready <= 1'b0; - else if (take_action_ocireg && ocireg_mrs) - monitor_ready <= 1'b1; - if (take_action_ocimem_a && jdo[25]) - monitor_error <= 1'b0; - else if (take_action_ocireg && ocireg_ers) - monitor_error <= 1'b1; - if (take_action_ocimem_a && jdo[23]) - monitor_go <= 1'b1; - else if (st_ready_test_idle) - monitor_go <= 1'b0; - end - end - - - assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq; - assign debugack = ~hbreak_enabled; - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_ociram_sp_ram_module ( - // inputs: - address, - byteenable, - clock, - data, - wren, - - // outputs: - q - ) -; - - parameter lpm_file = "UNUSED"; - - - output [ 31: 0] q; - input [ 7: 0] address; - input [ 3: 0] byteenable; - input clock; - input [ 31: 0] data; - input wren; - - wire [ 31: 0] q; - wire [ 31: 0] ram_q; - assign q = ram_q; - altsyncram the_altsyncram - ( - .address_a (address), - .byteena_a (byteenable), - .clock0 (clock), - .data_a (data), - .q_a (ram_q), - .wren_a (wren) - ); - - defparam the_altsyncram.init_file = lpm_file, - the_altsyncram.maximum_depth = 0, - the_altsyncram.numwords_a = 256, - the_altsyncram.operation_mode = "SINGLE_PORT", - the_altsyncram.outdata_reg_a = "UNREGISTERED", - the_altsyncram.ram_block_type = "AUTO", - the_altsyncram.width_a = 32, - the_altsyncram.width_byteena_a = 4, - the_altsyncram.widthad_a = 8; - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_ocimem ( - // inputs: - address, - byteenable, - clk, - debugaccess, - jdo, - jrst_n, - read, - take_action_ocimem_a, - take_action_ocimem_b, - take_no_action_ocimem_a, - write, - writedata, - - // outputs: - MonDReg, - ociram_readdata, - waitrequest - ) -; - - output [ 31: 0] MonDReg; - output [ 31: 0] ociram_readdata; - output waitrequest; - input [ 8: 0] address; - input [ 3: 0] byteenable; - input clk; - input debugaccess; - input [ 37: 0] jdo; - input jrst_n; - input read; - input take_action_ocimem_a; - input take_action_ocimem_b; - input take_no_action_ocimem_a; - input write; - input [ 31: 0] writedata; - - reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire [ 8: 0] MonARegAddrInc; - wire MonARegAddrIncAccessingRAM; - reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - reg avalon_ociram_readdata_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire avalon_ram_wr; - wire [ 31: 0] cfgrom_readdata; - reg jtag_ram_access /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - reg jtag_ram_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - reg jtag_ram_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - reg jtag_ram_wr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - reg jtag_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - reg jtag_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire [ 7: 0] ociram_addr; - wire [ 3: 0] ociram_byteenable; - wire [ 31: 0] ociram_readdata; - wire [ 31: 0] ociram_wr_data; - wire ociram_wr_en; - reg waitrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - jtag_rd <= 1'b0; - jtag_rd_d1 <= 1'b0; - jtag_ram_wr <= 1'b0; - jtag_ram_rd <= 1'b0; - jtag_ram_rd_d1 <= 1'b0; - jtag_ram_access <= 1'b0; - MonAReg <= 0; - MonDReg <= 0; - waitrequest <= 1'b1; - avalon_ociram_readdata_ready <= 1'b0; - end - else - begin - if (take_no_action_ocimem_a) - begin - MonAReg[10 : 2] <= MonARegAddrInc; - jtag_rd <= 1'b1; - jtag_ram_rd <= MonARegAddrIncAccessingRAM; - jtag_ram_access <= MonARegAddrIncAccessingRAM; - end - else if (take_action_ocimem_a) - begin - MonAReg[10 : 2] <= { jdo[17], - jdo[33 : 26] }; - - jtag_rd <= 1'b1; - jtag_ram_rd <= ~jdo[17]; - jtag_ram_access <= ~jdo[17]; - end - else if (take_action_ocimem_b) - begin - MonAReg[10 : 2] <= MonARegAddrInc; - MonDReg <= jdo[34 : 3]; - jtag_ram_wr <= MonARegAddrIncAccessingRAM; - jtag_ram_access <= MonARegAddrIncAccessingRAM; - end - else - begin - jtag_rd <= 0; - jtag_ram_wr <= 0; - jtag_ram_rd <= 0; - jtag_ram_access <= 0; - if (jtag_rd_d1) - MonDReg <= jtag_ram_rd_d1 ? ociram_readdata : cfgrom_readdata; - end - jtag_rd_d1 <= jtag_rd; - jtag_ram_rd_d1 <= jtag_ram_rd; - if (~waitrequest) - begin - waitrequest <= 1'b1; - avalon_ociram_readdata_ready <= 1'b0; - end - else if (write) - waitrequest <= ~address[8] & jtag_ram_access; - else if (read) - begin - avalon_ociram_readdata_ready <= ~(~address[8] & jtag_ram_access); - waitrequest <= ~avalon_ociram_readdata_ready; - end - else - begin - waitrequest <= 1'b1; - avalon_ociram_readdata_ready <= 1'b0; - end - end - end - - - assign MonARegAddrInc = MonAReg[10 : 2]+1; - assign MonARegAddrIncAccessingRAM = ~MonARegAddrInc[8]; - assign avalon_ram_wr = write & ~address[8] & debugaccess; - assign ociram_addr = jtag_ram_access ? MonAReg[9 : 2] : address[7 : 0]; - assign ociram_wr_data = jtag_ram_access ? MonDReg[31 : 0] : writedata; - assign ociram_byteenable = jtag_ram_access ? 4'b1111 : byteenable; - assign ociram_wr_en = jtag_ram_wr | avalon_ram_wr; -//nios_system_nios2_processor_ociram_sp_ram, which is an nios_sp_ram -nios_system_nios2_processor_ociram_sp_ram_module nios_system_nios2_processor_ociram_sp_ram - ( - .address (ociram_addr), - .byteenable (ociram_byteenable), - .clock (clk), - .data (ociram_wr_data), - .q (ociram_readdata), - .wren (ociram_wr_en) - ); - -//synthesis translate_off -`ifdef NO_PLI -defparam nios_system_nios2_processor_ociram_sp_ram.lpm_file = "nios_system_nios2_processor_ociram_default_contents.dat"; -`else -defparam nios_system_nios2_processor_ociram_sp_ram.lpm_file = "nios_system_nios2_processor_ociram_default_contents.hex"; -`endif -//synthesis translate_on -//synthesis read_comments_as_HDL on -//defparam nios_system_nios2_processor_ociram_sp_ram.lpm_file = "nios_system_nios2_processor_ociram_default_contents.mif"; -//synthesis read_comments_as_HDL off - assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h00000020 : - (MonAReg[4 : 2] == 3'd1)? 32'h00001313 : - (MonAReg[4 : 2] == 3'd2)? 32'h00040000 : - (MonAReg[4 : 2] == 3'd3)? 32'h00000000 : - (MonAReg[4 : 2] == 3'd4)? 32'h20000000 : - (MonAReg[4 : 2] == 3'd5)? 32'h00000000 : - (MonAReg[4 : 2] == 3'd6)? 32'h00000000 : - 32'h00000000; - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_avalon_reg ( - // inputs: - address, - clk, - debugaccess, - monitor_error, - monitor_go, - monitor_ready, - reset_n, - write, - writedata, - - // outputs: - oci_ienable, - oci_reg_readdata, - oci_single_step_mode, - ocireg_ers, - ocireg_mrs, - take_action_ocireg - ) -; - - output [ 31: 0] oci_ienable; - output [ 31: 0] oci_reg_readdata; - output oci_single_step_mode; - output ocireg_ers; - output ocireg_mrs; - output take_action_ocireg; - input [ 8: 0] address; - input clk; - input debugaccess; - input monitor_error; - input monitor_go; - input monitor_ready; - input reset_n; - input write; - input [ 31: 0] writedata; - - reg [ 31: 0] oci_ienable; - wire oci_reg_00_addressed; - wire oci_reg_01_addressed; - wire [ 31: 0] oci_reg_readdata; - reg oci_single_step_mode; - wire ocireg_ers; - wire ocireg_mrs; - wire ocireg_sstep; - wire take_action_oci_intr_mask_reg; - wire take_action_ocireg; - wire write_strobe; - assign oci_reg_00_addressed = address == 9'h100; - assign oci_reg_01_addressed = address == 9'h101; - assign write_strobe = write & debugaccess; - assign take_action_ocireg = write_strobe & oci_reg_00_addressed; - assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed; - assign ocireg_ers = writedata[1]; - assign ocireg_mrs = writedata[0]; - assign ocireg_sstep = writedata[3]; - assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go, - monitor_ready, monitor_error} : - oci_reg_01_addressed ? oci_ienable : - 32'b0; - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - oci_single_step_mode <= 1'b0; - else if (take_action_ocireg) - oci_single_step_mode <= ocireg_sstep; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - oci_ienable <= 32'b00000000000000000000000000100000; - else if (take_action_oci_intr_mask_reg) - oci_ienable <= writedata | ~(32'b00000000000000000000000000100000); - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_break ( - // inputs: - clk, - dbrk_break, - dbrk_goto0, - dbrk_goto1, - jdo, - jrst_n, - reset_n, - take_action_break_a, - take_action_break_b, - take_action_break_c, - take_no_action_break_a, - take_no_action_break_b, - take_no_action_break_c, - xbrk_goto0, - xbrk_goto1, - - // outputs: - break_readreg, - dbrk_hit0_latch, - dbrk_hit1_latch, - dbrk_hit2_latch, - dbrk_hit3_latch, - trigbrktype, - trigger_state_0, - trigger_state_1, - xbrk_ctrl0, - xbrk_ctrl1, - xbrk_ctrl2, - xbrk_ctrl3 - ) -; - - output [ 31: 0] break_readreg; - output dbrk_hit0_latch; - output dbrk_hit1_latch; - output dbrk_hit2_latch; - output dbrk_hit3_latch; - output trigbrktype; - output trigger_state_0; - output trigger_state_1; - output [ 7: 0] xbrk_ctrl0; - output [ 7: 0] xbrk_ctrl1; - output [ 7: 0] xbrk_ctrl2; - output [ 7: 0] xbrk_ctrl3; - input clk; - input dbrk_break; - input dbrk_goto0; - input dbrk_goto1; - input [ 37: 0] jdo; - input jrst_n; - input reset_n; - input take_action_break_a; - input take_action_break_b; - input take_action_break_c; - input take_no_action_break_a; - input take_no_action_break_b; - input take_no_action_break_c; - input xbrk_goto0; - input xbrk_goto1; - - wire [ 3: 0] break_a_wpr; - wire [ 1: 0] break_a_wpr_high_bits; - wire [ 1: 0] break_a_wpr_low_bits; - wire [ 1: 0] break_b_rr; - wire [ 1: 0] break_c_rr; - reg [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - wire dbrk0_high_value; - wire dbrk0_low_value; - wire dbrk1_high_value; - wire dbrk1_low_value; - wire dbrk2_high_value; - wire dbrk2_low_value; - wire dbrk3_high_value; - wire dbrk3_low_value; - wire dbrk_hit0_latch; - wire dbrk_hit1_latch; - wire dbrk_hit2_latch; - wire dbrk_hit3_latch; - wire take_action_any_break; - reg trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg trigger_state; - wire trigger_state_0; - wire trigger_state_1; - wire [ 31: 0] xbrk0_value; - wire [ 31: 0] xbrk1_value; - wire [ 31: 0] xbrk2_value; - wire [ 31: 0] xbrk3_value; - reg [ 7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg [ 7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg [ 7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg [ 7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - assign break_a_wpr = jdo[35 : 32]; - assign break_a_wpr_high_bits = break_a_wpr[3 : 2]; - assign break_a_wpr_low_bits = break_a_wpr[1 : 0]; - assign break_b_rr = jdo[33 : 32]; - assign break_c_rr = jdo[33 : 32]; - assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - xbrk_ctrl0 <= 0; - xbrk_ctrl1 <= 0; - xbrk_ctrl2 <= 0; - xbrk_ctrl3 <= 0; - trigbrktype <= 0; - end - else - begin - if (take_action_any_break) - trigbrktype <= 0; - else if (dbrk_break) - trigbrktype <= 1; - if (take_action_break_b) - begin - if ((break_b_rr == 2'b00) && (0 >= 1)) - begin - xbrk_ctrl0[0] <= jdo[27]; - xbrk_ctrl0[1] <= jdo[28]; - xbrk_ctrl0[2] <= jdo[29]; - xbrk_ctrl0[3] <= jdo[30]; - xbrk_ctrl0[4] <= jdo[21]; - xbrk_ctrl0[5] <= jdo[20]; - xbrk_ctrl0[6] <= jdo[19]; - xbrk_ctrl0[7] <= jdo[18]; - end - if ((break_b_rr == 2'b01) && (0 >= 2)) - begin - xbrk_ctrl1[0] <= jdo[27]; - xbrk_ctrl1[1] <= jdo[28]; - xbrk_ctrl1[2] <= jdo[29]; - xbrk_ctrl1[3] <= jdo[30]; - xbrk_ctrl1[4] <= jdo[21]; - xbrk_ctrl1[5] <= jdo[20]; - xbrk_ctrl1[6] <= jdo[19]; - xbrk_ctrl1[7] <= jdo[18]; - end - if ((break_b_rr == 2'b10) && (0 >= 3)) - begin - xbrk_ctrl2[0] <= jdo[27]; - xbrk_ctrl2[1] <= jdo[28]; - xbrk_ctrl2[2] <= jdo[29]; - xbrk_ctrl2[3] <= jdo[30]; - xbrk_ctrl2[4] <= jdo[21]; - xbrk_ctrl2[5] <= jdo[20]; - xbrk_ctrl2[6] <= jdo[19]; - xbrk_ctrl2[7] <= jdo[18]; - end - if ((break_b_rr == 2'b11) && (0 >= 4)) - begin - xbrk_ctrl3[0] <= jdo[27]; - xbrk_ctrl3[1] <= jdo[28]; - xbrk_ctrl3[2] <= jdo[29]; - xbrk_ctrl3[3] <= jdo[30]; - xbrk_ctrl3[4] <= jdo[21]; - xbrk_ctrl3[5] <= jdo[20]; - xbrk_ctrl3[6] <= jdo[19]; - xbrk_ctrl3[7] <= jdo[18]; - end - end - end - end - - - assign dbrk_hit0_latch = 1'b0; - assign dbrk0_low_value = 0; - assign dbrk0_high_value = 0; - assign dbrk_hit1_latch = 1'b0; - assign dbrk1_low_value = 0; - assign dbrk1_high_value = 0; - assign dbrk_hit2_latch = 1'b0; - assign dbrk2_low_value = 0; - assign dbrk2_high_value = 0; - assign dbrk_hit3_latch = 1'b0; - assign dbrk3_low_value = 0; - assign dbrk3_high_value = 0; - assign xbrk0_value = 32'b0; - assign xbrk1_value = 32'b0; - assign xbrk2_value = 32'b0; - assign xbrk3_value = 32'b0; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - break_readreg <= 32'b0; - else if (take_action_any_break) - break_readreg <= jdo[31 : 0]; - else if (take_no_action_break_a) - case (break_a_wpr_high_bits) - - 2'd0: begin - case (break_a_wpr_low_bits) // synthesis full_case - - 2'd0: begin - break_readreg <= xbrk0_value; - end // 2'd0 - - 2'd1: begin - break_readreg <= xbrk1_value; - end // 2'd1 - - 2'd2: begin - break_readreg <= xbrk2_value; - end // 2'd2 - - 2'd3: begin - break_readreg <= xbrk3_value; - end // 2'd3 - - endcase // break_a_wpr_low_bits - end // 2'd0 - - 2'd1: begin - break_readreg <= 32'b0; - end // 2'd1 - - 2'd2: begin - case (break_a_wpr_low_bits) // synthesis full_case - - 2'd0: begin - break_readreg <= dbrk0_low_value; - end // 2'd0 - - 2'd1: begin - break_readreg <= dbrk1_low_value; - end // 2'd1 - - 2'd2: begin - break_readreg <= dbrk2_low_value; - end // 2'd2 - - 2'd3: begin - break_readreg <= dbrk3_low_value; - end // 2'd3 - - endcase // break_a_wpr_low_bits - end // 2'd2 - - 2'd3: begin - case (break_a_wpr_low_bits) // synthesis full_case - - 2'd0: begin - break_readreg <= dbrk0_high_value; - end // 2'd0 - - 2'd1: begin - break_readreg <= dbrk1_high_value; - end // 2'd1 - - 2'd2: begin - break_readreg <= dbrk2_high_value; - end // 2'd2 - - 2'd3: begin - break_readreg <= dbrk3_high_value; - end // 2'd3 - - endcase // break_a_wpr_low_bits - end // 2'd3 - - endcase // break_a_wpr_high_bits - else if (take_no_action_break_b) - break_readreg <= jdo[31 : 0]; - else if (take_no_action_break_c) - break_readreg <= jdo[31 : 0]; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - trigger_state <= 0; - else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0)) - trigger_state <= 0; - else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1)) - trigger_state <= -1; - end - - - assign trigger_state_0 = ~trigger_state; - assign trigger_state_1 = trigger_state; - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_xbrk ( - // inputs: - D_valid, - E_valid, - F_pc, - clk, - reset_n, - trigger_state_0, - trigger_state_1, - xbrk_ctrl0, - xbrk_ctrl1, - xbrk_ctrl2, - xbrk_ctrl3, - - // outputs: - xbrk_break, - xbrk_goto0, - xbrk_goto1, - xbrk_traceoff, - xbrk_traceon, - xbrk_trigout - ) -; - - output xbrk_break; - output xbrk_goto0; - output xbrk_goto1; - output xbrk_traceoff; - output xbrk_traceon; - output xbrk_trigout; - input D_valid; - input E_valid; - input [ 16: 0] F_pc; - input clk; - input reset_n; - input trigger_state_0; - input trigger_state_1; - input [ 7: 0] xbrk_ctrl0; - input [ 7: 0] xbrk_ctrl1; - input [ 7: 0] xbrk_ctrl2; - input [ 7: 0] xbrk_ctrl3; - - wire D_cpu_addr_en; - wire E_cpu_addr_en; - reg E_xbrk_goto0; - reg E_xbrk_goto1; - reg E_xbrk_traceoff; - reg E_xbrk_traceon; - reg E_xbrk_trigout; - wire [ 18: 0] cpu_i_address; - wire xbrk0_armed; - wire xbrk0_break_hit; - wire xbrk0_goto0_hit; - wire xbrk0_goto1_hit; - wire xbrk0_toff_hit; - wire xbrk0_ton_hit; - wire xbrk0_tout_hit; - wire xbrk1_armed; - wire xbrk1_break_hit; - wire xbrk1_goto0_hit; - wire xbrk1_goto1_hit; - wire xbrk1_toff_hit; - wire xbrk1_ton_hit; - wire xbrk1_tout_hit; - wire xbrk2_armed; - wire xbrk2_break_hit; - wire xbrk2_goto0_hit; - wire xbrk2_goto1_hit; - wire xbrk2_toff_hit; - wire xbrk2_ton_hit; - wire xbrk2_tout_hit; - wire xbrk3_armed; - wire xbrk3_break_hit; - wire xbrk3_goto0_hit; - wire xbrk3_goto1_hit; - wire xbrk3_toff_hit; - wire xbrk3_ton_hit; - wire xbrk3_tout_hit; - reg xbrk_break; - wire xbrk_break_hit; - wire xbrk_goto0; - wire xbrk_goto0_hit; - wire xbrk_goto1; - wire xbrk_goto1_hit; - wire xbrk_toff_hit; - wire xbrk_ton_hit; - wire xbrk_tout_hit; - wire xbrk_traceoff; - wire xbrk_traceon; - wire xbrk_trigout; - assign cpu_i_address = {F_pc, 2'b00}; - assign D_cpu_addr_en = D_valid; - assign E_cpu_addr_en = E_valid; - assign xbrk0_break_hit = 0; - assign xbrk0_ton_hit = 0; - assign xbrk0_toff_hit = 0; - assign xbrk0_tout_hit = 0; - assign xbrk0_goto0_hit = 0; - assign xbrk0_goto1_hit = 0; - assign xbrk1_break_hit = 0; - assign xbrk1_ton_hit = 0; - assign xbrk1_toff_hit = 0; - assign xbrk1_tout_hit = 0; - assign xbrk1_goto0_hit = 0; - assign xbrk1_goto1_hit = 0; - assign xbrk2_break_hit = 0; - assign xbrk2_ton_hit = 0; - assign xbrk2_toff_hit = 0; - assign xbrk2_tout_hit = 0; - assign xbrk2_goto0_hit = 0; - assign xbrk2_goto1_hit = 0; - assign xbrk3_break_hit = 0; - assign xbrk3_ton_hit = 0; - assign xbrk3_toff_hit = 0; - assign xbrk3_tout_hit = 0; - assign xbrk3_goto0_hit = 0; - assign xbrk3_goto1_hit = 0; - assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit); - assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit); - assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit); - assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit); - assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit); - assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - xbrk_break <= 0; - else if (E_cpu_addr_en) - xbrk_break <= xbrk_break_hit; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_xbrk_traceon <= 0; - else if (E_cpu_addr_en) - E_xbrk_traceon <= xbrk_ton_hit; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_xbrk_traceoff <= 0; - else if (E_cpu_addr_en) - E_xbrk_traceoff <= xbrk_toff_hit; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_xbrk_trigout <= 0; - else if (E_cpu_addr_en) - E_xbrk_trigout <= xbrk_tout_hit; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_xbrk_goto0 <= 0; - else if (E_cpu_addr_en) - E_xbrk_goto0 <= xbrk_goto0_hit; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_xbrk_goto1 <= 0; - else if (E_cpu_addr_en) - E_xbrk_goto1 <= xbrk_goto1_hit; - end - - - assign xbrk_traceon = 1'b0; - assign xbrk_traceoff = 1'b0; - assign xbrk_trigout = 1'b0; - assign xbrk_goto0 = 1'b0; - assign xbrk_goto1 = 1'b0; - assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) || - (xbrk_ctrl0[5] & trigger_state_1); - - assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) || - (xbrk_ctrl1[5] & trigger_state_1); - - assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) || - (xbrk_ctrl2[5] & trigger_state_1); - - assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) || - (xbrk_ctrl3[5] & trigger_state_1); - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_dbrk ( - // inputs: - E_st_data, - av_ld_data_aligned_filtered, - clk, - d_address, - d_read, - d_waitrequest, - d_write, - debugack, - reset_n, - - // outputs: - cpu_d_address, - cpu_d_read, - cpu_d_readdata, - cpu_d_wait, - cpu_d_write, - cpu_d_writedata, - dbrk_break, - dbrk_goto0, - dbrk_goto1, - dbrk_traceme, - dbrk_traceoff, - dbrk_traceon, - dbrk_trigout - ) -; - - output [ 18: 0] cpu_d_address; - output cpu_d_read; - output [ 31: 0] cpu_d_readdata; - output cpu_d_wait; - output cpu_d_write; - output [ 31: 0] cpu_d_writedata; - output dbrk_break; - output dbrk_goto0; - output dbrk_goto1; - output dbrk_traceme; - output dbrk_traceoff; - output dbrk_traceon; - output dbrk_trigout; - input [ 31: 0] E_st_data; - input [ 31: 0] av_ld_data_aligned_filtered; - input clk; - input [ 18: 0] d_address; - input d_read; - input d_waitrequest; - input d_write; - input debugack; - input reset_n; - - wire [ 18: 0] cpu_d_address; - wire cpu_d_read; - wire [ 31: 0] cpu_d_readdata; - wire cpu_d_wait; - wire cpu_d_write; - wire [ 31: 0] cpu_d_writedata; - wire dbrk0_armed; - wire dbrk0_break_pulse; - wire dbrk0_goto0; - wire dbrk0_goto1; - wire dbrk0_traceme; - wire dbrk0_traceoff; - wire dbrk0_traceon; - wire dbrk0_trigout; - wire dbrk1_armed; - wire dbrk1_break_pulse; - wire dbrk1_goto0; - wire dbrk1_goto1; - wire dbrk1_traceme; - wire dbrk1_traceoff; - wire dbrk1_traceon; - wire dbrk1_trigout; - wire dbrk2_armed; - wire dbrk2_break_pulse; - wire dbrk2_goto0; - wire dbrk2_goto1; - wire dbrk2_traceme; - wire dbrk2_traceoff; - wire dbrk2_traceon; - wire dbrk2_trigout; - wire dbrk3_armed; - wire dbrk3_break_pulse; - wire dbrk3_goto0; - wire dbrk3_goto1; - wire dbrk3_traceme; - wire dbrk3_traceoff; - wire dbrk3_traceon; - wire dbrk3_trigout; - reg dbrk_break; - reg dbrk_break_pulse; - wire [ 31: 0] dbrk_data; - reg dbrk_goto0; - reg dbrk_goto1; - reg dbrk_traceme; - reg dbrk_traceoff; - reg dbrk_traceon; - reg dbrk_trigout; - assign cpu_d_address = d_address; - assign cpu_d_readdata = av_ld_data_aligned_filtered; - assign cpu_d_read = d_read; - assign cpu_d_writedata = E_st_data; - assign cpu_d_write = d_write; - assign cpu_d_wait = d_waitrequest; - assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - dbrk_break <= 0; - else - dbrk_break <= dbrk_break ? ~debugack - : dbrk_break_pulse; - - end - - - assign dbrk0_armed = 1'b0; - assign dbrk0_trigout = 1'b0; - assign dbrk0_break_pulse = 1'b0; - assign dbrk0_traceoff = 1'b0; - assign dbrk0_traceon = 1'b0; - assign dbrk0_traceme = 1'b0; - assign dbrk0_goto0 = 1'b0; - assign dbrk0_goto1 = 1'b0; - assign dbrk1_armed = 1'b0; - assign dbrk1_trigout = 1'b0; - assign dbrk1_break_pulse = 1'b0; - assign dbrk1_traceoff = 1'b0; - assign dbrk1_traceon = 1'b0; - assign dbrk1_traceme = 1'b0; - assign dbrk1_goto0 = 1'b0; - assign dbrk1_goto1 = 1'b0; - assign dbrk2_armed = 1'b0; - assign dbrk2_trigout = 1'b0; - assign dbrk2_break_pulse = 1'b0; - assign dbrk2_traceoff = 1'b0; - assign dbrk2_traceon = 1'b0; - assign dbrk2_traceme = 1'b0; - assign dbrk2_goto0 = 1'b0; - assign dbrk2_goto1 = 1'b0; - assign dbrk3_armed = 1'b0; - assign dbrk3_trigout = 1'b0; - assign dbrk3_break_pulse = 1'b0; - assign dbrk3_traceoff = 1'b0; - assign dbrk3_traceon = 1'b0; - assign dbrk3_traceme = 1'b0; - assign dbrk3_goto0 = 1'b0; - assign dbrk3_goto1 = 1'b0; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - dbrk_trigout <= 0; - dbrk_break_pulse <= 0; - dbrk_traceoff <= 0; - dbrk_traceon <= 0; - dbrk_traceme <= 0; - dbrk_goto0 <= 0; - dbrk_goto1 <= 0; - end - else - begin - dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout; - dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse; - dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff; - dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon; - dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme; - dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0; - dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1; - end - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_itrace ( - // inputs: - clk, - dbrk_traceoff, - dbrk_traceon, - jdo, - jrst_n, - take_action_tracectrl, - trc_enb, - xbrk_traceoff, - xbrk_traceon, - xbrk_wrap_traceoff, - - // outputs: - dct_buffer, - dct_count, - itm, - trc_ctrl, - trc_on - ) -; - - output [ 29: 0] dct_buffer; - output [ 3: 0] dct_count; - output [ 35: 0] itm; - output [ 15: 0] trc_ctrl; - output trc_on; - input clk; - input dbrk_traceoff; - input dbrk_traceon; - input [ 15: 0] jdo; - input jrst_n; - input take_action_tracectrl; - input trc_enb; - input xbrk_traceoff; - input xbrk_traceon; - input xbrk_wrap_traceoff; - - wire curr_pid; - reg [ 29: 0] dct_buffer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 1: 0] dct_code; - reg [ 3: 0] dct_count /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire dct_is_taken; - wire [ 31: 0] excaddr; - wire instr_retired; - wire is_advanced_exception; - wire is_cond_dct; - wire is_dct; - wire is_exception_no_break; - wire is_fast_tlb_miss_exception; - wire is_idct; - reg [ 35: 0] itm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire not_in_debug_mode; - reg pending_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg [ 31: 0] pending_excaddr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg pending_exctype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg [ 3: 0] pending_frametype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg pending_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg prev_pid_valid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire record_dct_outcome_in_sync; - wire record_itrace; - wire [ 31: 0] retired_pcb; - reg snapped_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg snapped_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg snapped_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 1: 0] sync_code; - wire [ 6: 0] sync_interval; - wire sync_pending; - reg [ 6: 0] sync_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 6: 0] sync_timer_next; - reg trc_clear /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; - wire [ 15: 0] trc_ctrl; - reg [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire trc_on; - assign is_cond_dct = 1'b0; - assign is_dct = 1'b0; - assign dct_is_taken = 1'b0; - assign is_idct = 1'b0; - assign retired_pcb = 32'b0; - assign not_in_debug_mode = 1'b0; - assign instr_retired = 1'b0; - assign is_advanced_exception = 1'b0; - assign is_exception_no_break = 1'b0; - assign is_fast_tlb_miss_exception = 1'b0; - assign curr_pid = 1'b0; - assign excaddr = 32'b0; - assign sync_code = trc_ctrl[3 : 2]; - assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 }; - assign sync_pending = sync_timer == 0; - assign record_dct_outcome_in_sync = dct_is_taken & sync_pending; - assign sync_timer_next = sync_pending ? sync_timer : (sync_timer - 1); - assign record_itrace = trc_on & trc_ctrl[4]; - assign dct_code = {is_cond_dct, dct_is_taken}; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - trc_clear <= 0; - else - trc_clear <= ~trc_enb & - take_action_tracectrl & jdo[4]; - - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - itm <= 0; - dct_buffer <= 0; - dct_count <= 0; - sync_timer <= 0; - pending_frametype <= 4'b0000; - pending_exctype <= 1'b0; - pending_excaddr <= 0; - prev_pid <= 0; - prev_pid_valid <= 0; - snapped_pid <= 0; - snapped_curr_pid <= 0; - snapped_prev_pid <= 0; - pending_curr_pid <= 0; - pending_prev_pid <= 0; - end - else if (trc_clear || (!0 && !0)) - begin - itm <= 0; - dct_buffer <= 0; - dct_count <= 0; - sync_timer <= 0; - pending_frametype <= 4'b0000; - pending_exctype <= 1'b0; - pending_excaddr <= 0; - prev_pid <= 0; - prev_pid_valid <= 0; - snapped_pid <= 0; - snapped_curr_pid <= 0; - snapped_prev_pid <= 0; - pending_curr_pid <= 0; - pending_prev_pid <= 0; - end - else - begin - if (!prev_pid_valid) - begin - prev_pid <= curr_pid; - prev_pid_valid <= 1; - end - if ((curr_pid != prev_pid) & prev_pid_valid & !snapped_pid) - begin - snapped_pid <= 1; - snapped_curr_pid <= curr_pid; - snapped_prev_pid <= prev_pid; - prev_pid <= curr_pid; - prev_pid_valid <= 1; - end - if (instr_retired | is_advanced_exception) - begin - if (~record_itrace) - pending_frametype <= 4'b1010; - else if (is_exception_no_break) - begin - pending_frametype <= 4'b0010; - pending_excaddr <= excaddr; - if (is_fast_tlb_miss_exception) - pending_exctype <= 1'b1; - else - pending_exctype <= 1'b0; - end - else if (is_idct) - pending_frametype <= 4'b1001; - else if (record_dct_outcome_in_sync) - pending_frametype <= 4'b1000; - else if (!is_dct & snapped_pid) - begin - pending_frametype <= 4'b0011; - pending_curr_pid <= snapped_curr_pid; - pending_prev_pid <= snapped_prev_pid; - snapped_pid <= 0; - end - else - pending_frametype <= 4'b0000; - if ((dct_count != 0) & - (~record_itrace | - is_exception_no_break | - is_idct | - record_dct_outcome_in_sync | - (!is_dct & snapped_pid))) - begin - itm <= {4'b0001, dct_buffer, 2'b00}; - dct_buffer <= 0; - dct_count <= 0; - sync_timer <= sync_timer_next; - end - else - begin - if (record_itrace & (is_dct & (dct_count != 4'd15)) & ~record_dct_outcome_in_sync & ~is_advanced_exception) - begin - dct_buffer <= {dct_code, dct_buffer[29 : 2]}; - dct_count <= dct_count + 1; - end - if (record_itrace & (pending_frametype == 4'b0010)) - itm <= {4'b0010, pending_excaddr[31 : 1], pending_exctype}; - else if (record_itrace & ( - (pending_frametype == 4'b1000) | - (pending_frametype == 4'b1010) | - (pending_frametype == 4'b1001))) - begin - itm <= {pending_frametype, retired_pcb}; - sync_timer <= sync_interval; - if (0 & - ((pending_frametype == 4'b1000) | (pending_frametype == 4'b1010)) & - !snapped_pid & prev_pid_valid) - begin - snapped_pid <= 1; - snapped_curr_pid <= curr_pid; - snapped_prev_pid <= prev_pid; - end - end - else if (record_itrace & - 0 & (pending_frametype == 4'b0011)) - itm <= {4'b0011, 2'b00, pending_prev_pid, 2'b00, pending_curr_pid}; - else if (record_itrace & is_dct) - begin - if (dct_count == 4'd15) - begin - itm <= {4'b0001, dct_code, dct_buffer}; - dct_buffer <= 0; - dct_count <= 0; - sync_timer <= sync_timer_next; - end - else - itm <= 4'b0000; - end - else - itm <= {4'b0000, 32'b0}; - end - end - else - itm <= {4'b0000, 32'b0}; - end - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - trc_ctrl_reg[0] <= 1'b0; - trc_ctrl_reg[1] <= 1'b0; - trc_ctrl_reg[3 : 2] <= 2'b00; - trc_ctrl_reg[4] <= 1'b0; - trc_ctrl_reg[7 : 5] <= 3'b000; - trc_ctrl_reg[8] <= 0; - trc_ctrl_reg[9] <= 1'b0; - trc_ctrl_reg[10] <= 1'b0; - end - else if (take_action_tracectrl) - begin - trc_ctrl_reg[0] <= jdo[5]; - trc_ctrl_reg[1] <= jdo[6]; - trc_ctrl_reg[3 : 2] <= jdo[8 : 7]; - trc_ctrl_reg[4] <= jdo[9]; - trc_ctrl_reg[9] <= jdo[14]; - trc_ctrl_reg[10] <= jdo[2]; - if (0) - trc_ctrl_reg[7 : 5] <= jdo[12 : 10]; - if (0 & 0) - trc_ctrl_reg[8] <= jdo[13]; - end - else if (xbrk_wrap_traceoff) - begin - trc_ctrl_reg[1] <= 0; - trc_ctrl_reg[0] <= 0; - end - else if (dbrk_traceoff | xbrk_traceoff) - trc_ctrl_reg[1] <= 0; - else if (trc_ctrl_reg[0] & - (dbrk_traceon | xbrk_traceon)) - trc_ctrl_reg[1] <= 1; - end - - - assign trc_ctrl = (0 || 0) ? {6'b000000, trc_ctrl_reg} : 0; - assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode); - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_td_mode ( - // inputs: - ctrl, - - // outputs: - td_mode - ) -; - - output [ 3: 0] td_mode; - input [ 8: 0] ctrl; - - wire [ 2: 0] ctrl_bits_for_mux; - reg [ 3: 0] td_mode; - assign ctrl_bits_for_mux = ctrl[7 : 5]; - always @(ctrl_bits_for_mux) - begin - case (ctrl_bits_for_mux) - - 3'b000: begin - td_mode = 4'b0000; - end // 3'b000 - - 3'b001: begin - td_mode = 4'b1000; - end // 3'b001 - - 3'b010: begin - td_mode = 4'b0100; - end // 3'b010 - - 3'b011: begin - td_mode = 4'b1100; - end // 3'b011 - - 3'b100: begin - td_mode = 4'b0010; - end // 3'b100 - - 3'b101: begin - td_mode = 4'b1010; - end // 3'b101 - - 3'b110: begin - td_mode = 4'b0101; - end // 3'b110 - - 3'b111: begin - td_mode = 4'b1111; - end // 3'b111 - - endcase // ctrl_bits_for_mux - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_dtrace ( - // inputs: - clk, - cpu_d_address, - cpu_d_read, - cpu_d_readdata, - cpu_d_wait, - cpu_d_write, - cpu_d_writedata, - jrst_n, - trc_ctrl, - - // outputs: - atm, - dtm - ) -; - - output [ 35: 0] atm; - output [ 35: 0] dtm; - input clk; - input [ 18: 0] cpu_d_address; - input cpu_d_read; - input [ 31: 0] cpu_d_readdata; - input cpu_d_wait; - input cpu_d_write; - input [ 31: 0] cpu_d_writedata; - input jrst_n; - input [ 15: 0] trc_ctrl; - - reg [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 31: 0] cpu_d_address_0_padded; - wire [ 31: 0] cpu_d_readdata_0_padded; - wire [ 31: 0] cpu_d_writedata_0_padded; - reg [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire record_load_addr; - wire record_load_data; - wire record_store_addr; - wire record_store_data; - wire [ 3: 0] td_mode_trc_ctrl; - assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0; - assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0; - assign cpu_d_address_0_padded = cpu_d_address | 32'b0; - //nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode, which is an e_instance - nios_system_nios2_processor_nios2_oci_td_mode nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode - ( - .ctrl (trc_ctrl[8 : 0]), - .td_mode (td_mode_trc_ctrl) - ); - - assign {record_load_addr, record_store_addr, - record_load_data, record_store_data} = td_mode_trc_ctrl; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - atm <= 0; - dtm <= 0; - end - else if (0) - begin - if (cpu_d_write & ~cpu_d_wait & record_store_addr) - atm <= {4'b0101, cpu_d_address_0_padded}; - else if (cpu_d_read & ~cpu_d_wait & record_load_addr) - atm <= {4'b0100, cpu_d_address_0_padded}; - else - atm <= {4'b0000, cpu_d_address_0_padded}; - if (cpu_d_write & ~cpu_d_wait & record_store_data) - dtm <= {4'b0111, cpu_d_writedata_0_padded}; - else if (cpu_d_read & ~cpu_d_wait & record_load_data) - dtm <= {4'b0110, cpu_d_readdata_0_padded}; - else - dtm <= {4'b0000, cpu_d_readdata_0_padded}; - end - else - begin - atm <= 0; - dtm <= 0; - end - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_compute_tm_count ( - // inputs: - atm_valid, - dtm_valid, - itm_valid, - - // outputs: - compute_tm_count - ) -; - - output [ 1: 0] compute_tm_count; - input atm_valid; - input dtm_valid; - input itm_valid; - - reg [ 1: 0] compute_tm_count; - wire [ 2: 0] switch_for_mux; - assign switch_for_mux = {itm_valid, atm_valid, dtm_valid}; - always @(switch_for_mux) - begin - case (switch_for_mux) - - 3'b000: begin - compute_tm_count = 0; - end // 3'b000 - - 3'b001: begin - compute_tm_count = 1; - end // 3'b001 - - 3'b010: begin - compute_tm_count = 1; - end // 3'b010 - - 3'b011: begin - compute_tm_count = 2; - end // 3'b011 - - 3'b100: begin - compute_tm_count = 1; - end // 3'b100 - - 3'b101: begin - compute_tm_count = 2; - end // 3'b101 - - 3'b110: begin - compute_tm_count = 2; - end // 3'b110 - - 3'b111: begin - compute_tm_count = 3; - end // 3'b111 - - endcase // switch_for_mux - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_fifowp_inc ( - // inputs: - free2, - free3, - tm_count, - - // outputs: - fifowp_inc - ) -; - - output [ 3: 0] fifowp_inc; - input free2; - input free3; - input [ 1: 0] tm_count; - - reg [ 3: 0] fifowp_inc; - always @(free2 or free3 or tm_count) - begin - if (free3 & (tm_count == 3)) - fifowp_inc = 3; - else if (free2 & (tm_count >= 2)) - fifowp_inc = 2; - else if (tm_count >= 1) - fifowp_inc = 1; - else - fifowp_inc = 0; - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_fifocount_inc ( - // inputs: - empty, - free2, - free3, - tm_count, - - // outputs: - fifocount_inc - ) -; - - output [ 4: 0] fifocount_inc; - input empty; - input free2; - input free3; - input [ 1: 0] tm_count; - - reg [ 4: 0] fifocount_inc; - always @(empty or free2 or free3 or tm_count) - begin - if (empty) - fifocount_inc = tm_count[1 : 0]; - else if (free3 & (tm_count == 3)) - fifocount_inc = 2; - else if (free2 & (tm_count >= 2)) - fifocount_inc = 1; - else if (tm_count >= 1) - fifocount_inc = 0; - else - fifocount_inc = {5{1'b1}}; - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_fifo ( - // inputs: - atm, - clk, - dbrk_traceme, - dbrk_traceoff, - dbrk_traceon, - dct_buffer, - dct_count, - dtm, - itm, - jrst_n, - reset_n, - test_ending, - test_has_ended, - trc_on, - - // outputs: - tw - ) -; - - output [ 35: 0] tw; - input [ 35: 0] atm; - input clk; - input dbrk_traceme; - input dbrk_traceoff; - input dbrk_traceon; - input [ 29: 0] dct_buffer; - input [ 3: 0] dct_count; - input [ 35: 0] dtm; - input [ 35: 0] itm; - input jrst_n; - input reset_n; - input test_ending; - input test_has_ended; - input trc_on; - - wire atm_valid; - wire [ 1: 0] compute_tm_count_tm_count; - wire dtm_valid; - wire empty; - reg [ 35: 0] fifo_0; - wire fifo_0_enable; - wire [ 35: 0] fifo_0_mux; - reg [ 35: 0] fifo_1; - reg [ 35: 0] fifo_10; - wire fifo_10_enable; - wire [ 35: 0] fifo_10_mux; - reg [ 35: 0] fifo_11; - wire fifo_11_enable; - wire [ 35: 0] fifo_11_mux; - reg [ 35: 0] fifo_12; - wire fifo_12_enable; - wire [ 35: 0] fifo_12_mux; - reg [ 35: 0] fifo_13; - wire fifo_13_enable; - wire [ 35: 0] fifo_13_mux; - reg [ 35: 0] fifo_14; - wire fifo_14_enable; - wire [ 35: 0] fifo_14_mux; - reg [ 35: 0] fifo_15; - wire fifo_15_enable; - wire [ 35: 0] fifo_15_mux; - wire fifo_1_enable; - wire [ 35: 0] fifo_1_mux; - reg [ 35: 0] fifo_2; - wire fifo_2_enable; - wire [ 35: 0] fifo_2_mux; - reg [ 35: 0] fifo_3; - wire fifo_3_enable; - wire [ 35: 0] fifo_3_mux; - reg [ 35: 0] fifo_4; - wire fifo_4_enable; - wire [ 35: 0] fifo_4_mux; - reg [ 35: 0] fifo_5; - wire fifo_5_enable; - wire [ 35: 0] fifo_5_mux; - reg [ 35: 0] fifo_6; - wire fifo_6_enable; - wire [ 35: 0] fifo_6_mux; - reg [ 35: 0] fifo_7; - wire fifo_7_enable; - wire [ 35: 0] fifo_7_mux; - reg [ 35: 0] fifo_8; - wire fifo_8_enable; - wire [ 35: 0] fifo_8_mux; - reg [ 35: 0] fifo_9; - wire fifo_9_enable; - wire [ 35: 0] fifo_9_mux; - wire [ 35: 0] fifo_read_mux; - reg [ 4: 0] fifocount /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 4: 0] fifocount_inc_fifocount; - wire [ 35: 0] fifohead; - reg [ 3: 0] fiforp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg [ 3: 0] fifowp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 3: 0] fifowp1; - wire [ 3: 0] fifowp2; - wire [ 3: 0] fifowp_inc_fifowp; - wire free2; - wire free3; - wire itm_valid; - reg ovf_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 35: 0] ovr_pending_atm; - wire [ 35: 0] ovr_pending_dtm; - wire [ 1: 0] tm_count; - wire tm_count_ge1; - wire tm_count_ge2; - wire tm_count_ge3; - wire trc_this; - wire [ 35: 0] tw; - assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme; - assign itm_valid = |itm[35 : 32]; - assign atm_valid = |atm[35 : 32] & trc_this; - assign dtm_valid = |dtm[35 : 32] & trc_this; - assign free2 = ~fifocount[4]; - assign free3 = ~fifocount[4] & ~&fifocount[3 : 0]; - assign empty = ~|fifocount; - assign fifowp1 = fifowp + 1; - assign fifowp2 = fifowp + 2; - //nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count, which is an e_instance - nios_system_nios2_processor_nios2_oci_compute_tm_count nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count - ( - .atm_valid (atm_valid), - .compute_tm_count (compute_tm_count_tm_count), - .dtm_valid (dtm_valid), - .itm_valid (itm_valid) - ); - - assign tm_count = compute_tm_count_tm_count; - //nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp, which is an e_instance - nios_system_nios2_processor_nios2_oci_fifowp_inc nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp - ( - .fifowp_inc (fifowp_inc_fifowp), - .free2 (free2), - .free3 (free3), - .tm_count (tm_count) - ); - - //nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount, which is an e_instance - nios_system_nios2_processor_nios2_oci_fifocount_inc nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount - ( - .empty (empty), - .fifocount_inc (fifocount_inc_fifocount), - .free2 (free2), - .free3 (free3), - .tm_count (tm_count) - ); - - //the_nios_system_nios2_processor_oci_test_bench, which is an e_instance - nios_system_nios2_processor_oci_test_bench the_nios_system_nios2_processor_oci_test_bench - ( - .dct_buffer (dct_buffer), - .dct_count (dct_count), - .test_ending (test_ending), - .test_has_ended (test_has_ended) - ); - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - fiforp <= 0; - fifowp <= 0; - fifocount <= 0; - ovf_pending <= 1; - end - else - begin - fifowp <= fifowp + fifowp_inc_fifowp; - fifocount <= fifocount + fifocount_inc_fifocount; - if (~empty) - fiforp <= fiforp + 1; - if (~trc_this || (~free2 & tm_count[1]) || (~free3 & (&tm_count))) - ovf_pending <= 1; - else if (atm_valid | dtm_valid) - ovf_pending <= 0; - end - end - - - assign fifohead = fifo_read_mux; - assign tw = 0 ? { (empty ? 4'h0 : fifohead[35 : 32]), fifohead[31 : 0]} : itm; - assign fifo_0_enable = ((fifowp == 4'd0) && tm_count_ge1) || (free2 && (fifowp1== 4'd0) && tm_count_ge2) ||(free3 && (fifowp2== 4'd0) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_0 <= 0; - else if (fifo_0_enable) - fifo_0 <= fifo_0_mux; - end - - - assign fifo_0_mux = (((fifowp == 4'd0) && itm_valid))? itm : - (((fifowp == 4'd0) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd0) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd0) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd0) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd0) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_1_enable = ((fifowp == 4'd1) && tm_count_ge1) || (free2 && (fifowp1== 4'd1) && tm_count_ge2) ||(free3 && (fifowp2== 4'd1) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_1 <= 0; - else if (fifo_1_enable) - fifo_1 <= fifo_1_mux; - end - - - assign fifo_1_mux = (((fifowp == 4'd1) && itm_valid))? itm : - (((fifowp == 4'd1) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd1) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd1) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd1) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd1) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_2_enable = ((fifowp == 4'd2) && tm_count_ge1) || (free2 && (fifowp1== 4'd2) && tm_count_ge2) ||(free3 && (fifowp2== 4'd2) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_2 <= 0; - else if (fifo_2_enable) - fifo_2 <= fifo_2_mux; - end - - - assign fifo_2_mux = (((fifowp == 4'd2) && itm_valid))? itm : - (((fifowp == 4'd2) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd2) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd2) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd2) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd2) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_3_enable = ((fifowp == 4'd3) && tm_count_ge1) || (free2 && (fifowp1== 4'd3) && tm_count_ge2) ||(free3 && (fifowp2== 4'd3) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_3 <= 0; - else if (fifo_3_enable) - fifo_3 <= fifo_3_mux; - end - - - assign fifo_3_mux = (((fifowp == 4'd3) && itm_valid))? itm : - (((fifowp == 4'd3) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd3) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd3) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd3) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd3) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_4_enable = ((fifowp == 4'd4) && tm_count_ge1) || (free2 && (fifowp1== 4'd4) && tm_count_ge2) ||(free3 && (fifowp2== 4'd4) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_4 <= 0; - else if (fifo_4_enable) - fifo_4 <= fifo_4_mux; - end - - - assign fifo_4_mux = (((fifowp == 4'd4) && itm_valid))? itm : - (((fifowp == 4'd4) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd4) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd4) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd4) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd4) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_5_enable = ((fifowp == 4'd5) && tm_count_ge1) || (free2 && (fifowp1== 4'd5) && tm_count_ge2) ||(free3 && (fifowp2== 4'd5) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_5 <= 0; - else if (fifo_5_enable) - fifo_5 <= fifo_5_mux; - end - - - assign fifo_5_mux = (((fifowp == 4'd5) && itm_valid))? itm : - (((fifowp == 4'd5) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd5) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd5) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd5) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd5) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_6_enable = ((fifowp == 4'd6) && tm_count_ge1) || (free2 && (fifowp1== 4'd6) && tm_count_ge2) ||(free3 && (fifowp2== 4'd6) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_6 <= 0; - else if (fifo_6_enable) - fifo_6 <= fifo_6_mux; - end - - - assign fifo_6_mux = (((fifowp == 4'd6) && itm_valid))? itm : - (((fifowp == 4'd6) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd6) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd6) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd6) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd6) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_7_enable = ((fifowp == 4'd7) && tm_count_ge1) || (free2 && (fifowp1== 4'd7) && tm_count_ge2) ||(free3 && (fifowp2== 4'd7) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_7 <= 0; - else if (fifo_7_enable) - fifo_7 <= fifo_7_mux; - end - - - assign fifo_7_mux = (((fifowp == 4'd7) && itm_valid))? itm : - (((fifowp == 4'd7) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd7) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd7) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd7) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd7) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_8_enable = ((fifowp == 4'd8) && tm_count_ge1) || (free2 && (fifowp1== 4'd8) && tm_count_ge2) ||(free3 && (fifowp2== 4'd8) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_8 <= 0; - else if (fifo_8_enable) - fifo_8 <= fifo_8_mux; - end - - - assign fifo_8_mux = (((fifowp == 4'd8) && itm_valid))? itm : - (((fifowp == 4'd8) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd8) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd8) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd8) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd8) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_9_enable = ((fifowp == 4'd9) && tm_count_ge1) || (free2 && (fifowp1== 4'd9) && tm_count_ge2) ||(free3 && (fifowp2== 4'd9) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_9 <= 0; - else if (fifo_9_enable) - fifo_9 <= fifo_9_mux; - end - - - assign fifo_9_mux = (((fifowp == 4'd9) && itm_valid))? itm : - (((fifowp == 4'd9) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd9) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd9) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd9) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd9) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_10_enable = ((fifowp == 4'd10) && tm_count_ge1) || (free2 && (fifowp1== 4'd10) && tm_count_ge2) ||(free3 && (fifowp2== 4'd10) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_10 <= 0; - else if (fifo_10_enable) - fifo_10 <= fifo_10_mux; - end - - - assign fifo_10_mux = (((fifowp == 4'd10) && itm_valid))? itm : - (((fifowp == 4'd10) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd10) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd10) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd10) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd10) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_11_enable = ((fifowp == 4'd11) && tm_count_ge1) || (free2 && (fifowp1== 4'd11) && tm_count_ge2) ||(free3 && (fifowp2== 4'd11) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_11 <= 0; - else if (fifo_11_enable) - fifo_11 <= fifo_11_mux; - end - - - assign fifo_11_mux = (((fifowp == 4'd11) && itm_valid))? itm : - (((fifowp == 4'd11) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd11) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd11) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd11) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd11) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_12_enable = ((fifowp == 4'd12) && tm_count_ge1) || (free2 && (fifowp1== 4'd12) && tm_count_ge2) ||(free3 && (fifowp2== 4'd12) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_12 <= 0; - else if (fifo_12_enable) - fifo_12 <= fifo_12_mux; - end - - - assign fifo_12_mux = (((fifowp == 4'd12) && itm_valid))? itm : - (((fifowp == 4'd12) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd12) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd12) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd12) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd12) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_13_enable = ((fifowp == 4'd13) && tm_count_ge1) || (free2 && (fifowp1== 4'd13) && tm_count_ge2) ||(free3 && (fifowp2== 4'd13) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_13 <= 0; - else if (fifo_13_enable) - fifo_13 <= fifo_13_mux; - end - - - assign fifo_13_mux = (((fifowp == 4'd13) && itm_valid))? itm : - (((fifowp == 4'd13) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd13) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd13) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd13) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd13) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_14_enable = ((fifowp == 4'd14) && tm_count_ge1) || (free2 && (fifowp1== 4'd14) && tm_count_ge2) ||(free3 && (fifowp2== 4'd14) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_14 <= 0; - else if (fifo_14_enable) - fifo_14 <= fifo_14_mux; - end - - - assign fifo_14_mux = (((fifowp == 4'd14) && itm_valid))? itm : - (((fifowp == 4'd14) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd14) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd14) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd14) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd14) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_15_enable = ((fifowp == 4'd15) && tm_count_ge1) || (free2 && (fifowp1== 4'd15) && tm_count_ge2) ||(free3 && (fifowp2== 4'd15) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_15 <= 0; - else if (fifo_15_enable) - fifo_15 <= fifo_15_mux; - end - - - assign fifo_15_mux = (((fifowp == 4'd15) && itm_valid))? itm : - (((fifowp == 4'd15) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd15) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd15) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd15) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd15) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign tm_count_ge1 = |tm_count; - assign tm_count_ge2 = tm_count[1]; - assign tm_count_ge3 = &tm_count; - assign ovr_pending_atm = {ovf_pending, atm[34 : 0]}; - assign ovr_pending_dtm = {ovf_pending, dtm[34 : 0]}; - assign fifo_read_mux = (fiforp == 4'd0)? fifo_0 : - (fiforp == 4'd1)? fifo_1 : - (fiforp == 4'd2)? fifo_2 : - (fiforp == 4'd3)? fifo_3 : - (fiforp == 4'd4)? fifo_4 : - (fiforp == 4'd5)? fifo_5 : - (fiforp == 4'd6)? fifo_6 : - (fiforp == 4'd7)? fifo_7 : - (fiforp == 4'd8)? fifo_8 : - (fiforp == 4'd9)? fifo_9 : - (fiforp == 4'd10)? fifo_10 : - (fiforp == 4'd11)? fifo_11 : - (fiforp == 4'd12)? fifo_12 : - (fiforp == 4'd13)? fifo_13 : - (fiforp == 4'd14)? fifo_14 : - fifo_15; - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_pib ( - // inputs: - clk, - clkx2, - jrst_n, - tw, - - // outputs: - tr_clk, - tr_data - ) -; - - output tr_clk; - output [ 17: 0] tr_data; - input clk; - input clkx2; - input jrst_n; - input [ 35: 0] tw; - - wire phase; - wire tr_clk; - reg tr_clk_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 17: 0] tr_data; - reg [ 17: 0] tr_data_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg x1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg x2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - assign phase = x1^x2; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - x1 <= 0; - else - x1 <= ~x1; - end - - - always @(posedge clkx2 or negedge jrst_n) - begin - if (jrst_n == 0) - begin - x2 <= 0; - tr_clk_reg <= 0; - tr_data_reg <= 0; - end - else - begin - x2 <= x1; - tr_clk_reg <= ~phase; - tr_data_reg <= phase ? tw[17 : 0] : tw[35 : 18]; - end - end - - - assign tr_clk = 0 ? tr_clk_reg : 0; - assign tr_data = 0 ? tr_data_reg : 0; - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_im ( - // inputs: - clk, - jdo, - jrst_n, - reset_n, - take_action_tracectrl, - take_action_tracemem_a, - take_action_tracemem_b, - take_no_action_tracemem_a, - trc_ctrl, - tw, - - // outputs: - tracemem_on, - tracemem_trcdata, - tracemem_tw, - trc_enb, - trc_im_addr, - trc_wrap, - xbrk_wrap_traceoff - ) -; - - output tracemem_on; - output [ 35: 0] tracemem_trcdata; - output tracemem_tw; - output trc_enb; - output [ 6: 0] trc_im_addr; - output trc_wrap; - output xbrk_wrap_traceoff; - input clk; - input [ 37: 0] jdo; - input jrst_n; - input reset_n; - input take_action_tracectrl; - input take_action_tracemem_a; - input take_action_tracemem_b; - input take_no_action_tracemem_a; - input [ 15: 0] trc_ctrl; - input [ 35: 0] tw; - - wire tracemem_on; - wire [ 35: 0] tracemem_trcdata; - wire tracemem_tw; - wire trc_enb; - reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire [ 35: 0] trc_im_data; - reg [ 16: 0] trc_jtag_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; - wire trc_on_chip; - reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire tw_valid; - wire xbrk_wrap_traceoff; - assign trc_im_data = tw; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - trc_im_addr <= 0; - trc_wrap <= 0; - end - else if (!0) - begin - trc_im_addr <= 0; - trc_wrap <= 0; - end - else if (take_action_tracectrl && - (jdo[4] | jdo[3])) - begin - if (jdo[4]) - trc_im_addr <= 0; - if (jdo[3]) - trc_wrap <= 0; - end - else if (trc_enb & trc_on_chip & tw_valid) - begin - trc_im_addr <= trc_im_addr+1; - if (&trc_im_addr) - trc_wrap <= 1; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - trc_jtag_addr <= 0; - else if (take_action_tracemem_a || - take_no_action_tracemem_a || - take_action_tracemem_b) - trc_jtag_addr <= take_action_tracemem_a ? - jdo[35 : 19] : - trc_jtag_addr + 1; - - end - - - assign trc_enb = trc_ctrl[0]; - assign trc_on_chip = ~trc_ctrl[8]; - assign tw_valid = |trc_im_data[35 : 32]; - assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap; - assign tracemem_tw = trc_wrap; - assign tracemem_on = trc_enb; - assign tracemem_trcdata = 0; - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_performance_monitors -; - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci ( - // inputs: - D_valid, - E_st_data, - E_valid, - F_pc, - address_nxt, - av_ld_data_aligned_filtered, - byteenable_nxt, - clk, - d_address, - d_read, - d_waitrequest, - d_write, - debugaccess_nxt, - hbreak_enabled, - read_nxt, - reset, - reset_n, - test_ending, - test_has_ended, - write_nxt, - writedata_nxt, - - // outputs: - jtag_debug_module_debugaccess_to_roms, - oci_hbreak_req, - oci_ienable, - oci_single_step_mode, - readdata, - resetrequest, - waitrequest - ) -; - - output jtag_debug_module_debugaccess_to_roms; - output oci_hbreak_req; - output [ 31: 0] oci_ienable; - output oci_single_step_mode; - output [ 31: 0] readdata; - output resetrequest; - output waitrequest; - input D_valid; - input [ 31: 0] E_st_data; - input E_valid; - input [ 16: 0] F_pc; - input [ 8: 0] address_nxt; - input [ 31: 0] av_ld_data_aligned_filtered; - input [ 3: 0] byteenable_nxt; - input clk; - input [ 18: 0] d_address; - input d_read; - input d_waitrequest; - input d_write; - input debugaccess_nxt; - input hbreak_enabled; - input read_nxt; - input reset; - input reset_n; - input test_ending; - input test_has_ended; - input write_nxt; - input [ 31: 0] writedata_nxt; - - wire [ 31: 0] MonDReg; - reg [ 8: 0] address; - wire [ 35: 0] atm; - wire [ 31: 0] break_readreg; - reg [ 3: 0] byteenable; - wire clkx2; - wire [ 18: 0] cpu_d_address; - wire cpu_d_read; - wire [ 31: 0] cpu_d_readdata; - wire cpu_d_wait; - wire cpu_d_write; - wire [ 31: 0] cpu_d_writedata; - wire dbrk_break; - wire dbrk_goto0; - wire dbrk_goto1; - wire dbrk_hit0_latch; - wire dbrk_hit1_latch; - wire dbrk_hit2_latch; - wire dbrk_hit3_latch; - wire dbrk_traceme; - wire dbrk_traceoff; - wire dbrk_traceon; - wire dbrk_trigout; - wire [ 29: 0] dct_buffer; - wire [ 3: 0] dct_count; - reg debugaccess; - wire debugack; - wire debugreq; - wire [ 35: 0] dtm; - wire dummy_sink; - wire [ 35: 0] itm; - wire [ 37: 0] jdo; - wire jrst_n; - wire jtag_debug_module_debugaccess_to_roms; - wire monitor_error; - wire monitor_go; - wire monitor_ready; - wire oci_hbreak_req; - wire [ 31: 0] oci_ienable; - wire [ 31: 0] oci_reg_readdata; - wire oci_single_step_mode; - wire [ 31: 0] ociram_readdata; - wire ocireg_ers; - wire ocireg_mrs; - reg read; - reg [ 31: 0] readdata; - wire resetlatch; - wire resetrequest; - wire st_ready_test_idle; - wire take_action_break_a; - wire take_action_break_b; - wire take_action_break_c; - wire take_action_ocimem_a; - wire take_action_ocimem_b; - wire take_action_ocireg; - wire take_action_tracectrl; - wire take_action_tracemem_a; - wire take_action_tracemem_b; - wire take_no_action_break_a; - wire take_no_action_break_b; - wire take_no_action_break_c; - wire take_no_action_ocimem_a; - wire take_no_action_tracemem_a; - wire tr_clk; - wire [ 17: 0] tr_data; - wire tracemem_on; - wire [ 35: 0] tracemem_trcdata; - wire tracemem_tw; - wire [ 15: 0] trc_ctrl; - wire trc_enb; - wire [ 6: 0] trc_im_addr; - wire trc_on; - wire trc_wrap; - wire trigbrktype; - wire trigger_state_0; - wire trigger_state_1; - wire trigout; - wire [ 35: 0] tw; - wire waitrequest; - reg write; - reg [ 31: 0] writedata; - wire xbrk_break; - wire [ 7: 0] xbrk_ctrl0; - wire [ 7: 0] xbrk_ctrl1; - wire [ 7: 0] xbrk_ctrl2; - wire [ 7: 0] xbrk_ctrl3; - wire xbrk_goto0; - wire xbrk_goto1; - wire xbrk_traceoff; - wire xbrk_traceon; - wire xbrk_trigout; - wire xbrk_wrap_traceoff; - nios_system_nios2_processor_nios2_oci_debug the_nios_system_nios2_processor_nios2_oci_debug - ( - .clk (clk), - .dbrk_break (dbrk_break), - .debugack (debugack), - .debugreq (debugreq), - .hbreak_enabled (hbreak_enabled), - .jdo (jdo), - .jrst_n (jrst_n), - .monitor_error (monitor_error), - .monitor_go (monitor_go), - .monitor_ready (monitor_ready), - .oci_hbreak_req (oci_hbreak_req), - .ocireg_ers (ocireg_ers), - .ocireg_mrs (ocireg_mrs), - .reset (reset), - .resetlatch (resetlatch), - .resetrequest (resetrequest), - .st_ready_test_idle (st_ready_test_idle), - .take_action_ocimem_a (take_action_ocimem_a), - .take_action_ocireg (take_action_ocireg), - .xbrk_break (xbrk_break) - ); - - nios_system_nios2_processor_nios2_ocimem the_nios_system_nios2_processor_nios2_ocimem - ( - .MonDReg (MonDReg), - .address (address), - .byteenable (byteenable), - .clk (clk), - .debugaccess (debugaccess), - .jdo (jdo), - .jrst_n (jrst_n), - .ociram_readdata (ociram_readdata), - .read (read), - .take_action_ocimem_a (take_action_ocimem_a), - .take_action_ocimem_b (take_action_ocimem_b), - .take_no_action_ocimem_a (take_no_action_ocimem_a), - .waitrequest (waitrequest), - .write (write), - .writedata (writedata) - ); - - nios_system_nios2_processor_nios2_avalon_reg the_nios_system_nios2_processor_nios2_avalon_reg - ( - .address (address), - .clk (clk), - .debugaccess (debugaccess), - .monitor_error (monitor_error), - .monitor_go (monitor_go), - .monitor_ready (monitor_ready), - .oci_ienable (oci_ienable), - .oci_reg_readdata (oci_reg_readdata), - .oci_single_step_mode (oci_single_step_mode), - .ocireg_ers (ocireg_ers), - .ocireg_mrs (ocireg_mrs), - .reset_n (reset_n), - .take_action_ocireg (take_action_ocireg), - .write (write), - .writedata (writedata) - ); - - nios_system_nios2_processor_nios2_oci_break the_nios_system_nios2_processor_nios2_oci_break - ( - .break_readreg (break_readreg), - .clk (clk), - .dbrk_break (dbrk_break), - .dbrk_goto0 (dbrk_goto0), - .dbrk_goto1 (dbrk_goto1), - .dbrk_hit0_latch (dbrk_hit0_latch), - .dbrk_hit1_latch (dbrk_hit1_latch), - .dbrk_hit2_latch (dbrk_hit2_latch), - .dbrk_hit3_latch (dbrk_hit3_latch), - .jdo (jdo), - .jrst_n (jrst_n), - .reset_n (reset_n), - .take_action_break_a (take_action_break_a), - .take_action_break_b (take_action_break_b), - .take_action_break_c (take_action_break_c), - .take_no_action_break_a (take_no_action_break_a), - .take_no_action_break_b (take_no_action_break_b), - .take_no_action_break_c (take_no_action_break_c), - .trigbrktype (trigbrktype), - .trigger_state_0 (trigger_state_0), - .trigger_state_1 (trigger_state_1), - .xbrk_ctrl0 (xbrk_ctrl0), - .xbrk_ctrl1 (xbrk_ctrl1), - .xbrk_ctrl2 (xbrk_ctrl2), - .xbrk_ctrl3 (xbrk_ctrl3), - .xbrk_goto0 (xbrk_goto0), - .xbrk_goto1 (xbrk_goto1) - ); - - nios_system_nios2_processor_nios2_oci_xbrk the_nios_system_nios2_processor_nios2_oci_xbrk - ( - .D_valid (D_valid), - .E_valid (E_valid), - .F_pc (F_pc), - .clk (clk), - .reset_n (reset_n), - .trigger_state_0 (trigger_state_0), - .trigger_state_1 (trigger_state_1), - .xbrk_break (xbrk_break), - .xbrk_ctrl0 (xbrk_ctrl0), - .xbrk_ctrl1 (xbrk_ctrl1), - .xbrk_ctrl2 (xbrk_ctrl2), - .xbrk_ctrl3 (xbrk_ctrl3), - .xbrk_goto0 (xbrk_goto0), - .xbrk_goto1 (xbrk_goto1), - .xbrk_traceoff (xbrk_traceoff), - .xbrk_traceon (xbrk_traceon), - .xbrk_trigout (xbrk_trigout) - ); - - nios_system_nios2_processor_nios2_oci_dbrk the_nios_system_nios2_processor_nios2_oci_dbrk - ( - .E_st_data (E_st_data), - .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), - .clk (clk), - .cpu_d_address (cpu_d_address), - .cpu_d_read (cpu_d_read), - .cpu_d_readdata (cpu_d_readdata), - .cpu_d_wait (cpu_d_wait), - .cpu_d_write (cpu_d_write), - .cpu_d_writedata (cpu_d_writedata), - .d_address (d_address), - .d_read (d_read), - .d_waitrequest (d_waitrequest), - .d_write (d_write), - .dbrk_break (dbrk_break), - .dbrk_goto0 (dbrk_goto0), - .dbrk_goto1 (dbrk_goto1), - .dbrk_traceme (dbrk_traceme), - .dbrk_traceoff (dbrk_traceoff), - .dbrk_traceon (dbrk_traceon), - .dbrk_trigout (dbrk_trigout), - .debugack (debugack), - .reset_n (reset_n) - ); - - nios_system_nios2_processor_nios2_oci_itrace the_nios_system_nios2_processor_nios2_oci_itrace - ( - .clk (clk), - .dbrk_traceoff (dbrk_traceoff), - .dbrk_traceon (dbrk_traceon), - .dct_buffer (dct_buffer), - .dct_count (dct_count), - .itm (itm), - .jdo (jdo), - .jrst_n (jrst_n), - .take_action_tracectrl (take_action_tracectrl), - .trc_ctrl (trc_ctrl), - .trc_enb (trc_enb), - .trc_on (trc_on), - .xbrk_traceoff (xbrk_traceoff), - .xbrk_traceon (xbrk_traceon), - .xbrk_wrap_traceoff (xbrk_wrap_traceoff) - ); - - nios_system_nios2_processor_nios2_oci_dtrace the_nios_system_nios2_processor_nios2_oci_dtrace - ( - .atm (atm), - .clk (clk), - .cpu_d_address (cpu_d_address), - .cpu_d_read (cpu_d_read), - .cpu_d_readdata (cpu_d_readdata), - .cpu_d_wait (cpu_d_wait), - .cpu_d_write (cpu_d_write), - .cpu_d_writedata (cpu_d_writedata), - .dtm (dtm), - .jrst_n (jrst_n), - .trc_ctrl (trc_ctrl) - ); - - nios_system_nios2_processor_nios2_oci_fifo the_nios_system_nios2_processor_nios2_oci_fifo - ( - .atm (atm), - .clk (clk), - .dbrk_traceme (dbrk_traceme), - .dbrk_traceoff (dbrk_traceoff), - .dbrk_traceon (dbrk_traceon), - .dct_buffer (dct_buffer), - .dct_count (dct_count), - .dtm (dtm), - .itm (itm), - .jrst_n (jrst_n), - .reset_n (reset_n), - .test_ending (test_ending), - .test_has_ended (test_has_ended), - .trc_on (trc_on), - .tw (tw) - ); - - nios_system_nios2_processor_nios2_oci_pib the_nios_system_nios2_processor_nios2_oci_pib - ( - .clk (clk), - .clkx2 (clkx2), - .jrst_n (jrst_n), - .tr_clk (tr_clk), - .tr_data (tr_data), - .tw (tw) - ); - - nios_system_nios2_processor_nios2_oci_im the_nios_system_nios2_processor_nios2_oci_im - ( - .clk (clk), - .jdo (jdo), - .jrst_n (jrst_n), - .reset_n (reset_n), - .take_action_tracectrl (take_action_tracectrl), - .take_action_tracemem_a (take_action_tracemem_a), - .take_action_tracemem_b (take_action_tracemem_b), - .take_no_action_tracemem_a (take_no_action_tracemem_a), - .tracemem_on (tracemem_on), - .tracemem_trcdata (tracemem_trcdata), - .tracemem_tw (tracemem_tw), - .trc_ctrl (trc_ctrl), - .trc_enb (trc_enb), - .trc_im_addr (trc_im_addr), - .trc_wrap (trc_wrap), - .tw (tw), - .xbrk_wrap_traceoff (xbrk_wrap_traceoff) - ); - - assign trigout = dbrk_trigout | xbrk_trigout; - assign jtag_debug_module_debugaccess_to_roms = debugack; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - address <= 0; - else - address <= address_nxt; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - byteenable <= 0; - else - byteenable <= byteenable_nxt; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - writedata <= 0; - else - writedata <= writedata_nxt; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - debugaccess <= 0; - else - debugaccess <= debugaccess_nxt; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - read <= 0; - else - read <= read ? waitrequest : read_nxt; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - write <= 0; - else - write <= write ? waitrequest : write_nxt; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - readdata <= 0; - else - readdata <= address[8] ? oci_reg_readdata : ociram_readdata; - end - - - nios_system_nios2_processor_jtag_debug_module_wrapper the_nios_system_nios2_processor_jtag_debug_module_wrapper - ( - .MonDReg (MonDReg), - .break_readreg (break_readreg), - .clk (clk), - .dbrk_hit0_latch (dbrk_hit0_latch), - .dbrk_hit1_latch (dbrk_hit1_latch), - .dbrk_hit2_latch (dbrk_hit2_latch), - .dbrk_hit3_latch (dbrk_hit3_latch), - .debugack (debugack), - .jdo (jdo), - .jrst_n (jrst_n), - .monitor_error (monitor_error), - .monitor_ready (monitor_ready), - .reset_n (reset_n), - .resetlatch (resetlatch), - .st_ready_test_idle (st_ready_test_idle), - .take_action_break_a (take_action_break_a), - .take_action_break_b (take_action_break_b), - .take_action_break_c (take_action_break_c), - .take_action_ocimem_a (take_action_ocimem_a), - .take_action_ocimem_b (take_action_ocimem_b), - .take_action_tracectrl (take_action_tracectrl), - .take_action_tracemem_a (take_action_tracemem_a), - .take_action_tracemem_b (take_action_tracemem_b), - .take_no_action_break_a (take_no_action_break_a), - .take_no_action_break_b (take_no_action_break_b), - .take_no_action_break_c (take_no_action_break_c), - .take_no_action_ocimem_a (take_no_action_ocimem_a), - .take_no_action_tracemem_a (take_no_action_tracemem_a), - .tracemem_on (tracemem_on), - .tracemem_trcdata (tracemem_trcdata), - .tracemem_tw (tracemem_tw), - .trc_im_addr (trc_im_addr), - .trc_on (trc_on), - .trc_wrap (trc_wrap), - .trigbrktype (trigbrktype), - .trigger_state_1 (trigger_state_1) - ); - - //dummy sink, which is an e_mux - assign dummy_sink = tr_clk | - tr_data | - trigout | - debugack; - - assign debugreq = 0; - assign clkx2 = 0; - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor ( - // inputs: - clk, - d_irq, - d_readdata, - d_waitrequest, - i_readdata, - i_waitrequest, - jtag_debug_module_address, - jtag_debug_module_byteenable, - jtag_debug_module_debugaccess, - jtag_debug_module_read, - jtag_debug_module_write, - jtag_debug_module_writedata, - reset_n, - - // outputs: - d_address, - d_byteenable, - d_read, - d_write, - d_writedata, - i_address, - i_read, - jtag_debug_module_debugaccess_to_roms, - jtag_debug_module_readdata, - jtag_debug_module_resetrequest, - jtag_debug_module_waitrequest, - no_ci_readra - ) -; - - output [ 18: 0] d_address; - output [ 3: 0] d_byteenable; - output d_read; - output d_write; - output [ 31: 0] d_writedata; - output [ 18: 0] i_address; - output i_read; - output jtag_debug_module_debugaccess_to_roms; - output [ 31: 0] jtag_debug_module_readdata; - output jtag_debug_module_resetrequest; - output jtag_debug_module_waitrequest; - output no_ci_readra; - input clk; - input [ 31: 0] d_irq; - input [ 31: 0] d_readdata; - input d_waitrequest; - input [ 31: 0] i_readdata; - input i_waitrequest; - input [ 8: 0] jtag_debug_module_address; - input [ 3: 0] jtag_debug_module_byteenable; - input jtag_debug_module_debugaccess; - input jtag_debug_module_read; - input jtag_debug_module_write; - input [ 31: 0] jtag_debug_module_writedata; - input reset_n; - - wire [ 1: 0] D_compare_op; - wire D_ctrl_alu_force_xor; - wire D_ctrl_alu_signed_comparison; - wire D_ctrl_alu_subtract; - wire D_ctrl_b_is_dst; - wire D_ctrl_br; - wire D_ctrl_br_cmp; - wire D_ctrl_br_uncond; - wire D_ctrl_break; - wire D_ctrl_crst; - wire D_ctrl_custom; - wire D_ctrl_custom_multi; - wire D_ctrl_exception; - wire D_ctrl_force_src2_zero; - wire D_ctrl_hi_imm16; - wire D_ctrl_ignore_dst; - wire D_ctrl_implicit_dst_eretaddr; - wire D_ctrl_implicit_dst_retaddr; - wire D_ctrl_jmp_direct; - wire D_ctrl_jmp_indirect; - wire D_ctrl_ld; - wire D_ctrl_ld_io; - wire D_ctrl_ld_non_io; - wire D_ctrl_ld_signed; - wire D_ctrl_logic; - wire D_ctrl_rdctl_inst; - wire D_ctrl_retaddr; - wire D_ctrl_rot_right; - wire D_ctrl_shift_logical; - wire D_ctrl_shift_right_arith; - wire D_ctrl_shift_rot; - wire D_ctrl_shift_rot_right; - wire D_ctrl_src2_choose_imm; - wire D_ctrl_st; - wire D_ctrl_uncond_cti_non_br; - wire D_ctrl_unsigned_lo_imm16; - wire D_ctrl_wrctl_inst; - wire [ 4: 0] D_dst_regnum; - wire [ 55: 0] D_inst; - reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; - wire [ 4: 0] D_iw_a; - wire [ 4: 0] D_iw_b; - wire [ 4: 0] D_iw_c; - wire [ 2: 0] D_iw_control_regnum; - wire [ 7: 0] D_iw_custom_n; - wire D_iw_custom_readra; - wire D_iw_custom_readrb; - wire D_iw_custom_writerc; - wire [ 15: 0] D_iw_imm16; - wire [ 25: 0] D_iw_imm26; - wire [ 4: 0] D_iw_imm5; - wire [ 1: 0] D_iw_memsz; - wire [ 5: 0] D_iw_op; - wire [ 5: 0] D_iw_opx; - wire [ 4: 0] D_iw_shift_imm5; - wire [ 4: 0] D_iw_trap_break_imm5; - wire [ 16: 0] D_jmp_direct_target_waddr; - wire [ 1: 0] D_logic_op; - wire [ 1: 0] D_logic_op_raw; - wire D_mem16; - wire D_mem32; - wire D_mem8; - wire D_op_add; - wire D_op_addi; - wire D_op_and; - wire D_op_andhi; - wire D_op_andi; - wire D_op_beq; - wire D_op_bge; - wire D_op_bgeu; - wire D_op_blt; - wire D_op_bltu; - wire D_op_bne; - wire D_op_br; - wire D_op_break; - wire D_op_bret; - wire D_op_call; - wire D_op_callr; - wire D_op_cmpeq; - wire D_op_cmpeqi; - wire D_op_cmpge; - wire D_op_cmpgei; - wire D_op_cmpgeu; - wire D_op_cmpgeui; - wire D_op_cmplt; - wire D_op_cmplti; - wire D_op_cmpltu; - wire D_op_cmpltui; - wire D_op_cmpne; - wire D_op_cmpnei; - wire D_op_crst; - wire D_op_custom; - wire D_op_div; - wire D_op_divu; - wire D_op_eret; - wire D_op_flushd; - wire D_op_flushda; - wire D_op_flushi; - wire D_op_flushp; - wire D_op_hbreak; - wire D_op_initd; - wire D_op_initda; - wire D_op_initi; - wire D_op_intr; - wire D_op_jmp; - wire D_op_jmpi; - wire D_op_ldb; - wire D_op_ldbio; - wire D_op_ldbu; - wire D_op_ldbuio; - wire D_op_ldh; - wire D_op_ldhio; - wire D_op_ldhu; - wire D_op_ldhuio; - wire D_op_ldl; - wire D_op_ldw; - wire D_op_ldwio; - wire D_op_mul; - wire D_op_muli; - wire D_op_mulxss; - wire D_op_mulxsu; - wire D_op_mulxuu; - wire D_op_nextpc; - wire D_op_nor; - wire D_op_opx; - wire D_op_or; - wire D_op_orhi; - wire D_op_ori; - wire D_op_rdctl; - wire D_op_rdprs; - wire D_op_ret; - wire D_op_rol; - wire D_op_roli; - wire D_op_ror; - wire D_op_rsv02; - wire D_op_rsv09; - wire D_op_rsv10; - wire D_op_rsv17; - wire D_op_rsv18; - wire D_op_rsv25; - wire D_op_rsv26; - wire D_op_rsv33; - wire D_op_rsv34; - wire D_op_rsv41; - wire D_op_rsv42; - wire D_op_rsv49; - wire D_op_rsv57; - wire D_op_rsv61; - wire D_op_rsv62; - wire D_op_rsv63; - wire D_op_rsvx00; - wire D_op_rsvx10; - wire D_op_rsvx15; - wire D_op_rsvx17; - wire D_op_rsvx21; - wire D_op_rsvx25; - wire D_op_rsvx33; - wire D_op_rsvx34; - wire D_op_rsvx35; - wire D_op_rsvx42; - wire D_op_rsvx43; - wire D_op_rsvx44; - wire D_op_rsvx47; - wire D_op_rsvx50; - wire D_op_rsvx51; - wire D_op_rsvx55; - wire D_op_rsvx56; - wire D_op_rsvx60; - wire D_op_rsvx63; - wire D_op_sll; - wire D_op_slli; - wire D_op_sra; - wire D_op_srai; - wire D_op_srl; - wire D_op_srli; - wire D_op_stb; - wire D_op_stbio; - wire D_op_stc; - wire D_op_sth; - wire D_op_sthio; - wire D_op_stw; - wire D_op_stwio; - wire D_op_sub; - wire D_op_sync; - wire D_op_trap; - wire D_op_wrctl; - wire D_op_wrprs; - wire D_op_xor; - wire D_op_xorhi; - wire D_op_xori; - reg D_valid; - wire [ 55: 0] D_vinst; - wire D_wr_dst_reg; - wire [ 31: 0] E_alu_result; - reg E_alu_sub; - wire [ 32: 0] E_arith_result; - wire [ 31: 0] E_arith_src1; - wire [ 31: 0] E_arith_src2; - wire E_ci_multi_stall; - wire [ 31: 0] E_ci_result; - wire E_cmp_result; - wire [ 31: 0] E_control_rd_data; - wire E_eq; - reg E_invert_arith_src_msb; - wire E_ld_stall; - wire [ 31: 0] E_logic_result; - wire E_logic_result_is_0; - wire E_lt; - wire [ 18: 0] E_mem_baddr; - wire [ 3: 0] E_mem_byte_en; - reg E_new_inst; - reg [ 4: 0] E_shift_rot_cnt; - wire [ 4: 0] E_shift_rot_cnt_nxt; - wire E_shift_rot_done; - wire E_shift_rot_fill_bit; - reg [ 31: 0] E_shift_rot_result; - wire [ 31: 0] E_shift_rot_result_nxt; - wire E_shift_rot_stall; - reg [ 31: 0] E_src1; - reg [ 31: 0] E_src2; - wire [ 31: 0] E_st_data; - wire E_st_stall; - wire E_stall; - reg E_valid; - wire [ 55: 0] E_vinst; - wire E_wrctl_bstatus; - wire E_wrctl_estatus; - wire E_wrctl_ienable; - wire E_wrctl_status; - wire [ 31: 0] F_av_iw; - wire [ 4: 0] F_av_iw_a; - wire [ 4: 0] F_av_iw_b; - wire [ 4: 0] F_av_iw_c; - wire [ 2: 0] F_av_iw_control_regnum; - wire [ 7: 0] F_av_iw_custom_n; - wire F_av_iw_custom_readra; - wire F_av_iw_custom_readrb; - wire F_av_iw_custom_writerc; - wire [ 15: 0] F_av_iw_imm16; - wire [ 25: 0] F_av_iw_imm26; - wire [ 4: 0] F_av_iw_imm5; - wire [ 1: 0] F_av_iw_memsz; - wire [ 5: 0] F_av_iw_op; - wire [ 5: 0] F_av_iw_opx; - wire [ 4: 0] F_av_iw_shift_imm5; - wire [ 4: 0] F_av_iw_trap_break_imm5; - wire F_av_mem16; - wire F_av_mem32; - wire F_av_mem8; - wire [ 55: 0] F_inst; - wire [ 31: 0] F_iw; - wire [ 4: 0] F_iw_a; - wire [ 4: 0] F_iw_b; - wire [ 4: 0] F_iw_c; - wire [ 2: 0] F_iw_control_regnum; - wire [ 7: 0] F_iw_custom_n; - wire F_iw_custom_readra; - wire F_iw_custom_readrb; - wire F_iw_custom_writerc; - wire [ 15: 0] F_iw_imm16; - wire [ 25: 0] F_iw_imm26; - wire [ 4: 0] F_iw_imm5; - wire [ 1: 0] F_iw_memsz; - wire [ 5: 0] F_iw_op; - wire [ 5: 0] F_iw_opx; - wire [ 4: 0] F_iw_shift_imm5; - wire [ 4: 0] F_iw_trap_break_imm5; - wire F_mem16; - wire F_mem32; - wire F_mem8; - wire F_op_add; - wire F_op_addi; - wire F_op_and; - wire F_op_andhi; - wire F_op_andi; - wire F_op_beq; - wire F_op_bge; - wire F_op_bgeu; - wire F_op_blt; - wire F_op_bltu; - wire F_op_bne; - wire F_op_br; - wire F_op_break; - wire F_op_bret; - wire F_op_call; - wire F_op_callr; - wire F_op_cmpeq; - wire F_op_cmpeqi; - wire F_op_cmpge; - wire F_op_cmpgei; - wire F_op_cmpgeu; - wire F_op_cmpgeui; - wire F_op_cmplt; - wire F_op_cmplti; - wire F_op_cmpltu; - wire F_op_cmpltui; - wire F_op_cmpne; - wire F_op_cmpnei; - wire F_op_crst; - wire F_op_custom; - wire F_op_div; - wire F_op_divu; - wire F_op_eret; - wire F_op_flushd; - wire F_op_flushda; - wire F_op_flushi; - wire F_op_flushp; - wire F_op_hbreak; - wire F_op_initd; - wire F_op_initda; - wire F_op_initi; - wire F_op_intr; - wire F_op_jmp; - wire F_op_jmpi; - wire F_op_ldb; - wire F_op_ldbio; - wire F_op_ldbu; - wire F_op_ldbuio; - wire F_op_ldh; - wire F_op_ldhio; - wire F_op_ldhu; - wire F_op_ldhuio; - wire F_op_ldl; - wire F_op_ldw; - wire F_op_ldwio; - wire F_op_mul; - wire F_op_muli; - wire F_op_mulxss; - wire F_op_mulxsu; - wire F_op_mulxuu; - wire F_op_nextpc; - wire F_op_nor; - wire F_op_opx; - wire F_op_or; - wire F_op_orhi; - wire F_op_ori; - wire F_op_rdctl; - wire F_op_rdprs; - wire F_op_ret; - wire F_op_rol; - wire F_op_roli; - wire F_op_ror; - wire F_op_rsv02; - wire F_op_rsv09; - wire F_op_rsv10; - wire F_op_rsv17; - wire F_op_rsv18; - wire F_op_rsv25; - wire F_op_rsv26; - wire F_op_rsv33; - wire F_op_rsv34; - wire F_op_rsv41; - wire F_op_rsv42; - wire F_op_rsv49; - wire F_op_rsv57; - wire F_op_rsv61; - wire F_op_rsv62; - wire F_op_rsv63; - wire F_op_rsvx00; - wire F_op_rsvx10; - wire F_op_rsvx15; - wire F_op_rsvx17; - wire F_op_rsvx21; - wire F_op_rsvx25; - wire F_op_rsvx33; - wire F_op_rsvx34; - wire F_op_rsvx35; - wire F_op_rsvx42; - wire F_op_rsvx43; - wire F_op_rsvx44; - wire F_op_rsvx47; - wire F_op_rsvx50; - wire F_op_rsvx51; - wire F_op_rsvx55; - wire F_op_rsvx56; - wire F_op_rsvx60; - wire F_op_rsvx63; - wire F_op_sll; - wire F_op_slli; - wire F_op_sra; - wire F_op_srai; - wire F_op_srl; - wire F_op_srli; - wire F_op_stb; - wire F_op_stbio; - wire F_op_stc; - wire F_op_sth; - wire F_op_sthio; - wire F_op_stw; - wire F_op_stwio; - wire F_op_sub; - wire F_op_sync; - wire F_op_trap; - wire F_op_wrctl; - wire F_op_wrprs; - wire F_op_xor; - wire F_op_xorhi; - wire F_op_xori; - reg [ 16: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; - wire F_pc_en; - wire [ 16: 0] F_pc_no_crst_nxt; - wire [ 16: 0] F_pc_nxt; - wire [ 16: 0] F_pc_plus_one; - wire [ 1: 0] F_pc_sel_nxt; - wire [ 18: 0] F_pcb; - wire [ 18: 0] F_pcb_nxt; - wire [ 18: 0] F_pcb_plus_four; - wire F_valid; - wire [ 55: 0] F_vinst; - reg [ 1: 0] R_compare_op; - reg R_ctrl_alu_force_xor; - wire R_ctrl_alu_force_xor_nxt; - reg R_ctrl_alu_signed_comparison; - wire R_ctrl_alu_signed_comparison_nxt; - reg R_ctrl_alu_subtract; - wire R_ctrl_alu_subtract_nxt; - reg R_ctrl_b_is_dst; - wire R_ctrl_b_is_dst_nxt; - reg R_ctrl_br; - reg R_ctrl_br_cmp; - wire R_ctrl_br_cmp_nxt; - wire R_ctrl_br_nxt; - reg R_ctrl_br_uncond; - wire R_ctrl_br_uncond_nxt; - reg R_ctrl_break; - wire R_ctrl_break_nxt; - reg R_ctrl_crst; - wire R_ctrl_crst_nxt; - reg R_ctrl_custom; - reg R_ctrl_custom_multi; - wire R_ctrl_custom_multi_nxt; - wire R_ctrl_custom_nxt; - reg R_ctrl_exception; - wire R_ctrl_exception_nxt; - reg R_ctrl_force_src2_zero; - wire R_ctrl_force_src2_zero_nxt; - reg R_ctrl_hi_imm16; - wire R_ctrl_hi_imm16_nxt; - reg R_ctrl_ignore_dst; - wire R_ctrl_ignore_dst_nxt; - reg R_ctrl_implicit_dst_eretaddr; - wire R_ctrl_implicit_dst_eretaddr_nxt; - reg R_ctrl_implicit_dst_retaddr; - wire R_ctrl_implicit_dst_retaddr_nxt; - reg R_ctrl_jmp_direct; - wire R_ctrl_jmp_direct_nxt; - reg R_ctrl_jmp_indirect; - wire R_ctrl_jmp_indirect_nxt; - reg R_ctrl_ld; - reg R_ctrl_ld_io; - wire R_ctrl_ld_io_nxt; - reg R_ctrl_ld_non_io; - wire R_ctrl_ld_non_io_nxt; - wire R_ctrl_ld_nxt; - reg R_ctrl_ld_signed; - wire R_ctrl_ld_signed_nxt; - reg R_ctrl_logic; - wire R_ctrl_logic_nxt; - reg R_ctrl_rdctl_inst; - wire R_ctrl_rdctl_inst_nxt; - reg R_ctrl_retaddr; - wire R_ctrl_retaddr_nxt; - reg R_ctrl_rot_right; - wire R_ctrl_rot_right_nxt; - reg R_ctrl_shift_logical; - wire R_ctrl_shift_logical_nxt; - reg R_ctrl_shift_right_arith; - wire R_ctrl_shift_right_arith_nxt; - reg R_ctrl_shift_rot; - wire R_ctrl_shift_rot_nxt; - reg R_ctrl_shift_rot_right; - wire R_ctrl_shift_rot_right_nxt; - reg R_ctrl_src2_choose_imm; - wire R_ctrl_src2_choose_imm_nxt; - reg R_ctrl_st; - wire R_ctrl_st_nxt; - reg R_ctrl_uncond_cti_non_br; - wire R_ctrl_uncond_cti_non_br_nxt; - reg R_ctrl_unsigned_lo_imm16; - wire R_ctrl_unsigned_lo_imm16_nxt; - reg R_ctrl_wrctl_inst; - wire R_ctrl_wrctl_inst_nxt; - reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; - wire R_en; - reg [ 1: 0] R_logic_op; - wire [ 31: 0] R_rf_a; - wire [ 31: 0] R_rf_b; - wire [ 31: 0] R_src1; - wire [ 31: 0] R_src2; - wire [ 15: 0] R_src2_hi; - wire [ 15: 0] R_src2_lo; - reg R_src2_use_imm; - wire [ 7: 0] R_stb_data; - wire [ 15: 0] R_sth_data; - reg R_valid; - wire [ 55: 0] R_vinst; - reg R_wr_dst_reg; - reg [ 31: 0] W_alu_result; - wire W_br_taken; - reg W_bstatus_reg; - wire W_bstatus_reg_inst_nxt; - wire W_bstatus_reg_nxt; - reg W_cmp_result; - reg [ 31: 0] W_control_rd_data; - reg W_estatus_reg; - wire W_estatus_reg_inst_nxt; - wire W_estatus_reg_nxt; - reg [ 31: 0] W_ienable_reg; - wire [ 31: 0] W_ienable_reg_nxt; - reg [ 31: 0] W_ipending_reg; - wire [ 31: 0] W_ipending_reg_nxt; - wire [ 18: 0] W_mem_baddr; - wire [ 31: 0] W_rf_wr_data; - wire W_rf_wren; - wire W_status_reg; - reg W_status_reg_pie; - wire W_status_reg_pie_inst_nxt; - wire W_status_reg_pie_nxt; - reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; - wire [ 55: 0] W_vinst; - wire [ 31: 0] W_wr_data; - wire [ 31: 0] W_wr_data_non_zero; - wire av_fill_bit; - reg [ 1: 0] av_ld_align_cycle; - wire [ 1: 0] av_ld_align_cycle_nxt; - wire av_ld_align_one_more_cycle; - reg av_ld_aligning_data; - wire av_ld_aligning_data_nxt; - reg [ 7: 0] av_ld_byte0_data; - wire [ 7: 0] av_ld_byte0_data_nxt; - reg [ 7: 0] av_ld_byte1_data; - wire av_ld_byte1_data_en; - wire [ 7: 0] av_ld_byte1_data_nxt; - reg [ 7: 0] av_ld_byte2_data; - wire [ 7: 0] av_ld_byte2_data_nxt; - reg [ 7: 0] av_ld_byte3_data; - wire [ 7: 0] av_ld_byte3_data_nxt; - wire [ 31: 0] av_ld_data_aligned_filtered; - wire [ 31: 0] av_ld_data_aligned_unfiltered; - wire av_ld_done; - wire av_ld_extend; - wire av_ld_getting_data; - wire av_ld_rshift8; - reg av_ld_waiting_for_data; - wire av_ld_waiting_for_data_nxt; - wire av_sign_bit; - wire [ 18: 0] d_address; - reg [ 3: 0] d_byteenable; - reg d_read; - wire d_read_nxt; - wire d_write; - wire d_write_nxt; - reg [ 31: 0] d_writedata; - reg hbreak_enabled; - reg hbreak_pending; - wire hbreak_pending_nxt; - wire hbreak_req; - wire [ 18: 0] i_address; - reg i_read; - wire i_read_nxt; - wire [ 31: 0] iactive; - wire intr_req; - wire jtag_debug_module_clk; - wire jtag_debug_module_debugaccess_to_roms; - wire [ 31: 0] jtag_debug_module_readdata; - wire jtag_debug_module_reset; - wire jtag_debug_module_resetrequest; - wire jtag_debug_module_waitrequest; - wire no_ci_readra; - wire oci_hbreak_req; - wire [ 31: 0] oci_ienable; - wire oci_single_step_mode; - wire oci_tb_hbreak_req; - wire test_ending; - wire test_has_ended; - reg wait_for_one_post_bret_inst; - //the_nios_system_nios2_processor_test_bench, which is an e_instance - nios_system_nios2_processor_test_bench the_nios_system_nios2_processor_test_bench - ( - .D_iw (D_iw), - .D_iw_op (D_iw_op), - .D_iw_opx (D_iw_opx), - .D_valid (D_valid), - .E_valid (E_valid), - .F_pcb (F_pcb), - .F_valid (F_valid), - .R_ctrl_ld (R_ctrl_ld), - .R_ctrl_ld_non_io (R_ctrl_ld_non_io), - .R_dst_regnum (R_dst_regnum), - .R_wr_dst_reg (R_wr_dst_reg), - .W_valid (W_valid), - .W_vinst (W_vinst), - .W_wr_data (W_wr_data), - .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), - .av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered), - .clk (clk), - .d_address (d_address), - .d_byteenable (d_byteenable), - .d_read (d_read), - .d_write (d_write), - .d_write_nxt (d_write_nxt), - .i_address (i_address), - .i_read (i_read), - .i_readdata (i_readdata), - .i_waitrequest (i_waitrequest), - .reset_n (reset_n), - .test_has_ended (test_has_ended) - ); - - assign F_av_iw_a = F_av_iw[31 : 27]; - assign F_av_iw_b = F_av_iw[26 : 22]; - assign F_av_iw_c = F_av_iw[21 : 17]; - assign F_av_iw_custom_n = F_av_iw[13 : 6]; - assign F_av_iw_custom_readra = F_av_iw[16]; - assign F_av_iw_custom_readrb = F_av_iw[15]; - assign F_av_iw_custom_writerc = F_av_iw[14]; - assign F_av_iw_opx = F_av_iw[16 : 11]; - assign F_av_iw_op = F_av_iw[5 : 0]; - assign F_av_iw_shift_imm5 = F_av_iw[10 : 6]; - assign F_av_iw_trap_break_imm5 = F_av_iw[10 : 6]; - assign F_av_iw_imm5 = F_av_iw[10 : 6]; - assign F_av_iw_imm16 = F_av_iw[21 : 6]; - assign F_av_iw_imm26 = F_av_iw[31 : 6]; - assign F_av_iw_memsz = F_av_iw[4 : 3]; - assign F_av_iw_control_regnum = F_av_iw[8 : 6]; - assign F_av_mem8 = F_av_iw_memsz == 2'b00; - assign F_av_mem16 = F_av_iw_memsz == 2'b01; - assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1; - assign F_iw_a = F_iw[31 : 27]; - assign F_iw_b = F_iw[26 : 22]; - assign F_iw_c = F_iw[21 : 17]; - assign F_iw_custom_n = F_iw[13 : 6]; - assign F_iw_custom_readra = F_iw[16]; - assign F_iw_custom_readrb = F_iw[15]; - assign F_iw_custom_writerc = F_iw[14]; - assign F_iw_opx = F_iw[16 : 11]; - assign F_iw_op = F_iw[5 : 0]; - assign F_iw_shift_imm5 = F_iw[10 : 6]; - assign F_iw_trap_break_imm5 = F_iw[10 : 6]; - assign F_iw_imm5 = F_iw[10 : 6]; - assign F_iw_imm16 = F_iw[21 : 6]; - assign F_iw_imm26 = F_iw[31 : 6]; - assign F_iw_memsz = F_iw[4 : 3]; - assign F_iw_control_regnum = F_iw[8 : 6]; - assign F_mem8 = F_iw_memsz == 2'b00; - assign F_mem16 = F_iw_memsz == 2'b01; - assign F_mem32 = F_iw_memsz[1] == 1'b1; - assign D_iw_a = D_iw[31 : 27]; - assign D_iw_b = D_iw[26 : 22]; - assign D_iw_c = D_iw[21 : 17]; - assign D_iw_custom_n = D_iw[13 : 6]; - assign D_iw_custom_readra = D_iw[16]; - assign D_iw_custom_readrb = D_iw[15]; - assign D_iw_custom_writerc = D_iw[14]; - assign D_iw_opx = D_iw[16 : 11]; - assign D_iw_op = D_iw[5 : 0]; - assign D_iw_shift_imm5 = D_iw[10 : 6]; - assign D_iw_trap_break_imm5 = D_iw[10 : 6]; - assign D_iw_imm5 = D_iw[10 : 6]; - assign D_iw_imm16 = D_iw[21 : 6]; - assign D_iw_imm26 = D_iw[31 : 6]; - assign D_iw_memsz = D_iw[4 : 3]; - assign D_iw_control_regnum = D_iw[8 : 6]; - assign D_mem8 = D_iw_memsz == 2'b00; - assign D_mem16 = D_iw_memsz == 2'b01; - assign D_mem32 = D_iw_memsz[1] == 1'b1; - assign F_op_call = F_iw_op == 0; - assign F_op_jmpi = F_iw_op == 1; - assign F_op_ldbu = F_iw_op == 3; - assign F_op_addi = F_iw_op == 4; - assign F_op_stb = F_iw_op == 5; - assign F_op_br = F_iw_op == 6; - assign F_op_ldb = F_iw_op == 7; - assign F_op_cmpgei = F_iw_op == 8; - assign F_op_ldhu = F_iw_op == 11; - assign F_op_andi = F_iw_op == 12; - assign F_op_sth = F_iw_op == 13; - assign F_op_bge = F_iw_op == 14; - assign F_op_ldh = F_iw_op == 15; - assign F_op_cmplti = F_iw_op == 16; - assign F_op_initda = F_iw_op == 19; - assign F_op_ori = F_iw_op == 20; - assign F_op_stw = F_iw_op == 21; - assign F_op_blt = F_iw_op == 22; - assign F_op_ldw = F_iw_op == 23; - assign F_op_cmpnei = F_iw_op == 24; - assign F_op_flushda = F_iw_op == 27; - assign F_op_xori = F_iw_op == 28; - assign F_op_stc = F_iw_op == 29; - assign F_op_bne = F_iw_op == 30; - assign F_op_ldl = F_iw_op == 31; - assign F_op_cmpeqi = F_iw_op == 32; - assign F_op_ldbuio = F_iw_op == 35; - assign F_op_muli = F_iw_op == 36; - assign F_op_stbio = F_iw_op == 37; - assign F_op_beq = F_iw_op == 38; - assign F_op_ldbio = F_iw_op == 39; - assign F_op_cmpgeui = F_iw_op == 40; - assign F_op_ldhuio = F_iw_op == 43; - assign F_op_andhi = F_iw_op == 44; - assign F_op_sthio = F_iw_op == 45; - assign F_op_bgeu = F_iw_op == 46; - assign F_op_ldhio = F_iw_op == 47; - assign F_op_cmpltui = F_iw_op == 48; - assign F_op_initd = F_iw_op == 51; - assign F_op_orhi = F_iw_op == 52; - assign F_op_stwio = F_iw_op == 53; - assign F_op_bltu = F_iw_op == 54; - assign F_op_ldwio = F_iw_op == 55; - assign F_op_rdprs = F_iw_op == 56; - assign F_op_flushd = F_iw_op == 59; - assign F_op_xorhi = F_iw_op == 60; - assign F_op_rsv02 = F_iw_op == 2; - assign F_op_rsv09 = F_iw_op == 9; - assign F_op_rsv10 = F_iw_op == 10; - assign F_op_rsv17 = F_iw_op == 17; - assign F_op_rsv18 = F_iw_op == 18; - assign F_op_rsv25 = F_iw_op == 25; - assign F_op_rsv26 = F_iw_op == 26; - assign F_op_rsv33 = F_iw_op == 33; - assign F_op_rsv34 = F_iw_op == 34; - assign F_op_rsv41 = F_iw_op == 41; - assign F_op_rsv42 = F_iw_op == 42; - assign F_op_rsv49 = F_iw_op == 49; - assign F_op_rsv57 = F_iw_op == 57; - assign F_op_rsv61 = F_iw_op == 61; - assign F_op_rsv62 = F_iw_op == 62; - assign F_op_rsv63 = F_iw_op == 63; - assign F_op_eret = F_op_opx & (F_iw_opx == 1); - assign F_op_roli = F_op_opx & (F_iw_opx == 2); - assign F_op_rol = F_op_opx & (F_iw_opx == 3); - assign F_op_flushp = F_op_opx & (F_iw_opx == 4); - assign F_op_ret = F_op_opx & (F_iw_opx == 5); - assign F_op_nor = F_op_opx & (F_iw_opx == 6); - assign F_op_mulxuu = F_op_opx & (F_iw_opx == 7); - assign F_op_cmpge = F_op_opx & (F_iw_opx == 8); - assign F_op_bret = F_op_opx & (F_iw_opx == 9); - assign F_op_ror = F_op_opx & (F_iw_opx == 11); - assign F_op_flushi = F_op_opx & (F_iw_opx == 12); - assign F_op_jmp = F_op_opx & (F_iw_opx == 13); - assign F_op_and = F_op_opx & (F_iw_opx == 14); - assign F_op_cmplt = F_op_opx & (F_iw_opx == 16); - assign F_op_slli = F_op_opx & (F_iw_opx == 18); - assign F_op_sll = F_op_opx & (F_iw_opx == 19); - assign F_op_wrprs = F_op_opx & (F_iw_opx == 20); - assign F_op_or = F_op_opx & (F_iw_opx == 22); - assign F_op_mulxsu = F_op_opx & (F_iw_opx == 23); - assign F_op_cmpne = F_op_opx & (F_iw_opx == 24); - assign F_op_srli = F_op_opx & (F_iw_opx == 26); - assign F_op_srl = F_op_opx & (F_iw_opx == 27); - assign F_op_nextpc = F_op_opx & (F_iw_opx == 28); - assign F_op_callr = F_op_opx & (F_iw_opx == 29); - assign F_op_xor = F_op_opx & (F_iw_opx == 30); - assign F_op_mulxss = F_op_opx & (F_iw_opx == 31); - assign F_op_cmpeq = F_op_opx & (F_iw_opx == 32); - assign F_op_divu = F_op_opx & (F_iw_opx == 36); - assign F_op_div = F_op_opx & (F_iw_opx == 37); - assign F_op_rdctl = F_op_opx & (F_iw_opx == 38); - assign F_op_mul = F_op_opx & (F_iw_opx == 39); - assign F_op_cmpgeu = F_op_opx & (F_iw_opx == 40); - assign F_op_initi = F_op_opx & (F_iw_opx == 41); - assign F_op_trap = F_op_opx & (F_iw_opx == 45); - assign F_op_wrctl = F_op_opx & (F_iw_opx == 46); - assign F_op_cmpltu = F_op_opx & (F_iw_opx == 48); - assign F_op_add = F_op_opx & (F_iw_opx == 49); - assign F_op_break = F_op_opx & (F_iw_opx == 52); - assign F_op_hbreak = F_op_opx & (F_iw_opx == 53); - assign F_op_sync = F_op_opx & (F_iw_opx == 54); - assign F_op_sub = F_op_opx & (F_iw_opx == 57); - assign F_op_srai = F_op_opx & (F_iw_opx == 58); - assign F_op_sra = F_op_opx & (F_iw_opx == 59); - assign F_op_intr = F_op_opx & (F_iw_opx == 61); - assign F_op_crst = F_op_opx & (F_iw_opx == 62); - assign F_op_rsvx00 = F_op_opx & (F_iw_opx == 0); - assign F_op_rsvx10 = F_op_opx & (F_iw_opx == 10); - assign F_op_rsvx15 = F_op_opx & (F_iw_opx == 15); - assign F_op_rsvx17 = F_op_opx & (F_iw_opx == 17); - assign F_op_rsvx21 = F_op_opx & (F_iw_opx == 21); - assign F_op_rsvx25 = F_op_opx & (F_iw_opx == 25); - assign F_op_rsvx33 = F_op_opx & (F_iw_opx == 33); - assign F_op_rsvx34 = F_op_opx & (F_iw_opx == 34); - assign F_op_rsvx35 = F_op_opx & (F_iw_opx == 35); - assign F_op_rsvx42 = F_op_opx & (F_iw_opx == 42); - assign F_op_rsvx43 = F_op_opx & (F_iw_opx == 43); - assign F_op_rsvx44 = F_op_opx & (F_iw_opx == 44); - assign F_op_rsvx47 = F_op_opx & (F_iw_opx == 47); - assign F_op_rsvx50 = F_op_opx & (F_iw_opx == 50); - assign F_op_rsvx51 = F_op_opx & (F_iw_opx == 51); - assign F_op_rsvx55 = F_op_opx & (F_iw_opx == 55); - assign F_op_rsvx56 = F_op_opx & (F_iw_opx == 56); - assign F_op_rsvx60 = F_op_opx & (F_iw_opx == 60); - assign F_op_rsvx63 = F_op_opx & (F_iw_opx == 63); - assign F_op_opx = F_iw_op == 58; - assign F_op_custom = F_iw_op == 50; - assign D_op_call = D_iw_op == 0; - assign D_op_jmpi = D_iw_op == 1; - assign D_op_ldbu = D_iw_op == 3; - assign D_op_addi = D_iw_op == 4; - assign D_op_stb = D_iw_op == 5; - assign D_op_br = D_iw_op == 6; - assign D_op_ldb = D_iw_op == 7; - assign D_op_cmpgei = D_iw_op == 8; - assign D_op_ldhu = D_iw_op == 11; - assign D_op_andi = D_iw_op == 12; - assign D_op_sth = D_iw_op == 13; - assign D_op_bge = D_iw_op == 14; - assign D_op_ldh = D_iw_op == 15; - assign D_op_cmplti = D_iw_op == 16; - assign D_op_initda = D_iw_op == 19; - assign D_op_ori = D_iw_op == 20; - assign D_op_stw = D_iw_op == 21; - assign D_op_blt = D_iw_op == 22; - assign D_op_ldw = D_iw_op == 23; - assign D_op_cmpnei = D_iw_op == 24; - assign D_op_flushda = D_iw_op == 27; - assign D_op_xori = D_iw_op == 28; - assign D_op_stc = D_iw_op == 29; - assign D_op_bne = D_iw_op == 30; - assign D_op_ldl = D_iw_op == 31; - assign D_op_cmpeqi = D_iw_op == 32; - assign D_op_ldbuio = D_iw_op == 35; - assign D_op_muli = D_iw_op == 36; - assign D_op_stbio = D_iw_op == 37; - assign D_op_beq = D_iw_op == 38; - assign D_op_ldbio = D_iw_op == 39; - assign D_op_cmpgeui = D_iw_op == 40; - assign D_op_ldhuio = D_iw_op == 43; - assign D_op_andhi = D_iw_op == 44; - assign D_op_sthio = D_iw_op == 45; - assign D_op_bgeu = D_iw_op == 46; - assign D_op_ldhio = D_iw_op == 47; - assign D_op_cmpltui = D_iw_op == 48; - assign D_op_initd = D_iw_op == 51; - assign D_op_orhi = D_iw_op == 52; - assign D_op_stwio = D_iw_op == 53; - assign D_op_bltu = D_iw_op == 54; - assign D_op_ldwio = D_iw_op == 55; - assign D_op_rdprs = D_iw_op == 56; - assign D_op_flushd = D_iw_op == 59; - assign D_op_xorhi = D_iw_op == 60; - assign D_op_rsv02 = D_iw_op == 2; - assign D_op_rsv09 = D_iw_op == 9; - assign D_op_rsv10 = D_iw_op == 10; - assign D_op_rsv17 = D_iw_op == 17; - assign D_op_rsv18 = D_iw_op == 18; - assign D_op_rsv25 = D_iw_op == 25; - assign D_op_rsv26 = D_iw_op == 26; - assign D_op_rsv33 = D_iw_op == 33; - assign D_op_rsv34 = D_iw_op == 34; - assign D_op_rsv41 = D_iw_op == 41; - assign D_op_rsv42 = D_iw_op == 42; - assign D_op_rsv49 = D_iw_op == 49; - assign D_op_rsv57 = D_iw_op == 57; - assign D_op_rsv61 = D_iw_op == 61; - assign D_op_rsv62 = D_iw_op == 62; - assign D_op_rsv63 = D_iw_op == 63; - assign D_op_eret = D_op_opx & (D_iw_opx == 1); - assign D_op_roli = D_op_opx & (D_iw_opx == 2); - assign D_op_rol = D_op_opx & (D_iw_opx == 3); - assign D_op_flushp = D_op_opx & (D_iw_opx == 4); - assign D_op_ret = D_op_opx & (D_iw_opx == 5); - assign D_op_nor = D_op_opx & (D_iw_opx == 6); - assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7); - assign D_op_cmpge = D_op_opx & (D_iw_opx == 8); - assign D_op_bret = D_op_opx & (D_iw_opx == 9); - assign D_op_ror = D_op_opx & (D_iw_opx == 11); - assign D_op_flushi = D_op_opx & (D_iw_opx == 12); - assign D_op_jmp = D_op_opx & (D_iw_opx == 13); - assign D_op_and = D_op_opx & (D_iw_opx == 14); - assign D_op_cmplt = D_op_opx & (D_iw_opx == 16); - assign D_op_slli = D_op_opx & (D_iw_opx == 18); - assign D_op_sll = D_op_opx & (D_iw_opx == 19); - assign D_op_wrprs = D_op_opx & (D_iw_opx == 20); - assign D_op_or = D_op_opx & (D_iw_opx == 22); - assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23); - assign D_op_cmpne = D_op_opx & (D_iw_opx == 24); - assign D_op_srli = D_op_opx & (D_iw_opx == 26); - assign D_op_srl = D_op_opx & (D_iw_opx == 27); - assign D_op_nextpc = D_op_opx & (D_iw_opx == 28); - assign D_op_callr = D_op_opx & (D_iw_opx == 29); - assign D_op_xor = D_op_opx & (D_iw_opx == 30); - assign D_op_mulxss = D_op_opx & (D_iw_opx == 31); - assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32); - assign D_op_divu = D_op_opx & (D_iw_opx == 36); - assign D_op_div = D_op_opx & (D_iw_opx == 37); - assign D_op_rdctl = D_op_opx & (D_iw_opx == 38); - assign D_op_mul = D_op_opx & (D_iw_opx == 39); - assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40); - assign D_op_initi = D_op_opx & (D_iw_opx == 41); - assign D_op_trap = D_op_opx & (D_iw_opx == 45); - assign D_op_wrctl = D_op_opx & (D_iw_opx == 46); - assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48); - assign D_op_add = D_op_opx & (D_iw_opx == 49); - assign D_op_break = D_op_opx & (D_iw_opx == 52); - assign D_op_hbreak = D_op_opx & (D_iw_opx == 53); - assign D_op_sync = D_op_opx & (D_iw_opx == 54); - assign D_op_sub = D_op_opx & (D_iw_opx == 57); - assign D_op_srai = D_op_opx & (D_iw_opx == 58); - assign D_op_sra = D_op_opx & (D_iw_opx == 59); - assign D_op_intr = D_op_opx & (D_iw_opx == 61); - assign D_op_crst = D_op_opx & (D_iw_opx == 62); - assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0); - assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10); - assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15); - assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17); - assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21); - assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25); - assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33); - assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34); - assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35); - assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42); - assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43); - assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44); - assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47); - assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50); - assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51); - assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55); - assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56); - assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60); - assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63); - assign D_op_opx = D_iw_op == 58; - assign D_op_custom = D_iw_op == 50; - assign R_en = 1'b1; - assign E_ci_result = 0; - //custom_instruction_master, which is an e_custom_instruction_master - assign no_ci_readra = 1'b0; - assign E_ci_multi_stall = 1'b0; - assign iactive = d_irq[31 : 0] & 32'b00000000000000000000000000100000; - assign F_pc_sel_nxt = R_ctrl_exception ? 2'b00 : - R_ctrl_break ? 2'b01 : - (W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 : - 2'b11; - - assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 8 : - (F_pc_sel_nxt == 2'b01)? 66056 : - (F_pc_sel_nxt == 2'b10)? E_arith_result[18 : 2] : - F_pc_plus_one; - - assign F_pc_nxt = F_pc_no_crst_nxt; - assign F_pcb_nxt = {F_pc_nxt, 2'b00}; - assign F_pc_en = W_valid; - assign F_pc_plus_one = F_pc + 1; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - F_pc <= 0; - else if (F_pc_en) - F_pc <= F_pc_nxt; - end - - - assign F_pcb = {F_pc, 2'b00}; - assign F_pcb_plus_four = {F_pc_plus_one, 2'b00}; - assign F_valid = i_read & ~i_waitrequest; - assign i_read_nxt = W_valid | (i_read & i_waitrequest); - assign i_address = {F_pc, 2'b00}; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - i_read <= 1'b1; - else - i_read <= i_read_nxt; - end - - - assign oci_tb_hbreak_req = oci_hbreak_req; - assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled & ~(wait_for_one_post_bret_inst & ~W_valid); - assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled - : hbreak_req; - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - wait_for_one_post_bret_inst <= 1'b0; - else - wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 : (F_valid | ~oci_single_step_mode) ? 1'b0 : wait_for_one_post_bret_inst; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - hbreak_pending <= 1'b0; - else - hbreak_pending <= hbreak_pending_nxt; - end - - - assign intr_req = W_status_reg_pie & (W_ipending_reg != 0); - assign F_av_iw = i_readdata; - assign F_iw = hbreak_req ? 4040762 : - 1'b0 ? 127034 : - intr_req ? 3926074 : - F_av_iw; - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - D_iw <= 0; - else if (F_valid) - D_iw <= F_iw; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - D_valid <= 0; - else - D_valid <= F_valid; - end - - - assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 : - D_ctrl_implicit_dst_eretaddr ? 5'd29 : - D_ctrl_b_is_dst ? D_iw_b : - D_iw_c; - - assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst; - assign D_logic_op_raw = D_op_opx ? D_iw_opx[4 : 3] : - D_iw_op[4 : 3]; - - assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 : D_logic_op_raw; - assign D_compare_op = D_op_opx ? D_iw_opx[4 : 3] : - D_iw_op[4 : 3]; - - assign D_jmp_direct_target_waddr = D_iw[31 : 6]; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_valid <= 0; - else - R_valid <= D_valid; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_wr_dst_reg <= 0; - else - R_wr_dst_reg <= D_wr_dst_reg; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_dst_regnum <= 0; - else - R_dst_regnum <= D_dst_regnum; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_logic_op <= 0; - else - R_logic_op <= D_logic_op; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_compare_op <= 0; - else - R_compare_op <= D_compare_op; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_src2_use_imm <= 0; - else - R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid); - end - - - assign W_rf_wren = (R_wr_dst_reg & W_valid) | ~reset_n; - assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data; -//nios_system_nios2_processor_register_bank_a, which is an nios_sdp_ram -nios_system_nios2_processor_register_bank_a_module nios_system_nios2_processor_register_bank_a - ( - .clock (clk), - .data (W_rf_wr_data), - .q (R_rf_a), - .rdaddress (D_iw_a), - .wraddress (R_dst_regnum), - .wren (W_rf_wren) - ); - -//synthesis translate_off -`ifdef NO_PLI -defparam nios_system_nios2_processor_register_bank_a.lpm_file = "nios_system_nios2_processor_rf_ram_a.dat"; -`else -defparam nios_system_nios2_processor_register_bank_a.lpm_file = "nios_system_nios2_processor_rf_ram_a.hex"; -`endif -//synthesis translate_on -//synthesis read_comments_as_HDL on -//defparam nios_system_nios2_processor_register_bank_a.lpm_file = "nios_system_nios2_processor_rf_ram_a.mif"; -//synthesis read_comments_as_HDL off -//nios_system_nios2_processor_register_bank_b, which is an nios_sdp_ram -nios_system_nios2_processor_register_bank_b_module nios_system_nios2_processor_register_bank_b - ( - .clock (clk), - .data (W_rf_wr_data), - .q (R_rf_b), - .rdaddress (D_iw_b), - .wraddress (R_dst_regnum), - .wren (W_rf_wren) - ); - -//synthesis translate_off -`ifdef NO_PLI -defparam nios_system_nios2_processor_register_bank_b.lpm_file = "nios_system_nios2_processor_rf_ram_b.dat"; -`else -defparam nios_system_nios2_processor_register_bank_b.lpm_file = "nios_system_nios2_processor_rf_ram_b.hex"; -`endif -//synthesis translate_on -//synthesis read_comments_as_HDL on -//defparam nios_system_nios2_processor_register_bank_b.lpm_file = "nios_system_nios2_processor_rf_ram_b.mif"; -//synthesis read_comments_as_HDL off - assign R_src1 = (((R_ctrl_br & E_valid) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} : - ((R_ctrl_jmp_direct & E_valid))? {D_jmp_direct_target_waddr, 2'b00} : - R_rf_a; - - assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? 16'b0 : - (R_src2_use_imm)? D_iw_imm16 : - R_rf_b[15 : 0]; - - assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? 16'b0 : - (R_ctrl_hi_imm16)? D_iw_imm16 : - (R_src2_use_imm)? {16 {D_iw_imm16[15]}} : - R_rf_b[31 : 16]; - - assign R_src2 = {R_src2_hi, R_src2_lo}; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_valid <= 0; - else - E_valid <= R_valid | E_stall; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_new_inst <= 0; - else - E_new_inst <= R_valid; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_src1 <= 0; - else - E_src1 <= R_src1; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_src2 <= 0; - else - E_src2 <= R_src2; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_invert_arith_src_msb <= 0; - else - E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_alu_sub <= 0; - else - E_alu_sub <= D_ctrl_alu_subtract & R_valid; - end - - - assign E_stall = E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall; - assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb, - E_src1[30 : 0]}; - - assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb, - E_src2[30 : 0]}; - - assign E_arith_result = E_alu_sub ? - E_arith_src1 - E_arith_src2 : - E_arith_src1 + E_arith_src2; - - assign E_mem_baddr = E_arith_result[18 : 0]; - assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) : - (R_logic_op == 2'b01)? (E_src1 & E_src2) : - (R_logic_op == 2'b10)? (E_src1 | E_src2) : - (E_src1 ^ E_src2); - - assign E_logic_result_is_0 = E_logic_result == 0; - assign E_eq = E_logic_result_is_0; - assign E_lt = E_arith_result[32]; - assign E_cmp_result = (R_compare_op == 2'b00)? E_eq : - (R_compare_op == 2'b01)? ~E_lt : - (R_compare_op == 2'b10)? E_lt : - ~E_eq; - - assign E_shift_rot_cnt_nxt = E_new_inst ? E_src2[4 : 0] : E_shift_rot_cnt-1; - assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst; - assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done; - assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 : - (R_ctrl_rot_right ? E_shift_rot_result[0] : - E_shift_rot_result[31]); - - assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 : - (R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} : - {E_shift_rot_result[30 : 0], E_shift_rot_fill_bit}; - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_shift_rot_result <= 0; - else - E_shift_rot_result <= E_shift_rot_result_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_shift_rot_cnt <= 0; - else - E_shift_rot_cnt <= E_shift_rot_cnt_nxt; - end - - - assign E_control_rd_data = (D_iw_control_regnum == 3'd0)? W_status_reg : - (D_iw_control_regnum == 3'd1)? W_estatus_reg : - (D_iw_control_regnum == 3'd2)? W_bstatus_reg : - (D_iw_control_regnum == 3'd3)? W_ienable_reg : - (D_iw_control_regnum == 3'd4)? W_ipending_reg : - 0; - - assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rdctl_inst))? 0 : - (R_ctrl_shift_rot)? E_shift_rot_result : - (R_ctrl_logic)? E_logic_result : - (R_ctrl_custom)? E_ci_result : - E_arith_result; - - assign R_stb_data = R_rf_b[7 : 0]; - assign R_sth_data = R_rf_b[15 : 0]; - assign E_st_data = (D_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} : - (D_mem16)? {R_sth_data, R_sth_data} : - R_rf_b; - - assign E_mem_byte_en = ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b00})? 4'b0001 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b01})? 4'b0010 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b10})? 4'b0100 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b11})? 4'b1000 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0011 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0011 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b1100 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1100 : - 4'b1111; - - assign d_read_nxt = (R_ctrl_ld & E_new_inst) | (d_read & d_waitrequest); - assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst); - assign d_write_nxt = (R_ctrl_st & E_new_inst) | (d_write & d_waitrequest); - assign E_st_stall = d_write_nxt; - assign d_address = W_mem_baddr; - assign av_ld_getting_data = d_read & ~d_waitrequest; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - d_read <= 0; - else - d_read <= d_read_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - d_writedata <= 0; - else - d_writedata <= E_st_data; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - d_byteenable <= 0; - else - d_byteenable <= E_mem_byte_en; - end - - - assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1); - assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_mem16 ? 2 : 3); - assign av_ld_aligning_data_nxt = av_ld_aligning_data ? - ~av_ld_align_one_more_cycle : - (~D_mem32 & av_ld_getting_data); - - assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ? - ~av_ld_getting_data : - (R_ctrl_ld & E_new_inst); - - assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_mem32 | ~av_ld_aligning_data_nxt); - assign av_ld_rshift8 = av_ld_aligning_data & - (av_ld_align_cycle < (W_mem_baddr[1 : 0])); - - assign av_ld_extend = av_ld_aligning_data; - assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data : - av_ld_extend ? av_ld_byte0_data : - d_readdata[7 : 0]; - - assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data : - av_ld_extend ? {8 {av_fill_bit}} : - d_readdata[15 : 8]; - - assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data : - av_ld_extend ? {8 {av_fill_bit}} : - d_readdata[23 : 16]; - - assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data : - av_ld_extend ? {8 {av_fill_bit}} : - d_readdata[31 : 24]; - - assign av_ld_byte1_data_en = ~(av_ld_extend & D_mem16 & ~av_ld_rshift8); - assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data, - av_ld_byte1_data, av_ld_byte0_data}; - - assign av_sign_bit = D_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7]; - assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_align_cycle <= 0; - else - av_ld_align_cycle <= av_ld_align_cycle_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_waiting_for_data <= 0; - else - av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_aligning_data <= 0; - else - av_ld_aligning_data <= av_ld_aligning_data_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_byte0_data <= 0; - else - av_ld_byte0_data <= av_ld_byte0_data_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_byte1_data <= 0; - else if (av_ld_byte1_data_en) - av_ld_byte1_data <= av_ld_byte1_data_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_byte2_data <= 0; - else - av_ld_byte2_data <= av_ld_byte2_data_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_byte3_data <= 0; - else - av_ld_byte3_data <= av_ld_byte3_data_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_valid <= 0; - else - W_valid <= E_valid & ~E_stall; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_control_rd_data <= 0; - else - W_control_rd_data <= E_control_rd_data; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_cmp_result <= 0; - else - W_cmp_result <= E_cmp_result; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_alu_result <= 0; - else - W_alu_result <= E_alu_result; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_status_reg_pie <= 0; - else - W_status_reg_pie <= W_status_reg_pie_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_estatus_reg <= 0; - else - W_estatus_reg <= W_estatus_reg_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_bstatus_reg <= 0; - else - W_bstatus_reg <= W_bstatus_reg_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_ienable_reg <= 0; - else - W_ienable_reg <= W_ienable_reg_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_ipending_reg <= 0; - else - W_ipending_reg <= W_ipending_reg_nxt; - end - - - assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result : - R_ctrl_rdctl_inst ? W_control_rd_data : - W_alu_result[31 : 0]; - - assign W_wr_data = W_wr_data_non_zero; - assign W_br_taken = R_ctrl_br & W_cmp_result; - assign W_mem_baddr = W_alu_result[18 : 0]; - assign W_status_reg = W_status_reg_pie; - assign E_wrctl_status = R_ctrl_wrctl_inst & - (D_iw_control_regnum == 3'd0); - - assign E_wrctl_estatus = R_ctrl_wrctl_inst & - (D_iw_control_regnum == 3'd1); - - assign E_wrctl_bstatus = R_ctrl_wrctl_inst & - (D_iw_control_regnum == 3'd2); - - assign E_wrctl_ienable = R_ctrl_wrctl_inst & - (D_iw_control_regnum == 3'd3); - - assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst) ? 1'b0 : - (D_op_eret) ? W_estatus_reg : - (D_op_bret) ? W_bstatus_reg : - (E_wrctl_status) ? E_src1[0] : - W_status_reg_pie; - - assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie; - assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 : - (R_ctrl_exception) ? W_status_reg : - (E_wrctl_estatus) ? E_src1[0] : - W_estatus_reg; - - assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg; - assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg : - (E_wrctl_bstatus) ? E_src1[0] : - W_bstatus_reg; - - assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg; - assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ? - E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000000100000; - - assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000000100000; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - hbreak_enabled <= 1'b1; - else if (E_valid) - hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled; - end - - - nios_system_nios2_processor_nios2_oci the_nios_system_nios2_processor_nios2_oci - ( - .D_valid (D_valid), - .E_st_data (E_st_data), - .E_valid (E_valid), - .F_pc (F_pc), - .address_nxt (jtag_debug_module_address), - .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), - .byteenable_nxt (jtag_debug_module_byteenable), - .clk (jtag_debug_module_clk), - .d_address (d_address), - .d_read (d_read), - .d_waitrequest (d_waitrequest), - .d_write (d_write), - .debugaccess_nxt (jtag_debug_module_debugaccess), - .hbreak_enabled (hbreak_enabled), - .jtag_debug_module_debugaccess_to_roms (jtag_debug_module_debugaccess_to_roms), - .oci_hbreak_req (oci_hbreak_req), - .oci_ienable (oci_ienable), - .oci_single_step_mode (oci_single_step_mode), - .read_nxt (jtag_debug_module_read), - .readdata (jtag_debug_module_readdata), - .reset (jtag_debug_module_reset), - .reset_n (reset_n), - .resetrequest (jtag_debug_module_resetrequest), - .test_ending (test_ending), - .test_has_ended (test_has_ended), - .waitrequest (jtag_debug_module_waitrequest), - .write_nxt (jtag_debug_module_write), - .writedata_nxt (jtag_debug_module_writedata) - ); - - //jtag_debug_module, which is an e_avalon_slave - assign jtag_debug_module_clk = clk; - assign jtag_debug_module_reset = ~reset_n; - assign D_ctrl_custom = 1'b0; - assign R_ctrl_custom_nxt = D_ctrl_custom; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_custom <= 0; - else if (R_en) - R_ctrl_custom <= R_ctrl_custom_nxt; - end - - - assign D_ctrl_custom_multi = 1'b0; - assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_custom_multi <= 0; - else if (R_en) - R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt; - end - - - assign D_ctrl_jmp_indirect = D_op_eret| - D_op_bret| - D_op_rsvx17| - D_op_rsvx25| - D_op_ret| - D_op_jmp| - D_op_rsvx21| - D_op_callr; - - assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_jmp_indirect <= 0; - else if (R_en) - R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt; - end - - - assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi; - assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_jmp_direct <= 0; - else if (R_en) - R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt; - end - - - assign D_ctrl_implicit_dst_retaddr = D_op_call|D_op_rsv02; - assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_implicit_dst_retaddr <= 0; - else if (R_en) - R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt; - end - - - assign D_ctrl_implicit_dst_eretaddr = D_op_div|D_op_divu|D_op_mul|D_op_muli|D_op_mulxss|D_op_mulxsu|D_op_mulxuu; - assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_implicit_dst_eretaddr <= 0; - else if (R_en) - R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt; - end - - - assign D_ctrl_exception = D_op_trap| - D_op_rsvx44| - D_op_div| - D_op_divu| - D_op_mul| - D_op_muli| - D_op_mulxss| - D_op_mulxsu| - D_op_mulxuu| - D_op_intr| - D_op_rsvx60; - - assign R_ctrl_exception_nxt = D_ctrl_exception; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_exception <= 0; - else if (R_en) - R_ctrl_exception <= R_ctrl_exception_nxt; - end - - - assign D_ctrl_break = D_op_break|D_op_hbreak; - assign R_ctrl_break_nxt = D_ctrl_break; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_break <= 0; - else if (R_en) - R_ctrl_break <= R_ctrl_break_nxt; - end - - - assign D_ctrl_crst = D_op_crst|D_op_rsvx63; - assign R_ctrl_crst_nxt = D_ctrl_crst; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_crst <= 0; - else if (R_en) - R_ctrl_crst <= R_ctrl_crst_nxt; - end - - - assign D_ctrl_uncond_cti_non_br = D_op_call| - D_op_jmpi| - D_op_eret| - D_op_bret| - D_op_rsvx17| - D_op_rsvx25| - D_op_ret| - D_op_jmp| - D_op_rsvx21| - D_op_callr; - - assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_uncond_cti_non_br <= 0; - else if (R_en) - R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt; - end - - - assign D_ctrl_retaddr = D_op_call| - D_op_rsv02| - D_op_nextpc| - D_op_callr| - D_op_trap| - D_op_rsvx44| - D_op_div| - D_op_divu| - D_op_mul| - D_op_muli| - D_op_mulxss| - D_op_mulxsu| - D_op_mulxuu| - D_op_intr| - D_op_rsvx60| - D_op_break| - D_op_hbreak; - - assign R_ctrl_retaddr_nxt = D_ctrl_retaddr; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_retaddr <= 0; - else if (R_en) - R_ctrl_retaddr <= R_ctrl_retaddr_nxt; - end - - - assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl; - assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_shift_logical <= 0; - else if (R_en) - R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt; - end - - - assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra; - assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_shift_right_arith <= 0; - else if (R_en) - R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt; - end - - - assign D_ctrl_rot_right = D_op_rsvx10|D_op_ror|D_op_rsvx42|D_op_rsvx43; - assign R_ctrl_rot_right_nxt = D_ctrl_rot_right; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_rot_right <= 0; - else if (R_en) - R_ctrl_rot_right <= R_ctrl_rot_right_nxt; - end - - - assign D_ctrl_shift_rot_right = D_op_srli| - D_op_srl| - D_op_srai| - D_op_sra| - D_op_rsvx10| - D_op_ror| - D_op_rsvx42| - D_op_rsvx43; - - assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_shift_rot_right <= 0; - else if (R_en) - R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt; - end - - - assign D_ctrl_shift_rot = D_op_slli| - D_op_rsvx50| - D_op_sll| - D_op_rsvx51| - D_op_roli| - D_op_rsvx34| - D_op_rol| - D_op_rsvx35| - D_op_srli| - D_op_srl| - D_op_srai| - D_op_sra| - D_op_rsvx10| - D_op_ror| - D_op_rsvx42| - D_op_rsvx43; - - assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_shift_rot <= 0; - else if (R_en) - R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt; - end - - - assign D_ctrl_logic = D_op_and| - D_op_or| - D_op_xor| - D_op_nor| - D_op_andhi| - D_op_orhi| - D_op_xorhi| - D_op_andi| - D_op_ori| - D_op_xori; - - assign R_ctrl_logic_nxt = D_ctrl_logic; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_logic <= 0; - else if (R_en) - R_ctrl_logic <= R_ctrl_logic_nxt; - end - - - assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi; - assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_hi_imm16 <= 0; - else if (R_en) - R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt; - end - - - assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui| - D_op_cmpltui| - D_op_andi| - D_op_ori| - D_op_xori| - D_op_roli| - D_op_rsvx10| - D_op_slli| - D_op_srli| - D_op_rsvx34| - D_op_rsvx42| - D_op_rsvx50| - D_op_srai; - - assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_unsigned_lo_imm16 <= 0; - else if (R_en) - R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt; - end - - - assign D_ctrl_br_uncond = D_op_br|D_op_rsv02; - assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_br_uncond <= 0; - else if (R_en) - R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt; - end - - - assign D_ctrl_br = D_op_br| - D_op_bge| - D_op_blt| - D_op_bne| - D_op_beq| - D_op_bgeu| - D_op_bltu| - D_op_rsv62; - - assign R_ctrl_br_nxt = D_ctrl_br; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_br <= 0; - else if (R_en) - R_ctrl_br <= R_ctrl_br_nxt; - end - - - assign D_ctrl_alu_subtract = D_op_sub| - D_op_rsvx25| - D_op_cmplti| - D_op_cmpltui| - D_op_cmplt| - D_op_cmpltu| - D_op_blt| - D_op_bltu| - D_op_cmpgei| - D_op_cmpgeui| - D_op_cmpge| - D_op_cmpgeu| - D_op_bge| - D_op_rsv10| - D_op_bgeu| - D_op_rsv42; - - assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_alu_subtract <= 0; - else if (R_en) - R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt; - end - - - assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt; - assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_alu_signed_comparison <= 0; - else if (R_en) - R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt; - end - - - assign D_ctrl_br_cmp = D_op_br| - D_op_bge| - D_op_blt| - D_op_bne| - D_op_beq| - D_op_bgeu| - D_op_bltu| - D_op_rsv62| - D_op_cmpgei| - D_op_cmplti| - D_op_cmpnei| - D_op_cmpgeui| - D_op_cmpltui| - D_op_cmpeqi| - D_op_rsvx00| - D_op_cmpge| - D_op_cmplt| - D_op_cmpne| - D_op_cmpgeu| - D_op_cmpltu| - D_op_cmpeq| - D_op_rsvx56; - - assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_br_cmp <= 0; - else if (R_en) - R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt; - end - - - assign D_ctrl_ld_signed = D_op_ldb| - D_op_ldh| - D_op_ldl| - D_op_ldw| - D_op_ldbio| - D_op_ldhio| - D_op_ldwio| - D_op_rsv63; - - assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_ld_signed <= 0; - else if (R_en) - R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt; - end - - - assign D_ctrl_ld = D_op_ldb| - D_op_ldh| - D_op_ldl| - D_op_ldw| - D_op_ldbio| - D_op_ldhio| - D_op_ldwio| - D_op_rsv63| - D_op_ldbu| - D_op_ldhu| - D_op_ldbuio| - D_op_ldhuio; - - assign R_ctrl_ld_nxt = D_ctrl_ld; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_ld <= 0; - else if (R_en) - R_ctrl_ld <= R_ctrl_ld_nxt; - end - - - assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldl; - assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_ld_non_io <= 0; - else if (R_en) - R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt; - end - - - assign D_ctrl_st = D_op_stb| - D_op_sth| - D_op_stw| - D_op_stc| - D_op_stbio| - D_op_sthio| - D_op_stwio| - D_op_rsv61; - - assign R_ctrl_st_nxt = D_ctrl_st; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_st <= 0; - else if (R_en) - R_ctrl_st <= R_ctrl_st_nxt; - end - - - assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio|D_op_rsv63; - assign R_ctrl_ld_io_nxt = D_ctrl_ld_io; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_ld_io <= 0; - else if (R_en) - R_ctrl_ld_io <= R_ctrl_ld_io_nxt; - end - - - assign D_ctrl_b_is_dst = D_op_addi| - D_op_andhi| - D_op_orhi| - D_op_xorhi| - D_op_andi| - D_op_ori| - D_op_xori| - D_op_call| - D_op_rdprs| - D_op_cmpgei| - D_op_cmplti| - D_op_cmpnei| - D_op_cmpgeui| - D_op_cmpltui| - D_op_cmpeqi| - D_op_jmpi| - D_op_rsv09| - D_op_rsv17| - D_op_rsv25| - D_op_rsv33| - D_op_rsv41| - D_op_rsv49| - D_op_rsv57| - D_op_ldb| - D_op_ldh| - D_op_ldl| - D_op_ldw| - D_op_ldbio| - D_op_ldhio| - D_op_ldwio| - D_op_rsv63| - D_op_ldbu| - D_op_ldhu| - D_op_ldbuio| - D_op_ldhuio| - D_op_initd| - D_op_initda| - D_op_flushd| - D_op_flushda; - - assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_b_is_dst <= 0; - else if (R_en) - R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt; - end - - - assign D_ctrl_ignore_dst = D_op_br| - D_op_bge| - D_op_blt| - D_op_bne| - D_op_beq| - D_op_bgeu| - D_op_bltu| - D_op_rsv62| - D_op_stb| - D_op_sth| - D_op_stw| - D_op_stc| - D_op_stbio| - D_op_sthio| - D_op_stwio| - D_op_rsv61| - D_op_jmpi| - D_op_rsv09| - D_op_rsv17| - D_op_rsv25| - D_op_rsv33| - D_op_rsv41| - D_op_rsv49| - D_op_rsv57; - - assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_ignore_dst <= 0; - else if (R_en) - R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt; - end - - - assign D_ctrl_src2_choose_imm = D_op_addi| - D_op_andhi| - D_op_orhi| - D_op_xorhi| - D_op_andi| - D_op_ori| - D_op_xori| - D_op_call| - D_op_rdprs| - D_op_cmpgei| - D_op_cmplti| - D_op_cmpnei| - D_op_cmpgeui| - D_op_cmpltui| - D_op_cmpeqi| - D_op_jmpi| - D_op_rsv09| - D_op_rsv17| - D_op_rsv25| - D_op_rsv33| - D_op_rsv41| - D_op_rsv49| - D_op_rsv57| - D_op_ldb| - D_op_ldh| - D_op_ldl| - D_op_ldw| - D_op_ldbio| - D_op_ldhio| - D_op_ldwio| - D_op_rsv63| - D_op_ldbu| - D_op_ldhu| - D_op_ldbuio| - D_op_ldhuio| - D_op_initd| - D_op_initda| - D_op_flushd| - D_op_flushda| - D_op_stb| - D_op_sth| - D_op_stw| - D_op_stc| - D_op_stbio| - D_op_sthio| - D_op_stwio| - D_op_rsv61| - D_op_roli| - D_op_rsvx10| - D_op_slli| - D_op_srli| - D_op_rsvx34| - D_op_rsvx42| - D_op_rsvx50| - D_op_srai; - - assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_src2_choose_imm <= 0; - else if (R_en) - R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt; - end - - - assign D_ctrl_wrctl_inst = D_op_wrctl; - assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_wrctl_inst <= 0; - else if (R_en) - R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt; - end - - - assign D_ctrl_rdctl_inst = D_op_rdctl; - assign R_ctrl_rdctl_inst_nxt = D_ctrl_rdctl_inst; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_rdctl_inst <= 0; - else if (R_en) - R_ctrl_rdctl_inst <= R_ctrl_rdctl_inst_nxt; - end - - - assign D_ctrl_force_src2_zero = D_op_call| - D_op_rsv02| - D_op_nextpc| - D_op_callr| - D_op_trap| - D_op_rsvx44| - D_op_intr| - D_op_rsvx60| - D_op_break| - D_op_hbreak| - D_op_eret| - D_op_bret| - D_op_rsvx17| - D_op_rsvx25| - D_op_ret| - D_op_jmp| - D_op_rsvx21| - D_op_jmpi; - - assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_force_src2_zero <= 0; - else if (R_en) - R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt; - end - - - assign D_ctrl_alu_force_xor = D_op_cmpgei| - D_op_cmpgeui| - D_op_cmpeqi| - D_op_cmpge| - D_op_cmpgeu| - D_op_cmpeq| - D_op_cmpnei| - D_op_cmpne| - D_op_bge| - D_op_rsv10| - D_op_bgeu| - D_op_rsv42| - D_op_beq| - D_op_rsv34| - D_op_bne| - D_op_rsv62| - D_op_br| - D_op_rsv02; - - assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_alu_force_xor <= 0; - else if (R_en) - R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt; - end - - - //data_master, which is an e_avalon_master - //instruction_master, which is an e_avalon_master - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - assign F_inst = (F_op_call)? 56'h20202063616c6c : - (F_op_jmpi)? 56'h2020206a6d7069 : - (F_op_ldbu)? 56'h2020206c646275 : - (F_op_addi)? 56'h20202061646469 : - (F_op_stb)? 56'h20202020737462 : - (F_op_br)? 56'h20202020206272 : - (F_op_ldb)? 56'h202020206c6462 : - (F_op_cmpgei)? 56'h20636d70676569 : - (F_op_ldhu)? 56'h2020206c646875 : - (F_op_andi)? 56'h202020616e6469 : - (F_op_sth)? 56'h20202020737468 : - (F_op_bge)? 56'h20202020626765 : - (F_op_ldh)? 56'h202020206c6468 : - (F_op_cmplti)? 56'h20636d706c7469 : - (F_op_initda)? 56'h20696e69746461 : - (F_op_ori)? 56'h202020206f7269 : - (F_op_stw)? 56'h20202020737477 : - (F_op_blt)? 56'h20202020626c74 : - (F_op_ldw)? 56'h202020206c6477 : - (F_op_cmpnei)? 56'h20636d706e6569 : - (F_op_flushda)? 56'h666c7573686461 : - (F_op_xori)? 56'h202020786f7269 : - (F_op_bne)? 56'h20202020626e65 : - (F_op_cmpeqi)? 56'h20636d70657169 : - (F_op_ldbuio)? 56'h206c646275696f : - (F_op_muli)? 56'h2020206d756c69 : - (F_op_stbio)? 56'h2020737462696f : - (F_op_beq)? 56'h20202020626571 : - (F_op_ldbio)? 56'h20206c6462696f : - (F_op_cmpgeui)? 56'h636d7067657569 : - (F_op_ldhuio)? 56'h206c646875696f : - (F_op_andhi)? 56'h2020616e646869 : - (F_op_sthio)? 56'h2020737468696f : - (F_op_bgeu)? 56'h20202062676575 : - (F_op_ldhio)? 56'h20206c6468696f : - (F_op_cmpltui)? 56'h636d706c747569 : - (F_op_initd)? 56'h2020696e697464 : - (F_op_orhi)? 56'h2020206f726869 : - (F_op_stwio)? 56'h2020737477696f : - (F_op_bltu)? 56'h202020626c7475 : - (F_op_ldwio)? 56'h20206c6477696f : - (F_op_flushd)? 56'h20666c75736864 : - (F_op_xorhi)? 56'h2020786f726869 : - (F_op_eret)? 56'h20202065726574 : - (F_op_roli)? 56'h202020726f6c69 : - (F_op_rol)? 56'h20202020726f6c : - (F_op_flushp)? 56'h20666c75736870 : - (F_op_ret)? 56'h20202020726574 : - (F_op_nor)? 56'h202020206e6f72 : - (F_op_mulxuu)? 56'h206d756c787575 : - (F_op_cmpge)? 56'h2020636d706765 : - (F_op_bret)? 56'h20202062726574 : - (F_op_ror)? 56'h20202020726f72 : - (F_op_flushi)? 56'h20666c75736869 : - (F_op_jmp)? 56'h202020206a6d70 : - (F_op_and)? 56'h20202020616e64 : - (F_op_cmplt)? 56'h2020636d706c74 : - (F_op_slli)? 56'h202020736c6c69 : - (F_op_sll)? 56'h20202020736c6c : - (F_op_or)? 56'h20202020206f72 : - (F_op_mulxsu)? 56'h206d756c787375 : - (F_op_cmpne)? 56'h2020636d706e65 : - (F_op_srli)? 56'h20202073726c69 : - (F_op_srl)? 56'h2020202073726c : - (F_op_nextpc)? 56'h206e6578747063 : - (F_op_callr)? 56'h202063616c6c72 : - (F_op_xor)? 56'h20202020786f72 : - (F_op_mulxss)? 56'h206d756c787373 : - (F_op_cmpeq)? 56'h2020636d706571 : - (F_op_divu)? 56'h20202064697675 : - (F_op_div)? 56'h20202020646976 : - (F_op_rdctl)? 56'h2020726463746c : - (F_op_mul)? 56'h202020206d756c : - (F_op_cmpgeu)? 56'h20636d70676575 : - (F_op_initi)? 56'h2020696e697469 : - (F_op_trap)? 56'h20202074726170 : - (F_op_wrctl)? 56'h2020777263746c : - (F_op_cmpltu)? 56'h20636d706c7475 : - (F_op_add)? 56'h20202020616464 : - (F_op_break)? 56'h2020627265616b : - (F_op_hbreak)? 56'h2068627265616b : - (F_op_sync)? 56'h20202073796e63 : - (F_op_sub)? 56'h20202020737562 : - (F_op_srai)? 56'h20202073726169 : - (F_op_sra)? 56'h20202020737261 : - (F_op_intr)? 56'h202020696e7472 : - 56'h20202020424144; - - assign D_inst = (D_op_call)? 56'h20202063616c6c : - (D_op_jmpi)? 56'h2020206a6d7069 : - (D_op_ldbu)? 56'h2020206c646275 : - (D_op_addi)? 56'h20202061646469 : - (D_op_stb)? 56'h20202020737462 : - (D_op_br)? 56'h20202020206272 : - (D_op_ldb)? 56'h202020206c6462 : - (D_op_cmpgei)? 56'h20636d70676569 : - (D_op_ldhu)? 56'h2020206c646875 : - (D_op_andi)? 56'h202020616e6469 : - (D_op_sth)? 56'h20202020737468 : - (D_op_bge)? 56'h20202020626765 : - (D_op_ldh)? 56'h202020206c6468 : - (D_op_cmplti)? 56'h20636d706c7469 : - (D_op_initda)? 56'h20696e69746461 : - (D_op_ori)? 56'h202020206f7269 : - (D_op_stw)? 56'h20202020737477 : - (D_op_blt)? 56'h20202020626c74 : - (D_op_ldw)? 56'h202020206c6477 : - (D_op_cmpnei)? 56'h20636d706e6569 : - (D_op_flushda)? 56'h666c7573686461 : - (D_op_xori)? 56'h202020786f7269 : - (D_op_bne)? 56'h20202020626e65 : - (D_op_cmpeqi)? 56'h20636d70657169 : - (D_op_ldbuio)? 56'h206c646275696f : - (D_op_muli)? 56'h2020206d756c69 : - (D_op_stbio)? 56'h2020737462696f : - (D_op_beq)? 56'h20202020626571 : - (D_op_ldbio)? 56'h20206c6462696f : - (D_op_cmpgeui)? 56'h636d7067657569 : - (D_op_ldhuio)? 56'h206c646875696f : - (D_op_andhi)? 56'h2020616e646869 : - (D_op_sthio)? 56'h2020737468696f : - (D_op_bgeu)? 56'h20202062676575 : - (D_op_ldhio)? 56'h20206c6468696f : - (D_op_cmpltui)? 56'h636d706c747569 : - (D_op_initd)? 56'h2020696e697464 : - (D_op_orhi)? 56'h2020206f726869 : - (D_op_stwio)? 56'h2020737477696f : - (D_op_bltu)? 56'h202020626c7475 : - (D_op_ldwio)? 56'h20206c6477696f : - (D_op_flushd)? 56'h20666c75736864 : - (D_op_xorhi)? 56'h2020786f726869 : - (D_op_eret)? 56'h20202065726574 : - (D_op_roli)? 56'h202020726f6c69 : - (D_op_rol)? 56'h20202020726f6c : - (D_op_flushp)? 56'h20666c75736870 : - (D_op_ret)? 56'h20202020726574 : - (D_op_nor)? 56'h202020206e6f72 : - (D_op_mulxuu)? 56'h206d756c787575 : - (D_op_cmpge)? 56'h2020636d706765 : - (D_op_bret)? 56'h20202062726574 : - (D_op_ror)? 56'h20202020726f72 : - (D_op_flushi)? 56'h20666c75736869 : - (D_op_jmp)? 56'h202020206a6d70 : - (D_op_and)? 56'h20202020616e64 : - (D_op_cmplt)? 56'h2020636d706c74 : - (D_op_slli)? 56'h202020736c6c69 : - (D_op_sll)? 56'h20202020736c6c : - (D_op_or)? 56'h20202020206f72 : - (D_op_mulxsu)? 56'h206d756c787375 : - (D_op_cmpne)? 56'h2020636d706e65 : - (D_op_srli)? 56'h20202073726c69 : - (D_op_srl)? 56'h2020202073726c : - (D_op_nextpc)? 56'h206e6578747063 : - (D_op_callr)? 56'h202063616c6c72 : - (D_op_xor)? 56'h20202020786f72 : - (D_op_mulxss)? 56'h206d756c787373 : - (D_op_cmpeq)? 56'h2020636d706571 : - (D_op_divu)? 56'h20202064697675 : - (D_op_div)? 56'h20202020646976 : - (D_op_rdctl)? 56'h2020726463746c : - (D_op_mul)? 56'h202020206d756c : - (D_op_cmpgeu)? 56'h20636d70676575 : - (D_op_initi)? 56'h2020696e697469 : - (D_op_trap)? 56'h20202074726170 : - (D_op_wrctl)? 56'h2020777263746c : - (D_op_cmpltu)? 56'h20636d706c7475 : - (D_op_add)? 56'h20202020616464 : - (D_op_break)? 56'h2020627265616b : - (D_op_hbreak)? 56'h2068627265616b : - (D_op_sync)? 56'h20202073796e63 : - (D_op_sub)? 56'h20202020737562 : - (D_op_srai)? 56'h20202073726169 : - (D_op_sra)? 56'h20202020737261 : - (D_op_intr)? 56'h202020696e7472 : - 56'h20202020424144; - - assign F_vinst = F_valid ? F_inst : {7{8'h2d}}; - assign D_vinst = D_valid ? D_inst : {7{8'h2d}}; - assign R_vinst = R_valid ? D_inst : {7{8'h2d}}; - assign E_vinst = E_valid ? D_inst : {7{8'h2d}}; - assign W_vinst = W_valid ? D_inst : {7{8'h2d}}; - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on - -endmodule - diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v b/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v deleted file mode 100644 index 7daaec7..0000000 --- a/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v +++ /dev/null @@ -1,181 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_jtag_debug_module_sysclk ( - // inputs: - clk, - ir_in, - sr, - vs_udr, - vs_uir, - - // outputs: - jdo, - take_action_break_a, - take_action_break_b, - take_action_break_c, - take_action_ocimem_a, - take_action_ocimem_b, - take_action_tracectrl, - take_action_tracemem_a, - take_action_tracemem_b, - take_no_action_break_a, - take_no_action_break_b, - take_no_action_break_c, - take_no_action_ocimem_a, - take_no_action_tracemem_a - ) -; - - output [ 37: 0] jdo; - output take_action_break_a; - output take_action_break_b; - output take_action_break_c; - output take_action_ocimem_a; - output take_action_ocimem_b; - output take_action_tracectrl; - output take_action_tracemem_a; - output take_action_tracemem_b; - output take_no_action_break_a; - output take_no_action_break_b; - output take_no_action_break_c; - output take_no_action_ocimem_a; - output take_no_action_tracemem_a; - input clk; - input [ 1: 0] ir_in; - input [ 37: 0] sr; - input vs_udr; - input vs_uir; - - reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; - reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; - reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; - reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; - wire sync_udr; - wire sync_uir; - wire take_action_break_a; - wire take_action_break_b; - wire take_action_break_c; - wire take_action_ocimem_a; - wire take_action_ocimem_b; - wire take_action_tracectrl; - wire take_action_tracemem_a; - wire take_action_tracemem_b; - wire take_no_action_break_a; - wire take_no_action_break_b; - wire take_no_action_break_c; - wire take_no_action_ocimem_a; - wire take_no_action_tracemem_a; - wire unxunused_resetxx3; - wire unxunused_resetxx4; - reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; - assign unxunused_resetxx3 = 1'b1; - altera_std_synchronizer the_altera_std_synchronizer3 - ( - .clk (clk), - .din (vs_udr), - .dout (sync_udr), - .reset_n (unxunused_resetxx3) - ); - - defparam the_altera_std_synchronizer3.depth = 2; - - assign unxunused_resetxx4 = 1'b1; - altera_std_synchronizer the_altera_std_synchronizer4 - ( - .clk (clk), - .din (vs_uir), - .dout (sync_uir), - .reset_n (unxunused_resetxx4) - ); - - defparam the_altera_std_synchronizer4.depth = 2; - - always @(posedge clk) - begin - sync2_udr <= sync_udr; - update_jdo_strobe <= sync_udr & ~sync2_udr; - enable_action_strobe <= update_jdo_strobe; - sync2_uir <= sync_uir; - jxuir <= sync_uir & ~sync2_uir; - end - - - assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && - ~jdo[35] && jdo[34]; - - assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && - ~jdo[35] && ~jdo[34]; - - assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) && - jdo[35]; - - assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) && - ~jdo[37] && - jdo[36]; - - assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) && - ~jdo[37] && - ~jdo[36]; - - assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) && - jdo[37]; - - assign take_action_break_a = enable_action_strobe && (ir == 2'b10) && - ~jdo[36] && - jdo[37]; - - assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) && - ~jdo[36] && - ~jdo[37]; - - assign take_action_break_b = enable_action_strobe && (ir == 2'b10) && - jdo[36] && ~jdo[35] && - jdo[37]; - - assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) && - jdo[36] && ~jdo[35] && - ~jdo[37]; - - assign take_action_break_c = enable_action_strobe && (ir == 2'b10) && - jdo[36] && jdo[35] && - jdo[37]; - - assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) && - jdo[36] && jdo[35] && - ~jdo[37]; - - assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) && - jdo[15]; - - always @(posedge clk) - begin - if (jxuir) - ir <= ir_in; - if (update_jdo_strobe) - jdo <= sr; - end - - - -endmodule - diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v b/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v deleted file mode 100644 index 8e3a593..0000000 --- a/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v +++ /dev/null @@ -1,239 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_jtag_debug_module_tck ( - // inputs: - MonDReg, - break_readreg, - dbrk_hit0_latch, - dbrk_hit1_latch, - dbrk_hit2_latch, - dbrk_hit3_latch, - debugack, - ir_in, - jtag_state_rti, - monitor_error, - monitor_ready, - reset_n, - resetlatch, - tck, - tdi, - tracemem_on, - tracemem_trcdata, - tracemem_tw, - trc_im_addr, - trc_on, - trc_wrap, - trigbrktype, - trigger_state_1, - vs_cdr, - vs_sdr, - vs_uir, - - // outputs: - ir_out, - jrst_n, - sr, - st_ready_test_idle, - tdo - ) -; - - output [ 1: 0] ir_out; - output jrst_n; - output [ 37: 0] sr; - output st_ready_test_idle; - output tdo; - input [ 31: 0] MonDReg; - input [ 31: 0] break_readreg; - input dbrk_hit0_latch; - input dbrk_hit1_latch; - input dbrk_hit2_latch; - input dbrk_hit3_latch; - input debugack; - input [ 1: 0] ir_in; - input jtag_state_rti; - input monitor_error; - input monitor_ready; - input reset_n; - input resetlatch; - input tck; - input tdi; - input tracemem_on; - input [ 35: 0] tracemem_trcdata; - input tracemem_tw; - input [ 6: 0] trc_im_addr; - input trc_on; - input trc_wrap; - input trigbrktype; - input trigger_state_1; - input vs_cdr; - input vs_sdr; - input vs_uir; - - reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire debugack_sync; - reg [ 1: 0] ir_out; - wire jrst_n; - wire monitor_ready_sync; - reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire st_ready_test_idle; - wire tdo; - wire unxcomplemented_resetxx1; - wire unxcomplemented_resetxx2; - always @(posedge tck) - begin - if (vs_cdr) - case (ir_in) - - 2'b00: begin - sr[35] <= debugack_sync; - sr[34] <= monitor_error; - sr[33] <= resetlatch; - sr[32 : 1] <= MonDReg; - sr[0] <= monitor_ready_sync; - end // 2'b00 - - 2'b01: begin - sr[35 : 0] <= tracemem_trcdata; - sr[37] <= tracemem_tw; - sr[36] <= tracemem_on; - end // 2'b01 - - 2'b10: begin - sr[37] <= trigger_state_1; - sr[36] <= dbrk_hit3_latch; - sr[35] <= dbrk_hit2_latch; - sr[34] <= dbrk_hit1_latch; - sr[33] <= dbrk_hit0_latch; - sr[32 : 1] <= break_readreg; - sr[0] <= trigbrktype; - end // 2'b10 - - 2'b11: begin - sr[15 : 12] <= 1'b0; - sr[11 : 2] <= trc_im_addr; - sr[1] <= trc_wrap; - sr[0] <= trc_on; - end // 2'b11 - - endcase // ir_in - if (vs_sdr) - case (DRsize) - - 3'b000: begin - sr <= {tdi, sr[37 : 2], tdi}; - end // 3'b000 - - 3'b001: begin - sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]}; - end // 3'b001 - - 3'b010: begin - sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]}; - end // 3'b010 - - 3'b011: begin - sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]}; - end // 3'b011 - - 3'b100: begin - sr <= {tdi, sr[37], tdi, sr[35 : 1]}; - end // 3'b100 - - 3'b101: begin - sr <= {tdi, sr[37 : 1]}; - end // 3'b101 - - default: begin - sr <= {tdi, sr[37 : 2], tdi}; - end // default - - endcase // DRsize - if (vs_uir) - case (ir_in) - - 2'b00: begin - DRsize <= 3'b100; - end // 2'b00 - - 2'b01: begin - DRsize <= 3'b101; - end // 2'b01 - - 2'b10: begin - DRsize <= 3'b101; - end // 2'b10 - - 2'b11: begin - DRsize <= 3'b010; - end // 2'b11 - - endcase // ir_in - end - - - assign tdo = sr[0]; - assign st_ready_test_idle = jtag_state_rti; - assign unxcomplemented_resetxx1 = jrst_n; - altera_std_synchronizer the_altera_std_synchronizer1 - ( - .clk (tck), - .din (debugack), - .dout (debugack_sync), - .reset_n (unxcomplemented_resetxx1) - ); - - defparam the_altera_std_synchronizer1.depth = 2; - - assign unxcomplemented_resetxx2 = jrst_n; - altera_std_synchronizer the_altera_std_synchronizer2 - ( - .clk (tck), - .din (monitor_ready), - .dout (monitor_ready_sync), - .reset_n (unxcomplemented_resetxx2) - ); - - defparam the_altera_std_synchronizer2.depth = 2; - - always @(posedge tck or negedge jrst_n) - begin - if (jrst_n == 0) - ir_out <= 2'b0; - else - ir_out <= {debugack_sync, monitor_ready_sync}; - end - - - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - assign jrst_n = reset_n; - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on -//synthesis read_comments_as_HDL on -// assign jrst_n = 1; -//synthesis read_comments_as_HDL off - -endmodule - diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v b/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v deleted file mode 100644 index 1fd5cb7..0000000 --- a/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v +++ /dev/null @@ -1,233 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_jtag_debug_module_wrapper ( - // inputs: - MonDReg, - break_readreg, - clk, - dbrk_hit0_latch, - dbrk_hit1_latch, - dbrk_hit2_latch, - dbrk_hit3_latch, - debugack, - monitor_error, - monitor_ready, - reset_n, - resetlatch, - tracemem_on, - tracemem_trcdata, - tracemem_tw, - trc_im_addr, - trc_on, - trc_wrap, - trigbrktype, - trigger_state_1, - - // outputs: - jdo, - jrst_n, - st_ready_test_idle, - take_action_break_a, - take_action_break_b, - take_action_break_c, - take_action_ocimem_a, - take_action_ocimem_b, - take_action_tracectrl, - take_action_tracemem_a, - take_action_tracemem_b, - take_no_action_break_a, - take_no_action_break_b, - take_no_action_break_c, - take_no_action_ocimem_a, - take_no_action_tracemem_a - ) -; - - output [ 37: 0] jdo; - output jrst_n; - output st_ready_test_idle; - output take_action_break_a; - output take_action_break_b; - output take_action_break_c; - output take_action_ocimem_a; - output take_action_ocimem_b; - output take_action_tracectrl; - output take_action_tracemem_a; - output take_action_tracemem_b; - output take_no_action_break_a; - output take_no_action_break_b; - output take_no_action_break_c; - output take_no_action_ocimem_a; - output take_no_action_tracemem_a; - input [ 31: 0] MonDReg; - input [ 31: 0] break_readreg; - input clk; - input dbrk_hit0_latch; - input dbrk_hit1_latch; - input dbrk_hit2_latch; - input dbrk_hit3_latch; - input debugack; - input monitor_error; - input monitor_ready; - input reset_n; - input resetlatch; - input tracemem_on; - input [ 35: 0] tracemem_trcdata; - input tracemem_tw; - input [ 6: 0] trc_im_addr; - input trc_on; - input trc_wrap; - input trigbrktype; - input trigger_state_1; - - wire [ 37: 0] jdo; - wire jrst_n; - wire [ 37: 0] sr; - wire st_ready_test_idle; - wire take_action_break_a; - wire take_action_break_b; - wire take_action_break_c; - wire take_action_ocimem_a; - wire take_action_ocimem_b; - wire take_action_tracectrl; - wire take_action_tracemem_a; - wire take_action_tracemem_b; - wire take_no_action_break_a; - wire take_no_action_break_b; - wire take_no_action_break_c; - wire take_no_action_ocimem_a; - wire take_no_action_tracemem_a; - wire vji_cdr; - wire [ 1: 0] vji_ir_in; - wire [ 1: 0] vji_ir_out; - wire vji_rti; - wire vji_sdr; - wire vji_tck; - wire vji_tdi; - wire vji_tdo; - wire vji_udr; - wire vji_uir; - //Change the sld_virtual_jtag_basic's defparams to - //switch between a regular Nios II or an internally embedded Nios II. - //For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34. - //For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135. - nios_system_nios2_processor_jtag_debug_module_tck the_nios_system_nios2_processor_jtag_debug_module_tck - ( - .MonDReg (MonDReg), - .break_readreg (break_readreg), - .dbrk_hit0_latch (dbrk_hit0_latch), - .dbrk_hit1_latch (dbrk_hit1_latch), - .dbrk_hit2_latch (dbrk_hit2_latch), - .dbrk_hit3_latch (dbrk_hit3_latch), - .debugack (debugack), - .ir_in (vji_ir_in), - .ir_out (vji_ir_out), - .jrst_n (jrst_n), - .jtag_state_rti (vji_rti), - .monitor_error (monitor_error), - .monitor_ready (monitor_ready), - .reset_n (reset_n), - .resetlatch (resetlatch), - .sr (sr), - .st_ready_test_idle (st_ready_test_idle), - .tck (vji_tck), - .tdi (vji_tdi), - .tdo (vji_tdo), - .tracemem_on (tracemem_on), - .tracemem_trcdata (tracemem_trcdata), - .tracemem_tw (tracemem_tw), - .trc_im_addr (trc_im_addr), - .trc_on (trc_on), - .trc_wrap (trc_wrap), - .trigbrktype (trigbrktype), - .trigger_state_1 (trigger_state_1), - .vs_cdr (vji_cdr), - .vs_sdr (vji_sdr), - .vs_uir (vji_uir) - ); - - nios_system_nios2_processor_jtag_debug_module_sysclk the_nios_system_nios2_processor_jtag_debug_module_sysclk - ( - .clk (clk), - .ir_in (vji_ir_in), - .jdo (jdo), - .sr (sr), - .take_action_break_a (take_action_break_a), - .take_action_break_b (take_action_break_b), - .take_action_break_c (take_action_break_c), - .take_action_ocimem_a (take_action_ocimem_a), - .take_action_ocimem_b (take_action_ocimem_b), - .take_action_tracectrl (take_action_tracectrl), - .take_action_tracemem_a (take_action_tracemem_a), - .take_action_tracemem_b (take_action_tracemem_b), - .take_no_action_break_a (take_no_action_break_a), - .take_no_action_break_b (take_no_action_break_b), - .take_no_action_break_c (take_no_action_break_c), - .take_no_action_ocimem_a (take_no_action_ocimem_a), - .take_no_action_tracemem_a (take_no_action_tracemem_a), - .vs_udr (vji_udr), - .vs_uir (vji_uir) - ); - - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - assign vji_tck = 1'b0; - assign vji_tdi = 1'b0; - assign vji_sdr = 1'b0; - assign vji_cdr = 1'b0; - assign vji_rti = 1'b0; - assign vji_uir = 1'b0; - assign vji_udr = 1'b0; - assign vji_ir_in = 2'b0; - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on -//synthesis read_comments_as_HDL on -// sld_virtual_jtag_basic nios_system_nios2_processor_jtag_debug_module_phy -// ( -// .ir_in (vji_ir_in), -// .ir_out (vji_ir_out), -// .jtag_state_rti (vji_rti), -// .tck (vji_tck), -// .tdi (vji_tdi), -// .tdo (vji_tdo), -// .virtual_state_cdr (vji_cdr), -// .virtual_state_sdr (vji_sdr), -// .virtual_state_udr (vji_udr), -// .virtual_state_uir (vji_uir) -// ); -// -// defparam nios_system_nios2_processor_jtag_debug_module_phy.sld_auto_instance_index = "YES", -// nios_system_nios2_processor_jtag_debug_module_phy.sld_instance_index = 0, -// nios_system_nios2_processor_jtag_debug_module_phy.sld_ir_width = 2, -// nios_system_nios2_processor_jtag_debug_module_phy.sld_mfg_id = 70, -// nios_system_nios2_processor_jtag_debug_module_phy.sld_sim_action = "", -// nios_system_nios2_processor_jtag_debug_module_phy.sld_sim_n_scan = 0, -// nios_system_nios2_processor_jtag_debug_module_phy.sld_sim_total_length = 0, -// nios_system_nios2_processor_jtag_debug_module_phy.sld_type_id = 34, -// nios_system_nios2_processor_jtag_debug_module_phy.sld_version = 3; -// -//synthesis read_comments_as_HDL off - -endmodule - diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor_oci_test_bench.v b/nios_system/synthesis/submodules/nios_system_nios2_processor_oci_test_bench.v deleted file mode 100644 index 0046686..0000000 --- a/nios_system/synthesis/submodules/nios_system_nios2_processor_oci_test_bench.v +++ /dev/null @@ -1,37 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_oci_test_bench ( - // inputs: - dct_buffer, - dct_count, - test_ending, - test_has_ended - ) -; - - input [ 29: 0] dct_buffer; - input [ 3: 0] dct_count; - input test_ending; - input test_has_ended; - - -endmodule - diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor_ociram_default_contents.mif b/nios_system/synthesis/submodules/nios_system_nios2_processor_ociram_default_contents.mif deleted file mode 100644 index 44481aa..0000000 --- a/nios_system/synthesis/submodules/nios_system_nios2_processor_ociram_default_contents.mif +++ /dev/null @@ -1,267 +0,0 @@ --- Contents are randomly generated during RTL generation. -WIDTH=32; -DEPTH=256; - -ADDRESS_RADIX=HEX; -DATA_RADIX=HEX; - -CONTENT BEGIN - -00 : 88997af9; -01 : abaae595; -02 : 32fd14d1; -03 : b66193c4; -04 : c6a6aa09; -05 : 0b43de5b; -06 : d1d93028; -07 : bcd08e2a; -08 : 1c8bae85; -09 : b11dad63; -0a : 864ddf62; -0b : 68301486; -0c : 51a3d8d0; -0d : 7af7d39e; -0e : 4761b503; -0f : 2a976e14; -10 : 98141041; -11 : 4c1f6471; -12 : 41dc0a35; -13 : 7d484ae3; -14 : 2a1329f3; -15 : 44ecf499; -16 : dccdd125; -17 : 240142e9; -18 : 3b7e4b05; -19 : bb92e762; -1a : 4594a3c5; -1b : ea0d940f; -1c : 66525d7c; -1d : 0f552242; -1e : 452bd52d; -1f : d1f4ed11; -20 : 5d590422; -21 : c8016b5f; -22 : 9ab94f07; -23 : 16bac9b4; -24 : fe569ae3; -25 : c6e1e6e7; -26 : 2ff19932; -27 : feb058ad; -28 : 1dcce651; -29 : e18b9bfb; -2a : e2f4fc64; -2b : 05d34847; -2c : 077a8143; -2d : 2ce4207f; -2e : 3f3e5113; -2f : c24d2803; -30 : e289b503; -31 : d16bcd4e; -32 : 57a841cf; -33 : 1194f754; -34 : 5c925a31; -35 : 40fd6946; -36 : e397e5d7; -37 : eada7553; -38 : eba8ec01; -39 : f5b39d0b; -3a : 88af39a3; -3b : 5b7f243e; -3c : 4f2bb4ba; -3d : 9451a234; -3e : 10fd984d; -3f : ad4ef4f7; -40 : 7fe97f8b; -41 : 08ea614d; -42 : 9f2c5cf4; -43 : 3f90b7a2; -44 : 8c2bc774; -45 : 45dd63a5; -46 : 3204329c; -47 : 9909be0d; -48 : be65c97b; -49 : 78f3d4a4; -4a : 3ee8b71c; -4b : 9e9a0de4; -4c : 56db426b; -4d : e6869d81; -4e : 20ab0652; -4f : 05d247ed; -50 : 1edccf12; -51 : 1e483b5a; -52 : 8e48ef1e; -53 : f19aefbf; -54 : 98335d23; -55 : 954ac923; -56 : 4679ced6; -57 : ae18d9b8; -58 : be57db48; -59 : 2af933e3; -5a : 3f04e244; -5b : 5d11c958; -5c : 65bda8cb; -5d : c53fe664; -5e : 797ceac8; -5f : aaa406e5; -60 : f785e24e; -61 : 95510077; -62 : 5b6f55a3; -63 : 2a3c749a; -64 : a92e6ae6; -65 : b2117fb0; -66 : 262a254e; -67 : b8c4da74; -68 : f69070ee; -69 : 9e7f80b8; -6a : 834528b4; -6b : 4aaf6d98; -6c : 96023372; -6d : d11663ed; -6e : 33a3c007; -6f : 0e7f06ee; -70 : 34385787; -71 : 2edfd7b0; -72 : 00d60e4b; -73 : 49535c30; -74 : e83f5c14; -75 : 5e0c4c59; -76 : 1d7b944a; -77 : 6ae69731; -78 : bf8414e4; -79 : 7451c212; -7a : 74ede6d2; -7b : 080eafa5; -7c : f21052d8; -7d : cc0819fb; -7e : 8993e5b6; -7f : e20f2df6; -80 : 0f267a65; -81 : 7a8e8407; -82 : e7be656d; -83 : 01ba4ca3; -84 : 7f998e44; -85 : 29d83420; -86 : 149f9a73; -87 : 643ae51e; -88 : 125714d3; -89 : 6e49dc21; -8a : 0b227946; -8b : 360a837d; -8c : b2187074; -8d : 17b0bdbd; -8e : 938fc73d; -8f : e73f501e; -90 : 70b5b87e; -91 : 2a2aed8a; -92 : f96cc881; -93 : 021b49e1; -94 : 8691600d; -95 : b45e1d12; -96 : 64d9644e; -97 : 486cbaf9; -98 : 386acf20; -99 : 0d1384d4; -9a : 62455f77; -9b : 866fde20; -9c : 006fecec; -9d : 94e84514; -9e : 7babc333; -9f : afaa8445; -a0 : b1175e3a; -a1 : e08de629; -a2 : 7f12a52d; -a3 : 0e322909; -a4 : 18784dc6; -a5 : b23bcc20; -a6 : 266c9e34; -a7 : c857eaf3; -a8 : 2ae3b164; -a9 : 038acf2a; -aa : c1abc60d; -ab : 8af787bd; -ac : 043723a9; -ad : c37c952d; -ae : 693a361f; -af : da4b8e99; -b0 : fb8fdb10; -b1 : 4d6365f2; -b2 : 712358e9; -b3 : 85dae0fa; -b4 : 7e82a418; -b5 : d3493768; -b6 : 739c65ec; -b7 : 73b66b19; -b8 : 22142816; -b9 : ff498322; -ba : 3266495e; -bb : e26e8214; -bc : c8c47131; -bd : 660793d8; -be : 689f8d69; -bf : faae340b; -c0 : 37518ba7; -c1 : f2865fe5; -c2 : 1bb44f3d; -c3 : 3bce44c5; -c4 : aff2d188; -c5 : 985442da; -c6 : 85bb58bd; -c7 : 0c53135d; -c8 : 495f80bc; -c9 : 853c95dc; -ca : dde937f1; -cb : 418f9452; -cc : 7669641c; -cd : 0e752434; -ce : b0fe17a7; -cf : d1be9b88; -d0 : cfbfeb76; -d1 : 80b48a11; -d2 : 9327c69e; -d3 : beca5a88; -d4 : e71d428f; -d5 : b318d275; -d6 : 56fea35e; -d7 : 140cd6bd; -d8 : b8c937ce; -d9 : 540eea36; -da : ee58fc7f; -db : 5615c389; -dc : 46692ad0; -dd : 5c713e51; -de : 6ba95f60; -df : 0e166732; -e0 : ac0e49f5; -e1 : c9a5ea76; -e2 : 05b04d86; -e3 : b29ac712; -e4 : 4e344493; -e5 : d45ede48; -e6 : 3da7e426; -e7 : 4d6a8937; -e8 : 99b59bd4; -e9 : 1f8a5751; -ea : 8b07e64e; -eb : b4dcd496; -ec : 42f84fe6; -ed : f1d5952f; -ee : a2e5a42d; -ef : 15b1af16; -f0 : 168012bc; -f1 : 2e276612; -f2 : 89913eaa; -f3 : c607a1a2; -f4 : fd8b544d; -f5 : aec31a53; -f6 : 25f958ad; -f7 : 365903ec; -f8 : 14761865; -f9 : 568cc23b; -fa : b0386305; -fb : fb9ebd8a; -fc : a25911d4; -fd : 806e3fbb; -fe : 9df35264; -ff : d62b3814; - -END; diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor_rf_ram_a.mif b/nios_system/synthesis/submodules/nios_system_nios2_processor_rf_ram_a.mif deleted file mode 100644 index 7969f10..0000000 --- a/nios_system/synthesis/submodules/nios_system_nios2_processor_rf_ram_a.mif +++ /dev/null @@ -1,42 +0,0 @@ -WIDTH=32; -DEPTH=32; - -ADDRESS_RADIX=HEX; -DATA_RADIX=HEX; - -CONTENT BEGIN - -00 : deadbeef; -01 : deadbeef; -02 : deadbeef; -03 : deadbeef; -04 : deadbeef; -05 : deadbeef; -06 : deadbeef; -07 : deadbeef; -08 : deadbeef; -09 : deadbeef; -0a : deadbeef; -0b : deadbeef; -0c : deadbeef; -0d : deadbeef; -0e : deadbeef; -0f : deadbeef; -10 : deadbeef; -11 : deadbeef; -12 : deadbeef; -13 : deadbeef; -14 : deadbeef; -15 : deadbeef; -16 : deadbeef; -17 : deadbeef; -18 : deadbeef; -19 : deadbeef; -1a : deadbeef; -1b : deadbeef; -1c : deadbeef; -1d : deadbeef; -1e : deadbeef; -1f : deadbeef; - -END; diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor_rf_ram_b.mif b/nios_system/synthesis/submodules/nios_system_nios2_processor_rf_ram_b.mif deleted file mode 100644 index 7969f10..0000000 --- a/nios_system/synthesis/submodules/nios_system_nios2_processor_rf_ram_b.mif +++ /dev/null @@ -1,42 +0,0 @@ -WIDTH=32; -DEPTH=32; - -ADDRESS_RADIX=HEX; -DATA_RADIX=HEX; - -CONTENT BEGIN - -00 : deadbeef; -01 : deadbeef; -02 : deadbeef; -03 : deadbeef; -04 : deadbeef; -05 : deadbeef; -06 : deadbeef; -07 : deadbeef; -08 : deadbeef; -09 : deadbeef; -0a : deadbeef; -0b : deadbeef; -0c : deadbeef; -0d : deadbeef; -0e : deadbeef; -0f : deadbeef; -10 : deadbeef; -11 : deadbeef; -12 : deadbeef; -13 : deadbeef; -14 : deadbeef; -15 : deadbeef; -16 : deadbeef; -17 : deadbeef; -18 : deadbeef; -19 : deadbeef; -1a : deadbeef; -1b : deadbeef; -1c : deadbeef; -1d : deadbeef; -1e : deadbeef; -1f : deadbeef; - -END; diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor_test_bench.v b/nios_system/synthesis/submodules/nios_system_nios2_processor_test_bench.v deleted file mode 100644 index 9ce093e..0000000 --- a/nios_system/synthesis/submodules/nios_system_nios2_processor_test_bench.v +++ /dev/null @@ -1,667 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_test_bench ( - // inputs: - D_iw, - D_iw_op, - D_iw_opx, - D_valid, - E_valid, - F_pcb, - F_valid, - R_ctrl_ld, - R_ctrl_ld_non_io, - R_dst_regnum, - R_wr_dst_reg, - W_valid, - W_vinst, - W_wr_data, - av_ld_data_aligned_unfiltered, - clk, - d_address, - d_byteenable, - d_read, - d_write_nxt, - i_address, - i_read, - i_readdata, - i_waitrequest, - reset_n, - - // outputs: - av_ld_data_aligned_filtered, - d_write, - test_has_ended - ) -; - - output [ 31: 0] av_ld_data_aligned_filtered; - output d_write; - output test_has_ended; - input [ 31: 0] D_iw; - input [ 5: 0] D_iw_op; - input [ 5: 0] D_iw_opx; - input D_valid; - input E_valid; - input [ 18: 0] F_pcb; - input F_valid; - input R_ctrl_ld; - input R_ctrl_ld_non_io; - input [ 4: 0] R_dst_regnum; - input R_wr_dst_reg; - input W_valid; - input [ 55: 0] W_vinst; - input [ 31: 0] W_wr_data; - input [ 31: 0] av_ld_data_aligned_unfiltered; - input clk; - input [ 18: 0] d_address; - input [ 3: 0] d_byteenable; - input d_read; - input d_write_nxt; - input [ 18: 0] i_address; - input i_read; - input [ 31: 0] i_readdata; - input i_waitrequest; - input reset_n; - - wire D_op_add; - wire D_op_addi; - wire D_op_and; - wire D_op_andhi; - wire D_op_andi; - wire D_op_beq; - wire D_op_bge; - wire D_op_bgeu; - wire D_op_blt; - wire D_op_bltu; - wire D_op_bne; - wire D_op_br; - wire D_op_break; - wire D_op_bret; - wire D_op_call; - wire D_op_callr; - wire D_op_cmpeq; - wire D_op_cmpeqi; - wire D_op_cmpge; - wire D_op_cmpgei; - wire D_op_cmpgeu; - wire D_op_cmpgeui; - wire D_op_cmplt; - wire D_op_cmplti; - wire D_op_cmpltu; - wire D_op_cmpltui; - wire D_op_cmpne; - wire D_op_cmpnei; - wire D_op_crst; - wire D_op_custom; - wire D_op_div; - wire D_op_divu; - wire D_op_eret; - wire D_op_flushd; - wire D_op_flushda; - wire D_op_flushi; - wire D_op_flushp; - wire D_op_hbreak; - wire D_op_initd; - wire D_op_initda; - wire D_op_initi; - wire D_op_intr; - wire D_op_jmp; - wire D_op_jmpi; - wire D_op_ldb; - wire D_op_ldbio; - wire D_op_ldbu; - wire D_op_ldbuio; - wire D_op_ldh; - wire D_op_ldhio; - wire D_op_ldhu; - wire D_op_ldhuio; - wire D_op_ldl; - wire D_op_ldw; - wire D_op_ldwio; - wire D_op_mul; - wire D_op_muli; - wire D_op_mulxss; - wire D_op_mulxsu; - wire D_op_mulxuu; - wire D_op_nextpc; - wire D_op_nor; - wire D_op_opx; - wire D_op_or; - wire D_op_orhi; - wire D_op_ori; - wire D_op_rdctl; - wire D_op_rdprs; - wire D_op_ret; - wire D_op_rol; - wire D_op_roli; - wire D_op_ror; - wire D_op_rsv02; - wire D_op_rsv09; - wire D_op_rsv10; - wire D_op_rsv17; - wire D_op_rsv18; - wire D_op_rsv25; - wire D_op_rsv26; - wire D_op_rsv33; - wire D_op_rsv34; - wire D_op_rsv41; - wire D_op_rsv42; - wire D_op_rsv49; - wire D_op_rsv57; - wire D_op_rsv61; - wire D_op_rsv62; - wire D_op_rsv63; - wire D_op_rsvx00; - wire D_op_rsvx10; - wire D_op_rsvx15; - wire D_op_rsvx17; - wire D_op_rsvx21; - wire D_op_rsvx25; - wire D_op_rsvx33; - wire D_op_rsvx34; - wire D_op_rsvx35; - wire D_op_rsvx42; - wire D_op_rsvx43; - wire D_op_rsvx44; - wire D_op_rsvx47; - wire D_op_rsvx50; - wire D_op_rsvx51; - wire D_op_rsvx55; - wire D_op_rsvx56; - wire D_op_rsvx60; - wire D_op_rsvx63; - wire D_op_sll; - wire D_op_slli; - wire D_op_sra; - wire D_op_srai; - wire D_op_srl; - wire D_op_srli; - wire D_op_stb; - wire D_op_stbio; - wire D_op_stc; - wire D_op_sth; - wire D_op_sthio; - wire D_op_stw; - wire D_op_stwio; - wire D_op_sub; - wire D_op_sync; - wire D_op_trap; - wire D_op_wrctl; - wire D_op_wrprs; - wire D_op_xor; - wire D_op_xorhi; - wire D_op_xori; - wire [ 31: 0] av_ld_data_aligned_filtered; - wire av_ld_data_aligned_unfiltered_0_is_x; - wire av_ld_data_aligned_unfiltered_10_is_x; - wire av_ld_data_aligned_unfiltered_11_is_x; - wire av_ld_data_aligned_unfiltered_12_is_x; - wire av_ld_data_aligned_unfiltered_13_is_x; - wire av_ld_data_aligned_unfiltered_14_is_x; - wire av_ld_data_aligned_unfiltered_15_is_x; - wire av_ld_data_aligned_unfiltered_16_is_x; - wire av_ld_data_aligned_unfiltered_17_is_x; - wire av_ld_data_aligned_unfiltered_18_is_x; - wire av_ld_data_aligned_unfiltered_19_is_x; - wire av_ld_data_aligned_unfiltered_1_is_x; - wire av_ld_data_aligned_unfiltered_20_is_x; - wire av_ld_data_aligned_unfiltered_21_is_x; - wire av_ld_data_aligned_unfiltered_22_is_x; - wire av_ld_data_aligned_unfiltered_23_is_x; - wire av_ld_data_aligned_unfiltered_24_is_x; - wire av_ld_data_aligned_unfiltered_25_is_x; - wire av_ld_data_aligned_unfiltered_26_is_x; - wire av_ld_data_aligned_unfiltered_27_is_x; - wire av_ld_data_aligned_unfiltered_28_is_x; - wire av_ld_data_aligned_unfiltered_29_is_x; - wire av_ld_data_aligned_unfiltered_2_is_x; - wire av_ld_data_aligned_unfiltered_30_is_x; - wire av_ld_data_aligned_unfiltered_31_is_x; - wire av_ld_data_aligned_unfiltered_3_is_x; - wire av_ld_data_aligned_unfiltered_4_is_x; - wire av_ld_data_aligned_unfiltered_5_is_x; - wire av_ld_data_aligned_unfiltered_6_is_x; - wire av_ld_data_aligned_unfiltered_7_is_x; - wire av_ld_data_aligned_unfiltered_8_is_x; - wire av_ld_data_aligned_unfiltered_9_is_x; - reg d_write; - wire test_has_ended; - assign D_op_call = D_iw_op == 0; - assign D_op_jmpi = D_iw_op == 1; - assign D_op_ldbu = D_iw_op == 3; - assign D_op_addi = D_iw_op == 4; - assign D_op_stb = D_iw_op == 5; - assign D_op_br = D_iw_op == 6; - assign D_op_ldb = D_iw_op == 7; - assign D_op_cmpgei = D_iw_op == 8; - assign D_op_ldhu = D_iw_op == 11; - assign D_op_andi = D_iw_op == 12; - assign D_op_sth = D_iw_op == 13; - assign D_op_bge = D_iw_op == 14; - assign D_op_ldh = D_iw_op == 15; - assign D_op_cmplti = D_iw_op == 16; - assign D_op_initda = D_iw_op == 19; - assign D_op_ori = D_iw_op == 20; - assign D_op_stw = D_iw_op == 21; - assign D_op_blt = D_iw_op == 22; - assign D_op_ldw = D_iw_op == 23; - assign D_op_cmpnei = D_iw_op == 24; - assign D_op_flushda = D_iw_op == 27; - assign D_op_xori = D_iw_op == 28; - assign D_op_stc = D_iw_op == 29; - assign D_op_bne = D_iw_op == 30; - assign D_op_ldl = D_iw_op == 31; - assign D_op_cmpeqi = D_iw_op == 32; - assign D_op_ldbuio = D_iw_op == 35; - assign D_op_muli = D_iw_op == 36; - assign D_op_stbio = D_iw_op == 37; - assign D_op_beq = D_iw_op == 38; - assign D_op_ldbio = D_iw_op == 39; - assign D_op_cmpgeui = D_iw_op == 40; - assign D_op_ldhuio = D_iw_op == 43; - assign D_op_andhi = D_iw_op == 44; - assign D_op_sthio = D_iw_op == 45; - assign D_op_bgeu = D_iw_op == 46; - assign D_op_ldhio = D_iw_op == 47; - assign D_op_cmpltui = D_iw_op == 48; - assign D_op_initd = D_iw_op == 51; - assign D_op_orhi = D_iw_op == 52; - assign D_op_stwio = D_iw_op == 53; - assign D_op_bltu = D_iw_op == 54; - assign D_op_ldwio = D_iw_op == 55; - assign D_op_rdprs = D_iw_op == 56; - assign D_op_flushd = D_iw_op == 59; - assign D_op_xorhi = D_iw_op == 60; - assign D_op_rsv02 = D_iw_op == 2; - assign D_op_rsv09 = D_iw_op == 9; - assign D_op_rsv10 = D_iw_op == 10; - assign D_op_rsv17 = D_iw_op == 17; - assign D_op_rsv18 = D_iw_op == 18; - assign D_op_rsv25 = D_iw_op == 25; - assign D_op_rsv26 = D_iw_op == 26; - assign D_op_rsv33 = D_iw_op == 33; - assign D_op_rsv34 = D_iw_op == 34; - assign D_op_rsv41 = D_iw_op == 41; - assign D_op_rsv42 = D_iw_op == 42; - assign D_op_rsv49 = D_iw_op == 49; - assign D_op_rsv57 = D_iw_op == 57; - assign D_op_rsv61 = D_iw_op == 61; - assign D_op_rsv62 = D_iw_op == 62; - assign D_op_rsv63 = D_iw_op == 63; - assign D_op_eret = D_op_opx & (D_iw_opx == 1); - assign D_op_roli = D_op_opx & (D_iw_opx == 2); - assign D_op_rol = D_op_opx & (D_iw_opx == 3); - assign D_op_flushp = D_op_opx & (D_iw_opx == 4); - assign D_op_ret = D_op_opx & (D_iw_opx == 5); - assign D_op_nor = D_op_opx & (D_iw_opx == 6); - assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7); - assign D_op_cmpge = D_op_opx & (D_iw_opx == 8); - assign D_op_bret = D_op_opx & (D_iw_opx == 9); - assign D_op_ror = D_op_opx & (D_iw_opx == 11); - assign D_op_flushi = D_op_opx & (D_iw_opx == 12); - assign D_op_jmp = D_op_opx & (D_iw_opx == 13); - assign D_op_and = D_op_opx & (D_iw_opx == 14); - assign D_op_cmplt = D_op_opx & (D_iw_opx == 16); - assign D_op_slli = D_op_opx & (D_iw_opx == 18); - assign D_op_sll = D_op_opx & (D_iw_opx == 19); - assign D_op_wrprs = D_op_opx & (D_iw_opx == 20); - assign D_op_or = D_op_opx & (D_iw_opx == 22); - assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23); - assign D_op_cmpne = D_op_opx & (D_iw_opx == 24); - assign D_op_srli = D_op_opx & (D_iw_opx == 26); - assign D_op_srl = D_op_opx & (D_iw_opx == 27); - assign D_op_nextpc = D_op_opx & (D_iw_opx == 28); - assign D_op_callr = D_op_opx & (D_iw_opx == 29); - assign D_op_xor = D_op_opx & (D_iw_opx == 30); - assign D_op_mulxss = D_op_opx & (D_iw_opx == 31); - assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32); - assign D_op_divu = D_op_opx & (D_iw_opx == 36); - assign D_op_div = D_op_opx & (D_iw_opx == 37); - assign D_op_rdctl = D_op_opx & (D_iw_opx == 38); - assign D_op_mul = D_op_opx & (D_iw_opx == 39); - assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40); - assign D_op_initi = D_op_opx & (D_iw_opx == 41); - assign D_op_trap = D_op_opx & (D_iw_opx == 45); - assign D_op_wrctl = D_op_opx & (D_iw_opx == 46); - assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48); - assign D_op_add = D_op_opx & (D_iw_opx == 49); - assign D_op_break = D_op_opx & (D_iw_opx == 52); - assign D_op_hbreak = D_op_opx & (D_iw_opx == 53); - assign D_op_sync = D_op_opx & (D_iw_opx == 54); - assign D_op_sub = D_op_opx & (D_iw_opx == 57); - assign D_op_srai = D_op_opx & (D_iw_opx == 58); - assign D_op_sra = D_op_opx & (D_iw_opx == 59); - assign D_op_intr = D_op_opx & (D_iw_opx == 61); - assign D_op_crst = D_op_opx & (D_iw_opx == 62); - assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0); - assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10); - assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15); - assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17); - assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21); - assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25); - assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33); - assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34); - assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35); - assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42); - assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43); - assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44); - assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47); - assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50); - assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51); - assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55); - assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56); - assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60); - assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63); - assign D_op_opx = D_iw_op == 58; - assign D_op_custom = D_iw_op == 50; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - d_write <= 0; - else - d_write <= d_write_nxt; - end - - - assign test_has_ended = 1'b0; - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - //Clearing 'X' data bits - assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx; - - assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0]; - assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx; - assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1]; - assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx; - assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2]; - assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx; - assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3]; - assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx; - assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4]; - assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx; - assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5]; - assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx; - assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6]; - assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx; - assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7]; - assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx; - assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8]; - assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx; - assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9]; - assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx; - assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10]; - assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx; - assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11]; - assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx; - assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12]; - assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx; - assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13]; - assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx; - assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14]; - assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx; - assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15]; - assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx; - assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16]; - assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx; - assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17]; - assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx; - assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18]; - assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx; - assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19]; - assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx; - assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20]; - assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx; - assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21]; - assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx; - assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22]; - assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx; - assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23]; - assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx; - assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24]; - assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx; - assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25]; - assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx; - assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26]; - assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx; - assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27]; - assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx; - assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28]; - assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx; - assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29]; - assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx; - assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30]; - assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx; - assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31]; - always @(posedge clk) - begin - if (reset_n) - if (^(F_valid) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/F_valid is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk) - begin - if (reset_n) - if (^(D_valid) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/D_valid is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk) - begin - if (reset_n) - if (^(E_valid) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/E_valid is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk) - begin - if (reset_n) - if (^(W_valid) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/W_valid is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (W_valid) - if (^(R_wr_dst_reg) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/R_wr_dst_reg is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (W_valid & R_wr_dst_reg) - if (^(W_wr_data) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/W_wr_data is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (W_valid & R_wr_dst_reg) - if (^(R_dst_regnum) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/R_dst_regnum is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk) - begin - if (reset_n) - if (^(d_write) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_write is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (d_write) - if (^(d_byteenable) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_byteenable is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (d_write | d_read) - if (^(d_address) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_address is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk) - begin - if (reset_n) - if (^(d_read) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_read is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk) - begin - if (reset_n) - if (^(i_read) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/i_read is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (i_read) - if (^(i_address) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/i_address is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (i_read & ~i_waitrequest) - if (^(i_readdata) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/i_readdata is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (W_valid & R_ctrl_ld) - if (^(av_ld_data_aligned_unfiltered) === 1'bx) - begin - $write("%0d ns: WARNING: nios_system_nios2_processor_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time); - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (W_valid & R_wr_dst_reg) - if (^(W_wr_data) === 1'bx) - begin - $write("%0d ns: WARNING: nios_system_nios2_processor_test_bench/W_wr_data is 'x'\n", $time); - end - end - - - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on -//synthesis read_comments_as_HDL on -// -// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered; -// -//synthesis read_comments_as_HDL off - -endmodule - diff --git a/nios_system/synthesis/submodules/nios_system_onchip_memory.hex b/nios_system/synthesis/submodules/nios_system_onchip_memory.hex deleted file mode 100644 index e265501..0000000 --- a/nios_system/synthesis/submodules/nios_system_onchip_memory.hex +++ /dev/null @@ -1,51201 +0,0 @@ -:0400000000000000FC -:0400010000000000FB -:0400020000000000FA -:0400030000000000F9 -:0400040000000000F8 -:0400050000000000F7 -:0400060000000000F6 -:0400070000000000F5 -:0400080000000000F4 -:0400090000000000F3 -:04000A0000000000F2 -:04000B0000000000F1 -:04000C0000000000F0 -:04000D0000000000EF -:04000E0000000000EE -:04000F0000000000ED -:0400100000000000EC -:0400110000000000EB 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a/nios_system/synthesis/submodules/nios_system_onchip_memory.v b/nios_system/synthesis/submodules/nios_system_onchip_memory.v deleted file mode 100644 index c12e1cd..0000000 --- a/nios_system/synthesis/submodules/nios_system_onchip_memory.v +++ /dev/null @@ -1,85 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_onchip_memory ( - // inputs: - address, - byteenable, - chipselect, - clk, - clken, - reset, - reset_req, - write, - writedata, - - // outputs: - readdata - ) -; - - parameter INIT_FILE = "nios_system_onchip_memory.hex"; - - - output [ 31: 0] readdata; - input [ 15: 0] address; - input [ 3: 0] byteenable; - input chipselect; - input clk; - input clken; - input reset; - input reset_req; - input write; - input [ 31: 0] writedata; - - wire clocken0; - wire [ 31: 0] readdata; - wire wren; - assign wren = chipselect & write; - assign clocken0 = clken & ~reset_req; - altsyncram the_altsyncram - ( - .address_a (address), - .byteena_a (byteenable), - .clock0 (clk), - .clocken0 (clocken0), - .data_a (writedata), - .q_a (readdata), - .wren_a (wren) - ); - - defparam the_altsyncram.byte_size = 8, - the_altsyncram.init_file = INIT_FILE, - the_altsyncram.lpm_type = "altsyncram", - the_altsyncram.maximum_depth = 51200, - the_altsyncram.numwords_a = 51200, - the_altsyncram.operation_mode = "SINGLE_PORT", - the_altsyncram.outdata_reg_a = "UNREGISTERED", - the_altsyncram.ram_block_type = "AUTO", - the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", - the_altsyncram.width_a = 32, - the_altsyncram.width_byteena_a = 4, - the_altsyncram.widthad_a = 16; - - //s1, which is an e_avalon_slave - //s2, which is an e_avalon_slave - -endmodule - diff --git a/nios_system/synthesis/submodules/nios_system_pio_0.v b/nios_system/synthesis/submodules/nios_system_pio_0.v deleted file mode 100644 index 9cd2e61..0000000 --- a/nios_system/synthesis/submodules/nios_system_pio_0.v +++ /dev/null @@ -1,58 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_pio_0 ( - // inputs: - address, - clk, - in_port, - reset_n, - - // outputs: - readdata - ) -; - - output [ 31: 0] readdata; - input [ 1: 0] address; - input clk; - input [ 17: 0] in_port; - input reset_n; - - wire clk_en; - wire [ 17: 0] data_in; - wire [ 17: 0] read_mux_out; - reg [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {18 {(address == 0)}} & data_in; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - readdata <= 0; - else if (clk_en) - readdata <= {32'b0 | read_mux_out}; - end - - - assign data_in = in_port; - -endmodule - diff --git a/nios_system/synthesis/submodules/nios_system_push_switches.v b/nios_system/synthesis/submodules/nios_system_push_switches.v deleted file mode 100644 index 5b3cb8d..0000000 --- a/nios_system/synthesis/submodules/nios_system_push_switches.v +++ /dev/null @@ -1,58 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_push_switches ( - // inputs: - address, - clk, - in_port, - reset_n, - - // outputs: - readdata - ) -; - - output [ 31: 0] readdata; - input [ 1: 0] address; - input clk; - input [ 2: 0] in_port; - input reset_n; - - wire clk_en; - wire [ 2: 0] data_in; - wire [ 2: 0] read_mux_out; - reg [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {3 {(address == 0)}} & data_in; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - readdata <= 0; - else if (clk_en) - readdata <= {32'b0 | read_mux_out}; - end - - - assign data_in = in_port; - -endmodule - diff --git a/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux.sv b/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux.sv deleted file mode 100644 index 44c4d45..0000000 --- a/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux.sv +++ /dev/null @@ -1,116 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------- -// Merlin Demultiplexer -// -// Asserts valid on the appropriate output -// given a one-hot channel signal. -// ------------------------------------- - -`timescale 1 ns / 1 ns - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_rsp_xbar_demux -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// NUM_OUTPUTS: 2 -// VALID_WIDTH: 1 -// ------------------------------------------ - -//------------------------------------------ -// Message Supression Used -// QIS Warnings -// 15610 - Warning: Design contains x input pin(s) that do not drive logic -//------------------------------------------ - -module nios_system_rsp_xbar_demux -( - // ------------------- - // Sink - // ------------------- - input [1-1 : 0] sink_valid, - input [96-1 : 0] sink_data, // ST_DATA_W=96 - input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Sources - // ------------------- - output reg src0_valid, - output reg [96-1 : 0] src0_data, // ST_DATA_W=96 - output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 - output reg src0_startofpacket, - output reg src0_endofpacket, - input src0_ready, - - output reg src1_valid, - output reg [96-1 : 0] src1_data, // ST_DATA_W=96 - output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18 - output reg src1_startofpacket, - output reg src1_endofpacket, - input src1_ready, - - - // ------------------- - // Clock & Reset - // ------------------- - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk - input clk, - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset - input reset - -); - - localparam NUM_OUTPUTS = 2; - wire [NUM_OUTPUTS - 1 : 0] ready_vector; - - // ------------------- - // Demux - // ------------------- - always @* begin - src0_data = sink_data; - src0_startofpacket = sink_startofpacket; - src0_endofpacket = sink_endofpacket; - src0_channel = sink_channel >> NUM_OUTPUTS; - - src0_valid = sink_channel[0] && sink_valid; - - src1_data = sink_data; - src1_startofpacket = sink_startofpacket; - src1_endofpacket = sink_endofpacket; - src1_channel = sink_channel >> NUM_OUTPUTS; - - src1_valid = sink_channel[1] && sink_valid; - - end - - // ------------------- - // Backpressure - // ------------------- - assign ready_vector[0] = src0_ready; - assign ready_vector[1] = src1_ready; - - assign sink_ready = |(sink_channel & {{16{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); - -endmodule - - diff --git a/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux_002.sv b/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux_002.sv deleted file mode 100644 index 52411df..0000000 --- a/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux_002.sv +++ /dev/null @@ -1,101 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------- -// Merlin Demultiplexer -// -// Asserts valid on the appropriate output -// given a one-hot channel signal. -// ------------------------------------- - -`timescale 1 ns / 1 ns - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_rsp_xbar_demux_002 -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// NUM_OUTPUTS: 1 -// VALID_WIDTH: 1 -// ------------------------------------------ - -//------------------------------------------ -// Message Supression Used -// QIS Warnings -// 15610 - Warning: Design contains x input pin(s) that do not drive logic -//------------------------------------------ - -module nios_system_rsp_xbar_demux_002 -( - // ------------------- - // Sink - // ------------------- - input [1-1 : 0] sink_valid, - input [96-1 : 0] sink_data, // ST_DATA_W=96 - input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Sources - // ------------------- - output reg src0_valid, - output reg [96-1 : 0] src0_data, // ST_DATA_W=96 - output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 - output reg src0_startofpacket, - output reg src0_endofpacket, - input src0_ready, - - - // ------------------- - // Clock & Reset - // ------------------- - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk - input clk, - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset - input reset - -); - - localparam NUM_OUTPUTS = 1; - wire [NUM_OUTPUTS - 1 : 0] ready_vector; - - // ------------------- - // Demux - // ------------------- - always @* begin - src0_data = sink_data; - src0_startofpacket = sink_startofpacket; - src0_endofpacket = sink_endofpacket; - src0_channel = sink_channel >> NUM_OUTPUTS; - - src0_valid = sink_channel[0] && sink_valid; - - end - - // ------------------- - // Backpressure - // ------------------- - assign ready_vector[0] = src0_ready; - - assign sink_ready = |(sink_channel & {{17{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); - -endmodule - - diff --git a/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux_003.sv b/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux_003.sv deleted file mode 100644 index 755ac9e..0000000 --- a/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux_003.sv +++ /dev/null @@ -1,101 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------- -// Merlin Demultiplexer -// -// Asserts valid on the appropriate output -// given a one-hot channel signal. -// ------------------------------------- - -`timescale 1 ns / 1 ns - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_rsp_xbar_demux_003 -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// NUM_OUTPUTS: 1 -// VALID_WIDTH: 1 -// ------------------------------------------ - -//------------------------------------------ -// Message Supression Used -// QIS Warnings -// 15610 - Warning: Design contains x input pin(s) that do not drive logic -//------------------------------------------ - -module nios_system_rsp_xbar_demux_003 -( - // ------------------- - // Sink - // ------------------- - input [1-1 : 0] sink_valid, - input [96-1 : 0] sink_data, // ST_DATA_W=96 - input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Sources - // ------------------- - output reg src0_valid, - output reg [96-1 : 0] src0_data, // ST_DATA_W=96 - output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 - output reg src0_startofpacket, - output reg src0_endofpacket, - input src0_ready, - - - // ------------------- - // Clock & Reset - // ------------------- - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk - input clk, - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset - input reset - -); - - localparam NUM_OUTPUTS = 1; - wire [NUM_OUTPUTS - 1 : 0] ready_vector; - - // ------------------- - // Demux - // ------------------- - always @* begin - src0_data = sink_data; - src0_startofpacket = sink_startofpacket; - src0_endofpacket = sink_endofpacket; - src0_channel = sink_channel >> NUM_OUTPUTS; - - src0_valid = sink_channel[0] && sink_valid; - - end - - // ------------------- - // Backpressure - // ------------------- - assign ready_vector[0] = src0_ready; - - assign sink_ready = |(sink_channel & {{17{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); - -endmodule - - diff --git a/nios_system/synthesis/submodules/nios_system_rsp_xbar_mux.sv b/nios_system/synthesis/submodules/nios_system_rsp_xbar_mux.sv deleted file mode 100644 index 6f30bfb..0000000 --- a/nios_system/synthesis/submodules/nios_system_rsp_xbar_mux.sv +++ /dev/null @@ -1,331 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------ -// Merlin Multiplexer -// ------------------------------------------ - -`timescale 1 ns / 1 ns - - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_rsp_xbar_mux -// NUM_INPUTS: 2 -// ARBITRATION_SHARES: 1 1 -// ARBITRATION_SCHEME "no-arb" -// PIPELINE_ARB: 0 -// PKT_TRANS_LOCK: 59 (arbitration locking enabled) -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// ------------------------------------------ - -module nios_system_rsp_xbar_mux -( - // ---------------------- - // Sinks - // ---------------------- - input sink0_valid, - input [96-1 : 0] sink0_data, - input [18-1: 0] sink0_channel, - input sink0_startofpacket, - input sink0_endofpacket, - output sink0_ready, - - input sink1_valid, - input [96-1 : 0] sink1_data, - input [18-1: 0] sink1_channel, - input sink1_startofpacket, - input sink1_endofpacket, - output sink1_ready, - - - // ---------------------- - // Source - // ---------------------- - output src_valid, - output [96-1 : 0] src_data, - output [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready, - - // ---------------------- - // Clock & Reset - // ---------------------- - input clk, - input reset -); - localparam PAYLOAD_W = 96 + 18 + 2; - localparam NUM_INPUTS = 2; - localparam SHARE_COUNTER_W = 1; - localparam PIPELINE_ARB = 0; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam PKT_TRANS_LOCK = 59; - - // ------------------------------------------ - // Signals - // ------------------------------------------ - wire [NUM_INPUTS - 1 : 0] request; - wire [NUM_INPUTS - 1 : 0] valid; - wire [NUM_INPUTS - 1 : 0] grant; - wire [NUM_INPUTS - 1 : 0] next_grant; - reg [NUM_INPUTS - 1 : 0] saved_grant; - reg [PAYLOAD_W - 1 : 0] src_payload; - wire last_cycle; - reg packet_in_progress; - reg update_grant; - - wire [PAYLOAD_W - 1 : 0] sink0_payload; - wire [PAYLOAD_W - 1 : 0] sink1_payload; - - assign valid[0] = sink0_valid; - assign valid[1] = sink1_valid; - - - // ------------------------------------------ - // ------------------------------------------ - // Grant Logic & Updates - // ------------------------------------------ - // ------------------------------------------ - reg [NUM_INPUTS - 1 : 0] lock; - always @* begin - lock[0] = sink0_data[59]; - lock[1] = sink1_data[59]; - end - - assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); - - // ------------------------------------------ - // We're working on a packet at any time valid is high, except - // when this is the endofpacket. - // ------------------------------------------ - always @(posedge clk or posedge reset) begin - if (reset) begin - packet_in_progress <= 1'b0; - end - else begin - if (src_valid) - packet_in_progress <= 1'b1; - if (last_cycle) - packet_in_progress <= 1'b0; - end - end - - - // ------------------------------------------ - // Shares - // - // Special case: all-equal shares _should_ be optimized into assigning a - // constant to next_grant_share. - // Special case: all-1's shares _should_ result in the share counter - // being optimized away. - // ------------------------------------------ - // Input | arb shares | counter load value - // 0 | 1 | 0 - // 1 | 1 | 0 - wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; - - // ------------------------------------------ - // Choose the share value corresponding to the grant. - // ------------------------------------------ - reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; - always @* begin - next_grant_share = - share_0 & { SHARE_COUNTER_W {next_grant[0]} } | - share_1 & { SHARE_COUNTER_W {next_grant[1]} }; - end - - // ------------------------------------------ - // Flag to indicate first packet of an arb sequence. - // ------------------------------------------ - wire grant_changed = ~packet_in_progress && !(saved_grant & valid); - reg first_packet_r; - wire first_packet = grant_changed | first_packet_r; - always @(posedge clk or posedge reset) begin - if (reset) begin - first_packet_r <= 1'b0; - end - else begin - if (update_grant) - first_packet_r <= 1'b1; - else if (last_cycle) - first_packet_r <= 1'b0; - else if (grant_changed) - first_packet_r <= 1'b1; - end - end - - // ------------------------------------------ - // Compute the next share-count value. - // ------------------------------------------ - reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; - reg [SHARE_COUNTER_W - 1 : 0] share_count; - reg share_count_zero_flag; - - always @* begin - if (first_packet) begin - p1_share_count = next_grant_share; - end - else begin - // Update the counter, but don't decrement below 0. - p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; - end - end - - // ------------------------------------------ - // Update the share counter and share-counter=zero flag. - // ------------------------------------------ - always @(posedge clk or posedge reset) begin - if (reset) begin - share_count <= '0; - share_count_zero_flag <= 1'b1; - end - else begin - if (last_cycle) begin - share_count <= p1_share_count; - share_count_zero_flag <= (p1_share_count == '0); - end - end - end - - // ------------------------------------------ - // For each input, maintain a final_packet signal which goes active for the - // last packet of a full-share packet sequence. Example: if I have 4 - // shares and I'm continuously requesting, final_packet is active in the - // 4th packet. - // ------------------------------------------ - wire final_packet_0 = 1'b1; - - wire final_packet_1 = 1'b1; - - - // ------------------------------------------ - // Concatenate all final_packet signals (wire or reg) into a handy vector. - // ------------------------------------------ - wire [NUM_INPUTS - 1 : 0] final_packet = { - final_packet_1, - final_packet_0 - }; - - // ------------------------------------------ - // ------------------------------------------ - wire p1_done = |(final_packet & grant); - - // ------------------------------------------ - // Flag for the first cycle of packets within an - // arb sequence - // ------------------------------------------ - reg first_cycle; - always @(posedge clk, posedge reset) begin - if (reset) - first_cycle <= 0; - else - first_cycle <= last_cycle && ~p1_done; - end - - - always @* begin - update_grant = 0; - - // ------------------------------------------ - // No arbitration pipeline, update grant whenever - // the current arb winner has consumed all shares, - // or all requests are low - // ------------------------------------------ - update_grant = (last_cycle && p1_done) || (first_cycle && !valid); - update_grant = last_cycle; - end - - wire save_grant; - assign save_grant = 1; - assign grant = next_grant; - - always @(posedge clk, posedge reset) begin - if (reset) - saved_grant <= '0; - else if (save_grant) - saved_grant <= next_grant; - end - - // ------------------------------------------ - // ------------------------------------------ - // Arbitrator - // ------------------------------------------ - // ------------------------------------------ - - // ------------------------------------------ - // Create a request vector that stays high during - // the packet for unpipelined arbitration. - // - // The pipelined arbitration scheme does not require - // request to be held high during the packet. - // ------------------------------------------ - assign request = valid; - - - altera_merlin_arbitrator - #( - .NUM_REQUESTERS(NUM_INPUTS), - .SCHEME ("no-arb"), - .PIPELINE (0) - ) arb ( - .clk (clk), - .reset (reset), - .request (request), - .grant (next_grant), - .save_top_priority (src_valid), - .increment_top_priority (update_grant) - ); - - // ------------------------------------------ - // ------------------------------------------ - // Mux - // - // Implemented as a sum of products. - // ------------------------------------------ - // ------------------------------------------ - - assign sink0_ready = src_ready && grant[0]; - assign sink1_ready = src_ready && grant[1]; - - assign src_valid = |(grant & valid); - - always @* begin - src_payload = - sink0_payload & {PAYLOAD_W {grant[0]} } | - sink1_payload & {PAYLOAD_W {grant[1]} }; - end - - // ------------------------------------------ - // Mux Payload Mapping - // ------------------------------------------ - - assign sink0_payload = {sink0_channel,sink0_data, - sink0_startofpacket,sink0_endofpacket}; - assign sink1_payload = {sink1_channel,sink1_data, - sink1_startofpacket,sink1_endofpacket}; - - assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; - -endmodule - - - diff --git a/nios_system/synthesis/submodules/nios_system_rsp_xbar_mux_001.sv b/nios_system/synthesis/submodules/nios_system_rsp_xbar_mux_001.sv deleted file mode 100644 index ce9f7a1..0000000 --- a/nios_system/synthesis/submodules/nios_system_rsp_xbar_mux_001.sv +++ /dev/null @@ -1,651 +0,0 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------ -// Merlin Multiplexer -// ------------------------------------------ - -`timescale 1 ns / 1 ns - - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_rsp_xbar_mux_001 -// NUM_INPUTS: 18 -// ARBITRATION_SHARES: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -// ARBITRATION_SCHEME "no-arb" -// PIPELINE_ARB: 0 -// PKT_TRANS_LOCK: 59 (arbitration locking enabled) -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// ------------------------------------------ - -module nios_system_rsp_xbar_mux_001 -( - // ---------------------- - // Sinks - // ---------------------- - input sink0_valid, - input [96-1 : 0] sink0_data, - input [18-1: 0] sink0_channel, - input sink0_startofpacket, - input sink0_endofpacket, - output sink0_ready, - - input sink1_valid, - input [96-1 : 0] sink1_data, - input [18-1: 0] sink1_channel, - input sink1_startofpacket, - input sink1_endofpacket, - output sink1_ready, - - input sink2_valid, - input [96-1 : 0] sink2_data, - input [18-1: 0] sink2_channel, - input sink2_startofpacket, - input sink2_endofpacket, - output sink2_ready, - - input sink3_valid, - input [96-1 : 0] sink3_data, - input [18-1: 0] sink3_channel, - input sink3_startofpacket, - input sink3_endofpacket, - output sink3_ready, - - input sink4_valid, - input [96-1 : 0] sink4_data, - input [18-1: 0] sink4_channel, - input sink4_startofpacket, - input sink4_endofpacket, - output sink4_ready, - - input sink5_valid, - input [96-1 : 0] sink5_data, - input [18-1: 0] sink5_channel, - input sink5_startofpacket, - input sink5_endofpacket, - output sink5_ready, - - input sink6_valid, - input [96-1 : 0] sink6_data, - input [18-1: 0] sink6_channel, - input sink6_startofpacket, - input sink6_endofpacket, - output sink6_ready, - - input sink7_valid, - input [96-1 : 0] sink7_data, - input [18-1: 0] sink7_channel, - input sink7_startofpacket, - input sink7_endofpacket, - output sink7_ready, - - input sink8_valid, - input [96-1 : 0] sink8_data, - input [18-1: 0] sink8_channel, - input sink8_startofpacket, - input sink8_endofpacket, - output sink8_ready, - - input sink9_valid, - input [96-1 : 0] sink9_data, - input [18-1: 0] sink9_channel, - input sink9_startofpacket, - input sink9_endofpacket, - output sink9_ready, - - input sink10_valid, - input [96-1 : 0] sink10_data, - input [18-1: 0] sink10_channel, - input sink10_startofpacket, - input sink10_endofpacket, - output sink10_ready, - - input sink11_valid, - input [96-1 : 0] sink11_data, - input [18-1: 0] sink11_channel, - input sink11_startofpacket, - input sink11_endofpacket, - output sink11_ready, - - input sink12_valid, - input [96-1 : 0] sink12_data, - input [18-1: 0] sink12_channel, - input sink12_startofpacket, - input sink12_endofpacket, - output sink12_ready, - - input sink13_valid, - input [96-1 : 0] sink13_data, - input [18-1: 0] sink13_channel, - input sink13_startofpacket, - input sink13_endofpacket, - output sink13_ready, - - input sink14_valid, - input [96-1 : 0] sink14_data, - input [18-1: 0] sink14_channel, - input sink14_startofpacket, - input sink14_endofpacket, - output sink14_ready, - - input sink15_valid, - input [96-1 : 0] sink15_data, - input [18-1: 0] sink15_channel, - input sink15_startofpacket, - input sink15_endofpacket, - output sink15_ready, - - input sink16_valid, - input [96-1 : 0] sink16_data, - input [18-1: 0] sink16_channel, - input sink16_startofpacket, - input sink16_endofpacket, - output sink16_ready, - - input sink17_valid, - input [96-1 : 0] sink17_data, - input [18-1: 0] sink17_channel, - input sink17_startofpacket, - input sink17_endofpacket, - output sink17_ready, - - - // ---------------------- - // Source - // ---------------------- - output src_valid, - output [96-1 : 0] src_data, - output [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready, - - // ---------------------- - // Clock & Reset - // ---------------------- - input clk, - input reset -); - localparam PAYLOAD_W = 96 + 18 + 2; - localparam NUM_INPUTS = 18; - localparam SHARE_COUNTER_W = 1; - localparam PIPELINE_ARB = 0; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam PKT_TRANS_LOCK = 59; - - // ------------------------------------------ - // Signals - // ------------------------------------------ - wire [NUM_INPUTS - 1 : 0] request; - wire [NUM_INPUTS - 1 : 0] valid; - wire [NUM_INPUTS - 1 : 0] grant; - wire [NUM_INPUTS - 1 : 0] next_grant; - reg [NUM_INPUTS - 1 : 0] saved_grant; - reg [PAYLOAD_W - 1 : 0] src_payload; - wire last_cycle; - reg packet_in_progress; - reg update_grant; - - wire [PAYLOAD_W - 1 : 0] sink0_payload; - wire [PAYLOAD_W - 1 : 0] sink1_payload; - wire [PAYLOAD_W - 1 : 0] sink2_payload; - wire [PAYLOAD_W - 1 : 0] sink3_payload; - wire [PAYLOAD_W - 1 : 0] sink4_payload; - wire [PAYLOAD_W - 1 : 0] sink5_payload; - wire [PAYLOAD_W - 1 : 0] sink6_payload; - wire [PAYLOAD_W - 1 : 0] sink7_payload; - wire [PAYLOAD_W - 1 : 0] sink8_payload; - wire [PAYLOAD_W - 1 : 0] sink9_payload; - wire [PAYLOAD_W - 1 : 0] sink10_payload; - wire [PAYLOAD_W - 1 : 0] sink11_payload; - wire [PAYLOAD_W - 1 : 0] sink12_payload; - wire [PAYLOAD_W - 1 : 0] sink13_payload; - wire [PAYLOAD_W - 1 : 0] sink14_payload; - wire [PAYLOAD_W - 1 : 0] sink15_payload; - wire [PAYLOAD_W - 1 : 0] sink16_payload; - wire [PAYLOAD_W - 1 : 0] sink17_payload; - - assign valid[0] = sink0_valid; - assign valid[1] = sink1_valid; - assign valid[2] = sink2_valid; - assign valid[3] = sink3_valid; - assign valid[4] = sink4_valid; - assign valid[5] = sink5_valid; - assign valid[6] = sink6_valid; - assign valid[7] = sink7_valid; - assign valid[8] = sink8_valid; - assign valid[9] = sink9_valid; - assign valid[10] = sink10_valid; - assign valid[11] = sink11_valid; - assign valid[12] = sink12_valid; - assign valid[13] = sink13_valid; - assign valid[14] = sink14_valid; - assign valid[15] = sink15_valid; - assign valid[16] = sink16_valid; - assign valid[17] = sink17_valid; - - - // ------------------------------------------ - // ------------------------------------------ - // Grant Logic & Updates - // ------------------------------------------ - // ------------------------------------------ - reg [NUM_INPUTS - 1 : 0] lock; - always @* begin - lock[0] = sink0_data[59]; - lock[1] = sink1_data[59]; - lock[2] = sink2_data[59]; - lock[3] = sink3_data[59]; - lock[4] = sink4_data[59]; - lock[5] = sink5_data[59]; - lock[6] = sink6_data[59]; - lock[7] = sink7_data[59]; - lock[8] = sink8_data[59]; - lock[9] = sink9_data[59]; - lock[10] = sink10_data[59]; - lock[11] = sink11_data[59]; - lock[12] = sink12_data[59]; - lock[13] = sink13_data[59]; - lock[14] = sink14_data[59]; - lock[15] = sink15_data[59]; - lock[16] = sink16_data[59]; - lock[17] = sink17_data[59]; - end - - assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); - - // ------------------------------------------ - // We're working on a packet at any time valid is high, except - // when this is the endofpacket. - // ------------------------------------------ - always @(posedge clk or posedge reset) begin - if (reset) begin - packet_in_progress <= 1'b0; - end - else begin - if (src_valid) - packet_in_progress <= 1'b1; - if (last_cycle) - packet_in_progress <= 1'b0; - end - end - - - // ------------------------------------------ - // Shares - // - // Special case: all-equal shares _should_ be optimized into assigning a - // constant to next_grant_share. - // Special case: all-1's shares _should_ result in the share counter - // being optimized away. - // ------------------------------------------ - // Input | arb shares | counter load value - // 0 | 1 | 0 - // 1 | 1 | 0 - // 2 | 1 | 0 - // 3 | 1 | 0 - // 4 | 1 | 0 - // 5 | 1 | 0 - // 6 | 1 | 0 - // 7 | 1 | 0 - // 8 | 1 | 0 - // 9 | 1 | 0 - // 10 | 1 | 0 - // 11 | 1 | 0 - // 12 | 1 | 0 - // 13 | 1 | 0 - // 14 | 1 | 0 - // 15 | 1 | 0 - // 16 | 1 | 0 - // 17 | 1 | 0 - wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_6 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_7 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_8 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_9 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_10 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_11 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_12 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_13 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_14 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_15 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_16 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_17 = 1'd0; - - // ------------------------------------------ - // Choose the share value corresponding to the grant. - // ------------------------------------------ - reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; - always @* begin - next_grant_share = - share_0 & { SHARE_COUNTER_W {next_grant[0]} } | - share_1 & { SHARE_COUNTER_W {next_grant[1]} } | - share_2 & { SHARE_COUNTER_W {next_grant[2]} } | - share_3 & { SHARE_COUNTER_W {next_grant[3]} } | - share_4 & { SHARE_COUNTER_W {next_grant[4]} } | - share_5 & { SHARE_COUNTER_W {next_grant[5]} } | - share_6 & { SHARE_COUNTER_W {next_grant[6]} } | - share_7 & { SHARE_COUNTER_W {next_grant[7]} } | - share_8 & { SHARE_COUNTER_W {next_grant[8]} } | - share_9 & { SHARE_COUNTER_W {next_grant[9]} } | - share_10 & { SHARE_COUNTER_W {next_grant[10]} } | - share_11 & { SHARE_COUNTER_W {next_grant[11]} } | - share_12 & { SHARE_COUNTER_W {next_grant[12]} } | - share_13 & { SHARE_COUNTER_W {next_grant[13]} } | - share_14 & { SHARE_COUNTER_W {next_grant[14]} } | - share_15 & { SHARE_COUNTER_W {next_grant[15]} } | - share_16 & { SHARE_COUNTER_W {next_grant[16]} } | - share_17 & { SHARE_COUNTER_W {next_grant[17]} }; - end - - // ------------------------------------------ - // Flag to indicate first packet of an arb sequence. - // ------------------------------------------ - wire grant_changed = ~packet_in_progress && !(saved_grant & valid); - reg first_packet_r; - wire first_packet = grant_changed | first_packet_r; - always @(posedge clk or posedge reset) begin - if (reset) begin - first_packet_r <= 1'b0; - end - else begin - if (update_grant) - first_packet_r <= 1'b1; - else if (last_cycle) - first_packet_r <= 1'b0; - else if (grant_changed) - first_packet_r <= 1'b1; - end - end - - // ------------------------------------------ - // Compute the next share-count value. - // ------------------------------------------ - reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; - reg [SHARE_COUNTER_W - 1 : 0] share_count; - reg share_count_zero_flag; - - always @* begin - if (first_packet) begin - p1_share_count = next_grant_share; - end - else begin - // Update the counter, but don't decrement below 0. - p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; - end - end - - // ------------------------------------------ - // Update the share counter and share-counter=zero flag. - // ------------------------------------------ - always @(posedge clk or posedge reset) begin - if (reset) begin - share_count <= '0; - share_count_zero_flag <= 1'b1; - end - else begin - if (last_cycle) begin - share_count <= p1_share_count; - share_count_zero_flag <= (p1_share_count == '0); - end - end - end - - // ------------------------------------------ - // For each input, maintain a final_packet signal which goes active for the - // last packet of a full-share packet sequence. Example: if I have 4 - // shares and I'm continuously requesting, final_packet is active in the - // 4th packet. - // ------------------------------------------ - wire final_packet_0 = 1'b1; - - wire final_packet_1 = 1'b1; - - wire final_packet_2 = 1'b1; - - wire final_packet_3 = 1'b1; - - wire final_packet_4 = 1'b1; - - wire final_packet_5 = 1'b1; - - wire final_packet_6 = 1'b1; - - wire final_packet_7 = 1'b1; - - wire final_packet_8 = 1'b1; - - wire final_packet_9 = 1'b1; - - wire final_packet_10 = 1'b1; - - wire final_packet_11 = 1'b1; - - wire final_packet_12 = 1'b1; - - wire final_packet_13 = 1'b1; - - wire final_packet_14 = 1'b1; - - wire final_packet_15 = 1'b1; - - wire final_packet_16 = 1'b1; - - wire final_packet_17 = 1'b1; - - - // ------------------------------------------ - // Concatenate all final_packet signals (wire or reg) into a handy vector. - // ------------------------------------------ - wire [NUM_INPUTS - 1 : 0] final_packet = { - final_packet_17, - final_packet_16, - final_packet_15, - final_packet_14, - final_packet_13, - final_packet_12, - final_packet_11, - final_packet_10, - final_packet_9, - final_packet_8, - final_packet_7, - final_packet_6, - final_packet_5, - final_packet_4, - final_packet_3, - final_packet_2, - final_packet_1, - final_packet_0 - }; - - // ------------------------------------------ - // ------------------------------------------ - wire p1_done = |(final_packet & grant); - - // ------------------------------------------ - // Flag for the first cycle of packets within an - // arb sequence - // ------------------------------------------ - reg first_cycle; - always @(posedge clk, posedge reset) begin - if (reset) - first_cycle <= 0; - else - first_cycle <= last_cycle && ~p1_done; - end - - - always @* begin - update_grant = 0; - - // ------------------------------------------ - // No arbitration pipeline, update grant whenever - // the current arb winner has consumed all shares, - // or all requests are low - // ------------------------------------------ - update_grant = (last_cycle && p1_done) || (first_cycle && !valid); - update_grant = last_cycle; - end - - wire save_grant; - assign save_grant = 1; - assign grant = next_grant; - - always @(posedge clk, posedge reset) begin - if (reset) - saved_grant <= '0; - else if (save_grant) - saved_grant <= next_grant; - end - - // ------------------------------------------ - // ------------------------------------------ - // Arbitrator - // ------------------------------------------ - // ------------------------------------------ - - // ------------------------------------------ - // Create a request vector that stays high during - // the packet for unpipelined arbitration. - // - // The pipelined arbitration scheme does not require - // request to be held high during the packet. - // ------------------------------------------ - assign request = valid; - - - altera_merlin_arbitrator - #( - .NUM_REQUESTERS(NUM_INPUTS), - .SCHEME ("no-arb"), - .PIPELINE (0) - ) arb ( - .clk (clk), - .reset (reset), - .request (request), - .grant (next_grant), - .save_top_priority (src_valid), - .increment_top_priority (update_grant) - ); - - // ------------------------------------------ - // ------------------------------------------ - // Mux - // - // Implemented as a sum of products. - // ------------------------------------------ - // ------------------------------------------ - - assign sink0_ready = src_ready && grant[0]; - assign sink1_ready = src_ready && grant[1]; - assign sink2_ready = src_ready && grant[2]; - assign sink3_ready = src_ready && grant[3]; - assign sink4_ready = src_ready && grant[4]; - assign sink5_ready = src_ready && grant[5]; - assign sink6_ready = src_ready && grant[6]; - assign sink7_ready = src_ready && grant[7]; - assign sink8_ready = src_ready && grant[8]; - assign sink9_ready = src_ready && grant[9]; - assign sink10_ready = src_ready && grant[10]; - assign sink11_ready = src_ready && grant[11]; - assign sink12_ready = src_ready && grant[12]; - assign sink13_ready = src_ready && grant[13]; - assign sink14_ready = src_ready && grant[14]; - assign sink15_ready = src_ready && grant[15]; - assign sink16_ready = src_ready && grant[16]; - assign sink17_ready = src_ready && grant[17]; - - assign src_valid = |(grant & valid); - - always @* begin - src_payload = - sink0_payload & {PAYLOAD_W {grant[0]} } | - sink1_payload & {PAYLOAD_W {grant[1]} } | - sink2_payload & {PAYLOAD_W {grant[2]} } | - sink3_payload & {PAYLOAD_W {grant[3]} } | - sink4_payload & {PAYLOAD_W {grant[4]} } | - sink5_payload & {PAYLOAD_W {grant[5]} } | - sink6_payload & {PAYLOAD_W {grant[6]} } | - sink7_payload & {PAYLOAD_W {grant[7]} } | - sink8_payload & {PAYLOAD_W {grant[8]} } | - sink9_payload & {PAYLOAD_W {grant[9]} } | - sink10_payload & {PAYLOAD_W {grant[10]} } | - sink11_payload & {PAYLOAD_W {grant[11]} } | - sink12_payload & {PAYLOAD_W {grant[12]} } | - sink13_payload & {PAYLOAD_W {grant[13]} } | - sink14_payload & {PAYLOAD_W {grant[14]} } | - sink15_payload & {PAYLOAD_W {grant[15]} } | - sink16_payload & {PAYLOAD_W {grant[16]} } | - sink17_payload & {PAYLOAD_W {grant[17]} }; - end - - // ------------------------------------------ - // Mux Payload Mapping - // ------------------------------------------ - - assign sink0_payload = {sink0_channel,sink0_data, - sink0_startofpacket,sink0_endofpacket}; - assign sink1_payload = {sink1_channel,sink1_data, - sink1_startofpacket,sink1_endofpacket}; - assign sink2_payload = {sink2_channel,sink2_data, - sink2_startofpacket,sink2_endofpacket}; - assign sink3_payload = {sink3_channel,sink3_data, - sink3_startofpacket,sink3_endofpacket}; - assign sink4_payload = {sink4_channel,sink4_data, - sink4_startofpacket,sink4_endofpacket}; - assign sink5_payload = {sink5_channel,sink5_data, - sink5_startofpacket,sink5_endofpacket}; - assign sink6_payload = {sink6_channel,sink6_data, - sink6_startofpacket,sink6_endofpacket}; - assign sink7_payload = {sink7_channel,sink7_data, - sink7_startofpacket,sink7_endofpacket}; - assign sink8_payload = {sink8_channel,sink8_data, - sink8_startofpacket,sink8_endofpacket}; - assign sink9_payload = {sink9_channel,sink9_data, - sink9_startofpacket,sink9_endofpacket}; - assign sink10_payload = {sink10_channel,sink10_data, - sink10_startofpacket,sink10_endofpacket}; - assign sink11_payload = {sink11_channel,sink11_data, - sink11_startofpacket,sink11_endofpacket}; - assign sink12_payload = {sink12_channel,sink12_data, - sink12_startofpacket,sink12_endofpacket}; - assign sink13_payload = {sink13_channel,sink13_data, - sink13_startofpacket,sink13_endofpacket}; - assign sink14_payload = {sink14_channel,sink14_data, - sink14_startofpacket,sink14_endofpacket}; - assign sink15_payload = {sink15_channel,sink15_data, - sink15_startofpacket,sink15_endofpacket}; - assign sink16_payload = {sink16_channel,sink16_data, - sink16_startofpacket,sink16_endofpacket}; - assign sink17_payload = {sink17_channel,sink17_data, - sink17_startofpacket,sink17_endofpacket}; - - assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; - -endmodule - - - diff --git a/nios_system/synthesis/submodules/nios_system_switches.v b/nios_system/synthesis/submodules/nios_system_switches.v deleted file mode 100644 index 1fd0e98..0000000 --- a/nios_system/synthesis/submodules/nios_system_switches.v +++ /dev/null @@ -1,58 +0,0 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_switches ( - // inputs: - address, - clk, - in_port, - reset_n, - - // outputs: - readdata - ) -; - - output [ 31: 0] readdata; - input [ 1: 0] address; - input clk; - input [ 17: 0] in_port; - input reset_n; - - wire clk_en; - wire [ 17: 0] data_in; - wire [ 17: 0] read_mux_out; - reg [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {18 {(address == 0)}} & data_in; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - readdata <= 0; - else if (clk_en) - readdata <= {32'b0 | read_mux_out}; - end - - - assign data_in = in_port; - -endmodule - diff --git a/output_files/lights.cdf b/output_files/lights.cdf deleted file mode 100644 index 8cd075f..0000000 --- a/output_files/lights.cdf +++ /dev/null @@ -1,13 +0,0 @@ -/* Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */ -JedecChain; - FileRevision(JESD32A); - DefaultMfr(6E); - - P ActionCode(Cfg) - Device PartName(EP4CE115F29) Path("C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/") File("lights.sof") MfrSpec(OpMask(1)); - -ChainEnd; - -AlteraBegin; - ChainType(JTAG); -AlteraEnd; diff --git a/output_files/lights.done b/output_files/lights.done deleted file mode 100644 index 354d5fa..0000000 --- a/output_files/lights.done +++ /dev/null @@ -1 +0,0 @@ -Thu Dec 22 10:08:49 2016 diff --git a/output_files/lights.fit.smsg b/output_files/lights.fit.smsg deleted file mode 100644 index 558ea95..0000000 --- a/output_files/lights.fit.smsg +++ /dev/null @@ -1,8 +0,0 @@ -Extra Info (176273): Performing register packing on registers with non-logic cell location assignments -Extra Info (176274): Completed register packing on registers with non-logic cell location assignments -Extra Info (176236): Started Fast Input/Output/OE register processing -Extra Info (176237): Finished Fast Input/Output/OE register processing -Extra Info (176238): Start inferring scan chains for DSP blocks -Extra Info (176239): Inferring scan chains for DSP blocks is complete -Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density -Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/output_files/lights.fit.summary b/output_files/lights.fit.summary deleted file mode 100644 index 87d9510..0000000 --- a/output_files/lights.fit.summary +++ /dev/null @@ -1,16 +0,0 @@ -Fitter Status : Successful - Thu Dec 22 10:08:30 2016 -Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition -Revision Name : lights -Top-level Entity Name : lights -Family : Cyclone IV E -Device : EP4CE115F29C7 -Timing Models : Final -Total logic elements : 2,234 / 114,480 ( 2 % ) - Total combinational functions : 2,060 / 114,480 ( 2 % ) - Dedicated logic registers : 1,204 / 114,480 ( 1 % ) -Total registers : 1204 -Total pins : 118 / 529 ( 22 % ) -Total virtual pins : 0 -Total memory bits : 1,649,664 / 3,981,312 ( 41 % ) -Embedded Multiplier 9-bit elements : 0 / 532 ( 0 % ) -Total PLLs : 0 / 4 ( 0 % ) diff --git a/output_files/lights.jdi b/output_files/lights.jdi deleted file mode 100644 index ef8cbee..0000000 --- a/output_files/lights.jdi +++ /dev/null @@ -1,144 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/output_files/lights.map.smsg b/output_files/lights.map.smsg deleted file mode 100644 index 9cb4eec..0000000 --- a/output_files/lights.map.smsg +++ /dev/null @@ -1,12 +0,0 @@ -Info (10281): Verilog HDL Declaration information at nios_system_addr_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope -Info (10281): Verilog HDL Declaration information at nios_system_addr_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope -Info (10281): Verilog HDL Declaration information at nios_system_addr_router_001.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope -Info (10281): Verilog HDL Declaration information at nios_system_addr_router_001.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope -Info (10281): Verilog HDL Declaration information at nios_system_id_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope -Info (10281): Verilog HDL Declaration information at nios_system_id_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope -Info (10281): Verilog HDL Declaration information at nios_system_id_router_002.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope -Info (10281): Verilog HDL Declaration information at nios_system_id_router_002.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope -Warning (10037): Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1567): conditional expression evaluates to a constant -Warning (10037): Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1569): conditional expression evaluates to a constant -Warning (10037): Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1725): conditional expression evaluates to a constant -Warning (10037): Verilog HDL or VHDL warning at nios_system_nios2_processor.v(2553): conditional expression evaluates to a constant diff --git a/output_files/lights.map.summary b/output_files/lights.map.summary deleted file mode 100644 index cc7c897..0000000 --- a/output_files/lights.map.summary +++ /dev/null @@ -1,14 +0,0 @@ -Analysis & Synthesis Status : Successful - Thu Dec 22 10:07:53 2016 -Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition -Revision Name : lights -Top-level Entity Name : lights -Family : Cyclone IV E -Total logic elements : 2,331 - Total combinational functions : 2,056 - Dedicated logic registers : 1,212 -Total registers : 1212 -Total pins : 118 -Total virtual pins : 0 -Total memory bits : 1,649,664 -Embedded Multiplier 9-bit elements : 0 -Total PLLs : 0 diff --git a/output_files/lights.pin b/output_files/lights.pin deleted file mode 100644 index d64e56b..0000000 --- a/output_files/lights.pin +++ /dev/null @@ -1,850 +0,0 @@ - -- Copyright (C) 1991-2013 Altera Corporation - -- Your use of Altera Corporation's design tools, logic functions - -- and other software and tools, and its AMPP partner logic - -- functions, and any output files from any of the foregoing - -- (including device programming or simulation files), and any - -- associated documentation or information are expressly subject - -- to the terms and conditions of the Altera Program License - -- Subscription Agreement, Altera MegaCore Function License - -- Agreement, or other applicable license agreement, including, - -- without limitation, that your use is for the sole purpose of - -- programming logic devices manufactured by Altera and sold by - -- Altera or its authorized distributors. Please refer to the - -- applicable agreement for further details. - -- - -- This is a Quartus II output file. It is for reporting purposes only, and is - -- not intended for use as a Quartus II input file. This file cannot be used - -- to make Quartus II pin assignments - for instructions on how to make pin - -- assignments, please see Quartus II help. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- NC : No Connect. This pin has no internal connection to the device. - -- DNU : Do Not Use. This pin MUST NOT be connected. - -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). - -- VCCIO : Dedicated power pin, which MUST be connected to VCC - -- of its bank. - -- Bank 1: 3.3V - -- Bank 2: 3.3V - -- Bank 3: 3.3V - -- Bank 4: 3.3V - -- Bank 5: 2.5V - -- Bank 6: 2.5V - -- Bank 7: 2.5V - -- Bank 8: 2.5V - -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. - -- It can also be used to report unused dedicated pins. The connection - -- on the board for unused dedicated pins depends on whether this will - -- be used in a future design. One example is device migration. When - -- using device migration, refer to the device pin-tables. If it is a - -- GND pin in the pin table or if it will not be used in a future design - -- for another purpose the it MUST be connected to GND. If it is an unused - -- dedicated pin, then it can be connected to a valid signal on the board - -- (low, high, or toggling) if that signal is required for a different - -- revision of the design. - -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. - -- This pin should be connected to GND. It may also be connected to a - -- valid signal on the board (low, high, or toggling) if that signal - -- is required for a different revision of the design. - -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND - -- or leave it unconnected. - -- RESERVED : Unused I/O pin, which MUST be left unconnected. - -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. - -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. - -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. - -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- Pin directions (input, output or bidir) are based on device operating in user mode. - --------------------------------------------------------------------------------- - -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition -CHIP "lights" ASSIGNED TO AN: EP4CE115F29C7 - -Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment -------------------------------------------------------------------------------------------------------------- -VCCIO8 : A2 : power : : 2.5V : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : -VCCIO8 : A5 : power : : 2.5V : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 : -VCCIO8 : A9 : power : : 2.5V : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 8 : -VCCIO8 : A13 : power : : 2.5V : 8 : -GND+ : A14 : : : : 8 : -GND+ : A15 : : : : 7 : -VCCIO7 : A16 : power : : 2.5V : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 : -VCCIO7 : A20 : power : : 2.5V : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7 : -VCCIO7 : A24 : power : : 2.5V : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 7 : -VCCIO7 : A27 : power : : 2.5V : 7 : -VCCIO2 : AA1 : power : : 3.3V : 2 : -GND : AA2 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 : -GNDA1 : AA9 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 : -VCCIO3 : AA11 : power : : 3.3V : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3 : -HEX7[6] : AA14 : output : 3.3-V LVTTL : : 3 : Y -HEX6[5] : AA15 : output : 3.3-V LVTTL : : 4 : Y -HEX6[2] : AA16 : output : 3.3-V LVTTL : : 4 : Y -HEX6[0] : AA17 : output : 3.3-V LVTTL : : 4 : Y -VCCIO4 : AA18 : power : : 3.3V : 4 : -HEX4[1] : AA19 : output : 3.3-V LVTTL : : 4 : Y -GNDA4 : AA20 : gnd : : : : -HEX3[3] : AA21 : output : 3.3-V LVTTL : : 4 : Y -SW[15] : AA22 : input : 2.5 V : : 5 : Y -SW[14] : AA23 : input : 2.5 V : : 5 : Y -SW[13] : AA24 : input : 2.5 V : : 5 : Y -HEX2[0] : AA25 : output : 2.5 V : : 5 : Y -HEX2[1] : AA26 : output : 2.5 V : : 5 : Y -GND : AA27 : gnd : : : : -VCCIO5 : AA28 : power : : 2.5V : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB1 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 3 : -HEX6[4] : AB15 : output : 3.3-V LVTTL : : 4 : Y -HEX6[1] : AB16 : output : 3.3-V LVTTL : : 4 : Y -HEX6[3] : AB17 : output : 3.3-V LVTTL : : 4 : Y -HEX5[2] : AB18 : output : 3.3-V LVTTL : : 4 : Y -HEX4[0] : AB19 : output : 3.3-V LVTTL : : 4 : Y -HEX3[2] : AB20 : output : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4 : -SW[12] : AB23 : input : 2.5 V : : 5 : Y -SW[11] : AB24 : input : 2.5 V : : 5 : Y -SW[9] : AB25 : input : 2.5 V : : 5 : Y -SW[7] : AB26 : input : 2.5 V : : 5 : Y -SW[4] : AB27 : input : 2.5 V : : 5 : Y -SW[0] : AB28 : input : 2.5 V : : 5 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : AC1 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC2 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC3 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC5 : : : : 2 : -GND : AC6 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC7 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3 : -GND : AC9 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC11 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3 : -GND : AC13 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4 : -GND : AC16 : gnd : : : : -HEX6[6] : AC17 : output : 3.3-V LVTTL : : 4 : Y -HEX5[1] : AC18 : output : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4 : -GND : AC20 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC21 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4 : -GND : AC23 : gnd : : : : -SW[10] : AC24 : input : 2.5 V : : 5 : Y -SW[8] : AC25 : input : 2.5 V : : 5 : Y -SW[5] : AC26 : input : 2.5 V : : 5 : Y -SW[2] : AC27 : input : 2.5 V : : 5 : Y -SW[1] : AC28 : input : 2.5 V : : 5 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : AD1 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD2 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD3 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3 : -VCCIO3 : AD6 : power : : 3.3V : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3 : -VCCIO3 : AD9 : power : : 3.3V : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3 : -VCCIO3 : AD13 : power : : 3.3V : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD15 : : : : 4 : -VCCIO4 : AD16 : power : : 3.3V : 4 : -HEX7[0] : AD17 : output : 3.3-V LVTTL : : 4 : Y -HEX5[0] : AD18 : output : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4 : -VCCIO4 : AD20 : power : : 3.3V : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4 : -VCCIO4 : AD23 : power : : 3.3V : 4 : -HEX3[4] : AD24 : output : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 4 : -SW[6] : AD26 : input : 2.5 V : : 5 : Y -SW[3] : AD27 : input : 2.5 V : : 5 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE1 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE2 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE3 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE5 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4 : -HEX7[1] : AE17 : output : 3.3-V LVTTL : : 4 : Y -HEX4[6] : AE18 : output : 3.3-V LVTTL : : 4 : Y -HEX4[4] : AE19 : output : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5 : -GND : AF1 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF2 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF3 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4 : -HEX7[4] : AF17 : output : 3.3-V LVTTL : : 4 : Y -HEX5[5] : AF18 : output : 3.3-V LVTTL : : 4 : Y -HEX4[5] : AF19 : output : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4 : -HEX3[5] : AF23 : output : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 5 : -GND : AF28 : gnd : : : : -VCCIO2 : AG1 : power : : 3.3V : 2 : -GND : AG2 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AG4 : : : : 3 : -GND : AG5 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3 : -GND : AG9 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3 : -GND : AG13 : gnd : : : : -GND+ : AG14 : : : : 3 : -GND+ : AG15 : : : : 4 : -GND : AG16 : gnd : : : : -HEX7[2] : AG17 : output : 3.3-V LVTTL : : 4 : Y -HEX7[5] : AG18 : output : 3.3-V LVTTL : : 4 : Y -HEX5[4] : AG19 : output : 3.3-V LVTTL : : 4 : Y -GND : AG20 : gnd : : : : -HEX4[2] : AG21 : output : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4 : -GND : AG24 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4 : -GND : AG27 : gnd : : : : -VCCIO5 : AG28 : power : : 2.5V : 5 : -VCCIO3 : AH2 : power : : 3.3V : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3 : -VCCIO3 : AH5 : power : : 3.3V : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3 : -VCCIO3 : AH9 : power : : 3.3V : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3 : -VCCIO3 : AH13 : power : : 3.3V : 3 : -GND+ : AH14 : : : : 3 : -GND+ : AH15 : : : : 4 : -VCCIO4 : AH16 : power : : 3.3V : 4 : -HEX7[3] : AH17 : output : 3.3-V LVTTL : : 4 : Y -HEX5[6] : AH18 : output : 3.3-V LVTTL : : 4 : Y -HEX5[3] : AH19 : output : 3.3-V LVTTL : : 4 : Y -VCCIO4 : AH20 : power : : 3.3V : 4 : -HEX4[3] : AH21 : output : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4 : -VCCIO4 : AH24 : power : : 3.3V : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4 : -VCCIO4 : AH27 : power : : 3.3V : 4 : -VCCIO1 : B1 : power : : 3.3V : 1 : -GND : B2 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : -GND : B5 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 : -GND : B9 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 : -GND : B12 : gnd : : : : -GND : B13 : gnd : : : : -GND+ : B14 : : : : 8 : -GND+ : B15 : : : : 7 : -GND : B16 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 : -GND : B20 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7 : -GND : B24 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7 : -GND : B27 : gnd : : : : -VCCIO6 : B28 : power : : 2.5V : 6 : -GND : C1 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C27 : : : : 6 : -GND : C28 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1 : -GND : D3 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D23 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1 : -~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 3.3-V LVTTL : : 1 : N -RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 8 : -VCCIO8 : E6 : power : : 2.5V : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 : -VCCIO8 : E9 : power : : 2.5V : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8 : -VCCIO8 : E13 : power : : 2.5V : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 : -VCCIO7 : E16 : power : : 2.5V : 7 : -HEX0[2] : E17 : output : 2.5 V : : 7 : Y -LEDR[5] : E18 : output : 2.5 V : : 7 : Y -LEDR[2] : E19 : output : 2.5 V : : 7 : Y -VCCIO7 : E20 : power : : 2.5V : 7 : -LEDG[0] : E21 : output : 2.5 V : : 7 : Y -LEDG[1] : E22 : output : 2.5 V : : 7 : Y -VCCIO7 : E23 : power : : 2.5V : 7 : -LEDG[3] : E24 : output : 2.5 V : : 7 : Y -LEDG[2] : E25 : output : 2.5 V : : 7 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 : -~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : input : 3.3-V LVTTL : : 1 : N -RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 : -GND : F6 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 : -GND : F9 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 8 : -GND : F13 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8 : -LEDR[14] : F15 : output : 2.5 V : : 7 : Y -GND : F16 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 7 : -LEDR[4] : F18 : output : 2.5 V : : 7 : Y -LEDR[1] : F19 : output : 2.5 V : : 7 : Y -GND : F20 : gnd : : : : -LEDR[3] : F21 : output : 2.5 V : : 7 : Y -HEX0[1] : F22 : output : 2.5 V : : 7 : Y -GND : F23 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : F27 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 8 : -LEDR[15] : G15 : output : 2.5 V : : 7 : Y -LEDR[16] : G16 : output : 2.5 V : : 7 : Y -LEDR[9] : G17 : output : 2.5 V : : 7 : Y -HEX0[0] : G18 : output : 2.5 V : : 7 : Y -LEDR[0] : G19 : output : 2.5 V : : 7 : Y -LEDG[5] : G20 : output : 2.5 V : : 7 : Y -LEDG[7] : G21 : output : 2.5 V : : 7 : Y -LEDG[6] : G22 : output : 2.5 V : : 7 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6 : -VCCIO1 : H1 : power : : 3.3V : 1 : -GND : H2 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8 : -GNDA3 : H9 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 : -VCCIO8 : H11 : power : : 2.5V : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8 : -LEDR[17] : H15 : output : 2.5 V : : 7 : Y -LEDR[11] : H16 : output : 2.5 V : : 7 : Y -LEDR[13] : H17 : output : 2.5 V : : 7 : Y -VCCIO7 : H18 : power : : 2.5V : 7 : -LEDR[7] : H19 : output : 2.5 V : : 7 : Y -GNDA2 : H20 : gnd : : : : -LEDG[4] : H21 : output : 2.5 V : : 7 : Y -HEX0[6] : H22 : output : 2.5 V : : 6 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H26 : : : : 6 : -GND : H27 : gnd : : : : -VCCIO6 : H28 : power : : 2.5V : 6 : -GND+ : J1 : : : : 1 : -GND : J2 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 1 : -VCCA3 : J8 : power : : 2.5V : : -VCCD_PLL3 : J9 : power : : 1.2V : : -RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 : -GND : J11 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8 : -LEDR[10] : J15 : output : 2.5 V : : 7 : Y -LEDR[12] : J16 : output : 2.5 V : : 7 : Y -LEDR[8] : J17 : output : 2.5 V : : 7 : Y -GND : J18 : gnd : : : : -LEDR[6] : J19 : output : 2.5 V : : 7 : Y -VCCD_PLL2 : J20 : power : : 1.2V : : -VCCA2 : J21 : power : : 2.5V : : -HEX0[5] : J22 : output : 2.5 V : : 6 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6 : -GND+ : J27 : : : : 6 : -GND+ : J28 : : : : 6 : -LCD_data[4] : K1 : output : 3.3-V LVTTL : : 1 : Y -LCD_data[5] : K2 : output : 3.3-V LVTTL : : 1 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : K3 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1 : -VCCIO1 : K5 : power : : 3.3V : 1 : -GND : K6 : gnd : : : : -LCD_data[3] : K7 : output : 3.3-V LVTTL : : 1 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 : -VCCINT : K9 : power : : 1.2V : : -GND : K10 : gnd : : : : -VCCINT : K11 : power : : 1.2V : : -GND : K12 : gnd : : : : -VCCINT : K13 : power : : 1.2V : : -GND : K14 : gnd : : : : -VCCINT : K15 : power : : 1.2V : : -GND : K16 : gnd : : : : -VCCINT : K17 : power : : 1.2V : : -GND : K18 : gnd : : : : -VCCINT : K19 : power : : 1.2V : : -GND : K20 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 : -GND : K23 : gnd : : : : -VCCIO6 : K24 : power : : 2.5V : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6 : -LCD_data[1] : L1 : output : 3.3-V LVTTL : : 1 : Y -LCD_data[2] : L2 : output : 3.3-V LVTTL : : 1 : Y -LCD_data[0] : L3 : output : 3.3-V LVTTL : : 1 : Y -LCD_EN : L4 : output : 3.3-V LVTTL : : 1 : Y -LCD_ON : L5 : output : 3.3-V LVTTL : : 1 : Y -LCD_BLON : L6 : output : 3.3-V LVTTL : : 1 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 : -GND : L9 : gnd : : : : -VCCINT : L10 : power : : 1.2V : : -GND : L11 : gnd : : : : -VCCINT : L12 : power : : 1.2V : : -GND : L13 : gnd : : : : -VCCINT : L14 : power : : 1.2V : : -GND : L15 : gnd : : : : -VCCINT : L16 : power : : 1.2V : : -GND : L17 : gnd : : : : -VCCINT : L18 : power : : 1.2V : : -GND : L19 : gnd : : : : -VCCINT : L20 : power : : 1.2V : : -RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6 : -HEX0[4] : L25 : output : 2.5 V : : 6 : Y -HEX0[3] : L26 : output : 2.5 V : : 6 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : L27 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6 : -LCD_RW : M1 : output : 3.3-V LVTTL : : 1 : Y -LCD_RS : M2 : output : 3.3-V LVTTL : : 1 : Y -LCD_data[6] : M3 : output : 3.3-V LVTTL : : 1 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1 : -LCD_data[7] : M5 : output : 3.3-V LVTTL : : 1 : Y -nSTATUS : M6 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 1 : -VCCINT : M9 : power : : 1.2V : : -GND : M10 : gnd : : : : -VCCINT : M11 : power : : 1.2V : : -GND : M12 : gnd : : : : -VCCINT : M13 : power : : 1.2V : : -GND : M14 : gnd : : : : -VCCINT : M15 : power : : 1.2V : : -GND : M16 : gnd : : : : -VCCINT : M17 : power : : 1.2V : : -GND : M18 : gnd : : : : -VCCINT : M19 : power : : 1.2V : : -GND : M20 : gnd : : : : -KEY[1] : M21 : input : 2.5 V : : 6 : Y -MSEL2 : M22 : : : : 6 : -KEY[0] : M23 : input : 2.5 V : : 6 : Y -HEX1[0] : M24 : output : 2.5 V : : 6 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6 : -VCCIO1 : N1 : power : : 3.3V : 1 : -GND : N2 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 1 : -VCCIO1 : N5 : power : : 3.3V : 1 : -GND : N6 : gnd : : : : -~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : input : 3.3-V LVTTL : : 1 : N -RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 1 : -GND : N9 : gnd : : : : -VCCINT : N10 : power : : 1.2V : : -GND : N11 : gnd : : : : -VCCINT : N12 : power : : 1.2V : : -GND : N13 : gnd : : : : -VCCINT : N14 : power : : 1.2V : : -GND : N15 : gnd : : : : -VCCINT : N16 : power : : 1.2V : : -GND : N17 : gnd : : : : -VCCINT : N18 : power : : 1.2V : : -GND : N19 : gnd : : : : -VCCINT : N20 : power : : 1.2V : : -KEY[2] : N21 : input : 2.5 V : : 6 : Y -MSEL0 : N22 : : : : 6 : -GND : N23 : gnd : : : : -VCCIO6 : N24 : power : : 2.5V : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6 : -GND : N27 : gnd : : : : -VCCIO6 : N28 : power : : 2.5V : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 1 : -~ALTERA_DCLK~ : P3 : output : 3.3-V LVTTL : : 1 : N -nCONFIG : P4 : : : : 1 : -altera_reserved_tck : P5 : input : 3.3-V LVTTL : : 1 : N -altera_reserved_tdo : P6 : output : 3.3-V LVTTL : : 1 : N -altera_reserved_tdi : P7 : input : 3.3-V LVTTL : : 1 : N -altera_reserved_tms : P8 : input : 3.3-V LVTTL : : 1 : N -VCCINT : P9 : power : : 1.2V : : -GND : P10 : gnd : : : : -VCCINT : P11 : power : : 1.2V : : -GND : P12 : gnd : : : : -VCCINT : P13 : power : : 1.2V : : -GND : P14 : gnd : : : : -VCCINT : P15 : power : : 1.2V : : -GND : P16 : gnd : : : : -VCCINT : P17 : power : : 1.2V : : -GND : P18 : gnd : : : : -VCCINT : P19 : power : : 1.2V : : -GND : P20 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 : -MSEL3 : P22 : : : : 6 : -MSEL1 : P23 : : : : 6 : -CONF_DONE : P24 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6 : -~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : P28 : output : 2.5 V : : 6 : N -RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 : -nCE : R8 : : : : 1 : -GND : R9 : gnd : : : : -VCCINT : R10 : power : : 1.2V : : -GND : R11 : gnd : : : : -VCCINT : R12 : power : : 1.2V : : -GND : R13 : gnd : : : : -VCCINT : R14 : power : : 1.2V : : -GND : R15 : gnd : : : : -VCCINT : R16 : power : : 1.2V : : -GND : R17 : gnd : : : : -VCCINT : R18 : power : : 1.2V : : -GND : R19 : gnd : : : : -VCCINT : R20 : power : : 1.2V : : -RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5 : -KEY[3] : R24 : input : 2.5 V : : 5 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 5 : -VCCIO2 : T1 : power : : 3.3V : 2 : -GND : T2 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 : -VCCIO2 : T5 : power : : 3.3V : 2 : -GND : T6 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 2 : -VCCINT : T9 : power : : 1.2V : : -GND : T10 : gnd : : : : -VCCINT : T11 : power : : 1.2V : : -GND : T12 : gnd : : : : -VCCINT : T13 : power : : 1.2V : : -GND : T14 : gnd : : : : -VCCINT : T15 : power : : 1.2V : : -GND : T16 : gnd : : : : -VCCINT : T17 : power : : 1.2V : : -GND : T18 : gnd : : : : -VCCINT : T19 : power : : 1.2V : : -GND : T20 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 : -GND : T23 : gnd : : : : -VCCIO5 : T24 : power : : 2.5V : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5 : -GND : T27 : gnd : : : : -VCCIO5 : T28 : power : : 2.5V : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 2 : -GND : U9 : gnd : : : : -VCCINT : U10 : power : : 1.2V : : -GND : U11 : gnd : : : : -VCCINT : U12 : power : : 1.2V : : -GND : U13 : gnd : : : : -VCCINT : U14 : power : : 1.2V : : -GND : U15 : gnd : : : : -VCCINT : U16 : power : : 1.2V : : -GND : U17 : gnd : : : : -VCCINT : U18 : power : : 1.2V : : -GND : U19 : gnd : : : : -VCCINT : U20 : power : : 1.2V : : -HEX3[1] : U21 : output : 2.5 V : : 5 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 : -HEX1[5] : U23 : output : 2.5 V : : 5 : Y -HEX1[6] : U24 : output : 2.5 V : : 5 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 2 : -VCCINT : V9 : power : : 1.2V : : -GND : V10 : gnd : : : : -VCCINT : V11 : power : : 1.2V : : -GND : V12 : gnd : : : : -VCCINT : V13 : power : : 1.2V : : -GND : V14 : gnd : : : : -VCCINT : V15 : power : : 1.2V : : -GND : V16 : gnd : : : : -VCCINT : V17 : power : : 1.2V : : -GND : V18 : gnd : : : : -VCCINT : V19 : power : : 1.2V : : -GND : V20 : gnd : : : : -HEX3[0] : V21 : output : 2.5 V : : 5 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V26 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 2 : -VCCIO2 : W5 : power : : 3.3V : 2 : -GND : W6 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 2 : -GND : W9 : gnd : : : : -VCCINT : W10 : power : : 1.2V : : -GND : W11 : gnd : : : : -VCCINT : W12 : power : : 1.2V : : -GND : W13 : gnd : : : : -VCCINT : W14 : power : : 1.2V : : -GND : W15 : gnd : : : : -VCCINT : W16 : power : : 1.2V : : -GND : W17 : gnd : : : : -VCCINT : W18 : power : : 1.2V : : -GND : W19 : gnd : : : : -VCCINT : W20 : power : : 1.2V : : -HEX1[2] : W21 : output : 2.5 V : : 5 : Y -HEX1[3] : W22 : output : 2.5 V : : 5 : Y -GND : W23 : gnd : : : : -VCCIO5 : W24 : power : : 2.5V : 5 : -HEX1[4] : W25 : output : 2.5 V : : 5 : Y -HEX2[3] : W26 : output : 2.5 V : : 5 : Y -HEX2[5] : W27 : output : 2.5 V : : 5 : Y -HEX2[6] : W28 : output : 2.5 V : : 5 : Y -GND+ : Y1 : : : : 2 : -CLOCK_50 : Y2 : input : 3.3-V LVTTL : : 2 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 2 : -VCCA1 : Y8 : power : : 2.5V : : -VCCD_PLL1 : Y9 : power : : 1.2V : : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 : -GND : Y11 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y12 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 : -GND : Y18 : gnd : : : : -HEX3[6] : Y19 : output : 3.3-V LVTTL : : 4 : Y -VCCD_PLL4 : Y20 : power : : 1.2V : : -VCCA4 : Y21 : power : : 2.5V : : -HEX1[1] : Y22 : output : 2.5 V : : 5 : Y -SW[17] : Y23 : input : 2.5 V : : 5 : Y -SW[16] : Y24 : input : 2.5 V : : 5 : Y -HEX2[2] : Y25 : output : 2.5 V : : 5 : Y -HEX2[4] : Y26 : output : 2.5 V : : 5 : Y -GND+ : Y27 : : : : 5 : -GND+ : Y28 : : : : 5 : diff --git a/output_files/lights.sof b/output_files/lights.sof deleted file mode 100644 index 0e0d4db..0000000 --- a/output_files/lights.sof +++ /dev/null Binary files differ diff --git a/output_files/lights.sta.summary b/output_files/lights.sta.summary deleted file mode 100644 index 0146831..0000000 --- a/output_files/lights.sta.summary +++ /dev/null @@ -1,65 +0,0 @@ ------------------------------------------------------------- -TimeQuest Timing Analyzer Summary ------------------------------------------------------------- - -Type : Slow 1200mV 85C Model Setup 'altera_reserved_tck' -Slack : 46.656 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Hold 'altera_reserved_tck' -Slack : 0.401 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Recovery 'altera_reserved_tck' -Slack : 47.591 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Removal 'altera_reserved_tck' -Slack : 1.180 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Minimum Pulse Width 'altera_reserved_tck' -Slack : 49.555 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Setup 'altera_reserved_tck' -Slack : 47.042 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Hold 'altera_reserved_tck' -Slack : 0.353 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Recovery 'altera_reserved_tck' -Slack : 47.930 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Removal 'altera_reserved_tck' -Slack : 1.082 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Minimum Pulse Width 'altera_reserved_tck' -Slack : 49.489 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Setup 'altera_reserved_tck' -Slack : 48.710 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Hold 'altera_reserved_tck' -Slack : 0.178 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Recovery 'altera_reserved_tck' -Slack : 49.091 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Removal 'altera_reserved_tck' -Slack : 0.560 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Minimum Pulse Width 'altera_reserved_tck' -Slack : 49.301 -TNS : 0.000 - -------------------------------------------------------------