Newer
Older
DE2_115_PROG / lights.vhd
@takayun takayun on 16 Dec 2016 2 KB initial commit
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity lights is port (
	CLOCK_50	: in std_logic;
	KEY		: in std_logic_vector(3 downto 0);
	SW			: in std_logic_vector(17 downto 0);
	LEDG		: out std_logic_vector(7 downto 0);
	LEDR		: out std_logic_vector(17 downto 0);
	HEX0		: out std_logic_vector(6 downto 0);
	HEX1		: out std_logic_vector(6 downto 0);
	HEX2		: out std_logic_vector(6 downto 0);
	HEX3		: out std_logic_vector(6 downto 0);
	HEX4		: out std_logic_vector(6 downto 0);
	HEX5		: out std_logic_vector(6 downto 0);
	HEX6		: out std_logic_vector(6 downto 0);
	HEX7		: out std_logic_vector(6 downto 0);
	LCD_RS	: out std_logic;
	LCD_RW	: out std_logic;
	LCD_data	: out std_logic_vector(7 downto 0);
	LCD_EN	: out std_logic;
	LCD_ON	: out std_logic;
	LCD_BLON	: out std_logic
);
end lights;

architecture lights_rtl of lights is
	component nios_system
		port (
			signal clk_clk				: in std_logic;
			signal reset_reset_n		: in std_logic;
			signal switches_export	: in std_logic_vector(17 downto 0);
			signal push_switches_export	: in std_logic_vector(2 downto 0);
			signal leds_export		: out std_logic_vector(7 downto 0);
			signal ledrs_export		: out std_logic_vector(17 downto 0);
			signal hex0_export		: out std_logic_vector(6 downto 0);
			signal hex1_export		: out std_logic_vector(6 downto 0);
			signal hex2_export		: out std_logic_vector(6 downto 0);
			signal hex3_export		: out std_logic_vector(6 downto 0);
			signal hex4_export		: out std_logic_vector(6 downto 0);
			signal hex5_export		: out std_logic_vector(6 downto 0);
			signal hex6_export		: out std_logic_vector(6 downto 0);
			signal hex7_export		: out std_logic_vector(6 downto 0);
			signal lcd_16207_0_RS	: out std_logic;
			signal lcd_16207_0_RW	: out std_logic;
			signal lcd_16207_0_data	: out std_logic_vector(7 downto 0);
			signal lcd_16207_0_E		: out std_logic;
			signal lcd_on_export		: out std_logic;
			signal lcd_blon_export	: out std_logic
		);
	end component;
begin
	NiosII	: nios_system
		port map (
			clk_clk					=> CLOCK_50,
			reset_reset_n			=> KEY(0),
			switches_export		=> SW(17 downto 0),
			push_switches_export	=> KEY(3 downto 1),
			leds_export				=> LEDG(7 downto 0),
			ledrs_export			=> LEDR(17 downto 0),
			hex0_export				=> HEX0(6 downto 0),
			hex1_export				=> HEX1(6 downto 0),
			hex2_export				=> HEX2(6 downto 0),
			hex3_export				=> HEX3(6 downto 0),
			hex4_export				=> HEX4(6 downto 0),
			hex5_export				=> HEX5(6 downto 0),
			hex6_export				=> HEX6(6 downto 0),
			hex7_export				=> HEX7(6 downto 0),
			lcd_16207_0_RS			=> LCD_RS,
			lcd_16207_0_RW			=> LCD_RW,
			lcd_16207_0_data		=> LCD_DATA,
			lcd_16207_0_E			=> LCD_EN,
			lcd_on_export			=> LCD_ON,
			lcd_blon_export		=> LCD_BLON
		);
end lights_rtl;